BEGIN:VCALENDAR VERSION:2.0 PRODID:-//Marketing EDA - ECPv6.15.20//NONSGML v1.0//EN CALSCALE:GREGORIAN METHOD:PUBLISH X-ORIGINAL-URL:https://marketingeda.com X-WR-CALDESC:Events for Marketing EDA REFRESH-INTERVAL;VALUE=DURATION:PT1H X-Robots-Tag:noindex X-PUBLISHED-TTL:PT1H BEGIN:VTIMEZONE TZID:America/Los_Angeles BEGIN:DAYLIGHT TZOFFSETFROM:-0800 TZOFFSETTO:-0700 TZNAME:PDT DTSTART:20220313T100000 END:DAYLIGHT BEGIN:STANDARD TZOFFSETFROM:-0700 TZOFFSETTO:-0800 TZNAME:PST DTSTART:20221106T090000 END:STANDARD BEGIN:DAYLIGHT TZOFFSETFROM:-0800 TZOFFSETTO:-0700 TZNAME:PDT DTSTART:20230312T100000 END:DAYLIGHT BEGIN:STANDARD TZOFFSETFROM:-0700 TZOFFSETTO:-0800 TZNAME:PST DTSTART:20231105T090000 END:STANDARD BEGIN:DAYLIGHT TZOFFSETFROM:-0800 TZOFFSETTO:-0700 TZNAME:PDT DTSTART:20240310T100000 END:DAYLIGHT BEGIN:STANDARD TZOFFSETFROM:-0700 TZOFFSETTO:-0800 TZNAME:PST DTSTART:20241103T090000 END:STANDARD BEGIN:DAYLIGHT TZOFFSETFROM:-0800 TZOFFSETTO:-0700 TZNAME:PDT DTSTART:20250309T100000 END:DAYLIGHT BEGIN:STANDARD TZOFFSETFROM:-0700 TZOFFSETTO:-0800 TZNAME:PST DTSTART:20251102T090000 END:STANDARD BEGIN:DAYLIGHT TZOFFSETFROM:-0800 TZOFFSETTO:-0700 TZNAME:PDT DTSTART:20260308T100000 END:DAYLIGHT BEGIN:STANDARD TZOFFSETFROM:-0700 TZOFFSETTO:-0800 TZNAME:PST DTSTART:20261101T090000 END:STANDARD END:VTIMEZONE BEGIN:VTIMEZONE TZID:Asia/Tokyo BEGIN:STANDARD TZOFFSETFROM:+0900 TZOFFSETTO:+0900 TZNAME:JST DTSTART:20220101T000000 END:STANDARD END:VTIMEZONE BEGIN:VTIMEZONE TZID:Europe/London BEGIN:DAYLIGHT TZOFFSETFROM:+0000 TZOFFSETTO:+0100 TZNAME:BST DTSTART:20220327T010000 END:DAYLIGHT BEGIN:STANDARD TZOFFSETFROM:+0100 TZOFFSETTO:+0000 TZNAME:GMT DTSTART:20221030T010000 END:STANDARD BEGIN:DAYLIGHT TZOFFSETFROM:+0000 TZOFFSETTO:+0100 TZNAME:BST DTSTART:20230326T010000 END:DAYLIGHT BEGIN:STANDARD TZOFFSETFROM:+0100 TZOFFSETTO:+0000 TZNAME:GMT DTSTART:20231029T010000 END:STANDARD BEGIN:DAYLIGHT TZOFFSETFROM:+0000 TZOFFSETTO:+0100 TZNAME:BST DTSTART:20240331T010000 END:DAYLIGHT BEGIN:STANDARD TZOFFSETFROM:+0100 TZOFFSETTO:+0000 TZNAME:GMT DTSTART:20241027T010000 END:STANDARD BEGIN:DAYLIGHT TZOFFSETFROM:+0000 TZOFFSETTO:+0100 TZNAME:BST DTSTART:20250330T010000 END:DAYLIGHT BEGIN:STANDARD TZOFFSETFROM:+0100 TZOFFSETTO:+0000 TZNAME:GMT DTSTART:20251026T010000 END:STANDARD BEGIN:DAYLIGHT TZOFFSETFROM:+0000 TZOFFSETTO:+0100 TZNAME:BST DTSTART:20260329T010000 END:DAYLIGHT BEGIN:STANDARD TZOFFSETFROM:+0100 TZOFFSETTO:+0000 TZNAME:GMT DTSTART:20261025T010000 END:STANDARD END:VTIMEZONE BEGIN:VTIMEZONE TZID:Asia/Hong_Kong BEGIN:STANDARD TZOFFSETFROM:+0800 TZOFFSETTO:+0800 TZNAME:HKT DTSTART:20240101T000000 END:STANDARD END:VTIMEZONE BEGIN:VTIMEZONE TZID:Asia/Taipei BEGIN:STANDARD TZOFFSETFROM:+0800 TZOFFSETTO:+0800 TZNAME:CST DTSTART:20220101T000000 END:STANDARD END:VTIMEZONE BEGIN:VTIMEZONE TZID:Asia/Kolkata BEGIN:STANDARD TZOFFSETFROM:+0530 TZOFFSETTO:+0530 TZNAME:IST DTSTART:20230101T000000 END:STANDARD END:VTIMEZONE BEGIN:VTIMEZONE TZID:Europe/Berlin BEGIN:DAYLIGHT TZOFFSETFROM:+0100 TZOFFSETTO:+0200 TZNAME:CEST DTSTART:20220327T010000 END:DAYLIGHT BEGIN:STANDARD TZOFFSETFROM:+0200 TZOFFSETTO:+0100 TZNAME:CET DTSTART:20221030T010000 END:STANDARD BEGIN:DAYLIGHT TZOFFSETFROM:+0100 TZOFFSETTO:+0200 TZNAME:CEST DTSTART:20230326T010000 END:DAYLIGHT BEGIN:STANDARD TZOFFSETFROM:+0200 TZOFFSETTO:+0100 TZNAME:CET DTSTART:20231029T010000 END:STANDARD BEGIN:DAYLIGHT TZOFFSETFROM:+0100 TZOFFSETTO:+0200 TZNAME:CEST DTSTART:20240331T010000 END:DAYLIGHT BEGIN:STANDARD TZOFFSETFROM:+0200 TZOFFSETTO:+0100 TZNAME:CET DTSTART:20241027T010000 END:STANDARD BEGIN:DAYLIGHT TZOFFSETFROM:+0100 TZOFFSETTO:+0200 TZNAME:CEST DTSTART:20250330T010000 END:DAYLIGHT BEGIN:STANDARD TZOFFSETFROM:+0200 TZOFFSETTO:+0100 TZNAME:CET DTSTART:20251026T010000 END:STANDARD END:VTIMEZONE BEGIN:VTIMEZONE TZID:Indian/Maldives BEGIN:STANDARD TZOFFSETFROM:+0500 TZOFFSETTO:+0500 TZNAME:+05 DTSTART:20230101T000000 END:STANDARD END:VTIMEZONE BEGIN:VTIMEZONE TZID:Asia/Shanghai BEGIN:STANDARD TZOFFSETFROM:+0800 TZOFFSETTO:+0800 TZNAME:CST DTSTART:20220101T000000 END:STANDARD END:VTIMEZONE BEGIN:VTIMEZONE TZID:Asia/Seoul BEGIN:STANDARD TZOFFSETFROM:+0900 TZOFFSETTO:+0900 TZNAME:KST DTSTART:20220101T000000 END:STANDARD END:VTIMEZONE BEGIN:VEVENT DTSTART;TZID=America/Los_Angeles:20250319T080000 DTEND;TZID=America/Los_Angeles:20250320T170000 DTSTAMP:20260426T160312 CREATED:20241220T215313Z LAST-MODIFIED:20241220T215313Z UID:8694-1742371200-1742490000@marketingeda.com SUMMARY:SNUG Silicon Valley 2025 DESCRIPTION:Connecting the Synopsys User Community\n\n\n\n\n\n\n\n\n\n\nSNUG conferences have connected Synopsys global users for more than three decades. SNUG 2025 will once again provide a place where users and technical experts can meet\, network\, and share ideas about chip and system design. \nWe are thrilled to announce that SNUG Silicon Valley is celebrating its 35th year of innovation\, and we invite you to be a part of this milestone event. Have you used Synopsys technology to overcome difficult design issues or tackle one of those key challenges facing the industry? We’d like to hear from you! Showcase your work and share your experience with the community by submitting your proposal through the call for content process. \n\n\n\n\n\nShare this:\n Share on LinkedIn (Opens in new window)\n LinkedIn\n \n Share on X (Opens in new window)\n X\n \n Share on Facebook (Opens in new window)\n Facebook\n Like this:Like Loading... URL:https://marketingeda.com/event/snug-silicon-valley-2025/ LOCATION:Santa Clara Convention Center\, 5001 Great America Parkway\, Santa Clara\, CA\, 95054\, United States CATEGORIES:EDA,IP,User Group ATTACH;FMTTYPE=image/jpeg:https://marketingeda.com/wp-content/uploads/SNUG-Silicon-Valley-2025.jpeg END:VEVENT BEGIN:VEVENT DTSTART;TZID=Asia/Tokyo:20250123T100000 DTEND;TZID=Asia/Tokyo:20250123T170000 DTSTAMP:20260426T160312 CREATED:20241217T174422Z LAST-MODIFIED:20241217T174422Z UID:8611-1737626400-1737651600@marketingeda.com SUMMARY:Silvaco UseRs Global Event - Japan\, 2025 DESCRIPTION:SURGE (Silvaco UseRs Global Event) is a worldwide event held by Silvaco.\nSURGE is an event for discussing new technologies\, sharing user experiences\, and discovering innovative techniques for advanced semiconductor design in the fields of TCAD\, EDA\, and IP. The event will be held online. We look forward to your participation.\n\n\nWe will randomly select 8 lucky winners from those who participate on the day and fill out the questionnaire to receive a special prize.\n(Domestic shipping only.)\n\nPlease take this opportunity to register for SURGE Japan.\n\n\n\n\n\n\n\nDistribution : Online\ndistribution service : Zoom Meeting\nParticipation fee : Free\nLanguage : English \nAfter you register\, you will receive a notification email. \n\n\n\n\n\n\n\n\n\n\n\n\n\n\n\n\nAGENDA\n\n\n\n\n\n\n\nTime\nGeneral Session\n\n\n10:00 AM\nKeynote – Babak Taheri\, Chief Executive Officer and Director\, Silvaco​\n\n\n10:15 AM\nAI Takes EDA to the Next Level – Wally Rhines\, President and CEO of Cornami and Silvaco Board Member​\n\n\n10:30 AM\nNanoHub Workforce Development – Dr. Peter Griffin\, Stanford University\n\n\n\n\n\n\nTime\nSEMICONDUCTOR PROCESS AND DEVICE TRACK (TCAD)\n\n\n10:45 AM\nTCAD Update – Dr. Eric Guichard\, SVP and GM of TCAD Business Unit\, Silvaco​\n\n\n11:00 AM​\nLow-temperature Behavior in Nanowire Transistors by Quantum Transport Simulation – Sanam Moslemi-Tabrizi\, Analog Engineer\, Ciena\n\n\n11:15 AM\nMachine Learning for Multi-Scale Plasma Process Integration and Optimization – Associate Professor Dr. Lado Filipovic\, TU Vienna\n\n\n11:30 AM​\nTBA – Sumeet Pandey\, Micron Technologies​\n\n\n11:45 AM\nApplying Artificial Intelligence in Fab Technology Co-Optimization – Dr. Christian Caillat\, TCAD Senior Staff FAE\, Silvaco\n\n\n12:05 AM​\nDeveloping Silicon Carbide DMOSFETs: A Digital Twin Design Reference Flow – Dr. David Green\, TCAD Applications Engineer\, Silvaco\n\n\n12:25 AM​\nPower Devices SPICE Modeling with a Detailed SiC DMOS Parameter Extraction Methodology – Dr. Bogdan Tudor\, Head of Modeling\, Silvaco​\n\n\n1:00 PM\nLUNCH BREAK\n\n\n\n\n\n\nTime\nIC Design Track (EDA and IP)\n\n\n2:00 PM\nEDA and IP Updates – Dan Fitzpatrick\, VP and GM of EDA Business Unit\, Silvaco – Ben Louie\, VP and GM of IP Business Unit\, Silvaco\n\n\n2:20 PM\nEDA Solutions for Physical Design of Discrete Power Devices – Stefano Pettazzi\, Staff Applications Engineer\, Silvaco​\n\n\n2:40 PM\nJivaro Pro Advanced Parasitic Reduction – Chung-Chun Chen\, Director of Analog Design\, Silicon Creations ​\n\n\n3:00 PM\nUsing Viso to Investigate\, Analyze and Solve Advanced Parasitics Issues – Carlos Berlitz\, Corporate Applications Engineer\, Silvaco\n\n\n3:15 PM\nStandard Cells Characterization Challenges and Improvement – Siti Mariyam\, IP Design Enablement\, SilTerra\n\n\n3:35 PM\nLow Voltage Standard Cell Operation at 3nm – Fernando Carrion\, R&D Engineer\, Silvaco\n\n\n4:00 PM\nAdvanced Node Library Development with Cello FinFET – Felipe Bortolon\, Engineering Manager IP\, Silvaco​\n\n\n4:20 PM\nLDO and Bandgap References for Low Voltage Operation – Ahmad S. Mazumder\, Director of Engineering\, Silvaco – Shaikh A Shams\, Staff Engineer\, Silvaco\n\n\n4:35 PM\nIntroduction to CAN-XL\, Mauricio Brochi\, Director of Automotive IP\, Silvaco\n\n\n\n\n\n\n\nAgenda subject to change. \n\n\n\n\n\n\n\n\nShare this:\n Share on LinkedIn (Opens in new window)\n LinkedIn\n \n Share on X (Opens in new window)\n X\n \n Share on Facebook (Opens in new window)\n Facebook\n Like this:Like Loading... URL:https://marketingeda.com/event/silvaco-users-global-event-japan-2025/ LOCATION:CA CATEGORIES:EDA,IP,User Group ATTACH;FMTTYPE=image/jpeg:https://marketingeda.com/wp-content/uploads/Silvaco-SURGE-2025.jpg END:VEVENT BEGIN:VEVENT DTSTART;TZID=Europe/London:20250121T100000 DTEND;TZID=Europe/London:20250121T170000 DTSTAMP:20260426T160312 CREATED:20241217T174109Z LAST-MODIFIED:20241217T174512Z UID:8609-1737453600-1737478800@marketingeda.com SUMMARY:Silvaco UseRs Global Event - EMEA\, 2025 DESCRIPTION:Silvaco will hold its annual SURGE users event on January 21\, 2025. \nSURGE brings the TCAD\, EDA\, and IP communities together to discuss new technologies\, share users’ experiences\, and discover innovative techniques for advanced semiconductor design. \n\n\n\n\n\n\n\n\n\n\n\n\n\n\n\n\n\nAGENDA\n\n\n\n\n\n\n\nTime\nGeneral Session\n\n\n10:00\nKeynote – Babak Taheri\, Chief Executive Officer and Director\, Silvaco​\n\n\n10:15\nAI Takes EDA to the Next Level – Wally Rhines\, President and CEO of Cornami and Silvaco Board Member​\n\n\n10:30\nNanoHub Workforce Development – Dr. Peter Griffin\, Stanford University ​\n\n\n\n\n\n\nTime\nSEMICONDUCTOR PROCESS AND DEVICE TRACK (TCAD)\n\n\n10:45M\nTCAD Update – Dr. Eric Guichard\, SVP and GM of TCAD Business Unit\, Silvaco​\n\n\n11:00\nLow-temperature Behavior in Nanowire Transistors by Quantum Transport Simulation – Sanam Moslemi-Tabrizi\, Analog Engineer\, Ciena\n\n\n11:15\nMachine Learning for Multi-Scale Plasma Process Integration and Optimization – Associate Professor Dr. Lado Filipovic\, TU Vienna​\n\n\n11:30\nTBA – Sumeet Pandey\, Micron Technologies​\n\n\n11:45\nApplying Artificial Intelligence in Fab Technology Co-Optimization – Dr. Christian Caillat\, TCAD Senior Staff FAE\, Silvaco ​\n\n\n12:05\nDeveloping Silicon Carbide DMOSFETs: A Digital Twin Design Reference Flow – Dr. David Green\, TCAD Applications Engineer\, Silvaco​\n\n\n12:25\nPower Devices SPICE Modeling with a Detailed SiC DMOS Parameter Extraction Methodology – Dr. Bogdan Tudor\, Head of Modeling\, Silvaco​\n\n\n13:00\nLUNCH BREAK​\n\n\n\n\n\n\nTime\nIC Design Track (EDA and IP)​​\n\n\n14:00\nEDA and IP Updates – Dan Fitzpatrick\, VP and GM of EDA Business Unit\, Silvaco – Ben Louie\, VP and GM of IP Business Unit\, Silvaco​\n\n\n14:20\nEDA Solutions for Physical Design of Discrete Power Devices – Stefano Pettazzi\, Staff Applications Engineer\, Silvaco​\n\n\n14:40\nJivaro Pro Advanced Parasitic Reduction – Chung-Chun Chen\, Director of Analog Design\, Silicon Creations ​\n\n\n15:00\nUsing Viso to Investigate\, Analyze and Solve Advanced Parasitics Issues – Carlos Berlitz\, Corporate Applications Engineer\, Silvaco\n\n\n15:15\nStandard Cells Characterization Challenges and Improvement – Siti Mariyam\, IP Design Enablement\, SilTerra​\n\n\n15:35\nLow Voltage Standard Cell Operation at 3nm – Fernando Carrion\, R&D Engineer\, Silvaco​\n\n\n16:00\nAdvanced Node Library Development with Cello FinFET – Felipe Bortolon\, Engineering Manager IP\, Silvaco​\n\n\n16:20\nLDO and Bandgap References for Low Voltage Operation – Ahmad S. Mazumder\, Director of Engineering\, Silvaco – Shaikh A Shams\, Staff Engineer\, Silvaco​\n\n\n16:35\nIntroduction to CAN-XL\, Mauricio Brochi\, Director of Automotive IP\, Silvaco\n\n\n\n\n\n\n\nAgenda subject to change. \n\n\n\n\n\n\n\n\nShare this:\n Share on LinkedIn (Opens in new window)\n LinkedIn\n \n Share on X (Opens in new window)\n X\n \n Share on Facebook (Opens in new window)\n Facebook\n Like this:Like Loading... URL:https://marketingeda.com/event/silvaco-users-global-event-emea-2025/ LOCATION:CA CATEGORIES:EDA,IP,User Group ATTACH;FMTTYPE=image/jpeg:https://marketingeda.com/wp-content/uploads/Silvaco-SURGE-2025.jpg END:VEVENT BEGIN:VEVENT DTSTART;TZID=Asia/Hong_Kong:20250117T130000 DTEND;TZID=Asia/Hong_Kong:20250117T170000 DTSTAMP:20260426T160312 CREATED:20241217T173838Z LAST-MODIFIED:20241217T174747Z UID:8606-1737118800-1737133200@marketingeda.com SUMMARY:Silvaco UseRs Global Event - China\, 2025 DESCRIPTION:We sincerely invite you to attend the annual Silvaco Global User Conference – SURGE. This year’s SURGE China will be held online from 13:00 to 17:00 Beijing time on Friday\, January 17\, 2025. \nSURGE aims to provide a sustainable learning and exchange platform for global customers to share the latest technologies and user experience in the fields of TCAD\, EDA and IP\, and explore innovative technologies for advanced semiconductor design. \nLucky Draw: \nThe event has a lucky draw session\, and we have carefully prepared prizes. All users participating online have the chance to win! \n\n\nEvent Schedule\n\n\n\n\n\n\n\ntime\nMain venue\n\n\n13:00\nCEO Speech – Babak Taheri\, Silvaco\, CEO and Board Member​\n\n\n13:15\nHow AI will take EDA to new heights – Wally Rhines\, President and CEO of Cornami\, Board Member of Silvaco\n\n\n13:30\nSpeech Topic – Sumeet Pandey\, Micron Technologies\n\n\n13:45\nLucky draw and rest\n\n\n\n\n\n\ntime\nSemiconductor Process and Devices Session\n\n\n14:15\nTCAD Update – Dr. Eric Guichard\, Silvaco Vice President and General Manager of TCAD Division\n\n\n14:30\nStudying Low-Temperature Properties of Nanowire Transistors with Quantum Transport Simulation – Sanam Moslemi-Tabrizi\, Analog Engineer\, Ciena\n\n\n14:45\nMachine Learning for Multiscale Plasma Process Integration and Optimization – Dr. Lado Filipovic\, Associate\n\n\n15:00\nSpeech topic – Dr. Gao Peixiong\, CanSemi\, TCAD Simulation Manager\n\n\n15:15\nApplying Artificial Intelligence in Fab Technology Co-Optimization – Dr. Christian Caillat\, TCAD Application Engineer\n\n\n15:35\nPhysics and AI-based digital twins to accelerate SiC power device design optimization and manufacturing – Dr. David Green\, Silvaco\n\n\n15:55\nPower Device SPICE Modeling – Study on SiC DMOS Parameter Extraction Method – Dr. Bogdan Tudor\, Silvaco\, Modeling Leader​\n\n\n16:15\nEDA Solutions for Power Device Physical Design – Stefano Pettazzi\, Silvaco\, Application Engineer\n\n\n16:30\nLucky Draw and Closing\n\n\n\n\n\n\ntime\nIC Design Session\n\n\n14:15\nEDA and IP Updates – Dan Fitzpatrick\, Silvaco\, Vice President and General Manager of the EDA Division – Ben Louie\, Silvaco\, Vice President and General Manager\n\n\n14:35\nJivaro Pro Advanced Parasitic Reduction – Silicon Creation​\n\n\n14:55\nUsing Viso to Explore\, Analyze\, and Solve Advanced Parasitic Problems – Carlos Berlitz\, Applications Engineer\, Silvaco\n\n\n15:10\nChallenges and Improvements in Characterization of Standard Cell Libraries – Siti Mariyam\, Senior IP Engineer\n\n\n15:30\nLow Voltage Standard Cell Library Design at 3nm – Fernando Carrion\, Silvaco\, R&D Engineer\n\n\n15:55\nAdvanced Node Cell Library Development Using Cello FinFET – Felipe Bortolon\, Silvaco\, Engineering Manager​\n\n\n16:15\nLDO and Bandgap Benchmarks for Low Voltage Design – Ahmad S. Mazumder\, Shaikh A Shams\, Silvaco\n\n\n16:30\nIntroduction to CAN-XL Automotive Bus IP – Mauricio Brochi\, Silvaco\, Director of Automotive IP\n\n\n16:45\nLucky Draw and Closing\n\n\n\n\n\n\n\n\n\n\n*Please refer to the schedule announced on the day of the event. \n\n\n\n\n\nShare this:\n Share on LinkedIn (Opens in new window)\n LinkedIn\n \n Share on X (Opens in new window)\n X\n \n Share on Facebook (Opens in new window)\n Facebook\n Like this:Like Loading... URL:https://marketingeda.com/event/silvaco-users-global-event-china-2025/ LOCATION:CA CATEGORIES:EDA,IP,User Group ATTACH;FMTTYPE=image/jpeg:https://marketingeda.com/wp-content/uploads/Silvaco-SURGE-2025.jpg END:VEVENT BEGIN:VEVENT DTSTART;TZID=America/Los_Angeles:20250115T090000 DTEND;TZID=America/Los_Angeles:20250115T160000 DTSTAMP:20260426T160312 CREATED:20241217T173045Z LAST-MODIFIED:20241217T173045Z UID:8603-1736931600-1736956800@marketingeda.com SUMMARY:Silvaco UseRs Global Event - USA\, 2025 DESCRIPTION:Silvaco will hold its annual SURGE users event on January 15\, 2025.  \nSURGE brings the TCAD\, EDA\, and IP communities together to discuss new technologies\, share users’ experiences\, and discover innovative techniques for advanced semiconductor design. \nEveryone that registers will be entered into a drawing to win one of 2 pairs of Apple AirPods Pro 2. \nAll attendees will be entered into a drawing to win one Apple iPad Air 11″ M2. \n\n\n\n\n\n\n \n\n\n\n\n\n\n\n\n\n\n\n\n\n\n\n\nAGENDA\n\n\n\n\n\n\n\nTime\nGeneral Session\n\n\n9:00 AM\nKeynote – Babak Taheri\, Chief Executive Officer and Director\, Silvaco​\n\n\n9:15 AM​\nAI Takes EDA to the Next Level – Wally Rhines\, President and CEO of Cornami and Silvaco Board Member​\n\n\n9:30 AM\nNanoHub Workforce Development – Dr. Peter Griffin\, Stanford University ​\n\n\n\n\n\n\nTime\nSEMICONDUCTOR PROCESS AND DEVICE TRACK (TCAD)\n\n\n9:45 AM\nTCAD Update – Dr. Eric Guichard\, SVP and GM of TCAD Business Unit\, Silvaco​\n\n\n10:00 AM​\nLow-temperature Behavior in Nanowire Transistors by Quantum Transport Simulation – Sanam Moslemi-Tabrizi\, Analog Engineer\, Ciena\n\n\n10:15 AM​\nMachine Learning for Multi-Scale Plasma Process Integration and Optimization – Associate Professor Dr. Lado Filipovic\, TU Vienna​\n\n\n10:30 AM​\nTBA – Sumeet Pandey\, Micron Technologies​\n\n\n10:45 AM​\nApplying Artificial Intelligence in Fab Technology Co-Optimization – Dr. Christian Caillat\, TCAD Senior Staff FAE\, Silvaco ​\n\n\n11:05 AM​\nDeveloping Silicon Carbide DMOSFETs: A Digital Twin Design Reference Flow – Dr. David Green\, TCAD Applications Engineer\, Silvaco​\n\n\n11:25 AM​\nPower Devices SPICE Modeling with a Detailed SiC DMOS Parameter Extraction Methodology – Dr. Bogdan Tudor\, Head of Modeling\, Silvaco​\n\n\n12:00 PM​\nLUNCH BREAK​\n\n\n\n\n\n\nTime\nIC Design Track (EDA and IP)​​\n\n\n1:00 PM\nEDA and IP Updates – Dan Fitzpatrick\, VP and GM of EDA Business Unit\, Silvaco – Ben Louie\, VP and GM of IP Business Unit\, Silvaco​\n\n\n1:20 PM\nEDA Solutions for Physical Design of Discrete Power Devices – Stefano Pettazzi\, Staff Applications Engineer\, Silvaco​\n\n\n1:40 PM\nJivaro Pro Advanced Parasitic Reduction – Chung-Chun Chen\, Director of Analog Design\, Silicon Creations ​\n\n\n2:00 PM\nUsing Viso to Investigate\, Analyze and Solve Advanced Parasitics Issues – Carlos Berlitz\, Corporate Applications Engineer\, Silvaco\n\n\n2:15 PM\nStandard Cells Characterization Challenges and Improvement – Siti Mariyam\, IP Design Enablement\, SilTerra​\n\n\n2:35 PM\nLow Voltage Standard Cell Operation at 3nm – Fernando Carrion\, R&D Engineer\, Silvaco​\n\n\n3:00 PM\nAdvanced Node Library Development with Cello FinFET – Felipe Bortolon\, Engineering Manager IP\, Silvaco​\n\n\n3:20 PM\nLDO and Bandgap References for Low Voltage Operation – Ahmad S. Mazumder\, Director of Engineering\, Silvaco – Shaikh A Shams\, Staff Engineer\, Silvaco​\n\n\n3:35 PM\nIntroduction to CAN-XL\, Mauricio Brochi\, Director of Automotive IP\, Silvaco\n\n\n\n\n\n\n\nAgenda subject to change. \n\n\n\n\n\n\n\n\nShare this:\n Share on LinkedIn (Opens in new window)\n LinkedIn\n \n Share on X (Opens in new window)\n X\n \n Share on Facebook (Opens in new window)\n Facebook\n Like this:Like Loading... URL:https://marketingeda.com/event/silvaco-users-global-event-usa-2025/ LOCATION:CA CATEGORIES:EDA,IP,User Group ATTACH;FMTTYPE=image/jpeg:https://marketingeda.com/wp-content/uploads/Silvaco-SURGE-2025.jpg END:VEVENT BEGIN:VEVENT DTSTART;TZID=America/Los_Angeles:20241210T183000 DTEND;TZID=America/Los_Angeles:20241210T203000 DTSTAMP:20260426T160312 CREATED:20241121T224138Z LAST-MODIFIED:20241121T224138Z UID:8520-1733855400-1733862600@marketingeda.com SUMMARY:Synopsys TCAD Winter Reception DESCRIPTION:Join us in person at the Synopsys TCAD Winter Reception on December 10\, 2024. You have a chance to meet with our executives and product experts to learn about the latest insights on how Synopsys TCAD products can unleash the power of smart technology modeling – from atoms to circuits. Sign up and learn about the application of Synopsys TCAD solutions to accelerate the research\, development\, and optimization of semiconductor technologies. \nVenue: Hotel Nikko\, 222 Mason St\, San Francisco\, CA 94102 (across the IEDM Conference @ Hilton SF Union Square)\nRoom: Peninsula\, 25th floor\nRSVP: By Dec 6\, 2024 \nShare this:\n Share on LinkedIn (Opens in new window)\n LinkedIn\n \n Share on X (Opens in new window)\n X\n \n Share on Facebook (Opens in new window)\n Facebook\n Like this:Like Loading... URL:https://marketingeda.com/event/synopsys-tcad-winter-reception/ LOCATION:Hotel Nikko\, 222 Mason Street\, San Francisco\, CA\, United States CATEGORIES:EDA,User Group ATTACH;FMTTYPE=image/jpeg:https://marketingeda.com/wp-content/uploads/Synopsys-December-10-2024.jpg END:VEVENT BEGIN:VEVENT DTSTART;TZID=America/Los_Angeles:20241022T080000 DTEND;TZID=America/Los_Angeles:20241023T170000 DTSTAMP:20260426T160312 CREATED:20240725T182742Z LAST-MODIFIED:20240725T182818Z UID:8184-1729584000-1729702800@marketingeda.com SUMMARY:Jasper User Group San Jose 2024 DESCRIPTION:The CadenceCONNECT: Jasper User Group San Jose will be held in person on October 22 – 23 at the Cadence San Jose campus. This interactive\, in-depth technical conference connects designers\, verification engineers\, and engineering managers from around the world to share the latest design and verification practices based on Cadence’s Jasper formal verification technologies and methodologies. \nShare Your Story\nWe’re seeking your unique perspectives on using Jasper technologies and methodologies to achieve better results. If your presentation is accepted\, you can: \n\nIncrease industry visibility for you and your team’s field of expertise\nImprove and fine-tune your methods with insights from colleagues across the industry\nEarn wide acclaim with a Best Presentation Award nomination\n\n  \nPlease visit the website for further information. Accepted authors are expected to attend the conference and present in person. The deadline for abstract submission is 5:00pm PDT on Monday\, August 26\, 2024. \nConference registration will open at the end of August. We look forward to meeting you at Jasper User Group San Jose 2024! \nQuestions? Please email us. \nShare this:\n Share on LinkedIn (Opens in new window)\n LinkedIn\n \n Share on X (Opens in new window)\n X\n \n Share on Facebook (Opens in new window)\n Facebook\n Like this:Like Loading... URL:https://marketingeda.com/event/jasper-user-group-san-jose/ LOCATION:Cadence Design Systems\, Bldg 10\, 2655 Seeley Avenue\, San Jose\, CA\, United States CATEGORIES:EDA,User Group ATTACH;FMTTYPE=image/jpeg:https://marketingeda.com/wp-content/uploads/Jasper-October-22-23-2024.jpg END:VEVENT BEGIN:VEVENT DTSTART;TZID=America/Los_Angeles:20241017T080000 DTEND;TZID=America/Los_Angeles:20241017T170000 DTSTAMP:20260426T160312 CREATED:20240806T194900Z LAST-MODIFIED:20240806T194900Z UID:8209-1729152000-1729184400@marketingeda.com SUMMARY:OSMOSIS 2024 DESCRIPTION:Elevate your success with osmosis 2024\nThe annual osmosis event is a dynamic platform for exchanging successes achieved through applying formal techniques to overcome verification challenges. It offers a unique opportunity to connect and engage with our accomplished research and development (R&D) experts and participants. If you possess a compelling achievement narrative\, we invite you to unveil it at osmosis. \nYou will benefit from increased industry visibility as a subject matter expert\, and the conversations that follow may help you and others improve formal-based verification solutions. \n\n\nAbstract guidelines\nCraft a concise narrative outlining the essential bits of your success story\, encompassing: \n\nthe intricate problem you addressed\nrationale for employing formal technology-based solutions\ntangible outcomes\, ideally quantifiable\nkey learnings and findings\n\nFor utmost impact\, please limit your abstract to a single page\, front and back. \nInclude diagrams and code examples if desired. \nIf you have questions or need guidance in refining your narrative\, please reach out to us at osmosis.sisw@siemens.com \n\n\nSchedules and processes\nThe deadline for abstract submissions is 6 p.m. Central EU time on Mon.\, Sept. 23\, 2024. \nSubmissions will be evaluated as they are received. As we select abstracts\, we will begin working with the authors on their presentations. If we fill the agenda early\, we’ll close submissions. \n\n\nWe look forward to receiving your abstracts and seeing you in Munich! \n\n\nOn-demand presentations\nCheck out past\, on-demand presentations. \n\nOsmosis Aerospace and Defense – April 2024\nOsmosis Aerospace and Defense – 2023\n\n\nShare this:\n Share on LinkedIn (Opens in new window)\n LinkedIn\n \n Share on X (Opens in new window)\n X\n \n Share on Facebook (Opens in new window)\n Facebook\n Like this:Like Loading... URL:https://marketingeda.com/event/osmosis-2024/ LOCATION:Holiday Inn City Center\, Hochstraße 3\, Munich\, 81669\, Germany CATEGORIES:EDA,User Group ATTACH;FMTTYPE=image/jpeg:https://marketingeda.com/wp-content/uploads/OSMOSIS-2024-1.jpg END:VEVENT BEGIN:VEVENT DTSTART;TZID=America/Los_Angeles:20241003T090000 DTEND;TZID=America/Los_Angeles:20241003T170000 DTSTAMP:20260426T160312 CREATED:20240911T225059Z LAST-MODIFIED:20240911T225246Z UID:8328-1727946000-1727974800@marketingeda.com SUMMARY:VC Formal Special Interest Group DESCRIPTION:Register for the Synopsys VC Formal Special Interest Group (SIG) event today. This event provides an opportunity for users\, managers\, and enthusiasts to stay connected with the latest formal verification innovations\, techniques and methodologies. \nIndustry leaders such as Amazon\, Black Sesame\, Microsoft\, NVIDIA\, Samsung\, and Untether AI will share their experiences with the latest formal verification technologies. Topics that will be covered include strategies for achieving formal convergence\, exploring formal methodologies used for RISC-V verification\, and the integration of VC Formal with generative AI functionalities – which offer the potential to automate the creation of formal verification testbenches. \nKeynote Session \n\nThe Impact of LLMs on Formal Verification \nExplore how LLMs can transform formal verification\, reducing manual effort and improving results. We’ll discuss current benchmarks and future goals for deploying LLMs to enhance formal verification processes. \nPresented by Syed Suhaib\, NVIDIA \nShare this:\n Share on LinkedIn (Opens in new window)\n LinkedIn\n \n Share on X (Opens in new window)\n X\n \n Share on Facebook (Opens in new window)\n Facebook\n Like this:Like Loading... URL:https://marketingeda.com/event/vc-formal-special-interest-group/ LOCATION:Santa Clara Marriott\, 2700 Mission College Blvd\, Santa Clara\, CA\, 95054\, United States CATEGORIES:EDA,User Group ATTACH;FMTTYPE=image/jpeg:https://marketingeda.com/wp-content/uploads/VC-Formal-SIG-October-3-2024.jpg END:VEVENT BEGIN:VEVENT DTSTART;TZID=Asia/Taipei:20240822T080000 DTEND;TZID=Asia/Taipei:20240822T170000 DTSTAMP:20260426T160312 CREATED:20240821T171827Z LAST-MODIFIED:20240821T171827Z UID:8262-1724313600-1724346000@marketingeda.com SUMMARY:CadenceCONNECT Taiwan 2024 DESCRIPTION:CadenceCONNECT Taiwan event will introduce you to optimized design methodologies for electronics system applications. The event brings together Cadence technology users\, developers\, and industry experts for networking\, sharing best practices on critical design and verification issues and discovering new techniques for designing advanced silicon\, SoCs\, and systems. Don’t miss this opportunity to learn from industry experts and connect with peers in the electronics community. Registration is now open\, and seats are limited. \n\n\n\n\nWe introduce a new CadenceCONNECT Taiwan conference that encompasses a range of technology and vertical topics. \nCadenceCONNECT Taiwan 2024 will be held on August 22 at the Sheraton Hsinchu Hotel. CadenceCONNECT Taiwan provides a forum to share best practices on critical design implementation and verification issues\, and to discover inspiring new techniques for realizing advanced silicon\, system-on-chip (SoC ) designs\, and systems in different vertical markets. This event is organized to inspire and network with emerging technical experts to continue creating revolutionary possibilities with semiconductors. \nIn the face of today’s fierce international competition\, increasingly complex process development and application challenges\, design can not only realize creativity\, but also shape future innovation. Cadence has been based in Taiwan for more than 35 years and has always been the best assistant to local customers and partners. It will continue to work hard for electronic design innovation. This year\, the CadenceCONNECT Taiwan conference will be grandly presented at the Sheraton Hsinchu Hotel on August 22 (Thursday)\, providing an interactive platform to invite Cadence customers\, partners and industry elites to gather\, propose the best policies and case sharing for today’s electronic design\, and deeply discuss and exchange ideas for the future of Taiwan’s semiconductors\, and help and prosper together! \nThank you for your eagerness to register. Registration is now full! \nEvent Info\nEvent Date/Time: August 22\, 2024 (Thursday) 09:00-17:30PM \nVenue: 3F\, Sheraton Hsinchu Hotel \n\n\n\n\n\n\n\n\n\n\nKeynotes\nBe inspired by visionary keynotes as they discuss the latest trends and breakthrough technologies shaping the AI ​​era. \nChin-Chi Teng\nSenior Vice President and General Manager\nDigital & Signoff Group\, Cadence\n\n\n\nKS Pua\nFounder and CEO\nPhison Electronics\n\n\n\nAlbert Kuo\nHead of Automotive Business Unit\nRealtek\n\n\n\n\nCY Chang\nHardware and Operations Vice President\nMetanoia\n\n\n\nBen Gu\nCorporate Vice President\, Multi-Physics System Analysis Group\nCadence\n\n\nEunice Chiu\nVice President and General Manager Taiwan\nNVIDIA\n\n\n\nShare this:\n Share on LinkedIn (Opens in new window)\n LinkedIn\n \n Share on X (Opens in new window)\n X\n \n Share on Facebook (Opens in new window)\n Facebook\n Like this:Like Loading... URL:https://marketingeda.com/event/cadenceconnect-taiwan-2024/ LOCATION:Sheraton Hsinchu Hotel\, No. 265號\, E Section 1\, Guangming 6th Rd\, Zhubei City\, Taiwan CATEGORIES:EDA,IP,User Group ATTACH;FMTTYPE=image/jpeg:https://marketingeda.com/wp-content/uploads/Cadence-August-22-2024.jpg END:VEVENT BEGIN:VEVENT DTSTART;TZID=Asia/Kolkata:20240718T080000 DTEND;TZID=Asia/Kolkata:20240718T170000 DTSTAMP:20260426T160312 CREATED:20240712T024146Z LAST-MODIFIED:20240712T024146Z UID:8145-1721289600-1721322000@marketingeda.com SUMMARY:SNUG India 2024 DESCRIPTION:Since 1991\, the Synopsys Users Group (SNUG) has represented a global design community focused on innovating from Silicon to Software. Today\, as the electronics industry’s largest user conference\, SNUG brings together over 12\,000 Synopsys tool and technology users across North America\, Europe\, Asia\, and Japan. In addition to peer-reviewed technical presentations and insightful keynotes from industry leaders\, SNUG provides a unique opportunity to connect with Synopsys executives\, design ecosystem partners\, and members of your design community. \nJoin your fellow engineers at SNUG to hear practical information you can use on your current projects and the inspiration to create in the Era of Pervasive Intelligence. \nSNUG is restricted to Synopsys customers only\, and offered at no charge. \n\n\n\n\n\n\n\n\n\nWhy Attend? \n\n\n\n\n\n\n\n\n\n\n\n\n\n\n\n\n\n\nAttend tutorials for the latest advancements in Synopsys technology \n\n\n\n\n\n\n\n\n\n\n\n\nGain practical knowledge you can apply today \n\n\n\n\n\n\n\n\n\n\n\n\n\n\nChoose from among 7 Technical Tracks and see other users showcase best practices for design & verification challenges: Analog/Mixed-Signal Design and Simulation\, Digital Design Implementation\, IC Verification Software\, Signoff\, Silicon Test and Lifecycle Management\, Systems & IP\, and Verification Hardware \n\n\n\n\n\n\n\n\n\n\n\n\nHear users showcase best practices for design  & verification challenges \n\n\n\n\n\n\n\n\n\nShare this:\n Share on LinkedIn (Opens in new window)\n LinkedIn\n \n Share on X (Opens in new window)\n X\n \n Share on Facebook (Opens in new window)\n Facebook\n Like this:Like Loading... URL:https://marketingeda.com/event/snug-india-2024/ LOCATION:Sheraton Grand Bengaluru Whitefield\, Bengaluru\, India CATEGORIES:EDA,IP,User Group ATTACH;FMTTYPE=image/jpeg:https://marketingeda.com/wp-content/uploads/SNUG-India-2024.jpg END:VEVENT BEGIN:VEVENT DTSTART;TZID=Europe/Berlin:20240610T080000 DTEND;TZID=Europe/Berlin:20240611T170000 DTSTAMP:20260426T160312 CREATED:20240503T162031Z LAST-MODIFIED:20240503T162031Z UID:7940-1718006400-1718125200@marketingeda.com SUMMARY:SNUG Europe 2024 DESCRIPTION:Connecting the Synopsys User Community\nSince 1991\, the Synopsys Users Group (SNUG) has represented a global design community focused on innovating from Silicon to Software. Today\, as the electronics industry’s largest user conference\, SNUG brings together over 12\,000 Synopsys tool and technology users across North America\, Europe\, Asia\, and Japan. In addition to peer-reviewed technical presentations and insightful keynotes from industry leaders\, SNUG provides a unique opportunity to connect with Synopsys executives\, design ecosystem partners\, and members of your design community. \nJoin your fellow engineers at SNUG to hear practical information you can use on your current projects and the inspiration to create Smart Everything. \n\n\n\n\n\nTechnical Committee\n\nSNUG thanks the members of the Technical Committee who volunteer their time and expertise to support SNUG’s technical quality and deliver the benefit of their perspective to the users of Synopsys tools and technology.\n\n\n\n\n\n\n\n\n\n\n\n\n\n\nTechnical Committee Chair: \n\n\nFrank Poppen\, NXP Semiconductors \n\n\n\n\n\n\n\n\n\n\n\n\n\n\n\n\n\n\n\n\n\nCommittee Members: \nAlessandro Valerio\, STMicroelectronics \nAndreas Kuesel\, Micron Semiconductor GmbH \nAnshuman Anand\, Infineon \nCecile Specq\, STMicroelectronics \nClaus Kuntzsch\, University of Applied Sciences Nuremberg \nDidier Maurer\, IC’ALPS \nEnrico Castaldo\, STMicroelectronics \nFarid Labib\, GLOBALFOUNDRIES \nGiuseppe Notarangelo\, STMicroelectronics \nKarsten Matt\, GLOBALFOUNDRIES \nLars Graversen\, Demant (Oticon) \nLaurent Besson\, Easii IC \n\n\n\n\n\n\n\n\n\n\n\n\n\n\nMajid Ghameshlu\, Siemens AG (Austria) \nManfred Thanner\, NXP Semiconductors \nNathalie Meloux\, STMicroelectronics \nPeter Grove\, Renesas \nPierluigi Daglio\, STMicroelectronics \nRalph Goergen\, NXP Semiconductors \nRobert Siegmund\, GLOBALFOUNDRIES \nRoberto Anelli\, Nordic Semiconductor \nStefan Scharfenberg\, NXP \nSylvie Pierunek\, STMicroelectronics \nTarun Chawla\, STMicroelectronics \nThomas Buerner\, Nokia \nThomas Haase\, Renesas \n\n\n\n\n\n\n\n\n\n\n\nShare this:\n Share on LinkedIn (Opens in new window)\n LinkedIn\n \n Share on X (Opens in new window)\n X\n \n Share on Facebook (Opens in new window)\n Facebook\n Like this:Like Loading... URL:https://marketingeda.com/event/snug-europe-2024/ LOCATION:Hilton Munich Airport\, Terminalstraße Mitte 20\, 85356 München-Flughafen\, Munich\, Germany CATEGORIES:EDA,IP,User Group ATTACH;FMTTYPE=image/jpeg:https://marketingeda.com/wp-content/uploads/SNUG-Europe-2024.jpg END:VEVENT BEGIN:VEVENT DTSTART;TZID=Europe/Berlin:20240507T090000 DTEND;TZID=Europe/Berlin:20240507T220000 DTSTAMP:20260426T160312 CREATED:20240429T170320Z LAST-MODIFIED:20240429T170320Z UID:7928-1715072400-1715119200@marketingeda.com SUMMARY:User2User Europe 2024 DESCRIPTION:User2User is the perfect opportunity to learn\, share and network with fellow technical experts who design leading-edge products using Siemens EDA tools. \nDedicated to end-users of Siemens EDA solutions\, this conference is free to attend and includes innovative keynotes from industry leaders\, enriching technical sessions as well as a chance to network with colleagues and peers. \nThe full programme includes papers on these topics\n\nDesign For Test & Embedded Analytics\nElectronic System Design/PCB Design analysis and manufacturing\nFunctional Design & Verification\nHardware Assisted Verification\nHigh Level Synthesis: Digital design in C++/SystemC\nCustom IC Verification\nIC Backend\nSemiconductor packaging design\, analysis and manufacturing\n\nKeynotes\nEnabling imagination – An integrated approach to system design – Mike Ellow \nMike Ellow is the Executive Vice President of Electronic Design Automation (EDA) Global Sales Services and Customer Support for Siemens in North America. \nDelivering Silicon at Cloud Scale – Ronen Laviv \nRonen Laviv is the Enterprise Account Manager and EDA Sales Consultant at Amazon Web Services (AWS) based in Israel. \nTechnical breakouts\n\nIC Backend Track 1\n\nImproving the accuracy of Design for Manufacturability (DFM) sign-off checks with machine learning\nSignoff with Calibre as platform independent application\nUtilizing Calibre Tools for Chipfinishing within a Markefile\n\n\nIC Backend Track 2\n\nPERC-LDL Auto Waivers flow applied to Voltage Dependent Rules in BCD technologies\nMission IR Possible – Full Chip IR Drop Analysis of CMOS Cine-Image Sensor with Mpower\n\n\nCustom IC Verification\n\nSymphony Pro enablement in STMicroelectronics SmartPower Technologies\nHow AWS cloud compute helps scale custom IC verification workloads\nPLL Design and Simulation using the Advanced SPICE technology\nAccelerating verification of high frequency PLLs for Wireless Application in a Smarter World\n\n\nDesign for Test & Embedded Analytics\n\nAdvancing DFT with the Power of AI: Grand challenges\n\n\n\nShare this:\n Share on LinkedIn (Opens in new window)\n LinkedIn\n \n Share on X (Opens in new window)\n X\n \n Share on Facebook (Opens in new window)\n Facebook\n Like this:Like Loading... URL:https://marketingeda.com/event/user2user-europe-2024/ LOCATION:Hilton Munich Airport\, Terminalstraße Mitte 20\, 85356 München-Flughafen\, Munich\, Germany CATEGORIES:EDA,IP,User Group ATTACH;FMTTYPE=image/jpeg:https://marketingeda.com/wp-content/uploads/User2User-Europe-2024.jpg END:VEVENT BEGIN:VEVENT DTSTART;TZID=America/Los_Angeles:20240425T090000 DTEND;TZID=America/Los_Angeles:20240425T170000 DTSTAMP:20260426T160312 CREATED:20240423T003845Z LAST-MODIFIED:20240423T003845Z UID:7893-1714035600-1714064400@marketingeda.com SUMMARY:Siemens User2User Verification Forum 2024 India DESCRIPTION:Join us at the Siemens User2User Verification Forum 2024 in India next week! \nGain insights on Smart Verification – Using AI in Functional Verification and learn best practices in design and verification flows that can speed up your ASIC and FPGA design & verification cycle.\nDon’t miss the chance to leverage AI and ML based flows in some of the technologies. \nHyderabad on April 23\, 2024\, and Bangalore on April 25\, 2024\, at 9AM IST. \nShare this:\n Share on LinkedIn (Opens in new window)\n LinkedIn\n \n Share on X (Opens in new window)\n X\n \n Share on Facebook (Opens in new window)\n Facebook\n Like this:Like Loading... URL:https://marketingeda.com/event/siemens-user2user-verification-forum-2024-india-2/ LOCATION:Hotel Radission Blu\, Marathalli ORR\, 90/4 Outer Ring Road\, Bengaluru\, India CATEGORIES:EDA,User Group ATTACH;FMTTYPE=image/jpeg:https://marketingeda.com/wp-content/uploads/Siemens-User2User-Verification-India-2024.jpg END:VEVENT BEGIN:VEVENT DTSTART;TZID=Indian/Maldives:20240423T090000 DTEND;TZID=Indian/Maldives:20240423T170000 DTSTAMP:20260426T160312 CREATED:20240423T003434Z LAST-MODIFIED:20240423T003434Z UID:7889-1713862800-1713891600@marketingeda.com SUMMARY:Siemens User2User Verification Forum 2024 India DESCRIPTION:Join us at the Siemens User2User Verification Forum 2024 in India next week! \nGain insights on Smart Verification – Using AI in Functional Verification and learn best practices in design and verification flows that can speed up your ASIC and FPGA design & verification cycle.\nDon’t miss the chance to leverage AI and ML based flows in some of the technologies. \nHyderabad on April 23\, 2024\, and Bangalore on April 25\, 2024\, at 9AM IST. \nShare this:\n Share on LinkedIn (Opens in new window)\n LinkedIn\n \n Share on X (Opens in new window)\n X\n \n Share on Facebook (Opens in new window)\n Facebook\n Like this:Like Loading... URL:https://marketingeda.com/event/siemens-user2user-verification-forum-2024-india/ LOCATION:Hyatt Place\, Banjara Hills\, Road no 1\, Banjara Hills\, Hyderabad\, India CATEGORIES:EDA,User Group ATTACH;FMTTYPE=image/jpeg:https://marketingeda.com/wp-content/uploads/Siemens-User2User-Verification-India-2024.jpg END:VEVENT BEGIN:VEVENT DTSTART;TZID=America/Los_Angeles:20240417T081500 DTEND;TZID=America/Los_Angeles:20240417T170000 DTSTAMP:20260426T160312 CREATED:20240306T181435Z LAST-MODIFIED:20240306T181435Z UID:7716-1713341700-1713373200@marketingeda.com SUMMARY:CadenceLIVE Silicon Valley 2024 DESCRIPTION:Join us for CadenceLIVE Silicon Valley 2024 on April 17 at the Santa Clara Convention Center. This annual user conference features peer presentations that offer solutions for today’s design challenges that will impact tomorrow’s products. \nCadenceLIVE brings users\, developers\, and industry experts together to connect\, share ideas\, and inspire design creativity. Attendees have the opportunity to view captivating keynotes\, attend engaging user presentations\, and interact with Cadence experts\, peers\, and our sponsors in the Designer Expo. \nRegister today to secure your spot. \n\n\nApril 17\, 2024 08:15\n\nRegistration\n\n\n\n\n\n\nApril 17\, 2024 09:00\n\nSession Tracks\n\n\n\n\n\n\nApril 17\, 2024 10:15\n\nKeynotes\n\n\n\n\n\n\nApril 17\, 2024 11:45\n\nDesigner Expo and Lunch\n\n\n\n\n\n\nApril 17\, 2024 13:15\n\nSession Tracks\n\n\n\n\n\n\nApril 17\, 2024 15:45\n\nClosing Keynote\n\n\n\n\n\n\nApril 17\, 2024 16:30\n\nDesigner Expo / Reception / Awards\n\n\n\nShare this:\n Share on LinkedIn (Opens in new window)\n LinkedIn\n \n Share on X (Opens in new window)\n X\n \n Share on Facebook (Opens in new window)\n Facebook\n Like this:Like Loading... URL:https://marketingeda.com/event/cadencelive-silicon-valley-2024/ LOCATION:Santa Clara Convention Center\, 5001 Great America Parkway\, Santa Clara\, CA\, 95054\, United States CATEGORIES:EDA,IP,User Group ATTACH;FMTTYPE=image/jpeg:https://marketingeda.com/wp-content/uploads/Cadence-April-17-2024.jpg END:VEVENT BEGIN:VEVENT DTSTART;TZID=America/Los_Angeles:20240403T080000 DTEND;TZID=America/Los_Angeles:20240404T170000 DTSTAMP:20260426T160312 CREATED:20240212T202640Z LAST-MODIFIED:20240212T202640Z UID:7607-1712131200-1712250000@marketingeda.com SUMMARY:Siemens EDA User2User Conference DESCRIPTION:Engineer a smarter future\, faster at Siemens EDA User2User Conference \nApril 3-4\, 2024 Santa Clara\, CA. \nJoin your colleagues from around the industry for a day of technical sessions\, networking\, keynote sessions\, labs and more. User2User is free of charge for Siemens EDA customers and includes sessions\, lunch\, and parking. \nTechnology tracks covering the latest from: \n• 3DIC/Chiplet Package Design \n• Aprisa Digital IC Implementation \n• Calibre Design Solutions & Power Integrity Analysis \n• Custom IC Verification \n• Functional Design and Verification \n• Hardware Assisted Verification \n• High-Level Synthesis/Verification & RTL Power Estimation/Optimization \n• Package/PCB Analysis & Verification \n• Tessent Test and Embedded Analytics Solutions \nNEW this year\, the option to attend a full day of training from our Learning Services team. \nWe are excited to offer a unique training opportunity on Wednesday\, April 3rd\, the day before User2User! Our experts will deliver curated material from our most sought-after courses in a condensed format. User2User attendees who participate in either class will also take home a free ODT subscription for the full self-paced training course to expand your knowledge on the topic and perform hands-on labs in our virtual cloud-enabled environment. Space is extremely limited\, so click below to learn how you can get into this User2User-exclusive! \nShare this:\n Share on LinkedIn (Opens in new window)\n LinkedIn\n \n Share on X (Opens in new window)\n X\n \n Share on Facebook (Opens in new window)\n Facebook\n Like this:Like Loading... URL:https://marketingeda.com/event/siemens-eda-user2user-conference/ LOCATION:Santa Clara Marriott\, 2700 Mission College Blvd\, Santa Clara\, CA\, 95054\, United States CATEGORIES:EDA,IP,User Group ATTACH;FMTTYPE=image/jpeg:https://marketingeda.com/wp-content/uploads/Siemens-April-3-4-2024.jpg END:VEVENT BEGIN:VEVENT DTSTART;TZID=America/Los_Angeles:20240320T080000 DTEND;TZID=America/Los_Angeles:20240321T170000 DTSTAMP:20260426T160312 CREATED:20240305T220415Z LAST-MODIFIED:20240305T220415Z UID:7710-1710921600-1711040400@marketingeda.com SUMMARY:SNUG Silicon Valley 2024 DESCRIPTION:Connecting the Synopsys User Community\nSNUG conferences have connected Synopsys global users for more than three decades. SNUG 2024 will once again provide a place where users and technical experts can meet\, network\, and share ideas about chip and system design. \nTechnical Committee\nSNUG thanks the members of the Technical Committee who volunteer their time and expertise to support SNUG’s technical quality and deliver the benefit of their perspective to the users of Synopsys tools and technology. \nTechnical Committee Chair: \nDon Mills\, Microchip \nCommittee Members: \nAnand Iyer\, Synopsys \nAndy Copperhall\, Independent \nAnwarul Hasan\, Independent \nBrian Kane\, Northrop Grumman \nBryan Morris\, Ciena \nChris Kiegle\, Marvell Semiconductor \nCliff Cummings\, Paradigm Works \nFirouzeh Nourkhalaj\, Synopsys \nGlen McDonnell\, Broadcom \nHongda Lu\, SARC \nJack Dong\, Intel \nJason Rziha\, Microchip \nJeff Montesano\, Meta \nJing Zhang\, Intel \nJohn Thomson\, NVIDIA \nJohn Wei\, Independent \nJon Colburn\, NVIDIA \nJT Longino\, Tesla \nKarthik Rajan\, Microchip \nLeah Clark\, Synopsys \nMark Sprague\, Intel \nNaveen Mysore\, Intel \nNeel Sonara\, Broadcom \nNitin Navale\, AMD \nOlivia Poon\, Marvell Semiconductor \nPinal Patel\, eInfochips \nRavikishore Gandikota\, NVIDIA \nRonald Goodstein\, Lockheed Martin \nRonald Kalim\, Intel \nSachin Parikh\, Broadcom \nSangeetha Chandran Sarala\, Micron \nSathappan Palaniappan\, Broadcom \nSaurabh Bhadoriya\, NVIDIA \nSavita Banerjee\, Meta \nShaiful Alam\, Intel \nStella Matarrese\, Synopsys \nTom Mahatdejkul\, Arm \nTony Todesco\, AMD \nUpasna Vishnoi\, Marvell Semiconductor \nVictoria Kolesov\, Intel \nZafar Hasan\, NVIDIA \nShare this:\n Share on LinkedIn (Opens in new window)\n LinkedIn\n \n Share on X (Opens in new window)\n X\n \n Share on Facebook (Opens in new window)\n Facebook\n Like this:Like Loading... URL:https://marketingeda.com/event/snug-silicon-valley-2024/ LOCATION:Santa Clara Convention Center\, 5001 Great America Parkway\, Santa Clara\, CA\, 95054\, United States CATEGORIES:EDA,IP,User Group ATTACH;FMTTYPE=image/jpeg:https://marketingeda.com/wp-content/uploads/SNG-Silicon-Valley-2024.jpg END:VEVENT BEGIN:VEVENT DTSTART;TZID=America/Los_Angeles:20240131T183000 DTEND;TZID=America/Los_Angeles:20240131T210000 DTSTAMP:20260426T160312 CREATED:20231212T173907Z LAST-MODIFIED:20231212T174026Z UID:7163-1706725800-1706734800@marketingeda.com SUMMARY:Signal & Power Integrity Special Interest Group DESCRIPTION:Dear SIPI Engineer\, \nAs a member of the engineering community\, you are invited to attend Synopsys Signal & Power Integrity Special Interest Group event taking place at Hilton Santa Clara. \nThis event is conveniently located across the street from the DesignCon 2024 Conference allowing you to participate in both. The Synopsys SIPI SIG event will provide the opportunity for networking and interactive discussion with other SIPI engineers to exchange ideas and strategies on signal and power integrity challenges and solutions. \nWe will offer Synopsys and partner product demonstrations during our cocktail hour\, followed by a sit-down dinner with invited guest speakers and conclude with a panel discussion. Stay to the end for a chance to win a raffle prize! \nWe are excited to see you in-person once again. Please be sure to reserve your spot today as seating is limited. \nShare this:\n Share on LinkedIn (Opens in new window)\n LinkedIn\n \n Share on X (Opens in new window)\n X\n \n Share on Facebook (Opens in new window)\n Facebook\n Like this:Like Loading... URL:https://marketingeda.com/event/signal-power-integrity-special-interest-group/ LOCATION:Hilton Santa Clara\, 4949 Great America Parkway\, Santa Clara\, CA\, United States CATEGORIES:EDA,IP,User Group ATTACH;FMTTYPE=image/jpeg:https://marketingeda.com/wp-content/uploads/Synopsys-January-31-2024.jpg END:VEVENT BEGIN:VEVENT DTSTART;TZID=Asia/Shanghai:20231208T080000 DTEND;TZID=Asia/Shanghai:20231208T170000 DTSTAMP:20260426T160312 CREATED:20230925T223711Z LAST-MODIFIED:20230925T223711Z UID:6883-1702022400-1702054800@marketingeda.com SUMMARY:Silvaco UseRs Global Event (SURGE) 2023 – China DESCRIPTION:Silvaco UseRs Global Events (SURGE) bring together users\, developers\, and industry experts of the EDA\, IP\, and TCAD communities to understand new semiconductor technologies\, innovative applications\, and techniques for realizing advanced designs. \nPresentations\nA variety of presentations will cover semiconductor device simulation\, circuit design and verification\, and IP design. Roadmaps and exciting technology updates will also be included. Discover how Silvaco solutions are used to realize silicon success in power devices\, displays\, memories\, automotive\, IoT\, high-performance computing\, and 5G/6G applications. \nKeynote Speakers and Panelists\nHear from industry leaders and visionaries who influence the global electronics marketplace. They will discuss trends in systems\, silicon\, and applications and share their thoughts on the design challenges and opportunities that face us today. \nShare this:\n Share on LinkedIn (Opens in new window)\n LinkedIn\n \n Share on X (Opens in new window)\n X\n \n Share on Facebook (Opens in new window)\n Facebook\n Like this:Like Loading... URL:https://marketingeda.com/event/silvaco-users-global-event-surge-2023-china/ LOCATION:CA CATEGORIES:EDA,IP,User Group ATTACH;FMTTYPE=image/jpeg:https://marketingeda.com/wp-content/uploads/Surge-2023.jpg END:VEVENT BEGIN:VEVENT DTSTART;TZID=America/Los_Angeles:20231205T090000 DTEND;TZID=America/Los_Angeles:20231205T164500 DTSTAMP:20260426T160312 CREATED:20231116T171938Z LAST-MODIFIED:20231116T171938Z UID:7104-1701766800-1701794700@marketingeda.com SUMMARY:Conformal User Group Conference 2023 and Technology Day DESCRIPTION:It’s time for our inaugural CadenceCONNECT: Conformal® User Group Conference and Technology Day held on December 5th at the Cadence San Jose campus. This interactive\, in-depth technical conference connects designers\, verification engineers\, and engineering managers to share the latest design and verification practices based on Cadence’s Conformal family of solutions including logical equivalence checking (LEC)\, low power static signoff and compare\, and automated functional ECOs. The conference will be held in person at the Cadence auditorium in San Jose\, CA. There a lot of exciting changes happening for Conformal\, so don’t miss this chance to both improve your productivity using the latest recommended technologies and hear about what’s coming next! \n\n\n\n\n\n\n\n\n\n\n\n\nEvent highlights include: \n\nCadence technical presentations on core Conformal product solutions and flows\nUser presentations on application of Conformal solutions on real world design challenges\nR&D vision from new Conformal R&D head Zhuo Li\nRoadmap discussions and new technology previews\nNetworking lunch and post-event reception\n\n\n\n\n\n\n\n\n\n\n\n\n\nKey technical topics for 2023: \n\nStreamlining logical equivalence for users of the Genus and Innovus solutions\nOptimized functional ECO setup and patch implementation\nNew IEEE1801 (UPF) static low power signoff and compare features and flow\nAI/ML enhancements inside Conformal and multi-run debug/analytics using the Cadence JedAI Platform\nFunctional safety implementation and EC\nArchitectural improvements for runtime and capacity\n\n\n\n\n\n\n\nShare this:\n Share on LinkedIn (Opens in new window)\n LinkedIn\n \n Share on X (Opens in new window)\n X\n \n Share on Facebook (Opens in new window)\n Facebook\n Like this:Like Loading... URL:https://marketingeda.com/event/conformal-user-group-conference-2023-and-technology-day/ LOCATION:Cadence Design Systems\, Bldg 10\, 2655 Seeley Avenue\, San Jose\, CA\, United States CATEGORIES:EDA,User Group ATTACH;FMTTYPE=image/jpeg:https://marketingeda.com/wp-content/uploads/Cadence-December-5-2023-1.jpg END:VEVENT BEGIN:VEVENT DTSTART;TZID=America/Los_Angeles:20231130T080000 DTEND;TZID=America/Los_Angeles:20231130T170000 DTSTAMP:20260426T160312 CREATED:20231012T182718Z LAST-MODIFIED:20231012T182718Z UID:6946-1701331200-1701363600@marketingeda.com SUMMARY:Innovative Designs Enabled by Ansys Solutions - IDEAS 2023 DESCRIPTION:ANSYS’ VIRTUAL USER CONFERENCE FOR ELECTRONICS\, SEMICONDUCTORS AND PHOTONICS DESIGNERS \nJoin us for the IDEAS Digital Forum — a place to catch up on industry best practices and the latest semiconductor\, electronic\, and photonic design advances. IDEAS will explore future trends with keynotes from industry leaders and offer technical insights by expert chip designers from many of the world’s largest electronic and semiconductor companies. \nAre you ready to empower innovation at this year’s IDEAS? \nGain valuable insights into the latest technology and market trends in the electronics industry by tuning in to top industry leaders at IDEAS 2023. \nStay ahead of the curve by listening to the vision and expertise shared by our keynote speakers\, allowing you to stay informed and proactive in the ever-evolving chip design industry. \nPrith Bannerji\nCTO\, Ansys \nMurat Becer\nVP\, Ansys \nLalitha Immaneni\nVP\, Intel \nShare this:\n Share on LinkedIn (Opens in new window)\n LinkedIn\n \n Share on X (Opens in new window)\n X\n \n Share on Facebook (Opens in new window)\n Facebook\n Like this:Like Loading... URL:https://marketingeda.com/event/innovative-designs-enabled-by-ansys-solutions-ideas-2023/ LOCATION:CA CATEGORIES:EDA,User Group ATTACH;FMTTYPE=image/jpeg:https://marketingeda.com/wp-content/uploads/IDEAS-2023.jpg END:VEVENT BEGIN:VEVENT DTSTART;TZID=Asia/Tokyo:20231128T080000 DTEND;TZID=Asia/Tokyo:20231128T170000 DTSTAMP:20260426T160312 CREATED:20230925T223508Z LAST-MODIFIED:20230925T223508Z UID:6881-1701158400-1701190800@marketingeda.com SUMMARY:Silvaco UseRs Global Event (SURGE) 2023 – Japan DESCRIPTION:Silvaco UseRs Global Events (SURGE) bring together users\, developers\, and industry experts of the EDA\, IP\, and TCAD communities to understand new semiconductor technologies\, innovative applications\, and techniques for realizing advanced designs. \nPresentations\nA variety of presentations will cover semiconductor device simulation\, circuit design and verification\, and IP design. Roadmaps and exciting technology updates will also be included. Discover how Silvaco solutions are used to realize silicon success in power devices\, displays\, memories\, automotive\, IoT\, high-performance computing\, and 5G/6G applications. \nKeynote Speakers and Panelists\nHear from industry leaders and visionaries who influence the global electronics marketplace. They will discuss trends in systems\, silicon\, and applications and share their thoughts on the design challenges and opportunities that face us today. \nShare this:\n Share on LinkedIn (Opens in new window)\n LinkedIn\n \n Share on X (Opens in new window)\n X\n \n Share on Facebook (Opens in new window)\n Facebook\n Like this:Like Loading... URL:https://marketingeda.com/event/silvaco-users-global-event-surge-2023-japan/ LOCATION:CA CATEGORIES:EDA,IP,User Group ATTACH;FMTTYPE=image/jpeg:https://marketingeda.com/wp-content/uploads/Surge-2023.jpg END:VEVENT BEGIN:VEVENT DTSTART;TZID=Asia/Taipei:20231123T080000 DTEND;TZID=Asia/Taipei:20231123T170000 DTSTAMP:20260426T160312 CREATED:20230925T223336Z LAST-MODIFIED:20230925T223336Z UID:6879-1700726400-1700758800@marketingeda.com SUMMARY:Silvaco UseRs Global Event (SURGE) 2023 – Taiwan/Singapore DESCRIPTION:Silvaco UseRs Global Events (SURGE) bring together users\, developers\, and industry experts of the EDA\, IP\, and TCAD communities to understand new semiconductor technologies\, innovative applications\, and techniques for realizing advanced designs. \nPresentations\nA variety of presentations will cover semiconductor device simulation\, circuit design and verification\, and IP design. Roadmaps and exciting technology updates will also be included. Discover how Silvaco solutions are used to realize silicon success in power devices\, displays\, memories\, automotive\, IoT\, high-performance computing\, and 5G/6G applications. \nKeynote Speakers and Panelists\nHear from industry leaders and visionaries who influence the global electronics marketplace. They will discuss trends in systems\, silicon\, and applications and share their thoughts on the design challenges and opportunities that face us today. \nShare this:\n Share on LinkedIn (Opens in new window)\n LinkedIn\n \n Share on X (Opens in new window)\n X\n \n Share on Facebook (Opens in new window)\n Facebook\n Like this:Like Loading... URL:https://marketingeda.com/event/silvaco-users-global-event-surge-2023-taiwan-singapore/ LOCATION:CA CATEGORIES:EDA,IP,User Group ATTACH;FMTTYPE=image/jpeg:https://marketingeda.com/wp-content/uploads/Surge-2023.jpg END:VEVENT BEGIN:VEVENT DTSTART;TZID=America/Los_Angeles:20231121T080000 DTEND;TZID=America/Los_Angeles:20231121T170000 DTSTAMP:20260426T160312 CREATED:20230925T223154Z LAST-MODIFIED:20230925T223154Z UID:6877-1700553600-1700586000@marketingeda.com SUMMARY:Silvaco UseRs Global Event (SURGE) 2023 – EMEA DESCRIPTION:Silvaco UseRs Global Events (SURGE) bring together users\, developers\, and industry experts of the EDA\, IP\, and TCAD communities to understand new semiconductor technologies\, innovative applications\, and techniques for realizing advanced designs. \nPresentations\nA variety of presentations will cover semiconductor device simulation\, circuit design and verification\, and IP design. Roadmaps and exciting technology updates will also be included. Discover how Silvaco solutions are used to realize silicon success in power devices\, displays\, memories\, automotive\, IoT\, high-performance computing\, and 5G/6G applications. \nKeynote Speakers and Panelists\nHear from industry leaders and visionaries who influence the global electronics marketplace. They will discuss trends in systems\, silicon\, and applications and share their thoughts on the design challenges and opportunities that face us today. \nShare this:\n Share on LinkedIn (Opens in new window)\n LinkedIn\n \n Share on X (Opens in new window)\n X\n \n Share on Facebook (Opens in new window)\n Facebook\n Like this:Like Loading... URL:https://marketingeda.com/event/silvaco-users-global-event-surge-2023-emea/ LOCATION:CA CATEGORIES:EDA,IP,User Group ATTACH;FMTTYPE=image/jpeg:https://marketingeda.com/wp-content/uploads/Surge-2023.jpg END:VEVENT BEGIN:VEVENT DTSTART;TZID=Asia/Seoul:20231116T080000 DTEND;TZID=Asia/Seoul:20231116T170000 DTSTAMP:20260426T160312 CREATED:20230925T223032Z LAST-MODIFIED:20230925T223032Z UID:6875-1700121600-1700154000@marketingeda.com SUMMARY:Silvaco UseRs Global Event (SURGE) 2023 – Korea DESCRIPTION:Silvaco UseRs Global Events (SURGE) bring together users\, developers\, and industry experts of the EDA\, IP\, and TCAD communities to understand new semiconductor technologies\, innovative applications\, and techniques for realizing advanced designs. \nPresentations\nA variety of presentations will cover semiconductor device simulation\, circuit design and verification\, and IP design. Roadmaps and exciting technology updates will also be included. Discover how Silvaco solutions are used to realize silicon success in power devices\, displays\, memories\, automotive\, IoT\, high-performance computing\, and 5G/6G applications. \nKeynote Speakers and Panelists\nHear from industry leaders and visionaries who influence the global electronics marketplace. They will discuss trends in systems\, silicon\, and applications and share their thoughts on the design challenges and opportunities that face us today. \nShare this:\n Share on LinkedIn (Opens in new window)\n LinkedIn\n \n Share on X (Opens in new window)\n X\n \n Share on Facebook (Opens in new window)\n Facebook\n Like this:Like Loading... URL:https://marketingeda.com/event/silvaco-users-global-event-surge-2023-korea/ LOCATION:CA CATEGORIES:EDA,IP,User Group ATTACH;FMTTYPE=image/jpeg:https://marketingeda.com/wp-content/uploads/Surge-2023.jpg END:VEVENT BEGIN:VEVENT DTSTART;TZID=America/Los_Angeles:20231026T080000 DTEND;TZID=America/Los_Angeles:20231026T170000 DTSTAMP:20260426T160312 CREATED:20230925T222750Z LAST-MODIFIED:20230925T222750Z UID:6872-1698307200-1698339600@marketingeda.com SUMMARY:Silvaco UseRs Global Event (SURGE) 2023 - USA DESCRIPTION:Silvaco UseRs Global Events (SURGE) bring together users\, developers\, and industry experts of the EDA\, IP\, and TCAD communities to understand new semiconductor technologies\, innovative applications\, and techniques for realizing advanced designs. \nPresentations\nA variety of presentations will cover semiconductor device simulation\, circuit design and verification\, and IP design. Roadmaps and exciting technology updates will also be included. Discover how Silvaco solutions are used to realize silicon success in power devices\, displays\, memories\, automotive\, IoT\, high-performance computing\, and 5G/6G applications. \nKeynote Speakers and Panelists\nHear from industry leaders and visionaries who influence the global electronics marketplace. They will discuss trends in systems\, silicon\, and applications and share their thoughts on the design challenges and opportunities that face us today. \nShare this:\n Share on LinkedIn (Opens in new window)\n LinkedIn\n \n Share on X (Opens in new window)\n X\n \n Share on Facebook (Opens in new window)\n Facebook\n Like this:Like Loading... URL:https://marketingeda.com/event/silvaco-users-global-event-surge-2023-usa/ LOCATION:CA CATEGORIES:EDA,IP,User Group ATTACH;FMTTYPE=image/jpeg:https://marketingeda.com/wp-content/uploads/Surge-2023.jpg END:VEVENT BEGIN:VEVENT DTSTART;TZID=America/Los_Angeles:20231018T080000 DTEND;TZID=America/Los_Angeles:20231019T170000 DTSTAMP:20260426T160312 CREATED:20230615T174703Z LAST-MODIFIED:20230615T174703Z UID:6499-1697616000-1697734800@marketingeda.com SUMMARY:Jasper User Group 2023 DESCRIPTION:Ready to share and discuss the latest design and verification best practices with your peers from around the world? \nIt’s time for our annual CadenceCONNECT: Jasper™ User Group Conference\, held on October 18 and 19 at the Cadence San Jose campus. This interactive\, in-depth technical conference connects designers\, verification engineers\, and engineering managers from around the world to share the latest design and verification practices based on Cadence’s Jasper formal verification technologies and methodologies. The conference will be held in person at the Cadence auditorium in San Jose\, CA. The Jasper User Group Conference has become the premier industry event for formal experts and beginners alike to learn from each other how to effectively accelerate their design and validation processes by applying formal methods. \nGot a Story to Share? Our Call for Presentations Is Open \nWe’re seeking your unique perspectives on using Jasper technologies and methodologies to achieve better results. If your presentation is accepted\, you can: \n\nIncrease industry visibility for you and your team’s field of expertise\nImprove and fine-tune your methods with insights from colleagues across the industry\nEarn wide acclaim with a Best Presentation Award nomination\n\nPlease visit the website for further information. Accepted authors will be expected to attend the conference and present in person. The deadline for abstract submission is 5:00pm (PDT) on Wednesday\, August 23\, 2023. \nHot Topics for 2023 \n\nBest practices to achieve formal signoff\nAlgorithmic and datapath verification\nSafety and security verification\nSequential equivalence checking\nDeep deadlock and bug hunting\nMachine learning for performance and convergence gains\nFormal regressions and optimizing compute resources\nComplex proofs\, abstraction\, and reduction techniques\nProcessor ISA verification\nProtocol verification with assertion-based VIP\nBlending formal and dynamic verification flows\nDriving broader adoption of formal methods\nFormal verification for design teams\nNovel applications for formal verification\nRISC-V verification\n\nConference registration will open at the end of August. We look forward to meeting you at CadenceCONNECT: Jasper User Group 2023!\nQuestions? Please email us. \nShare this:\n Share on LinkedIn (Opens in new window)\n LinkedIn\n \n Share on X (Opens in new window)\n X\n \n Share on Facebook (Opens in new window)\n Facebook\n Like this:Like Loading... URL:https://marketingeda.com/event/jasper-user-group-2023/ LOCATION:CA CATEGORIES:EDA,User Group ATTACH;FMTTYPE=image/jpeg:https://marketingeda.com/wp-content/uploads/Jasper-2023.jpg END:VEVENT BEGIN:VEVENT DTSTART;TZID=Europe/London:20231012T083000 DTEND;TZID=Europe/London:20231012T173000 DTSTAMP:20260426T160312 CREATED:20230920T164559Z LAST-MODIFIED:20230920T164559Z UID:6833-1697099400-1697131800@marketingeda.com SUMMARY:Synopsys Technology Symposium UK 2023 DESCRIPTION:Synopsys is hosting a Technical Symposium focusing on critical aspects of doing state of the art designs at established and emerging nodes. This event provides an opportunity for users to stay connected with the latest innovations as well as getting tips & tricks and best practices that fellow users and Synopsys experts will share. \nMultiple sessions will be offered where experts will update you on exciting new technologies and features. \nWe will conclude the day with a social event where you will have the opportunity to meet and discuss with your industry peers and Synopsys experts in an informal atmosphere. \n\n\n\n\n\n\n\n\n\n\n\nDirect booking link: Synopsys \nThere are a limited number of discounted rooms available for the night of Wednesday 11th October at the adjoining Voco Hotel. To book your room now please use this link: Synopsys \n\n\n\n\nShare this:\n Share on LinkedIn (Opens in new window)\n LinkedIn\n \n Share on X (Opens in new window)\n X\n \n Share on Facebook (Opens in new window)\n Facebook\n Like this:Like Loading... URL:https://marketingeda.com/event/synopsys-technology-symposium-uk-2023/ LOCATION:Reading FC Conference Centre\, Reading RG2 0FL\, Berkshire\, United Kingdom CATEGORIES:EDA,User Group ATTACH;FMTTYPE=image/jpeg:https://marketingeda.com/wp-content/uploads/Synopsys-October-12-2023.jpg END:VEVENT BEGIN:VEVENT DTSTART;TZID=Europe/Berlin:20231010T080000 DTEND;TZID=Europe/Berlin:20231011T170000 DTSTAMP:20260426T160312 CREATED:20231004T162118Z LAST-MODIFIED:20231004T162118Z UID:6913-1696924800-1697043600@marketingeda.com SUMMARY:CadenceLIVE Europe 2023 DESCRIPTION:CadenceLIVE Europe 2023 – experience the power of intelligent system design – brings together users\, developers\, and industry experts to network\, share ideas\, and inspire design innovation in the most complex electronics and intelligent systems. The event features peer presentations that offer solutions for today’s design challenges that will impact tomorrow’s products. \nAttendees will be able to attend captivating keynotes\, watch user presentations packed full of innovation\, see new product demos\, and learn new ways to solve design challenges from industry leaders and Cadence experts. \nCadence® products\, solutions\, flow\, and techniques will be featured at the conference in the following areas: \n\nMultiphysics In-Design Analysis\nHeterogeneous Integration\nCustom IC / Mixed-Signal / RF\nDigital Full Flow\nPCB / Advanced Packaging\nVerification Hardware and Software\nWorkforce Development\n\nCadence customers and partners can attend the event for FREE. \nCheck out the agenda to see what’s in store. \nShare this:\n Share on LinkedIn (Opens in new window)\n LinkedIn\n \n Share on X (Opens in new window)\n X\n \n Share on Facebook (Opens in new window)\n Facebook\n Like this:Like Loading... URL:https://marketingeda.com/event/cadencelive-europe-2023/ LOCATION:Holiday Inn Munich – City Centre\, Hochstraße 3\, Munich\, 81669\, Germany CATEGORIES:EDA,IP,User Group ATTACH;FMTTYPE=image/jpeg:https://marketingeda.com/wp-content/uploads/CadenceLIVE-Europe-2023.jpg END:VEVENT END:VCALENDAR