Verifying the correct passage of data through a DUT in constrained-random simulation is easy to do for basic I/O cases – data loss, obvious corruption, and 1-1 data passage. But what about verifying out-of-order cases? Or intermittently dropped bytes? Granted, a testbench can be written to look out for these issues, but as the layers… Read More »Formal 101 – Exhaustive Scoreboarding and Data Integrity Verification Made Easy
Missed milestones, lack of traceability, and costly respins. These are examples of what you risk if you do not take planning seriously during semiconductor design. A rock-solid planning process in the SOC Design process is a must. At the same time, the era of innovation is changing the way teams organize their work. Driven by… Read More »Agile Planning for SoC Design
Join Dr. Thang Tran, Principal Architect of Andes Technology Corp. and veteran of high-performance computing (HPC), on September 29, 2021, at 09:00 AM PDT for the last in his four-part masterclass series on demystifying the RISC-V Vector Extension. In this session, Dr. Tran presents examples using vector instructions based on Andes NX27V. He discusses NX27V performance,… Read More »Exploring Andes’ NX27V Vector Processor Instructions
While IoT devices may seem simple to the end users (which is good), the electrical design complexity of these devices is often very high. Designers are required to work with limited board space while functionality and speed requirements continue to increase. These tight spaces, combined with the required highspeed signaling, leads to increased susceptibility to… Read More »Common Challenges when Designing IoT PCBs – And How to Solve Them with Cadence
oin us on Thursday, September 30th to learn why common design management capabilities are not enough and what next generation capabilities are needed for IP based digital design management. Register Today! Here’s what you can learn: Complete digital design management checklist Tagging, branching, and merging Project BOM and IP conflicts Logistics: The webinar will be… Read More »IP Based Digital Design Management that Goes Beyond the Basics
With advanced packaging and interface solutions, it is possible to connect multiple CPU clusters (near or far) and share external memory resources among them. We will review some of the IPs required to build such a platform and recommend applications that can benefit from it. This webinar will be useful to designers, architects, and application… Read More »Scalable HPC platform and memory expansion techniques using Die-to-Die and LPDDR subsystems
Thursday, September 30, 2021 | 11:00 -11:30 a.m. PDT The development of secure systems is of paramount importance in this age of software intensive electronic systems. Security weaknesses in the SoC hardware can lead to vulnerabilities that may be exploited later on by malicious software. These challenging problems must be addressed pre-silicon and require rigorous… Read More »Avoiding SoC Security Threats – What Verification Engineers Should Know
This online event from the producers of DesignCon features an education program with on-demand webinars presented by a standout speaker list, suppliers with easy-to-find products and services, and multiple matchmaking and networking opportunities – with the quality you’ve come to expect from a DesignCon event. All of our DesignCon Digital education and information presented will… Read More »DesignCon Digital
A large volume of data is required for high performance computing (HPC) workloads in data centers. As a result, enabling data processing between machines and servers across long reach channels at high rates becomes mandatory. SoCs for HPC applications such as data center, networking and AI, must support high throughput and minimum latency with maximum… Read More »Keeping Latency to a Minimum with 400G/800G Ethernet IP
Join Cadence® Training and Product Engineering Architect Joerg Mueller and Senior Application Engineer Tom Weiss for this free technical training webinar. As a chip designer, you’re probably spending as much headspace on security threats as you are on traditional challenges like power, speed, and functionality. Recent microarchitectural vulnerabilities like “Meltdown” and “Row Hammer” that expose… Read More »Addressing Growing Security Challenges with JasperGold
Many design teams have used some form of hardware verification throughout their verification cycle for years now. Some engineering teams prefer to use emulation, some prefer to use prototyping, and some even use both. Why would engineering teams invest in both platforms? Join our experts to understand why you should consider bridging emulation and prototyping… Read More »Benefits of a Common Methodology for Emulation and Prototyping
Abstract: Started with an early adaptor release as Accellera 1.0a, UVM has evolved into few significant versions including UVM 1.1 and UVM 1.2. As with many popular useful standards, UVM has attained the coveted IEEE standardization in 2017. Interestingly, UVM is the first verification methodology to be standardized, and the current version is IEEE 1800.2-2020.… Read More »UVM for FPGAs (Part 4): IEEE 1800.2 UVM Updates
Trends such as advanced driver assistance systems (ADAS) and autonomous driving (AD) make software the differentiating factor in the automotive industry. To keep pace with innovations and to shorten development cycles, testing of electronic control units (ECUs) must shift-left. The use of software-in-the-loop (SiL) simulations is a recognized and established approach to frontload test activities to earlier development phases. Recently, automotive… Read More »Entering a New Era with Linux-Based Automotive Software-in-the-Loop Test Tools
Presenter: Espen Tallaksen, CEO of EmLogic Thursday, October 14, 2021 Abstract: Cycle related corner cases are probably the worst and main reason for undetected bugs on many FPGAs. To explain this in a simple way, - a cycle related corner case is for instance if you have an event counter where the number of counted… Read More »The most error prone FPGA corner cases
Cloud computing is going through a significant overhaul and continues to grow globally with increasing presence of hyperscale cloud providers for big data, high-performance computing (HPC), and analytics. In-house data centers are increasingly going off-premise, resulting in the co-location of data centers that manage and store data for companies and application developers to improve scalability… Read More »Defending the Cloud: PCIe and CXL Data Security for High-Performance Computing
The Cadence® AWR® V16 for RF Design Excellence Webinar Series introduces the latest capabilities in Cadence® AWR Design Environment® Version 16 (V16), providing ready access to Cadence Clarity™ 3D Solver and Celsius™ Thermal Solver for unconstrained capacity to solve large-scale and complex RF systems directly from within the RF design platform. Our next webinar in… Read More »Advanced Antenna Design and Integration Through Circuit/EM Co-Simulation
Veriest is inviting you to another event in our series of online Verification Meetups. This time, we'll have two presentations on the polemic topic of using Python in Verification, one by an industry expert and the other by one of Veriest technical leaders. Save the date and watch this space for more details!
In the Webinar, we will show you how to construct, simulate, analyze, validate, and optimize an architecture model using pre-built components. We will compare micro and application benchmarks on system SoC models containing clusters of ARM Cortex A53/A77/A65AE/N1, SiFive u74, and other vendor cores. Aside from the processor resources such as cache and memory, the… Read More »Compare Performance-power of Arm Cortex vs RISC-V for AI applications
Open Verification Library (OVL) is a library of property checkers for digital circuit descriptions written in popular Hardware Description Languages and maintained by Accelera. The OVL checkers could be used not only in dynamic simulation, but also in formal verification and emulation. Also, the OVL-based verification technology provides the easiest way for designers to implement… Read More »Using OVL for Assertion-based Verification of Verilog and VHDL Designs
For the past 10+ years, semiconductor design has moved from a project-based "start again" mindset to a more modular, "IP-centric" approach. This has significantly reduced project cost and improved time-to-market by encouraging the outsourcing of niche areas of the design to specialists, enabling the use of foundry sourced IP (often for free) and emphasizing the… Read More »Managing SoC Subsystems and Other Hierarchy With Methodics IPLM
Overview Regressions time often becomes one of the biggest challenges to meet the tight project schedule with increasing complexity of the SoC designs and shorter time to market. Verification engineers apply a coverage-driven methodology and run a large number of constrained random tests with multiple seeds in massive regressions to meet their coverage goals. Thus,… Read More »Xcelium ML for 5X Faster Regression Throughput
The last webinar in The Cadence® AWR® V16 for RF Design Excellence Webinar Seriesintroduces groundbreaking cross-platform workflows from AWR® software to Allegro® PCB Designer, which help to deliver up to a 50% reduction in turnaround time compared to competing solutions. RF IP integration within a larger mixed-signal PCB system is hampered by disjointed workflows between… Read More »Intelligent Cross-Platform Workflows for RF PCB Integration
Webinar Overview: A common issue with constrained random simulation is being able to reproduce random stimulus for debug purposes and for locking down regressions test suites. This is especially problematic when the source code needs to be modified and is known in SystemVerilog as random stability. In this webinar, we explain: Random stability in SystemVerilog… Read More »Understanding Random Stability in SystemVerilog and UVM
Abstract: Testing digital hardware has never been an easy job, and it won’t get easier any time soon. But that doesn’t mean writing test code can’t be enjoyable and productive! Cocotb, an approach to use Python as verification language, is bringing the joy back to verification. It allows developers to start with small, directed testbenches,… Read More »Constraint Random Verification with Python and Cocotb