Webinar
Calendar of Events
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1 event,
LIVE WEBINAR: How to Simplify the Verification of Bus Interfaces (US)
LIVE WEBINAR: How to Simplify the Verification of Bus Interfaces (US)
Abstract: Today’s FPGAs and SoC FPGAs use various types of bus interconnect - such as AXI, APB, AHB, Avalon or Wishbone - for both internal (IP-level) and external communication. A recently added feature to Aldec’s ALINT-PRO allows designers to extract, review and verify the correctness of bus interface connections. In addition, ALINT-PRO is capable of… Read More »LIVE WEBINAR: How to Simplify the Verification of Bus Interfaces (US)
3 events,
Ensuring Standards Compliance: Automating Post-Route Analysis for Hundreds of Serial Links
Ensuring Standards Compliance: Automating Post-Route Analysis for Hundreds of Serial Links
Presented by Todd Westerhoff, Product Marketing Manager for High-Speed System Design, Siemens EDA Abstract The PCB layout team has just handed you back a routed database with hundreds of serial links routed to your specifications — now what? How can you validate every link-as-routed for protocol compliance before releasing the design? If you're like most… Read More »Ensuring Standards Compliance: Automating Post-Route Analysis for Hundreds of Serial Links
PCIe 6.0 From IP to Interconnect in High-Performance Computing
PCIe 6.0 From IP to Interconnect in High-Performance Computing
ABSTRACT: PCI Express (PCIe) is one of the most popular interface technologies in the world. Interconnects for high-performance computing (HPC) in the data center, cloud and AI edge continue to increase in speed and density. System architects, SoC designers, PCB developers and SI engineers are challenged as never before to implement bleeding edge solutions. In… Read More »PCIe 6.0 From IP to Interconnect in High-Performance Computing
Bug Tracking with Indago Interactive for Specman
Bug Tracking with Indago Interactive for Specman
Join Cadence® Training and Principal Application Engineer Daniel Bayer for this free technical training webinar. The Indago™ Debug Platform is optimized for scalability, supporting debug of simulation runs as well as emulation, where support for loading large source files and handling huge amounts of probe data is a must. Join this free Cadence Training Webinar… Read More »Bug Tracking with Indago Interactive for Specman
1 event,
How to Overcome the Pain Points of AI/ML Hardware Design
How to Overcome the Pain Points of AI/ML Hardware Design
Join Achronix for a live Webinar December 16th: 10-11 AM Pacific and Recorded On-Demand After the Event AI/ML hardware faces three common pain points: memory bandwidth, computational throughput and on-chip data movement. Next-generation FPGA technology includes a 2D network on chip, GDDR6 memory interfaces and high performance machine learning processors, which present new capabilities to… Read More »How to Overcome the Pain Points of AI/ML Hardware Design