BEGIN:VCALENDAR VERSION:2.0 PRODID:-//Marketing EDA - ECPv6.15.20//NONSGML v1.0//EN CALSCALE:GREGORIAN METHOD:PUBLISH X-ORIGINAL-URL:https://marketingeda.com X-WR-CALDESC:Events for Marketing EDA REFRESH-INTERVAL;VALUE=DURATION:PT1H X-Robots-Tag:noindex X-PUBLISHED-TTL:PT1H BEGIN:VTIMEZONE TZID:Europe/London BEGIN:DAYLIGHT TZOFFSETFROM:+0000 TZOFFSETTO:+0100 TZNAME:BST DTSTART:20230326T010000 END:DAYLIGHT BEGIN:STANDARD TZOFFSETFROM:+0100 TZOFFSETTO:+0000 TZNAME:GMT DTSTART:20231029T010000 END:STANDARD BEGIN:DAYLIGHT TZOFFSETFROM:+0000 TZOFFSETTO:+0100 TZNAME:BST DTSTART:20240331T010000 END:DAYLIGHT BEGIN:STANDARD TZOFFSETFROM:+0100 TZOFFSETTO:+0000 TZNAME:GMT DTSTART:20241027T010000 END:STANDARD BEGIN:DAYLIGHT TZOFFSETFROM:+0000 TZOFFSETTO:+0100 TZNAME:BST DTSTART:20250330T010000 END:DAYLIGHT BEGIN:STANDARD TZOFFSETFROM:+0100 TZOFFSETTO:+0000 TZNAME:GMT DTSTART:20251026T010000 END:STANDARD BEGIN:DAYLIGHT TZOFFSETFROM:+0000 TZOFFSETTO:+0100 TZNAME:BST DTSTART:20260329T010000 END:DAYLIGHT BEGIN:STANDARD TZOFFSETFROM:+0100 TZOFFSETTO:+0000 TZNAME:GMT DTSTART:20261025T010000 END:STANDARD END:VTIMEZONE BEGIN:VTIMEZONE TZID:America/Los_Angeles BEGIN:DAYLIGHT TZOFFSETFROM:-0800 TZOFFSETTO:-0700 TZNAME:PDT DTSTART:20230312T100000 END:DAYLIGHT BEGIN:STANDARD TZOFFSETFROM:-0700 TZOFFSETTO:-0800 TZNAME:PST DTSTART:20231105T090000 END:STANDARD BEGIN:DAYLIGHT TZOFFSETFROM:-0800 TZOFFSETTO:-0700 TZNAME:PDT DTSTART:20240310T100000 END:DAYLIGHT BEGIN:STANDARD TZOFFSETFROM:-0700 TZOFFSETTO:-0800 TZNAME:PST DTSTART:20241103T090000 END:STANDARD BEGIN:DAYLIGHT TZOFFSETFROM:-0800 TZOFFSETTO:-0700 TZNAME:PDT DTSTART:20250309T100000 END:DAYLIGHT BEGIN:STANDARD TZOFFSETFROM:-0700 TZOFFSETTO:-0800 TZNAME:PST DTSTART:20251102T090000 END:STANDARD BEGIN:DAYLIGHT TZOFFSETFROM:-0800 TZOFFSETTO:-0700 TZNAME:PDT DTSTART:20260308T100000 END:DAYLIGHT BEGIN:STANDARD TZOFFSETFROM:-0700 TZOFFSETTO:-0800 TZNAME:PST DTSTART:20261101T090000 END:STANDARD END:VTIMEZONE BEGIN:VTIMEZONE TZID:America/New_York BEGIN:DAYLIGHT TZOFFSETFROM:-0500 TZOFFSETTO:-0400 TZNAME:EDT DTSTART:20230312T070000 END:DAYLIGHT BEGIN:STANDARD TZOFFSETFROM:-0400 TZOFFSETTO:-0500 TZNAME:EST DTSTART:20231105T060000 END:STANDARD BEGIN:DAYLIGHT TZOFFSETFROM:-0500 TZOFFSETTO:-0400 TZNAME:EDT DTSTART:20240310T070000 END:DAYLIGHT BEGIN:STANDARD TZOFFSETFROM:-0400 TZOFFSETTO:-0500 TZNAME:EST DTSTART:20241103T060000 END:STANDARD BEGIN:DAYLIGHT TZOFFSETFROM:-0500 TZOFFSETTO:-0400 TZNAME:EDT DTSTART:20250309T070000 END:DAYLIGHT BEGIN:STANDARD TZOFFSETFROM:-0400 TZOFFSETTO:-0500 TZNAME:EST DTSTART:20251102T060000 END:STANDARD END:VTIMEZONE BEGIN:VEVENT DTSTART;TZID=Europe/London:20250221T090000 DTEND;TZID=Europe/London:20250221T140000 DTSTAMP:20260410T143237 CREATED:20250107T225935Z LAST-MODIFIED:20250107T225935Z UID:8878-1740128400-1740146400@marketingeda.com SUMMARY:Using AI in development and product for FPGA DESCRIPTION:FPGA Front Runner – Using AI in development and product for FPGA \nHow are they used? What input language is used and how does it find it’s way into the FPGA? \nHow is the AI trained? \nAny use case example \nAgenda (GMT) \n\n\n\nTime\nSpeaker\nDetails\n\n\n09.00\nArrival and registration\n\n\n09:30\nPete Leonard\, Renishaw\nIntroduction to Renishaw\n\n\n09:40\nGareth R\, TechWorks \nAI Manager\nTechWorks – https://www.techworks.org.uk/\n\n\n10:00\nAlexander Montgomerie \nCorcoran\, Heronic \nCEO\nHeronic – https://heronic.ai/\n\n\n10:30\nDavid Harold\, RED Semi \nChief Operating Officer\nREDSemi – https://redsemiconductor.com/\n\n\n11:00\nPedro Machado\, Nottingham Trent University\, Senior Lecturer in Computer Science\nNottingham Trent \nUniversity – https://www.ntu.ac.uk/\n\n\n11:30\nRefreshment break\n\n\n12:00\nJeremy Bennett\, Embecosm\, \nChief Executive\nEmbecosm – https://www.embecosm.com/\n\n\n12:30\nGiles Peckham\, Myrtle.ai\, \nHead Of Marketing\nMyrtle.ai – https://myrtle.ai/\n\n\n13:00\nSpeaker 8\n\n\n\n13:30\nLunch\n\n\n14:00\nEnd\n\n\n\nPartner \nFPGA Front Runner event Partner: TechWorks & Tessolve \nNOTE \nPlease be aware that if you register for both the in-person and virtual events\, your physical ticket will be cancelled\, preventing access on the event day. \nWe also maintain a blacklist; individuals who register for the in-person event but fail to attend will be restricted from participating in future events. If you book a physical ticket but cannot attend then please cancel it in advance. \n\n\nLocation\nRenishaw plc\, New Mills\, Wotton-under-Edge \, Gloucestershire\, GL12 8JR \nShare this:\n Share on LinkedIn (Opens in new window)\n LinkedIn\n \n Share on X (Opens in new window)\n X\n \n Share on Facebook (Opens in new window)\n Facebook\n Like this:Like Loading... URL:https://marketingeda.com/event/using-ai-in-development-and-product-for-fpga/ LOCATION:Renishaw plc\, New Mills\, Wotton-under-Edge\, Gloucestershire\, GL12 8JR\, United Kingdom CATEGORIES:Forum,Webinar ATTACH;FMTTYPE=image/jpeg:https://marketingeda.com/wp-content/uploads/Tessolve-Febuary-21-2025.jpeg END:VEVENT BEGIN:VEVENT DTSTART;TZID=Europe/London:20250123T150000 DTEND;TZID=Europe/London:20250123T160000 DTSTAMP:20260410T143237 CREATED:20250107T192555Z LAST-MODIFIED:20250107T192555Z UID:8875-1737644400-1737648000@marketingeda.com SUMMARY:Mastering SoC Design and Verification for DO-254 Compliance DESCRIPTION:System on Chip (SoC) devices are transforming the landscape of advanced aviation systems\, offering unparalleled integration of multiple functionalities within a single chip. These compact powerhouses bring numerous advantages\, from reduced power consumption to enhanced performance. Yet\, their inherent complexity introduces unique safety assurance challenges that must be addressed to meet DO-254 standards. \nJoin this co-webinar with friends and partners\, ConsuNova\, to dive deep into the role of SoC devices in aviation\, where we’ll discuss the benefits\, challenges\, and critical considerations for successful implementation. We’ll cover various SoC architectures\, their safety implications\, and practical strategies for design and verification to ensure compliance. Gain insights into applicable certification guidance for both hardware and software\, along with best practices for overcoming development and verification hurdles. \nAgenda: \n\nUnderstanding SoC\n\nWhat is an SoC\, and why is it used?\nTypical architectures and components (IPs)\n\n\nNavigating Certification\n\nRelevant hardware and software guidance\nDevelopment and verification issues\n\n\nEnsuring Compliance\n\nIntegration strategies to meet DO-254 standards\n\n\n\nWebinar Duration: \n\n45 min presentation\n15 min Q&A\n\n\n\n\n\n\n\n\n\n\n\n\n\n\n\n\n\n\n\n\nPresenters\n\n\n\n\n\n\n\n\n\n\n\n\n\n\n\n\n\n\n\n\n\n\n\n\n\n\n\n\n\n\n\n\n\n\n \n\n\n\n\n\n\n\n\n\n\n\n\n\n\n\n\n\n\n \n\n\n\n\n\n\n\n\n\n\n\n\n\n\n\n\n\n\n\n\n\n\n\n\n\n\n\n\n\n\n\n\nBios: \n\n\nMartin Beeby is the Head of Advanced Avionics Systems and Managing Director of ConsuNova EU. With over 35 years of experience in the development of avionics Systems\, Hardware and Software\, Martin has a wealth of certification experience with systems ranging from DAL-A to DAL-D. Martin is\, and has been\, also an active contributor to many industry standard working groups developing new guidance for avionics development and is an active CVE on a number of different programs in Europe. \n\n\n\n\n\nJanusz Kitel is the DO-254 program manager at Aldec with over 18 years of experience in software and hardware design and verification. He has developed expertise in DO-254 compliance for over 10 years\, ensuring Aldec products meet aerospace regulations and supporting customers with their tooling challenges in AEH projects.\n\n\n\n\n\n\n\n\n\n\n\n\n\n\n\nShare this:\n Share on LinkedIn (Opens in new window)\n LinkedIn\n \n Share on X (Opens in new window)\n X\n \n Share on Facebook (Opens in new window)\n Facebook\n Like this:Like Loading... URL:https://marketingeda.com/event/mastering-soc-design-and-verification-for-do-254-compliance/ CATEGORIES:EDA,Webinar ATTACH;FMTTYPE=image/jpeg:https://marketingeda.com/wp-content/uploads/Aldec-January-23-2025.jpg END:VEVENT BEGIN:VEVENT DTSTART;TZID=America/Los_Angeles:20250123T100000 DTEND;TZID=America/Los_Angeles:20250123T110000 DTSTAMP:20260410T143237 CREATED:20250109T181629Z LAST-MODIFIED:20250109T181629Z UID:8887-1737626400-1737630000@marketingeda.com SUMMARY:Simulating Auto Systems & E/E Architectures for power and performance using VisualSim DESCRIPTION:Estimating latency and power for different use-cases in Systems\, ECU and Networks \nOverview: This session will focus on a common system-level simulation platform that can be shared by Semiconductor companies\, Tier One Suppliers\, OEMs in designing the entire E/E architecture.  The transition to everything digital and electronics is causing a number of design challenges across the ECU\, processors\, semiconductors\, software and networks. Current systems engineering solutions are focused on the correctness of algorithms\, requirements management and SysML behavior model.  What is required is accurate latency\, throughput\, buffer occupancy\, optimal scheduling and power consumption measurement\, prior to development. \nWe will delve into the design challenges associated with the new generation automotive system design\, changes in the power efficiency and latency requirements\, and handling of Distributed\, Zonal\, and Centralized Architecture computational. We show examples with use cases that originate at the SysML and refine all the way to micro-architecture.  The examples will showcase the comparison and results for different use cases\, topology\, different SoC architectures\, hardware modeling abstraction\, software task graphs and traffic workload. We will look at applications such as braking\, lighting\, comfort\, ADAS\, EV\, battery and safety system. \nKey Discussion Points: \n\nE/E Architecture Evolution:\n\nComparing the cost\, performance and power consumed by the same use cases on Distributed\, Zonal and Centralised architectures.\nMethodology to trade-off software complexity with compute resources\, scheduling\, multi-core distribution and network architecture\nIntegrating legacy systems and meeting-bandwidth\, low-latency communication.\n\n\nSystems and Semiconductors Exploration\n\nSelect the hardware\, network and software to meet the requirements\nOptimize the system and semiconductor definition to share with OEMs and semiconductor suppliers\nDetect system bottlenecks\, latency and power consumption for different use cases\n\n\nIdentify System Bottlenecks prior to Integration:\n\nEvaluate responses to failures and validate ISO 26262 and SOTIF requirements.\nTrade-off between latency\, power consumption\, and computational efficiency.\nOptimal task mapping and resource allocation in multi-core processor systems.\n\n\nRole of VisualSim in Architecture Design:\n\nLearn how VisualSim system-level IPs accelerate model construction and enable rapid architecture trade-offs.\nThe methodology to debug system behaviors and failures\nRegression simulation to identify and optimize the system specification\n\n\nCase Studies and Real-World Applications:\n\nExamples of how VisualSim has been used to model different use cases on the hardware\, software\, OS and network to optimize automotive E/E systems.\nInsights into achieving significant reductions in latency and power through architectural refinements.\n\n\nFuture Trends in E/E Architectures:\n\nThe impact of emerging technologies such as AI-driven optimizations and multi-core ECUs.\nAdvancements in centralized architecture to increase modularity and scalability.\n\n\n\n  \nShare this:\n Share on LinkedIn (Opens in new window)\n LinkedIn\n \n Share on X (Opens in new window)\n X\n \n Share on Facebook (Opens in new window)\n Facebook\n Like this:Like Loading... URL:https://marketingeda.com/event/simulating-auto-systems-e-e-architectures-for-power-and-performance-using-visualsim/ CATEGORIES:EDA,Webinar ATTACH;FMTTYPE=image/jpeg:https://marketingeda.com/wp-content/uploads/Mirabilis-January-23-2025.jpg END:VEVENT BEGIN:VEVENT DTSTART;TZID=America/New_York:20241219T090000 DTEND;TZID=America/New_York:20241219T100000 DTSTAMP:20260410T143237 CREATED:20241217T192611Z LAST-MODIFIED:20241217T192611Z UID:8614-1734598800-1734602400@marketingeda.com SUMMARY:Signal and Power Integrity Challenges in Advanced Packaging Technologies for Disaggregated Integration DESCRIPTION:Abstract\n\nThe integrated circuit industry faces new challenges as chip complexity and area have been increasing to prohibitive ranges. Some segments have been adopting then a relatively new paradigm for heterogeneous integration based on chiplets at the first package level in combination with advanced 2.5 and 3D packaging technologies. \nThe chiplet approach has the advantage of reducing the single die complexity and size\, which is compatible with a high silicon yield\, but also allows a faster evolution of electronics systems by a selective redesign of certain chips within a disaggregated solution\, or the customization of the system by certain chiplet combinations. Nevertheless\, this dense packaging integration imposes signal and power integrity challenges\, as well as the necessity of new circuitry and novel validation and test methodologies to handle parallel-massive communication across dies. \nThis lecture discusses the challenges associated with advanced packaging technologies and chiplet integration from the electrical integrity perspective\, where high-density and high-speed signaling\, and narrow areas for power distribution impose some interesting trade-offs among performance and reliability\, together with the need of a new kind of interface\, called the embedded IO (EIO)\, for chip-to-chip communication. \n\n\nDescription\n\nThis talk will take place on 19 December 2024 at 09:00 AM EST (-5:00 UTC) and features a talk by Renato Rimolo-Donadio\, titled “Signal and Power Integrity Challenges in Advanced Packaging Technologies for Disaggregated Integration”. \nRegistration for this series is entirely free and will be limited to the first 1000 registrants per event. If you cannot register\, you can also attend the webinar via LinkedIn Live or access webinar recordings on the IEEE CASS Resource Center. \nRegistration for this series is entirely free and will be limited to the first 1\,000 registrants per event. If you cannot register\, you can also attend the webinar via LinkedIn Live. Following the webinar\, the recording will be available on the CASS Resource Center and as a lesson in the CASS Microlearning (CASS MiLe) e-learning platform. In CASS MiLe\, interested practitioners can learn through short didactic units (micro-lessons) with practical questions\, and upon lesson completion\, learners receive digital badges/certificates. \n\nShare this:\n Share on LinkedIn (Opens in new window)\n LinkedIn\n \n Share on X (Opens in new window)\n X\n \n Share on Facebook (Opens in new window)\n Facebook\n Like this:Like Loading... URL:https://marketingeda.com/event/signal-and-power-integrity-challenges-in-advanced-packaging-technologies-for-disaggregated-integration/ CATEGORIES:EDA,Webinar ATTACH;FMTTYPE=image/jpeg:https://marketingeda.com/wp-content/uploads/IEEE-CAS-December-19-2024.jpg END:VEVENT BEGIN:VEVENT DTSTART;TZID=America/Los_Angeles:20241219T090000 DTEND;TZID=America/Los_Angeles:20241219T100000 DTSTAMP:20260410T143237 CREATED:20241211T175317Z LAST-MODIFIED:20241211T175403Z UID:8567-1734598800-1734602400@marketingeda.com SUMMARY:Advantages of using IP-XACT and TGI for SoC Development DESCRIPTION:Are you looking for ways to simplify your SoC development process\, reduce rework\, and accelerate time-to-market? \nJoin us for an insightful webinar\, “Advantages of using IP-XACT and TGI for SoC Development\,” where we’ll explore how the latest features of IP-XACT 2022 can revolutionize your SoC design workflows. \nWhat’s on the Agenda?\n\nIntroduction to IP-XACT: A detailed overview of the standard and its core benefits.\nWhat’s New in IP-XACT 2022: Exploring the latest updates and how they empower developers.\nTGI API: Enabling programmability and automation for resource optimization.\nIP Packaging and Integration: Techniques to package IPs efficiently and integrate them into SoCs.\nCapturing Connectivity: Leveraging busInterfaces and adhocConnections effectively.\nVendor Extensions: How to use custom data capturing for specialized needs.\nBest Practices for SoC Development: Real-world tips for leveraging IP-XACT in your projects.\n\nDate: December 19th\, 2024\nTime: 9:00 PST/ 16:00 GMT \nRegister now and learn how IP-XACT can transform your SoC development process. \nShare this:\n Share on LinkedIn (Opens in new window)\n LinkedIn\n \n Share on X (Opens in new window)\n X\n \n Share on Facebook (Opens in new window)\n Facebook\n Like this:Like Loading... URL:https://marketingeda.com/event/advantages-of-using-ip-xact-and-tgi-for-soc-development/ CATEGORIES:EDA,Webinar ATTACH;FMTTYPE=image/jpeg:https://marketingeda.com/wp-content/uploads/Agnisys-December-19-2024.jpg END:VEVENT BEGIN:VEVENT DTSTART;TZID=America/Los_Angeles:20241212T100000 DTEND;TZID=America/Los_Angeles:20241212T110000 DTSTAMP:20260410T143237 CREATED:20241127T180212Z LAST-MODIFIED:20241127T180212Z UID:8540-1733997600-1734001200@marketingeda.com SUMMARY:Learn How to Utilize Victory Analytics and Machine Learning to Calibrate TCAD Data DESCRIPTION:Abstract\nPhysics-based design using technology computer-aided design (TCAD) has provided fundamental contributions to R&D in the semiconductor industry. Traditionally\, TCAD modeling is mostly developed manually by expert designers using a trial-and-error procedure. However\, the imperative acceleration of time-to-market to reduce development expenses calls for renovation of these conventional TCAD approaches. \nMachine learning (ML) and artificial intelligence (AI) techniques are currently considered to be essential enhancements for TCAD strategies. Silvaco\, a prominent provider of TCAD\, EDA software\, and SIP solutions used to enable semiconductor design\, is at the forefront in developing AI-powered TCAD. \nIn this webinar\, an ML-TCAD combined strategy is presented to boost the calibration of TCAD parameters to benchmark TCAD simulations against experimental data. This is achieved through a seamless flow between two of the latest tools from the Victory suite: Victory Design Of Experiment (DOE) and Victory Analytics. \nVDOE is a powerful project manager for efficiently running DOE with TCAD simulations. This essential step allows users to collect the TCAD outputs to be fed into Victory Analytics. Then\, Victory Analytics uses ML-modeling to optimize TCAD parameters to fit the experimental data. Calibration of TCAD parameters of AlGaN/GaN HEMT will be used to showcase this procedure as a case study. \nWhat You Will Learn\n\nBrief overview of TCAD calibration\nOverview of Victory TCAD tools\nVictory DoE\nVictory Analytics\nCalibration methodology using Victory Analytics and machine learning\nOverview of simulation\nGenerating DoEs using Victory DoE\nViewing and modeling results in Victory Analytics\nOptimizing parameters to fit experimental data\nVerifying results\n\n\n\n\n\n\nPresenter\n\n\n\n\nDr. Stefania Carapezzi is currently a Field Applications Engineer at Silvaco France. She joined in March 2023. She obtained a PhD in Physics at University of Bologna\, Italy\, in 2014. Then\, she was Post-Doc Researcher for several years at Advanced Research Center on Electronic System\, Bologna\, Italy and at LIRMM\, University of Montpellier\, CNRS\, Montpellier\, France. Her research work has been focused on TCAD simulation of Beyond CMOS devices and quantum effects in nanoscaled transistors. \n\n\n\n\n\nWHO SHOULD ATTEND:\n\n\n\n\nTCAD engineers\, fab engineers\, process engineers\, product managers\, and engineering management. \n\n\nShare this:\n Share on LinkedIn (Opens in new window)\n LinkedIn\n \n Share on X (Opens in new window)\n X\n \n Share on Facebook (Opens in new window)\n Facebook\n Like this:Like Loading... URL:https://marketingeda.com/event/learn-how-to-utilize-victory-analytics-and-machine-learning-to-calibrate-tcad-data/ CATEGORIES:EDA,Webinar ATTACH;FMTTYPE=image/jpeg:https://marketingeda.com/wp-content/uploads/Silvaco-December-12-2024.jpg END:VEVENT BEGIN:VEVENT DTSTART;TZID=America/Los_Angeles:20241212T100000 DTEND;TZID=America/Los_Angeles:20241212T110000 DTSTAMP:20260410T143237 CREATED:20241125T180804Z LAST-MODIFIED:20241125T180804Z UID:8537-1733997600-1734001200@marketingeda.com SUMMARY:Accelerating SoC Automotive Design with Chiplets DESCRIPTION:Step into the forefront of innovation with our upcoming webinar\, which explores how chiplet technology is revolutionizing the automotive industry and setting new benchmarks. Discover how Cadence is empowering customers to achieve unparalleled success with chiplets. Here’s what you can look forward to: \n\nMastering Chiplet Architecture: Dive into the intricacies of mastering chiplet architecture\, where you’ll learn how to integrate multiple chiplets\, including processing\, memory\, I/O\, and accelerators\, into a single\, streamlined solution. Understand the critical importance of chiplet interoperability and how Cadence and Arm collaborate on standards like the Arm Chiplet System Architecture to ensure seamless integration.\nThe Impact of Chiplets on Automotive Designs: Explore the transformative impact of chiplets on automotive designs\, particularly in building scalable and extendable systems for key functions such as ADAS. Learn about Cadence’s ADAS chiplet reference design and how it can accelerate product development with fewer engineering resources\, driving innovation in the automotive sector.\nCadence Chiplet Designs: Discover Cadence’s cutting-edge chiplet designs\, including the recent successful tapeout of Cadence’s first system chiplet. Learn how Cadence tools like the Helium Virtual Platform and 3D-IC are key enablers for quickly designing chiplet solutions\, helping customers bring their products to market faster and with greater efficiency.\n\nEquip yourself with the knowledge to thrive in this dynamic environment. We look forward to embarking on this exciting journey together! \nWho Should Attend:\nThis free event is a terrific opportunity for design/CAD engineers\, CAD managers\, IT managers and business leaders seeking to optimize their design flow and technology infrastructure. \nShare this:\n Share on LinkedIn (Opens in new window)\n LinkedIn\n \n Share on X (Opens in new window)\n X\n \n Share on Facebook (Opens in new window)\n Facebook\n Like this:Like Loading... URL:https://marketingeda.com/event/accelerating-soc-automotive-design-with-chiplets/ CATEGORIES:EDA,IP,Webinar ATTACH;FMTTYPE=image/jpeg:https://marketingeda.com/wp-content/uploads/Cadence-December-12-2024-1.jpg END:VEVENT BEGIN:VEVENT DTSTART;TZID=America/Los_Angeles:20241212T100000 DTEND;TZID=America/Los_Angeles:20241212T110000 DTSTAMP:20260410T143237 CREATED:20241112T212446Z LAST-MODIFIED:20241112T212446Z UID:8503-1733997600-1734001200@marketingeda.com SUMMARY:CadenceTECHTALK: Driving Intelligent System Design with 3D-IC Multiphysics DESCRIPTION:As the industry reaches the limits of device scaling at advanced nodes\, there is a growing demand for increased computing performance and data transfer in hyperscale data centers and AI designs. Advanced systems-on-chip (SoCs) are approaching the maximum size limits\, and there is a need to find innovative solutions to continue scaling according to Moore’s law and achieve better performance with lower power consumption. Stacking chips in the same package (3D) and using a multi-chiplet system with silicon interposers on the same package (2.5D) are emerging as preferred solutions\, but they come with their own challenges. \nThis webinar will discuss the requirements\, challenges\, and solutions for 3D-IC design and analysis achieved through an integrated 3D-IC platform. By receiving early feedback from system-level analysis processes\, 3D-IC designers can benefit from a system-driven approach to power\, performance\, and area (PPA) and avoid overdesigning individual chipsets. \nYou will learn about: \n\nThe requirements\, challenges\, and solutions for 3D-IC design\nHow the analysis of 3D-ICs is done through an integrated 3D-IC design platform\nHow feedback from early system-level analysis provides a system-driven approach to PPA\n\nShare this:\n Share on LinkedIn (Opens in new window)\n LinkedIn\n \n Share on X (Opens in new window)\n X\n \n Share on Facebook (Opens in new window)\n Facebook\n Like this:Like Loading... URL:https://marketingeda.com/event/cadencetechtalk-driving-intelligent-system-design-with-3d-ic-multiphysics/ CATEGORIES:EDA,Webinar ATTACH;FMTTYPE=image/jpeg:https://marketingeda.com/wp-content/uploads/Cadence-December-12-2024.jpg END:VEVENT BEGIN:VEVENT DTSTART;TZID=America/Los_Angeles:20241212T090000 DTEND;TZID=America/Los_Angeles:20241212T100000 DTSTAMP:20260410T143237 CREATED:20241122T193816Z LAST-MODIFIED:20241122T193816Z UID:8527-1733994000-1733997600@marketingeda.com SUMMARY:From Concept to QoR: Practical Generative AI for ASIC Managers and Engineers DESCRIPTION:Be among the first to see how Generative AI is advancing hardware design workflows\, providing solutions that reduce complexity and enable better results without steep learning curves. Witness how these tools offer immediate\, practical benefits for real-world use cases. \n\n\nWhat You’ll Learn:\n\n\n\n\nThis session offers a unique opportunity to explore how Generative AI solutions with Rise Design Automation are reshaping hardware design and verification workflows. Attendees will learn advanced techniques for enhancing design quality\, accelerating IP and module development\, and making more informed design trade-offs with minimal learning curves. Designed for engineers and managers with a background in hardware design\, this session is ideal for those eager to adopt innovative methods and witness how these tools perform in practical scenarios.  \nKey Takeaways:\nGenerative AI and Accelerated IP Development \n\nUnderstand the value of adopting a shift-left approach to enhance design abstraction and streamline processes beyond traditional RTL methods. \n\n\nLearn how project timelines can be reduced\, enabling faster IP/module development and delivering improved Quality of Results (QoR). \n\n  \nDesign Generation \n\nExplore how AI automates the creation of RTL code from natural or high-level languages\, such as SystemVerilog\, SystemC\, and C++. \n\n\nDiscover tools for AI-powered code completion\, generation\, and refactoring that ensure maintainable\, high-quality code with less manual effort and help RTL designers achieve excellent QoR without deep HLS expertise. \n\n  \nIntegrated Design Optimization \n\nEarly Design Exploration: Understand intelligent and iterative refinement techniques that help minimize late-stage design surprises. \nGradual Refinement: Explore workflows that support continuous refinement of high-level designs\, incorporating backend metrics and physical insights as they progress. \n\n\nCritical Parameter Optimization: Learn about AI-powered Design Space Exploration (DSE) to evaluate and optimize configurations such as loop unrolling\, pipelining\, and memory synthesis for superior Power\, Performance\, and Area (PPA). \n\n\nIntegrated EDA flows: Discover how Rise’s Generative AI integrates with both Synopsys and Cadence RTL Verilog workflows\, bridging early design exploration with downstream verification and physical implementation. \n\n\nReal-World Applications  \n\nHardware Design: Learn how Gen AI allows designers to focus on architectural innovations rather than manual coding. \n\n\nVerification Processes: Examine ways for AI to automate early verification steps to detect issues earlier\, with metrics and reduce the rework in later stages. \n\n\nCollaborative Approaches: See how AI-driven tools enhance collaboration among system architects\, hardware designers\, and verification engineers\, creating more cohesive and efficient workflows. \n\n\nFlexible Deployment Options  \n\nDeployment Support: Understand compatibility with cloud platforms like Amazon Bedrock and Microsoft Azure\, as well as options for on-premises environments that can be tailored to different operational and organizational needs. \n\n\nLegal Considerations: Review best practices for addressing data privacy\, intellectual property concerns\, and compliance with regulatory frameworks when leveraging AI-driven methodologies. \n\n\n\n\n\nWho Should Attend:\n\n\n\n\n\nDesign Engineers: Discover AI-guided strategies to improve control paths\, data flow\, and overall performance. \n\n\nVerification Engineers: Learn techniques to integrate early verification processes\, reducing risks and enhancing efficiency. \n\n\nProject Leads: Gain insights into managing trade-offs in power\, performance\, and area while introducing innovative AI tools into existing workflows. \nSystem Architects: Explore approaches for early modeling and validation of architectural decisions\, optimizing outcomes and preventing late-stage challenges. \nDesign Managers/Methodology team: Understand how AI combined with raising design abstraction can dramatically improve the overall productivity\, quality and ability for your design teams to deliver on new projects\n\n\n\nSpeakers\n\n\n\nMike Fingeroff\, Chief of High-Level Synthesis (HLS) With over 20 years of experience in hardware design automation\, Mike has specialized in High-Level Synthesis (HLS)\, focusing on machine learning and early performance modeling using SystemVerilog\, SystemC\, and MatchLib. He is the author of The High-Level Synthesis Blue Book\, and his expertise includes C++\, SystemC\, and video and wireless algorithms.\n\n\nAllan Klinck\, Co-Founder Allan is a co-founder of RDA and a technology leader with expertise in high-level design and AI/ML frameworks for verification. He has driven innovation in verification and low-power technologies\, helping teams enhance efficiency and performance in modern\, complex designs.\n\n\nEllie Burns currently serves as the Head of Marketing at Rise Design Automation (RDA). With over 30 years of experience in the semiconductor and EDA industries\, she has held diverse roles in engineering\, applications engineering\, technical marketing\, product management\, and senior leadership\, specializing in driving business growth through strategic marketing.\n\n\n\nShare this:\n Share on LinkedIn (Opens in new window)\n LinkedIn\n \n Share on X (Opens in new window)\n X\n \n Share on Facebook (Opens in new window)\n Facebook\n Like this:Like Loading... URL:https://marketingeda.com/event/from-concept-to-qor-practical-generative-ai-for-asic-managers-and-engineers/ CATEGORIES:EDA,Webinar ATTACH;FMTTYPE=image/jpeg:https://marketingeda.com/wp-content/uploads/Rise-December-12-2024.jpg END:VEVENT BEGIN:VEVENT DTSTART;TZID=America/Los_Angeles:20241211T100000 DTEND;TZID=America/Los_Angeles:20241211T140000 DTSTAMP:20260410T143237 CREATED:20241122T231141Z LAST-MODIFIED:20241122T231141Z UID:8534-1733911200-1733925600@marketingeda.com SUMMARY:Mastering EMC Simulations for Electronic Designs DESCRIPTION:Electromagnetic Compatibility (EMC) simulation ensures that electronic devices comply with regulatory standards and perform optimally in their intended environments. As the complexity of electronic systems increases\, the importance of EMC simulation grows\, allowing engineers to predict and mitigate potential electromagnetic interference (EMI) issues before physical prototypes are built. \nOverview\nIt can be challenging for EMC and product design engineers to understand how to use simulation tools effectively. This hands-on session with experts in full-device simulation offers a unique opportunity for engineers to dive into the world of EMC simulation. This session will provide practical experience\, demystifying the simulation process and empowering engineers with the knowledge to implement simulations early in the design phase. Experts will offer insights into best practices\, common pitfalls to avoid\, and strategies for interpreting simulation results. \nBy participating in such a session\, engineers can gain a deeper understanding of the nuances of EMC simulation. They learn to set up simulations that model their products’ real-world behavior\, identify potential EMI issues\, and explore design modifications to enhance EMC performance. This proactive approach ensures compliance with regulatory standards and contributes to the final product’s reliability and quality. \nEMC simulation is more than just a checkbox for compliance; it’s a strategic tool that\, when used effectively\, can significantly improve product design. Join this hands-on session guided by experts created for engineers looking to master EMC simulation and integrate it into their design process. It’s an investment in knowledge that will pay dividends throughout the product’s lifecycle\, ensuring that your efforts today will lead to better products in the future. \n  \nWhat attendees will learn\n\nCAD File Preparation: Master the process of importing mechanical CAD designs\, assigning materials\, and preparing for simulations.\nPCB and Package Setup: Discover the steps to import electronic design files for PCBs and packages\, including automation of the setup process.\nCable Specification: Gain hands-on experience in defining cables through the co-simulation with multi-conductor transmission line solvers.\nComponent Modeling: Understand how to represent components using ideal or SPICE circuit models for co-simulation with 3D geometries.\nPerformance Evaluation: Learn to transform simulation results into formats that facilitate comparison with standard measurements for device performance assessment.\n\n  \nWho should attend\nElectromagnetic Compatibility Engineers\, Mechanical Design Engineers\, RF Engineers\, Electrical Engineers \nShare this:\n Share on LinkedIn (Opens in new window)\n LinkedIn\n \n Share on X (Opens in new window)\n X\n \n Share on Facebook (Opens in new window)\n Facebook\n Like this:Like Loading... URL:https://marketingeda.com/event/mastering-emc-simulations-for-electronic-designs-2/ CATEGORIES:EDA,Webinar ATTACH;FMTTYPE=image/jpeg:https://marketingeda.com/wp-content/uploads/Ansys-December-11-2024-.jpg END:VEVENT BEGIN:VEVENT DTSTART;TZID=America/Los_Angeles:20241205T090000 DTEND;TZID=America/Los_Angeles:20241205T100000 DTSTAMP:20260410T143237 CREATED:20241203T172119Z LAST-MODIFIED:20241203T172119Z UID:8544-1733389200-1733392800@marketingeda.com SUMMARY:Optimizing Hardware Design with SystemRDL: Tools\, Techniques\, and Tips DESCRIPTION:Efficient management of registers and memory maps is critical for the success of modern System-on-Chip (SoC) designs. System Register Description Language (SystemRDL)\, combined with Agnisys’s IDesignSpec Suite\, provides an advanced solution to automate and simplify these complex processes. In this webinar\, “Optimizing Hardware Design with SystemRDL: Tools\, Techniques\, and Tips\,” we will demonstrate how the IDesignSpec Suite leverages SystemRDL to accelerate register design\, improve design quality\, and streamline SoC development. You’ll gain insights into best practices\, learn how to automate crucial tasks\, and see how our tools ensure compliance with industry standards. \nYou’ll learn:\n• Best Practices for register design and memory map management using SystemRDL.\n• How the IDesignSpec Suite accelerates SoC development with automation\, reducing manual errors and ensuring compliance with industry standards.\n• Practical use cases\, including generating design files\, firmware headers\, and comprehensive documentation for seamless hardware-software integration. \nExclusive Features and Highlights:\n• Explore how Agnisys’s SystemRDL VS Code Extension enhances your design workflow.\n• Discover the Agnisys PSS Compiler and its ability to simplify Portable Stimulus generation.\n• See real-world examples\, such as the Power Controller use case\, demonstrating the suite’s capabilities in addressing industrial challenges. \nWhat’s on the Agenda? \nThe webinar will guide you through every facet of SystemRDL and its integration with IDesignSpec:\n• Core Concepts: Registers\, Memory\, Address Maps\, and Parameters.\n• Advanced Techniques: Constraint Management\, Verification Constructs\, and Structural Testing.\n• Comprehensive Outputs: From HDL Path generation to SoC assembly and IP packaging.\n• Bonus: Insights into SoC Hardware-Software Interface (HSI) and device driver generation. \nReserve your spot today and join us for this hands-on\, practical session! \nShare this:\n Share on LinkedIn (Opens in new window)\n LinkedIn\n \n Share on X (Opens in new window)\n X\n \n Share on Facebook (Opens in new window)\n Facebook\n Like this:Like Loading... URL:https://marketingeda.com/event/optimizing-hardware-design-with-systemrdl-tools-techniques-and-tips/ CATEGORIES:EDA,Webinar ATTACH;FMTTYPE=image/jpeg:https://marketingeda.com/wp-content/uploads/Agnisys-December-5-2024.jpg END:VEVENT BEGIN:VEVENT DTSTART;TZID=America/Los_Angeles:20241203T100000 DTEND;TZID=America/Los_Angeles:20241203T170000 DTSTAMP:20260410T143237 CREATED:20241106T234135Z LAST-MODIFIED:20241106T234135Z UID:8481-1733220000-1733245200@marketingeda.com SUMMARY:Keysight EDA 2025 Launch event DESCRIPTION:New EDA Tools for 5G and AI Infrastructure Design\n\n\n\n\n\nWe are ready to share the latest release of our electronic design automation (EDA) software suites. This update will help you design smarter with faster multidomain insights and workflows enhanced by artificial intelligence (AI). \nGet the Roadmap\nThe webinar will kick off with an overview of the Keysight EDA 2025 roadmap from Richard Duvall\, senior EDA marketing manager. Then\, you can choose the discussion topic that interests you most. Explore product release highlights\, watch demo videos\, and participate in question-and-answer sessions. After the live webinar\, use the same registration link to watch other topics on demand. \nTrack 1: What’s New in Advanced System Design (ADS) for RF Circuit Design \n\n\n\nLearn how RF circuit design tools with Python APIs enable open workflows that help you address the complex design challenges of sub-terahertz chipsets.\nWatch advanced RF simulation enable a multi-domain co-design cockpit\, essential for troubleshooting designs with nonlinear\, power\, electromagnetic\, thermal\, and wideband 5G digital modulation.\nHarness the latest AI and machine learning (ML) technology to create reliable power amplifier simulation models with minimal effort using artificial neural networks.\n\nTrack 2: What’s New in ADS for High-Speed Digital Circuit Design \n\n\n\nDiscover how to use the Keysight Chiplet PHY Designer to predict the true end-to-end link margin and verify compliance with cross talk analysis and quarter-rate clock support.\nLearn how the Keysight PCIe® Designer can help you perform complete PCIe system analysis and simulation-driven virtual compliance tests with a streamlined workflow.\nWatch the Keysight Power Integrity Designer enable simulations that deliver thousands of amps to the next generation of custom multi-die packages\, AI chips\, and cloud server applications.\n\nTrack 3: What’s New in Device Modeling and Characterization \n\nLearn how new AI / ML-based algorithms in IC-CAP can help fully automate the model recentering process and increase productivity by 10 times\, from days to hours.\nSee how the Keysight Model Builder Pro leverages Python to automate the modeling process\, helping standardize the modeling flow and reducing turnaround time.\nLearn how the Keysight Model Generator framework enables a turnkey workflow that is 30% faster with less programming and more automation.\n\n\n\n\n\n\n\n\n\nShare this:\n Share on LinkedIn (Opens in new window)\n LinkedIn\n \n Share on X (Opens in new window)\n X\n \n Share on Facebook (Opens in new window)\n Facebook\n Like this:Like Loading... URL:https://marketingeda.com/event/keysight-eda-2025-launch-event/ CATEGORIES:EDA,Webinar ATTACH;FMTTYPE=image/jpeg:https://marketingeda.com/wp-content/uploads/Keysight-December-3-2024.jpg END:VEVENT BEGIN:VEVENT DTSTART;TZID=Europe/London:20241127T150000 DTEND;TZID=Europe/London:20241127T153000 DTSTAMP:20260410T143237 CREATED:20241105T181903Z LAST-MODIFIED:20241105T181903Z UID:8475-1732719600-1732721400@marketingeda.com SUMMARY:Webinar 3: Tessolve AI assisted advanced DV Flow and Use cases DESCRIPTION:Webinar 3: Tessolve AI assisted advanced DV Flow and Use cases \nWith the increasing importance of AI in engineering and the exciting potential for it’s use in Design Verification\, Tessolve has been working on improving internal DV processes\, with impressive reductions in both effort and costs\, and with many clients to improve both efficiency and quality in DV through AI. In this series of 3 short webinars\, Tessolve will outline the work done to demonstrate the potential for improving both productivity and quality\, and how you could get involved in this (zero cost) collaboration to capture similar benefits. \nAgenda (GMT) \n15:00 Welcome and Introduction – Mike Bartley\, Tessolve \n15:00 Marmik Soni & Mike Bartley\, Tessolve Semiconductor \n15:20 Close \nAdditional Information on Tessolve AI assisted advanced DV Flow and Use cases\n\nAI Training Bots\nAI Assistance\, CoPilot\nAI Code CoPilot\nRAG\nRAG Assessment\nAI Agents\n\nTessolve reserves the right to cancel registration at its discretion. \nShare this:\n Share on LinkedIn (Opens in new window)\n LinkedIn\n \n Share on X (Opens in new window)\n X\n \n Share on Facebook (Opens in new window)\n Facebook\n Like this:Like Loading... URL:https://marketingeda.com/event/webinar-3-tessolve-ai-assisted-advanced-dv-flow-and-use-cases/ CATEGORIES:EDA,Webinar ATTACH;FMTTYPE=image/jpeg:https://marketingeda.com/wp-content/uploads/Tessolve-November-27-2024.jpg END:VEVENT BEGIN:VEVENT DTSTART;TZID=Europe/London:20241121T093000 DTEND;TZID=Europe/London:20241121T140000 DTSTAMP:20260410T143237 CREATED:20241113T173601Z LAST-MODIFIED:20241113T173601Z UID:8506-1732181400-1732197600@marketingeda.com SUMMARY:FPGA Front Runner: FPGA Safety and Security DESCRIPTION:This event covers the challenges in ensuring an FPGA is secure and demonstrably safe as per the relevant industry safety standards. This includes supply chains\, FPGA hardware and the IP used on the FPGA\n \nAgenda (GMT) \n\n\n\nTime\nSpeaker\nDetails\n\n\n09.30\nArrival and registration\n\n\n10.00\nTobias Adryan\, Synopsys\nSecuring FPGAs Beyond the Bitstream\n\n\n10.30\nEspen Tallaksen\, EmLogic\nFPGA Requirements Tracking and the Requirements Traceability Matrix\n\n\n11.00\nAndrew Swirski\, Beetlebox\nSecuring FPGA Development Pipelines with DevSecOps\n\n\n11.30\nRefreshment break\n\n\n12.00\nIan Pearson\, Microchip Technology Inc.\nEU Cyber Resilience Act – Impacts on Business and Product Design\n\n\n12.30\nFlemming Christensen\, Sundance Multiprocessor Technology Ltd\nHow to secure supply of ‘COTS’ FPGA Modules\n\n\n13.00\nPeter Davies\, Thales\n\n\n\n13.30\nLunch and networking\n\n\n14.00\nEnd\n\n\n\n\n\n\n\n FPGA Front Runner event Partner: TechWorks & Tessolve \nNOTE \nPlease be aware that if you register for both the in-person and virtual events\, your physical ticket will be cancelled\, preventing access on the event day. \nWe also maintain a blacklist; individuals who register for the in-person event but fail to attend will be restricted from participating in future events. If you book a physical ticket but cannot attend then please cancel it in advance. \nShare this:\n Share on LinkedIn (Opens in new window)\n LinkedIn\n \n Share on X (Opens in new window)\n X\n \n Share on Facebook (Opens in new window)\n Facebook\n Like this:Like Loading... URL:https://marketingeda.com/event/fpga-front-runner-fpga-safety-and-security/ LOCATION:The Cass Centre\, Shaftesbury Road\, Cambridge\, CB2 8BS\, United Kingdom CATEGORIES:EDA,Webinar ATTACH;FMTTYPE=image/jpeg:https://marketingeda.com/wp-content/uploads/Tessolve-21-November-2024.jpg END:VEVENT BEGIN:VEVENT DTSTART;TZID=America/Los_Angeles:20241121T080000 DTEND;TZID=America/Los_Angeles:20241121T090000 DTSTAMP:20260410T143237 CREATED:20241107T182710Z LAST-MODIFIED:20241107T182710Z UID:8486-1732176000-1732179600@marketingeda.com SUMMARY:Accelerating Electric Vehicle Development: Integrated design flow for power modules with functional safety and reliability focus DESCRIPTION:This webinar to delve into the integrated design flow for power modules for electric vehicles (EVs) for enhanced functional safety and reliability. The power modules are distinguished by their high voltage and current requirements\, substantial power dissipation\, and the resulting temperature rise. Ensuring their safety and reliability is paramount. We will explore how Cadence’s cutting-edge solutions – Allegro X\, PSpice\, Clarity 3D Solver\, and Celsius Thermal Solver—designed to support a thermally aware design process\, come together in an end-to-end integrated design solution \nShare this:\n Share on LinkedIn (Opens in new window)\n LinkedIn\n \n Share on X (Opens in new window)\n X\n \n Share on Facebook (Opens in new window)\n Facebook\n Like this:Like Loading... URL:https://marketingeda.com/event/accelerating-electric-vehicle-development-integrated-design-flow-for-power-modules-with-functional-safety-and-reliability-focus/ CATEGORIES:EDA,Webinar ATTACH;FMTTYPE=image/jpeg:https://marketingeda.com/wp-content/uploads/Cadence-November-21-2024.jpg END:VEVENT BEGIN:VEVENT DTSTART;TZID=America/Los_Angeles:20241121T080000 DTEND;TZID=America/Los_Angeles:20241121T090000 DTSTAMP:20260410T143237 CREATED:20241031T164508Z LAST-MODIFIED:20241031T164508Z UID:8466-1732176000-1732179600@marketingeda.com SUMMARY:Boost your verification productivity with Questa Verification IQ DESCRIPTION:This session will explore Questa Verification IQ (VIQ)\, Siemens EDA’s next-generation collaborative and data-driven verification solution. VIQ revolutionizes the verification process by providing advanced analytics\, enhanced collaboration\, and comprehensive traceability. By leveraging machine learning\, VIQ significantly enhances verification efficiency to boost your productivity. \nWhat you will learn: \n\n‌How to implement a collaborative\, plan-driven verification process\, complemented by a requirement-driven process for complete traceability from requirements to implementation and verification results\nSetting up a collaborative regression environment with live visibility and control to drive debug and optimize verification flows\nEnabling team-based collaborative analysis to accelerate coverage closure by applying analytics\nConfiguring dashboards with visualizations and insights into what happened and why\, utilizing trending data\, gauges\, and cross-analytics\n‌\n\nWho should attend: \nVerification Engineers & Managers \n\n\nProducts Covered:   \n\nQuesta Verification IQ:\n\nTestplan Author\nRegression Navigator\nCoverage Analyzer\nVerification Insight\n\n\n\n\n\nSpeaker:\n\n\n\n\n\n\nMark Carey\nProduct Engineer\, Siemens EDA\n\n\n\n\nMark Carey is a Product Engineer in the Digital Verification Technologies division at Siemens EDA. With over two decades of experience in EDA\, he started his career as a software developer before moving into technical marketing and product management roles across design\, virtual prototyping\, requirement traceability\, and now works as part of the verification management team. \n\n\n\nShare this:\n Share on LinkedIn (Opens in new window)\n LinkedIn\n \n Share on X (Opens in new window)\n X\n \n Share on Facebook (Opens in new window)\n Facebook\n Like this:Like Loading... URL:https://marketingeda.com/event/boost-your-verification-productivity-with-questa-verification-iq/ CATEGORIES:EDA,Webinar ATTACH;FMTTYPE=image/jpeg:https://marketingeda.com/wp-content/uploads/Siemens-November-21-2024.jpg END:VEVENT BEGIN:VEVENT DTSTART;TZID=Europe/London:20241120T150000 DTEND;TZID=Europe/London:20241120T153000 DTSTAMP:20260410T143237 CREATED:20241105T181405Z LAST-MODIFIED:20241105T181405Z UID:8472-1732114800-1732116600@marketingeda.com SUMMARY:Webinar 2: Tessolve AI assisted DV Flow DESCRIPTION:With the increasing importance of AI in engineering and the exciting potential for it’s use in Design Verification\, Tessolve has been working on improving internal DV processes\, with impressive reductions in both effort and costs\, and with many clients to improve both efficiency and quality in DV through AI. In this series of 3 short webinars\, Tessolve will outline the work done to demonstrate the potential for improving both productivity and quality\, and how you could get involved in this (zero cost) collaboration to capture similar benefits. \nAgenda (GMT) \n15:00 Welcome and Introduction – Mike Bartley\, Tessolve \n15:00 Marmik Soni & Mike Bartley\, Tessolve Semiconductor \n15:20 Close \nAdditional Information Tessolve AI assisted DV Flow\n  \n\nSpec Analysis\nRegister Extraction\nTest Flow\nAssertion Generation\nCoverpoints\nTestcases\nScripts for UVM etc.\n\nTessolve reserves the right to cancel registration at its discretion. \nShare this:\n Share on LinkedIn (Opens in new window)\n LinkedIn\n \n Share on X (Opens in new window)\n X\n \n Share on Facebook (Opens in new window)\n Facebook\n Like this:Like Loading... URL:https://marketingeda.com/event/webinar-2-tessolve-ai-assisted-dv-flow/ CATEGORIES:EDA,Webinar ATTACH;FMTTYPE=image/jpeg:https://marketingeda.com/wp-content/uploads/Tessolve-November-20-2024.jpg END:VEVENT BEGIN:VEVENT DTSTART;TZID=America/Los_Angeles:20241120T070000 DTEND;TZID=America/Los_Angeles:20241120T090000 DTSTAMP:20260410T143237 CREATED:20241025T162958Z LAST-MODIFIED:20241025T162958Z UID:8453-1732086000-1732093200@marketingeda.com SUMMARY:Fast Track RTL Debug with the Verisium Debug Python App Store DESCRIPTION:Working with debugging scripts locally and manually can be challenging\, as can reusing and organizing them. What if there was a way to create your own app with the required functionality and to register it with the tool? \nThe answer lies in the Verisium Debug Python App Store. Instantly add additional features and capabilities to your Verisium Debug Application using Python Apps that interact with Verisium Debug via the Python API. \nJoin us for this Training Webinar and discover the Verisium Debug Python App Store. The app store allows you to search for existing apps\, learn about them\, install\, or uninstall them\, and even customize existing apps. \nDate and Time\nWednesday\, November 20\, 2024\n07:00 PST San Jose / 10:00 EST New York / 15:00 GMT London / 16:00 CET Munich / 17:00 IST Jerusalem / 20:30 IST Bangalore / 23:00 CST Beijing \n  \nTo register for this webinar\, sign in with your Cadence Support account (email ID and password) to log in to the Learning and Support System*. Then select Enroll to register. Once registered\, you’ll receive a confirmation email containing all login details. \nA quick reminder: \n\nIf you haven’t received a registration confirmation within one hour of registering\, please check your spam folder and ensure your pop-up blockers are off and cookies are enabled.\nFor issues with registration or other inquiries\, reach out to eur_training_webinars@cadence.com\n\nShare this:\n Share on LinkedIn (Opens in new window)\n LinkedIn\n \n Share on X (Opens in new window)\n X\n \n Share on Facebook (Opens in new window)\n Facebook\n Like this:Like Loading... URL:https://marketingeda.com/event/fast-track-rtl-debug-with-the-verisium-debug-python-app-store/ CATEGORIES:EDA,Webinar ATTACH;FMTTYPE=image/jpeg:https://marketingeda.com/wp-content/uploads/Cadence-November-20-2024.jpg END:VEVENT BEGIN:VEVENT DTSTART;TZID=America/Los_Angeles:20241119T090000 DTEND;TZID=America/Los_Angeles:20241119T100000 DTSTAMP:20260410T143237 CREATED:20241019T030235Z LAST-MODIFIED:20241019T030235Z UID:8436-1732006800-1732010400@marketingeda.com SUMMARY:Ansys-Synopsys Technology Update: The Latest Advances in Multi-Die Design DESCRIPTION:The semiconductor industry is rapidly adopting 2.5D and 3D multi-die designs as the significant benefits have become clear for applications like HPC\, GPU\, mobile\, and AI/ML. Multi-die design technology has been quickly evolving with early experiences leading to the development of more advanced implementation and analysis techniques. \nFor the past years\, Synopsys and Ansys have been creating design flows that carry designers through early exploration\, implementation\, and final signoff. They are deeply engaged with semiconductor designers on advanced multi-die projects and have helped customers bring successful designs to market. \nRegister now to learn about:\n– Multi-die design best practices for thermal\, signal\, and power integrity\n– Insights from practical multi-die design case studies\n– More advanced packaging technologies for thermal management\, backside power\, and co-packaged optics \nSPEAKERS \nMarc Swinnen is Product Marketing Director for semiconductor products at Ansys in San Jose\, CA. Before joining Ansys\, Marc was Director of Product Marketing at Cadence Design Systems and has worked in Marketing and Technical Support positions at Synopsys\, Azuro\, and Sequence Design\, where he gained experience with a wide array of digital and analog design tools. \nKeith Lanier is a Product Management Director at Synopsys focusing on multi-die and 3D heterogeneous integration (3DHI) solutions involving the latest advanced packaging technology. He brings over 30 years of experience in custom design\, analog/mixed signal (AMS) and RF/mmWave product experience\, including 8 years designing high speed data converters and amplifiers at Analog Devices. \nShare this:\n Share on LinkedIn (Opens in new window)\n LinkedIn\n \n Share on X (Opens in new window)\n X\n \n Share on Facebook (Opens in new window)\n Facebook\n Like this:Like Loading... URL:https://marketingeda.com/event/ansys-synopsys-technology-update-the-latest-advances-in-multi-die-design/ CATEGORIES:EDA,IP,Webinar ATTACH;FMTTYPE=image/jpeg:https://marketingeda.com/wp-content/uploads/Ansys-Synopsys-November-19-2024.jpg END:VEVENT BEGIN:VEVENT DTSTART;TZID=America/Los_Angeles:20241114T100000 DTEND;TZID=America/Los_Angeles:20241114T110000 DTSTAMP:20260410T143237 CREATED:20241030T170948Z LAST-MODIFIED:20241030T170948Z UID:8460-1731578400-1731582000@marketingeda.com SUMMARY:Optimize Systems and Semiconductor Architecture for Deep Learning Algorithms Using System-Level Modeling DESCRIPTION:In a world where artificial intelligence and machine learning are embedded in critical applications—from real-time tracking and object detection to autonomous systems—the architecture behind these innovations must be both powerful and efficient. To help engineers and architects address these challenges\, our upcoming webinar will demonstrate how System-Level Modeling can be a game-changer in optimizing the performance and power efficiency of deep learning algorithms\, including Deep and Convolutional Neural Networks (DNNs and CNNs). \nThrough system-level modeling\, design teams can analyze and optimize critical factors such as response time\, power consumption\, component selection\, and cost-effectiveness before finalizing their designs. This session is particularly beneficial for SoC architects\, embedded systems designers\, and other professionals working to balance performance\, power\, and cost for AI deployments in demanding environments. \nWhat You’ll Learn \nWith AI systems like CNNs now integral to technologies in real-time tracking\, object detection\, and autonomous navigation\, the need for architecture trade-offs has intensified. Our approach to system-level modeling allows teams to: \n\nEvaluate Hardware Combinations: Assess combinations of CPUs\, GPUs\, AI-specific processing units\, and standalone FPGAs to select the best configuration for your needs.\nOptimize Task Partitioning: Partition tasks across chips to achieve targeted performance without compromising power efficiency or exceeding budget constraints.\nRealistic Workload Simulation: Use cycle-accurate models to depict AI/ML algorithm performance under real-world conditions\, creating accurate simulations of hardware components in action.\n\nThrough detailed case studies across industries like automotive\, avionics\, data centers\, and radar systems\, you’ll see how this methodology applies to diverse scenarios\, helping to trade off key performance indicators (e.g.\, vehicle mileage vs. processing power). \n\n\n\n\nKey Takeaways\n\n\n\n\n\nTrade-Off Latency\, Power\, and Cost Using Early Simulation\n\nBy modeling early\, teams can visualize trade-offs and make informed decisions on processor and component selection to hit project goals effectively.\n\n\nIntegrate Shift-Left and Shift-Right Strategies in System-Level Modeling\n\nBring software testing and design validation forward to avoid issues in later stages\, enhancing the quality of final designs.\n\n\nMap Applications to Diverse Processing Units\n\nLearn to deploy applications seamlessly across CPUs\, GPUs\, TPUs\, and AI engines to maximize AI’s impact while optimizing for cost and power.\n\n\nFoster Collaboration Between OEMs\, Tier 1 Suppliers\, and Semiconductor Manufacturers\n\nUse our methodology to facilitate better communication and integration across all stakeholders involved in the AI hardware design process.\n\n\n\nWhether you’re involved in automotive\, avionics\, or advanced SoC architectures\, this session offers an invaluable opportunity to master the nuances of system-level modeling for AI architecture and streamline your deep learning deployment. \nDon’t Miss Out on Transforming Your AI Deployment Strategy!\nJoin us for this exclusive session and gain the insights you need to optimize your systems and semiconductor architecture for cutting-edge deep learning applications. \n\n\n\n\nDate: November 14th\, 2024\nSession 1: 11:30 AM India / 3:00 PM Japan or Korea / 2:00 PM China \nSign up: https://bit.ly/4eZqnjP \nSession 2: 10:00 AM USA PDT / 1:00 PM USA EDT \nRegister: https://bit.ly/3YFM82o \n\n\nShare this:\n Share on LinkedIn (Opens in new window)\n LinkedIn\n \n Share on X (Opens in new window)\n X\n \n Share on Facebook (Opens in new window)\n Facebook\n Like this:Like Loading... URL:https://marketingeda.com/event/optimize-systems-and-semiconductor-architecture-for-deep-learning-algorithms-using-system-level-modeling/ CATEGORIES:EDA,Webinar ATTACH;FMTTYPE=image/jpeg:https://marketingeda.com/wp-content/uploads/Mirabilis-November-14-2024.jpg END:VEVENT BEGIN:VEVENT DTSTART;TZID=America/Los_Angeles:20241114T100000 DTEND;TZID=America/Los_Angeles:20241114T110000 DTSTAMP:20260410T143237 CREATED:20241025T163841Z LAST-MODIFIED:20241025T163841Z UID:8456-1731578400-1731582000@marketingeda.com SUMMARY:AI-Driven Constraint Generation for PCB and IC Package Design DESCRIPTION:Join our webinar to discover how AI-driven optimization and automation in constraint generation can boost productivity and shorten design cycles for PCB and IC package design. Learn how integrating Allegro X and Sigrity X can streamline your workflow. \nKey Takeaways:\n \n\nLearn how the Sigrity Topology Workbench\, a robust system-level SI/PI environment for what-if and pre-route analysis\, is linked to the Allegro X PCB and IC package implementation tools.\nExperience the power of AI optimization in simulating parameterized structures to quickly reach target objectives\, and see how the physical attributes that meet these target objectives are automatically fed into the implementation tool as constraints.\nEnvision the efficiency of reusing or updating AI-generated constraints in future designs to consistently reduce design cycle time\n\nShare this:\n Share on LinkedIn (Opens in new window)\n LinkedIn\n \n Share on X (Opens in new window)\n X\n \n Share on Facebook (Opens in new window)\n Facebook\n Like this:Like Loading... URL:https://marketingeda.com/event/ai-driven-constraint-generation-for-pcb-and-ic-package-design/ CATEGORIES:EDA,Webinar ATTACH;FMTTYPE=image/jpeg:https://marketingeda.com/wp-content/uploads/Cadence-November-14-2024.jpg END:VEVENT BEGIN:VEVENT DTSTART;TZID=Europe/London:20241113T150000 DTEND;TZID=Europe/London:20241113T153000 DTSTAMP:20260410T143237 CREATED:20241105T180842Z LAST-MODIFIED:20241105T180842Z UID:8469-1731510000-1731511800@marketingeda.com SUMMARY:Tessolve AI Strategy & Eco System for DV DESCRIPTION:With the increasing importance of AI in engineering and the exciting potential for it’s use in Design Verification\, Tessolve has been working on improving internal DV processes\, with impressive reductions in both effort and costs\, and with many clients to improve both efficiency and quality in DV through AI. In this series of 3 short webinars\, Tessolve will outline the work done to demonstrate the potential for improving both productivity and quality\, and how you could get involved in this (zero cost) collaboration to capture similar benefits. \nAgenda (GMT) \n15:00 Welcome and Introduction – Mike Bartley\, Tessolve \n15:00 Marmik Soni & Mike Bartley\, Tessolve Semiconductor \n15:20 Close \nAdditional Information on Tessolve AI Strategy & Eco System for DV\n\nAI Strategies at Tessolve\nAI Tool range for DV-\n\nDV RAG Tool\,\nAssertify\,\nUnit TB Generation\,\nUVM AI\,\nISO26262 AI etc.\n\n\n\n  \nTessolve reserves the right to cancel registration at its discretion. \nShare this:\n Share on LinkedIn (Opens in new window)\n LinkedIn\n \n Share on X (Opens in new window)\n X\n \n Share on Facebook (Opens in new window)\n Facebook\n Like this:Like Loading... URL:https://marketingeda.com/event/tessolve-ai-strategy-eco-system-for-dv/ CATEGORIES:EDA,Webinar ATTACH;FMTTYPE=image/jpeg:https://marketingeda.com/wp-content/uploads/Tesolve-November-13-2024.jpg END:VEVENT BEGIN:VEVENT DTSTART;TZID=America/New_York:20241113T090000 DTEND;TZID=America/New_York:20241113T100000 DTSTAMP:20260410T143237 CREATED:20241016T181319Z LAST-MODIFIED:20241016T181319Z UID:8422-1731488400-1731492000@marketingeda.com SUMMARY:ASIP University Day 2024: Domain-Specific Processor Design using ASIP Designer DESCRIPTION:The AI revolution and other application domains\, like data centers\, advanced wireless communications\, image and video processing\, automated driving assistance\, and post-quantum cryptography need more powerful architectures with higher performance. This is driving demand for heterogeneous multicore systems including application specific instruction set processors (ASIPs). \nASIPs have become a mainstream implementation option for modern SoCs\, i.e. when standard processor IP cannot meet challenging application-specific requirements\, and fixed hardware is not flexible enough. This growth has driven many university projects and increased interest in initiatives like RISC-V\, which has significantly expanded beyond UC Berkeley. \n\nWhy Attend? \nYou will hear from leading university teams about their ASIP design project results across various application domains. Additionally\, Synopsys will provide a technical update on ASIP Designer with reference examples. \nThis event offers a great opportunity to exchange ideas\, build networks\, and gain valuable insights from university partners. \nDon’t miss out – register now to secure your spot! \nShare this:\n Share on LinkedIn (Opens in new window)\n LinkedIn\n \n Share on X (Opens in new window)\n X\n \n Share on Facebook (Opens in new window)\n Facebook\n Like this:Like Loading... URL:https://marketingeda.com/event/asip-university-day-2024-domain-specific-processor-design-using-asip-designer/ CATEGORIES:IP,Webinar ATTACH;FMTTYPE=image/jpeg:https://marketingeda.com/wp-content/uploads/Synopsys-November-13-2024.jpg END:VEVENT BEGIN:VEVENT DTSTART;TZID=America/Los_Angeles:20241112T110000 DTEND;TZID=America/Los_Angeles:20241112T120000 DTSTAMP:20260410T143237 CREATED:20241021T181622Z LAST-MODIFIED:20241021T181734Z UID:8440-1731409200-1731412800@marketingeda.com SUMMARY:Rise Together Beyond RTL : Practical Techniques for Improving ASIC Design Efficiency and Early Verification DESCRIPTION:High-level design techniques and automation tools to address the limitations of traditional RTL\, reduce verification times\, improve performance\, and manage growing design complexity—integrating seamlessly.\n\n\nWhat You’ll Learn:\n\n\n\n\nThis Lunch & Learn offers an in-depth look at Rise Design Automation tools and illustrates how high-level design and early verification techniques can bring value to your projects. No prior experience with high-level design is necessary\, but familiarity with hardware design and RTL synthesis is recommended. \nSome key takeaways you can expect: \n** Rise Design Automation Overview – Introduction to the tools\, use cases\, methodologies\, and project value of raising the abstraction beyond RTL with Rise. \n** SystemVerilog – Technical details of how to use SystemVerilog for high-level design – highlighting both “loosely-timed” and “untimed” SystemVerilog. \n** Handling Control and Data Flow – Learn practical approaches to optimizing control and data paths to meet timing and performance requirements without adding unnecessary complexity. \n** Applying Design Space Exploration – Explore design configurations by adjusting loop unrolling\, pipelining\, and scheduling to optimize power\, performance\, and area—while gaining early insights into trade-offs. \n** Improving Early Verification – How to integrate verification earlier in the design process to detect bugs faster and reduce the risk of late-stage rework. \n** Real-World Use Cases – See how high-level design techniques are used to efficiently build a high-performance compute accelerator for applications like machine learning\, DSP\, and video/image processing. \n** Learn how collaboration between system architects\, RTL designers\, and verification engineers speeds up development and delivers more reliable hardware. \n\n\n\n\nWho should attend:\n\n\n\n\n** Design Engineers looking to improve control paths\, data flow\, and performance\, while adopting new methods gradually and with minimal risk. \n** Verification Engineers looking to implement earlier\, more efficient verification processes to minimize risk and accelerate timelines\, without overhauling their current flows. \n** Project Leads managing trade-offs in timelines\, power\, performance\, and area\, while ensuring smooth integration of new techniques into existing processes. \n** System Architects looking to model\, explore\, and validate architectural decisions early\, focusing on performance\, power\, and area trade-offs without late-stage surprises. \n\n\n\n\nSpeakers\n\n\n\nMike Fingeroff\, Chief of High-Level Synthesis (HLS) With over 20 years of experience in hardware design automation\, Mike has specialized in High-Level Synthesis (HLS)\, focusing on machine learning and early performance modeling using SystemVerilog\, SystemC\, and MatchLib. He is the author of The High-Level Synthesis Blue Book\, and his expertise includes C++\, SystemC\, and video and wireless algorithms.\n\n\nAllan Klinck\, Co-Founder Allan is a co-founder of RDA and a technology leader with expertise in high-level design and AI/ML frameworks for verification. He has driven innovation in verification and low-power technologies\, helping teams enhance efficiency and performance in modern\, complex designs.\n\n\nEllie Burns currently serves as the Head of Marketing at Rise Design Automation (RDA). With over 30 years of experience in the semiconductor and EDA industries\, she has held diverse roles in engineering\, applications engineering\, technical marketing\, product management\, and senior leadership\, specializing in driving business growth through strategic marketing.\n\nShare this:\n Share on LinkedIn (Opens in new window)\n LinkedIn\n \n Share on X (Opens in new window)\n X\n \n Share on Facebook (Opens in new window)\n Facebook\n Like this:Like Loading... URL:https://marketingeda.com/event/rise-together-beyond-rtl-practical-techniques-for-improving-asic-design-efficiency-and-early-verification/ CATEGORIES:EDA,Webinar ATTACH;FMTTYPE=image/jpeg:https://marketingeda.com/wp-content/uploads/Rise-DA-November-12-2024.jpg END:VEVENT BEGIN:VEVENT DTSTART;TZID=America/Los_Angeles:20241107T070000 DTEND;TZID=America/Los_Angeles:20241107T080000 DTSTAMP:20260410T143237 CREATED:20241023T171101Z LAST-MODIFIED:20241023T171101Z UID:8449-1730962800-1730966400@marketingeda.com SUMMARY:Navigating COTS-IP in DO-254: Strategies for Safe and Efficient FPGA Design DESCRIPTION:The integration of COTS-IP (Commercial Off-The-Shelf Intellectual Property) components in FPGA-based Avionics systems can significantly speed up development and enhance performance. However\, it also introduces unique challenges\, as these components may not align with the strict aviation development assurance standards required for DO-254 compliance. This webinar will guide you through the process of balancing the benefits and risks associated with COTS-IP in Avionics designs. \nIn this joint webinar with friends and partners\, Aldec\, we’ll explore different types of IPs available on the market\, their roles in the design assurance process\, and practical strategies for integrating them safely. You’ll discover key factors for choosing the right vendor and IP\, best practices for verification\, and effective planning and execution techniques to ensure your systems meet safety requirements. \nWhat you’ll learn:\n1. COTS-IP usage:\na. What are COTS-IPs and what are the different IP types\nb. Applicable guidance for COTS-IP\nc. Verification strategies and methods\nd. Methods for achieving coverage\ne. Putting it all together and showing compliance \nSpeakers: \nMartin Beeby\, Head of Advanced Avionics Systems and Managing Director of ConsuNova EU\, ConsuNova With over 35 years of experience in the development of avionics Systems\, Hardware and Software\, Martin has a wealth of certification experience with systems ranging from DAL-A to DAL-D. Martin is an active contributor to many industry standard working groups developing new guidance for Avionics development and is an active CVE on multiple European programs. \nJanusz Kitel\, DO-254 Program Manager\, Aldec Janusz brings over 18 years of experience in software and hardware design and verification\, with more than a decade dedicated to mastering DO-254 compliance. His work ensures that Aldec products meet the strict standards of the aerospace industry\, while also providing customers with valuable support in overcoming tooling challenges in airborne electronic hardware (AEH) projects. \nShare this:\n Share on LinkedIn (Opens in new window)\n LinkedIn\n \n Share on X (Opens in new window)\n X\n \n Share on Facebook (Opens in new window)\n Facebook\n Like this:Like Loading... URL:https://marketingeda.com/event/navigating-cots-ip-in-do-254-strategies-for-safe-and-efficient-fpga-design/ CATEGORIES:EDA,IP,Webinar ATTACH;FMTTYPE=image/jpeg:https://marketingeda.com/wp-content/uploads/Aldec-November-7-2024.jpg END:VEVENT BEGIN:VEVENT DTSTART;TZID=America/Los_Angeles:20241106T100000 DTEND;TZID=America/Los_Angeles:20241106T110000 DTSTAMP:20260410T143237 CREATED:20241018T165537Z LAST-MODIFIED:20241018T165537Z UID:8433-1730887200-1730890800@marketingeda.com SUMMARY:Navigating Trends and Tools in Automotive Design with Cadence DESCRIPTION:Join us for our first webinar in this insightful series\, where we explore the rapidly evolving automotive landscape. We will focus on the rise of autonomous and electric vehicles\, highlighting key trends such as ADAS\, software-defined vehicles\, and zonal architectures. \nLearn how Cadence’s advanced automotive solutions are addressing the increasing compute demands and in-vehicle networking requirements while prioritizing power efficiency and safety. \nEquip yourself with the knowledge to thrive in this dynamic environment. We look forward to traveling this road together! \nWhat will be covered: \n\nEmerging trends in ADAS\, software-defined vehicles\, zonal architectures\, connectivity\, and electrification\nHow high-performance centralized computing\, cloud-native software development\, power management\, safety design support\, and system design and analysis are creating new opportunities for industry players and reshaping automotive design.\n\nWho Should Attend: \n\nThis free event is a terrific opportunity for design/CAD engineers\, CAD managers\, IT managers\, and business leaders seeking to optimize their design flow and technology infrastructure within the automotive industry.\n\nShare this:\n Share on LinkedIn (Opens in new window)\n LinkedIn\n \n Share on X (Opens in new window)\n X\n \n Share on Facebook (Opens in new window)\n Facebook\n Like this:Like Loading... URL:https://marketingeda.com/event/navigating-trends-and-tools-in-automotive-design-with-cadence/ CATEGORIES:EDA,Webinar ATTACH;FMTTYPE=image/jpeg:https://marketingeda.com/wp-content/uploads/Cadence-Nnovember-6-2024.jpg END:VEVENT BEGIN:VEVENT DTSTART;TZID=America/Los_Angeles:20241030T090000 DTEND;TZID=America/Los_Angeles:20241030T100000 DTSTAMP:20260410T143237 CREATED:20241016T180601Z LAST-MODIFIED:20241016T180601Z UID:8419-1730278800-1730282400@marketingeda.com SUMMARY:Verifying the next generation High Bandwidth Memory controllers for AI and HPC applications DESCRIPTION:High Bandwidth Memory (HBM) has revolutionized AI\, machine learning\, and High-Performance Computing by significantly increasing data transfer speeds and alleviating performance bottlenecks. The introduction of next-generation HBM4 is especially transformative\, enabling faster training and execution of complex AI models. JEDEC has announced that the HBM4 specification is nearing finalization. In this webinar\, you will learn how Siemens’s scalable and customizable Avery HBM Verification IP helps companies like Rambus verify their industry-leading HBM4 Controller IP through rigorous testing to ensure reliability and performance. \n\n  \nWhat You Will Learn:  \n\nWhat’s new in HBM4\nChallenges involved in verifying advanced HBM generations\nUnique features in Siemens’s HBM4 memory models\nRambus’s newly-announced HBM4 memory controller IP\n\nWho Should Attend:  \n\nDesign & Verification Engineers\, Architects\nManagers and Directors for memory controllers\n\nWhat/Which Products are Covered:   \n\nSiemens Avery HBM4 Verification IP\nRambus HBM4 Memory Controller\n\nSpeakers:\n\n\n\n\n\n\nKamlesh Mulchandani\nApplication Engineering Consultant\, Siemens EDA\n\n\n\n\nKamlesh Mulchandani is an Application Engineering Consultant at Siemens EDA. In his role as a Verification IP AE\, Kamlesh bridges the gap between Verification IP technology and customer needs through collaboration\, technical support and by tailoring Siemens solutions for specific user applications. Prior to Siemens\, Kamlesh worked at Cadence as a Memory Subsystem Design & Verification Engineer where he worked on verifying LPDDRx/DDRx & GDDRx IPs. \n\n\n\n\n\n\n\nNidish Kamath\nDirector of Product Management for Memory Interface IP\, Rambus\n\n\n\n\nNidish Kamath is the Director of Product Management for Memory Interface IP at Rambus.  He previously held marketing and product management roles at AMD\, Kioxia (formerly Toshiba Memory)\, Avalanche Technologies\, Brocade and Qualcomm\, where he worked on computational storage\, SmartNICs and GPU cluster networking solutions. He has served in various standards and industry associations such as SNIA\, Center for Open Source Software (CROSS)\, CXL Consortium\, UEC and JEDEC. \n\n\n\nShare this:\n Share on LinkedIn (Opens in new window)\n LinkedIn\n \n Share on X (Opens in new window)\n X\n \n Share on Facebook (Opens in new window)\n Facebook\n Like this:Like Loading... URL:https://marketingeda.com/event/verifying-the-next-generation-high-bandwidth-memory-controllers-for-ai-and-hpc-applications/ CATEGORIES:EDA,Webinar ATTACH;FMTTYPE=image/jpeg:https://marketingeda.com/wp-content/uploads/Siemens-October-30-2024.jpg END:VEVENT BEGIN:VEVENT DTSTART;TZID=America/Los_Angeles:20241023T090000 DTEND;TZID=America/Los_Angeles:20241023T100000 DTSTAMP:20260410T143237 CREATED:20241009T193236Z LAST-MODIFIED:20241009T193236Z UID:8402-1729674000-1729677600@marketingeda.com SUMMARY:Hardware Verification using VirtuaLAB DESCRIPTION:VirtuaLAB protocol solutions offer a full-stack testing environment with seamless connectivity and stimulus traffic generation for designs under test. It operates autonomously\, adapting to scenarios without requiring protocol knowledge from the user. VirtuaLAB significantly reduces test and compliance suite regression times\, running at high emulation speeds\, integrated with Protocol Analyzer for complete protocol visibility and performance metrics. Supporting any scenario\, it enables users to focus on their design’s unique value while ensuring reliable standard protocol interactions. \nWho Should Attend: \n\nEngineers and Managers responsible for System Design Verification of complex SoCs\nEngineers and Managers responsible for design performance verification\n\nWhat you will learn: \n\nAttendees will learn how VirtuaLAB protocol solutions provide a full stack from the physical to the application layer to connect to your design under test and create stimulus traffic as a host\, or respond to commands in the form of a compliant device.\nAttendees will learn the ease of bring-up of a VirtuaLAB environment with no testbench required\, but how to use real-world software to create workloads exactly matching the end-user of your silicon.\nAttendees will see a demonstration of VirtuaLAB running a back-to-back UFS4 host model and RTL SSD model DUT\, running the LLAMA 3.1 LLM\, and providing query responses in real-time.\n\nSpeaker:\n\n\n\n\n\n\nBen Whitehead\nDirector of Product Management\, Siemens EDA\n\n\n\n\n\nShare this:\n Share on LinkedIn (Opens in new window)\n LinkedIn\n \n Share on X (Opens in new window)\n X\n \n Share on Facebook (Opens in new window)\n Facebook\n Like this:Like Loading... URL:https://marketingeda.com/event/hardware-verification-using-virtualab/ CATEGORIES:EDA,Webinar ATTACH;FMTTYPE=image/jpeg:https://marketingeda.com/wp-content/uploads/Siemens-October-23-2024.jpg END:VEVENT BEGIN:VEVENT DTSTART;TZID=America/Los_Angeles:20241017T110000 DTEND;TZID=America/Los_Angeles:20241017T120000 DTSTAMP:20260410T143237 CREATED:20241014T214312Z LAST-MODIFIED:20241014T214312Z UID:8416-1729162800-1729166400@marketingeda.com SUMMARY:Static and Dynamic CDC Verification of AXI4 Stream-based IPs DESCRIPTION:The AXI4 Stream protocol is used as a standard interface to exchange data between connected IPs within FPGA designs. For crossing clock domains\, the AXI4 Stream interconnect is based on switches capable of transferring data to another asynchronous clock domain. The alternative solution is a dual-port AXI4 Stream IP\, capable of changing clock domains when packet routing is not required. \nStatic and dynamic clock domain crossing (CDC) verification methods complement each other to ensure flawless operation of multi-clock designs. ALDEC_CDC rules plugin contains 58 rules for checking design quality\, design constraints\, and clock and reset trees. It is also used for validating design synchronization circuits. However\, static CDC verification methods alone may not guarantee the completeness of the CDC verification task. Dynamic CDC verification is crucial. The two main methods for dynamic CDC verification are checking with CDC assertions and modeling of random delay insertion on clock domain crossings.\n\nIn this webinar\, we will introduce both static and dynamic verification methods for CDC verification of AXI4 Stream-based IPs. We will discuss the CDC assertions that are auto-generated from ALINT-PRO\, and we will also demonstrate the design and usage of the synchronizer models with random delay insertion.\n\nAgenda:\n\nCDC verification process overview\n\nStatic CDC verification checks\nAssertions usage in CDC verification\nThe concept of delay randomization at CDC crossing in functional simulation\n\n\nAXI Stream protocol overview\nAXI CDC Port Verification\n\nRunning CDC static checks with ALINT-PRO\nGeneration SV Assertion with ALINT-PRO\nDeveloping the testbench for AXI CDC Port dynamic verification\nSimulating design with generated CDC assertions\nSimulating design with random delay insertion in synchronizer models\n\n\nConclusion\nQ&A\n\n\nWebinar Duration\n\n45 min presentation/live demo\n\nBio: \nAlex Gnusin\, Aldec’s ALINT-PRO Product Manager \nAlex accumulated 27 years of hands-on experience in various aspects of ASIC and FPGA design and verification. As a verification prime for a multi-million gates project in companies such as IBM\, Nortel\, Ericsson and Synopsys Inc\, he combined various verification methods such as static linting\, formal property checking\, dynamic simulation and hardware-assisted acceleration to efficiently achieve design verification goals. He received his M.S. in Electronics from Technion\, Israel Institute of Technology. \nShare this:\n Share on LinkedIn (Opens in new window)\n LinkedIn\n \n Share on X (Opens in new window)\n X\n \n Share on Facebook (Opens in new window)\n Facebook\n Like this:Like Loading... URL:https://marketingeda.com/event/static-and-dynamic-cdc-verification-of-axi4-stream-based-ips/ CATEGORIES:EDA,IP,Webinar ATTACH;FMTTYPE=image/jpeg:https://marketingeda.com/wp-content/uploads/Aldec-October-17-2024.jpg END:VEVENT BEGIN:VEVENT DTSTART;TZID=America/Los_Angeles:20241015T100000 DTEND;TZID=America/Los_Angeles:20241015T110000 DTSTAMP:20260410T143237 CREATED:20241008T164139Z LAST-MODIFIED:20241008T164139Z UID:8399-1728986400-1728990000@marketingeda.com SUMMARY:ARM corelink\, Arteris NoC\, UCIe\, Bunch-of-wires\, CXL and PCIe- Designing the interconnect is not for the weak-hearted DESCRIPTION:There are so many options for Network-on-Chip: ARM-Corelink CMN700\, Arteris FlexNoC\, open-source NoC interconnect\, and of course developing home-grown fully customized solutions. Where does each solution fit? Where do we use it- backplane vs inside domains? How does AMBA AXI or PCIe or CXL fit in the mix? With the advent of chiplet\, do we go with UCIe or bunch-of-wires. Where do we locate the DRAM and the task scheduler? Lots of questions need to be answered before the SoC or chiplets can be implemented. \nIn this Webinar\, we will take the mystery out of these architecture decisions by demonstrating how system modeling can provide quantitative metrics to validate and optimize these requirements. For this purpose we will use the mapping of a CNN- Resnet 50 on an AI processor\, Open Architecture Management (OAM) system\, heterogeneous compute SoC-FPGA and development of a custom NoC. \nTo measure the quality of the design\, we will show the running of standard and synthetic workloads. Quantitative metrics generated will include latency\, throughput\, buffer occupancy\, peak power consumed\, heat generated\, cache hit-miss and memory bandwidth. We will also show how the source of bottlenecks can be identified. The design can be experimented with different routing schemes\, schedulers\, buffer size\, clock speeds\, flits\, clock domains\, flow control credit and quality-of-service. \nShare this:\n Share on LinkedIn (Opens in new window)\n LinkedIn\n \n Share on X (Opens in new window)\n X\n \n Share on Facebook (Opens in new window)\n Facebook\n Like this:Like Loading... URL:https://marketingeda.com/event/arm-corelink-arteris-noc-ucie-bunch-of-wires-cxl-and-pcie-designing-the-interconnect-is-not-for-the-weak-hearted/ CATEGORIES:EDA,IP,Webinar ATTACH;FMTTYPE=image/jpeg:https://marketingeda.com/wp-content/uploads/Mirabilis-October-15-2024.jpg END:VEVENT END:VCALENDAR