BEGIN:VCALENDAR
VERSION:2.0
PRODID:-//Marketing EDA - ECPv6.17.5//NONSGML v1.0//EN
CALSCALE:GREGORIAN
METHOD:PUBLISH
X-ORIGINAL-URL:https://marketingeda.com
X-WR-CALDESC:Events for Marketing EDA
REFRESH-INTERVAL;VALUE=DURATION:PT1H
X-Robots-Tag:noindex
X-PUBLISHED-TTL:PT1H
BEGIN:VTIMEZONE
TZID:America/Los_Angeles
BEGIN:DAYLIGHT
TZOFFSETFROM:-0800
TZOFFSETTO:-0700
TZNAME:PDT
DTSTART:20220313T100000
END:DAYLIGHT
BEGIN:STANDARD
TZOFFSETFROM:-0700
TZOFFSETTO:-0800
TZNAME:PST
DTSTART:20221106T090000
END:STANDARD
BEGIN:DAYLIGHT
TZOFFSETFROM:-0800
TZOFFSETTO:-0700
TZNAME:PDT
DTSTART:20230312T100000
END:DAYLIGHT
BEGIN:STANDARD
TZOFFSETFROM:-0700
TZOFFSETTO:-0800
TZNAME:PST
DTSTART:20231105T090000
END:STANDARD
BEGIN:DAYLIGHT
TZOFFSETFROM:-0800
TZOFFSETTO:-0700
TZNAME:PDT
DTSTART:20240310T100000
END:DAYLIGHT
BEGIN:STANDARD
TZOFFSETFROM:-0700
TZOFFSETTO:-0800
TZNAME:PST
DTSTART:20241103T090000
END:STANDARD
BEGIN:DAYLIGHT
TZOFFSETFROM:-0800
TZOFFSETTO:-0700
TZNAME:PDT
DTSTART:20250309T100000
END:DAYLIGHT
BEGIN:STANDARD
TZOFFSETFROM:-0700
TZOFFSETTO:-0800
TZNAME:PST
DTSTART:20251102T090000
END:STANDARD
END:VTIMEZONE
BEGIN:VTIMEZONE
TZID:America/New_York
BEGIN:DAYLIGHT
TZOFFSETFROM:-0500
TZOFFSETTO:-0400
TZNAME:EDT
DTSTART:20230312T070000
END:DAYLIGHT
BEGIN:STANDARD
TZOFFSETFROM:-0400
TZOFFSETTO:-0500
TZNAME:EST
DTSTART:20231105T060000
END:STANDARD
BEGIN:DAYLIGHT
TZOFFSETFROM:-0500
TZOFFSETTO:-0400
TZNAME:EDT
DTSTART:20240310T070000
END:DAYLIGHT
BEGIN:STANDARD
TZOFFSETFROM:-0400
TZOFFSETTO:-0500
TZNAME:EST
DTSTART:20241103T060000
END:STANDARD
BEGIN:DAYLIGHT
TZOFFSETFROM:-0500
TZOFFSETTO:-0400
TZNAME:EDT
DTSTART:20250309T070000
END:DAYLIGHT
BEGIN:STANDARD
TZOFFSETFROM:-0400
TZOFFSETTO:-0500
TZNAME:EST
DTSTART:20251102T060000
END:STANDARD
END:VTIMEZONE
BEGIN:VTIMEZONE
TZID:Europe/Paris
BEGIN:DAYLIGHT
TZOFFSETFROM:+0100
TZOFFSETTO:+0200
TZNAME:CEST
DTSTART:20230326T010000
END:DAYLIGHT
BEGIN:STANDARD
TZOFFSETFROM:+0200
TZOFFSETTO:+0100
TZNAME:CET
DTSTART:20231029T010000
END:STANDARD
BEGIN:DAYLIGHT
TZOFFSETFROM:+0100
TZOFFSETTO:+0200
TZNAME:CEST
DTSTART:20240331T010000
END:DAYLIGHT
BEGIN:STANDARD
TZOFFSETFROM:+0200
TZOFFSETTO:+0100
TZNAME:CET
DTSTART:20241027T010000
END:STANDARD
BEGIN:DAYLIGHT
TZOFFSETFROM:+0100
TZOFFSETTO:+0200
TZNAME:CEST
DTSTART:20250330T010000
END:DAYLIGHT
BEGIN:STANDARD
TZOFFSETFROM:+0200
TZOFFSETTO:+0100
TZNAME:CET
DTSTART:20251026T010000
END:STANDARD
END:VTIMEZONE
BEGIN:VTIMEZONE
TZID:Europe/London
BEGIN:DAYLIGHT
TZOFFSETFROM:+0000
TZOFFSETTO:+0100
TZNAME:BST
DTSTART:20230326T010000
END:DAYLIGHT
BEGIN:STANDARD
TZOFFSETFROM:+0100
TZOFFSETTO:+0000
TZNAME:GMT
DTSTART:20231029T010000
END:STANDARD
BEGIN:DAYLIGHT
TZOFFSETFROM:+0000
TZOFFSETTO:+0100
TZNAME:BST
DTSTART:20240331T010000
END:DAYLIGHT
BEGIN:STANDARD
TZOFFSETFROM:+0100
TZOFFSETTO:+0000
TZNAME:GMT
DTSTART:20241027T010000
END:STANDARD
BEGIN:DAYLIGHT
TZOFFSETFROM:+0000
TZOFFSETTO:+0100
TZNAME:BST
DTSTART:20250330T010000
END:DAYLIGHT
BEGIN:STANDARD
TZOFFSETFROM:+0100
TZOFFSETTO:+0000
TZNAME:GMT
DTSTART:20251026T010000
END:STANDARD
END:VTIMEZONE
BEGIN:VTIMEZONE
TZID:America/Chicago
BEGIN:DAYLIGHT
TZOFFSETFROM:-0600
TZOFFSETTO:-0500
TZNAME:CDT
DTSTART:20230312T080000
END:DAYLIGHT
BEGIN:STANDARD
TZOFFSETFROM:-0500
TZOFFSETTO:-0600
TZNAME:CST
DTSTART:20231105T070000
END:STANDARD
BEGIN:DAYLIGHT
TZOFFSETFROM:-0600
TZOFFSETTO:-0500
TZNAME:CDT
DTSTART:20240310T080000
END:DAYLIGHT
BEGIN:STANDARD
TZOFFSETFROM:-0500
TZOFFSETTO:-0600
TZNAME:CST
DTSTART:20241103T070000
END:STANDARD
BEGIN:DAYLIGHT
TZOFFSETFROM:-0600
TZOFFSETTO:-0500
TZNAME:CDT
DTSTART:20250309T080000
END:DAYLIGHT
BEGIN:STANDARD
TZOFFSETFROM:-0500
TZOFFSETTO:-0600
TZNAME:CST
DTSTART:20251102T070000
END:STANDARD
END:VTIMEZONE
BEGIN:VTIMEZONE
TZID:UTC
BEGIN:STANDARD
TZOFFSETFROM:+0000
TZOFFSETTO:+0000
TZNAME:UTC
DTSTART:20220101T000000
END:STANDARD
END:VTIMEZONE
BEGIN:VEVENT
DTSTART;TZID=America/Los_Angeles:20240215T110000
DTEND;TZID=America/Los_Angeles:20240215T120000
DTSTAMP:20240202T185233Z
CREATED:20240202T185233Z
LAST-MODIFIED:20240202T185233Z
UID:7574-1707994800-1707998400@marketingeda.com
SUMMARY:Essential Steps to Simplify VHDL Testbenches Using OSVVM
DESCRIPTION:This “Getting Started” webinar focuses on the first\, essential steps you need to take when looking to improve your VHDL testbench approach. In this webinar we examine transaction-based testing\, self-checking tests\, messaging\, reports\, and Open Source VHDL Verification Methodology (OSVVM) helper utilities. \n  \nThe “transaction” in transaction-based testing is just a fancy word for an abstraction that represents a single action on an interface – such as a Send or Get on a streaming interface. We will look at alternatives in implementing transactions – including using OSVVM’s Model Independent Transaction library. Using transactions is important because they accelerate test case development\, increase reuse\, and reduce maintenance costs. \n  \nSelf-checking is essential in test cases as checking waveform output manually is time consuming\, error prone\, and soul-crushingly boring. Self-checking involves counting errors and using the count to create a pass/fail report when the test is completed. If we use signals (and there may be a collection\, some of which might be in a different entity) we will need to sum them up and generate an error report. However\, it is easy to forget one and give a false pass condition. OSVVM simplifies error counting and makes it reliable by creating a data structure in a package and using it to track the multitude of error sources. The pass/fail report is created by looking at the entire data structure for errors – so nothing is missed. We can even track and report separate sources of errors – such as different interfaces. \n  \nMessaging (a.k.a. verbosity control) is about creating detailed informational messages when we are debugging and just pass/fail messages when running regressions. Since the messages may be generated by different entities\, we need controls that have a wide scope. Furthermore\, we may want to control different sources of messages independently. OSVVM simplifies the control of log messages (enable/disable) using the same data structure we use for tracking errors. \n  \nTest reports are about quickly finding which tests in a suite of tests failed and why. OSVVM creates two levels of test reports. The OSVVM build summary report gives a summary of the pass/fail status of each separate test case that was run\, and the OSVVM test case report provides details on the self-checking\, functional coverage\, and scoreboard/FIFO usage for each test case. When running sets of tests (such as during regression testing)\, these reports help us quickly find which test cases failed and why. \n  \nThe OSVVM helper utilities target simplifying testbench development with capabilities that include clock generation\, reset generation and test case development with synchronization utilities such as WaitForClock and WaitForBarrier. \n  \nAbout OSVVM \nOSVVM is a suite of libraries that allows any VHDL engineer to write VHDL testbenches and test cases for both simple unit/RTL level tests and complex\, randomized full chip or system level tests. OSVVM is developed by VHDL experts who actively contribute to VHDL standards development to provide VHDL with verification capabilities that rival SystemVerilog + UVM.\nGetting your entire team united in using OSVVM will simplify deploying VHDL engineers to projects. Why VHDL for verification? According to the 2022 Wilson Research Group Functional Verification Study\, in the FPGA market\, 66% use VHDL for design\, 58% use VHDL for verification\, and 28% use OSVVM. Hence\, VHDL is #1 for FPGA development and OSVVM is #1 for VHDL verification. \n  \nWebinar Duration: \n\n45 min presentation/live demo\n10 min Q&A\n\n  \nPresenter BIO \nJim Lewis is an innovator and leader in the VHDL community. He has 30 plus years of design and teaching experience. He is the Chair of the IEEE 1076 VHDL Standards Working Group. He is a co-founder of the Open Source VHDL Verification Methodology (OSVVM) and the chief architect of the packages and methodology. He is an expert VHDL trainer for SynthWorks Design Inc. In his design practice\, he has created designs for print servers\, IMA E1/T1 networking\, fighter jets\, video phones\, and spacecraft.\nWhether teaching\, developing OSVVM\, consulting on VHDL design and verification projects\, or working on the IEEE VHDL standard\, Jim brings a deep understanding of VHDL to architect solutions that solve difficult problems in simple ways.
URL:https://marketingeda.com/event/essential-steps-to-simplify-vhdl-testbenches-using-osvvm/
CATEGORIES:EDA,Webinar
ATTACH;FMTTYPE=image/jpeg:https://marketingeda.com/wp-content/uploads/Aldec-February-15-2024.jpg
END:VEVENT
BEGIN:VEVENT
DTSTART;TZID=America/New_York:20240213T110000
DTEND;TZID=America/New_York:20240213T120000
DTSTAMP:20240206T191819Z
CREATED:20240206T191819Z
LAST-MODIFIED:20240206T191819Z
UID:7581-1707822000-1707825600@marketingeda.com
SUMMARY:Introducing Ansys AI: A New Chapter in Engineering Simulation
DESCRIPTION:Join us to learn more about the AI and Simulation Revolution in this upcoming webinar. We’re revolutionizing engineering simulation with the power of Artificial Intelligence with SimAI\, AnsysGPT\, and Ansys AI+. \nOverview\nAt Ansys\, we are revolutionizing engineering simulation with the power of Artificial Intelligence. Our AI-augmented simulation technology is a game-changer\, bringing unprecedented speed\, innovation\, and accessibility to the engineering world. With Ansys AI\, we enable product engineers to leverage their previous simulation and measurement data to reliably assess the performance of new designs in minutes instead of hours. We are not just accelerating simulations but transforming how engineers work\, making simulation simple\, natural\, and accessible. \nWhat you will learn\n\nFirst\, we’ll introduce Ansys SimAI\, a machine learning platform for engineers who must rapidly explore and predict the performance of new concepts across design phases. SimAI provides reliable and fast results\, accessible through user-friendly cloud-native application\, targeting a broad engineering audience that includes all simulation engineers and designers.\nSecond\, we’ll showcase the AnsysGPT chatbot\, which re-imagines the user and support experience through simple\, natural language interaction.\nFinally\, we’ll demonstrate how Ansys AI+ add-ons augment the product capabilities across the Ansys collection\, starting with optiSLang AI+ and Granta MI AI+.\n\nWho should attend\nCAE/CAD Engineers / Designers / Simulation Analyst / Engineers\, Computation Engineers \nSpeaker\nIlya Tolchinsky
URL:https://marketingeda.com/event/introducing-ansys-ai-a-new-chapter-in-engineering-simulation/
CATEGORIES:EDA,Webinar
ATTACH;FMTTYPE=image/jpeg:https://marketingeda.com/wp-content/uploads/Ansys-February-13-2024-1.jpg
END:VEVENT
BEGIN:VEVENT
DTSTART;TZID=Europe/Paris:20240213T100000
DTEND;TZID=Europe/Paris:20240213T110000
DTSTAMP:20240205T215030Z
CREATED:20240205T215030Z
LAST-MODIFIED:20240205T215030Z
UID:7578-1707818400-1707822000@marketingeda.com
SUMMARY:Power Innovations in Consumer Electronics Using LF EM Solutions
DESCRIPTION:This webinar will cover how the Ansys simulation tools are now widely used in many low-frequency (LF) EM applications\, such as wireless charging\, power supplies\, transformers\, magnetic latches and actuators\, PCB/ECAD\, and more. Discover how Ansys Maxwell enables rapid and accurate simulation of EM fields in electronic and consumer devices to reduce design iterations\, component footprint\, size\, and time to market. \n\n\n\n\nWhat You Will Learn\n\nComponent design considerations for consumer electronics devices (i.e.\,smartphones\, tablets\, watches\, earbuds\, and digital cameras)\nAnsys Maxwell solution for EM component design\nNew Maxwell capabilities for PCB and ECAD\nMultiphysics workflows for coupling EM with structural/kinematic\, NVH\, and thermal for comprehensive product design\n\nWho should attend?\nPCB Designers\, Consumer Electronics Engineers\, Systems Engineers\, Power Solutions Engineers\, SI/PI Engineers\, Product Design Engineers\, Power Module Engineers \nSpeakers\nIrene Woyna
URL:https://marketingeda.com/event/power-innovations-in-consumer-electronics-using-lf-em-solutions/
CATEGORIES:EDA,Webinar
ATTACH;FMTTYPE=image/jpeg:https://marketingeda.com/wp-content/uploads/Ansys-February-13-2024.jpg
END:VEVENT
BEGIN:VEVENT
DTSTART;TZID=America/Los_Angeles:20240208T100000
DTEND;TZID=America/Los_Angeles:20240208T110000
DTSTAMP:20240122T184006Z
CREATED:20240122T183940Z
LAST-MODIFIED:20240122T184006Z
UID:7546-1707386400-1707390000@marketingeda.com
SUMMARY:Seamless SI/PI Signoff of Allegro PCB Designs Driven by In-Design Analysis
DESCRIPTION:Signal and power integrity (SI/PI) are top priorities for engineers designing today’s high-speed\, high-density PCBs. Easy-to-use in-design analysis directly integrated into the Allegro PCB design environment uncovers SI/PI issues early in the design process\, leading to faster signoff of designs. With analysis shifting left in the design cycle\, design teams can achieve efficient signoff of high-speed PCB designs that include complex power delivery networks\, gigabit-speed serializer/deserializer (SerDes)\, and the latest double-data rate (DDR) memory interfaces. \nLearn about three key issues that engineers must overcome to sign off on high-speed PCB designs: serial link compliance (SerDes)\, power analysis\, and DDR memory interface compliance. We will demonstrate how Cadence’s PCB design methodology\, including Sigrity Aurora\, Sigrity SystemSI\, and Allegro technologies\, empowers EEs to create successful products on time and on budget.\nAttendees will learn to address: \n\nSerDes compliance\nPower analysis\nDDR memory interface compliance
URL:https://marketingeda.com/event/seamless-si-pi-signoff-of-allegro-pcb-designs-driven-by-in-design-analysis/
CATEGORIES:EDA,Webinar
ATTACH;FMTTYPE=image/jpeg:https://marketingeda.com/wp-content/uploads/Cadence-February-8-2024.jpg
END:VEVENT
BEGIN:VEVENT
DTSTART;TZID=America/Los_Angeles:20240208T100000
DTEND;TZID=America/Los_Angeles:20240208T103000
DTSTAMP:20240118T213134Z
CREATED:20240118T213134Z
LAST-MODIFIED:20240118T213134Z
UID:7526-1707386400-1707388200@marketingeda.com
SUMMARY:Power Devices SPICE Modeling for Si\, GaN and SiC Technologies
DESCRIPTION:We start by examining the different technologies used in the manufacturing of power devices\, including Si\, GaN\, and SiC\, considering their respective particularities and advantages.\nWe will then analyze various approaches to the SPICE modeling of power devices\, including compact models and macromodels.\nA significant portion of our presentation will be dedicated to the topic of power FET modeling. In particular we will illustrate how to properly address its specific bias-dependent capacitances and how to deal with model tuning based on dynamic characteristics.\nFinally\, we will share some of our expertise in dealing with the unique challenges of power devices\, including parasitic elements and model accuracy. \nWhat You Will Learn\n\nSPICE models for GaN and SiC FET\nModeling power FET-specific capacitances\nGeneral power FET model extraction methodology\nAdvantages of TCAD-based SPICE modeling\nSPICE modeling examples of Si\, GaN\, and SiC devices\n\n\n\n\n\n\nPresenter\n\n\n\n\nBogdan Tudor\, Senior Manager\, Device Characterization \nBogdan Tudor is Head of Device Characterization for Silvaco\, leading the Utmost and Modeling Service teams. He has over 20 years of experience in model development and characterization software. \n\n\n\n\n\nWHO SHOULD ATTEND:\n\n\n\n\nSemiconductor Device and Process engineers\, product managers\, and engineering management.
URL:https://marketingeda.com/event/power-devices-spice-modeling-for-si-gan-and-sic-technologies/
CATEGORIES:EDA,Webinar
ATTACH;FMTTYPE=image/jpeg:https://marketingeda.com/wp-content/uploads/Silvaco-February-8-2024.jpg
END:VEVENT
BEGIN:VEVENT
DTSTART;TZID=America/New_York:20240207T090000
DTEND;TZID=America/New_York:20240207T100000
DTSTAMP:20240202T014858Z
CREATED:20240202T014858Z
LAST-MODIFIED:20240202T014858Z
UID:7571-1707296400-1707300000@marketingeda.com
SUMMARY:Design Exploration of RF GaN Amplifier\, 3D Packaging\, and Thermal Analysis
DESCRIPTION:Join us for this webinar on RF GaN amplifier design using electromagnetic/thermal 3D solvers. We will discuss the step-by-step process of building a GaN amplifier\, beginning with the transistor model in the circuit simulator. The webinar will outline the steps required to convert this to a physical layout for electromagnetic simulation and verification while integrating packaging and thermal effects co-simulation to analyze a complete packaged system. Discover how this comprehensive approach yields innovative solutions\, important design insights\, and their potential impact on packaged performance. \nTime:\nFebruary 7\, 2024\n9 AM EST / 3 PM CET / 7:30 PM IST \nVenue:\nDigital
URL:https://marketingeda.com/event/design-exploration-of-rf-gan-amplifier-3d-packaging-and-thermal-analysis/
CATEGORIES:EDA,Webinar
ATTACH;FMTTYPE=image/jpeg:https://marketingeda.com/wp-content/uploads/Ansys-Feb-7-2024.jpg
END:VEVENT
BEGIN:VEVENT
DTSTART;TZID=Europe/London:20240206T120000
DTEND;TZID=Europe/London:20240206T130000
DTSTAMP:20240102T172514Z
CREATED:20240102T172514Z
LAST-MODIFIED:20240102T172514Z
UID:7487-1707220800-1707224400@marketingeda.com
SUMMARY:DVClub Europe: Verifying Safety in Automotive
DESCRIPTION:Hardware designs intended for the automotive domain need to implement safety mechanisms to minimize the risk of accidents and injuries caused by hardware-related issues in vehicles. In this DVClub we will cover how those safety mechanisms need to be verified to be compliant with ISO26262\, the international standard covering automotive safety. \nAgenda (GMT) \n12:00 Welcome and Introduction – Mike Bartley\, Tessolve \n12:00 Hans Leo\, CPS Safety Academy GmbH \n12:30 TBD \n12:45 TBD \n13:00 Close \n  \nAdditional Information\nFor additional information please visit the Tessolve DVClub Europe webpage for this event.\n \nSponsors\nDVClub Europe is made possible through the generous support of our sponsors: TBD. \nTessolve reserves the right to cancel registration at its discretion.
URL:https://marketingeda.com/event/dvclub-europe-verifying-safety-in-automotive/
CATEGORIES:Webinar
ATTACH;FMTTYPE=image/jpeg:https://marketingeda.com/wp-content/uploads/DVClub-6-Feb-2024.jpg
END:VEVENT
BEGIN:VEVENT
DTSTART;TZID=America/Los_Angeles:20240206T100000
DTEND;TZID=America/Los_Angeles:20240206T110000
DTSTAMP:20240116T175320Z
CREATED:20240116T175320Z
LAST-MODIFIED:20240116T175320Z
UID:7520-1707213600-1707217200@marketingeda.com
SUMMARY:Functional Verification workflow for Trusted and Assured Microelectronics
DESCRIPTION:In a world of increasing trust and assurance challenges for microelectronic devices\, emerging industry standards and defense policy demand early and advanced functional verification methods before ICs may be deployed in critical end products and systems. Questa technologies\, built upon a foundation of world-class simulation and formal engines\, provide the results desired for raising and meeting higher levels of trust and assurance for microelectronic designs. In this presentation\, we will introduce apps that provide advanced automated functional checking\, secure data path verification\, trustworthiness assessment\, and equivalence checking for extending the foundation of functional verification to attack the complex IC integrity challenges of today. \n  \nWhat You Will Learn: \n\nHow to identify security threats and vulnerabilities in your ASIC/FPGA microelectronic designs\nHow to identify and mitigate Common Weakness Enumeration (CWE) threats in your ASIC/FPGA designs\nHow to meet reporting requirements for your Trust and Assurance verification\n\nWho Should Attend: \n\nHardware Assurance & Security Experts\nSystems Engineers\nASIC\, FPGA & Program Manager\nDesign & Verification Engineers\n\n  \nWhat/Which Products are Covered:  \n\nQuesta Inspect\nQuesta Verify Secure\nQuesta Verify Trust\nQuesta Equivalent FPGA\n\n\n\nSpeaker:\n\n\n\n\n\n\nJohn Hallman\nAerospace and Defense Solutions Manager\, Siemens EDA\n\n\n\n\nMr. John Hallman is the Aerospace and Defense Solutions Manager with Siemens EDA focusing on verification workflows for A&D customers. His experience spans multiple defense industrial base organizations and EDA companies and includes ASIC/FPGA design\, verification\, application of formal technologies\, and microelectronics trustworthiness research. Today his responsibilities include enabling the development of automated tools for Trust and Assurance\, as well as enhancing productivity for the defense workforce. John is active in several organizations\, such as SAE\, IEEE\, and NDIA\, and has interests in numerous standards activities that raise the bar for microelectronic trust\, assurance and security.
URL:https://marketingeda.com/event/functional-verification-workflow-for-trusted-and-assured-microelectronics/
CATEGORIES:EDA,Webinar
ATTACH;FMTTYPE=image/jpeg:https://marketingeda.com/wp-content/uploads/Siemens-February-6-2024.jpg
END:VEVENT
BEGIN:VEVENT
DTSTART;TZID=America/Los_Angeles:20240125T110000
DTEND;TZID=America/Los_Angeles:20240125T120000
DTSTAMP:20240122T173407Z
CREATED:20240122T173407Z
LAST-MODIFIED:20240122T173407Z
UID:7533-1706180400-1706184000@marketingeda.com
SUMMARY:Verifying AXI Interconnects with ALINT-PRO and Riviera-PRO
DESCRIPTION:AXI has become the most popular internal bus protocol with today’s FPGA and SoC FPGA designs. ALINT-PRO enables FPGA designers to extract\, review and statically verify AXI bus interfaces. In addition\, ALINT-PRO can assist with automatic generation of test harnesses for dynamic verification. For dynamic verification of AXI interconnects\, Aldec provides FPGA vendor-agnostic AXI Bus Functional Models (BFM) as well as Riviera-PRO functional verification platform. \nIn this webinar\, we will present AXI bus interface extraction and static verification with ALINT-PRO. Then\, we will show how ALINT-PRO assists in test harness wrapper generation for dynamic verification with Riviera-PRO. Finally\, we will show the usage of Aldec AXI BFM solution for dynamic interconnect verification. \nAgenda: \n\nBus interfaces extraction\nBus interfaces static verification \nTest harness development (script-based) \nAldec AXI BFM overview\nDynamic verification of AXI interconnect design using Aldec AXI BFM and Riviera-PRO\nLive demo\nConclusion\nQ&A\n\nWebinar Duration \n\n45 min presentation/live demo\n15 min Q&A\n\nPresenter \n\nBio: \nAlex accumulated 27 years of hands-on experience in various aspects of ASIC and FPGA design and verification. As a verification prime for a multi-million gates project in companies such as IBM\, Nortel\, Ericsson and Synopsys Inc\, he combined various verification methods such as static linting\, formal property checking\, dynamic simulation and hardware-assisted acceleration to efficiently achieve design verification goals. He received his M.S. in Electronics from Technion\, Israel Institute of Technology.
URL:https://marketingeda.com/event/verifying-axi-interconnects-with-alint-pro-and-riviera-pro/
CATEGORIES:EDA,Webinar
ATTACH;FMTTYPE=image/jpeg:https://marketingeda.com/wp-content/uploads/Aldec-January-252024.jpg
END:VEVENT
BEGIN:VEVENT
DTSTART;TZID=America/Los_Angeles:20240125T100000
DTEND;TZID=America/Los_Angeles:20240125T110000
DTSTAMP:20240111T184907Z
CREATED:20240111T184907Z
LAST-MODIFIED:20240111T184907Z
UID:7512-1706176800-1706180400@marketingeda.com
SUMMARY:Validating Clarity 3D Solver Accuracy Through Measurement Correlation
DESCRIPTION:Cadence’s Clarity 3D Solver is an industry-leading EM simulation platform used by hundreds of design teams to address signal and power integrity (SI/PI) challenges. By solving bigger problems on more efficient compute resources\, Clarity 3D Solver users have reimagined what can be done with 3D finite element method (FEM) solver technology. However\, EM extraction results to 50GHz and beyond require correlation to lab measurement. \n\nThis webinar presents a case study that shares the experience and best practices for achieving measurement-to-simulation correlation with Clarity based on the Wild River CMP-50 IEEE P370 compliant test fixture\, where lab measurements have been taken from DC to 50GHz. Topics covered include material property identification\, correlation challenges\, the influence of connector models\, manufacturing tolerance/variation\, and more. \n\nThe audience will learn: \n\nBest practices for using Clarity to achieve measurement-to-simulation correlation\nCase study using the Wild River CMP-50 IEEE P370 compliant test fixture with lab measurements from DC to 50GHz\nExplanation of material property identification\, correlation challenges\, influence of connector models\, manufacturing tolerance/variation\, and more
URL:https://marketingeda.com/event/validating-clarity-3d-solver-accuracy-through-measurement-correlation/
CATEGORIES:EDA,Webinar
ATTACH;FMTTYPE=image/jpeg:https://marketingeda.com/wp-content/uploads/Cadence-January-25-2024.jpg
END:VEVENT
BEGIN:VEVENT
DTSTART;TZID=America/Los_Angeles:20240125T090000
DTEND;TZID=America/Los_Angeles:20240125T100000
DTSTAMP:20231227T171414Z
CREATED:20231227T171414Z
LAST-MODIFIED:20231227T171414Z
UID:7455-1706173200-1706176800@marketingeda.com
SUMMARY:Releasing All Potential of RISC-V: Total Solutions of Andes Core Processors Series
DESCRIPTION:Join us for an engaging webinar as we delve into the boundless possibilities of RISC-V architecture with a focus on the comprehensive Total Solutions offered by the Andes Series. Explore how these cutting-edge RISC-V CPU cores are reshaping the landscape of computing\, powering innovations across diverse applications such as automotive and AI. Our experts will guide you through the features\, advantages\, and real-world applications of the Andes Series\, showcasing its ability to unlock the full potential of RISC-V technology. Whether you’re in the automotive industry or the AI sector\, this webinar is your gateway to understanding how Andes Series Total Solutions can elevate your projects to new heights. Don’t miss this opportunity to stay at the forefront of RISC-V advancements and explore the unlimited possibilities that lie ahead!
URL:https://marketingeda.com/event/releasing-all-potential-of-risc-v-total-solutions-of-andes-core-processors-series/
CATEGORIES:IP,Webinar
ATTACH;FMTTYPE=image/jpeg:https://marketingeda.com/wp-content/uploads/Andes-January-25-2024.jpg
END:VEVENT
BEGIN:VEVENT
DTSTART;TZID=America/Los_Angeles:20240124T090000
DTEND;TZID=America/Los_Angeles:20240124T100000
DTSTAMP:20240117T174723Z
CREATED:20240117T174723Z
LAST-MODIFIED:20240117T174723Z
UID:7523-1706086800-1706090400@marketingeda.com
SUMMARY:Introducing OrCAD X\, Our Next-Generation PCB Layout Solution
DESCRIPTION:Whether you’re a beginner or a seasoned engineer\, this webinar is a must-watch for anyone in the electronic design space. Join us to discuss how you can accelerate your PCB design process with our new and improved OrCAD X layout environment. \n\nLearn how you can: \n\nDesign with an intuitive UI\nCollaborate using design review and markup\nUse the new and improved 3D engine\nVisualize and set up of 3D DRCs\nSet up and navigate to flex regions\nUse dynamic shapes\nSave time generating manufacturing documentation with LiveDOC\n\n\nSpeaker: John Carney\, Product Engineering Architect\, Cadence \nHost: Supreeth Mannava\, Senior Principal Product Manager\, Cadence
URL:https://marketingeda.com/event/introducing-orcad-x-our-next-generation-pcb-layout-solution/
CATEGORIES:EDA,Webinar
ATTACH;FMTTYPE=image/png:https://marketingeda.com/wp-content/uploads/Cadence-January-24-2024.png
END:VEVENT
BEGIN:VEVENT
DTSTART;TZID=America/Los_Angeles:20240124T080000
DTEND;TZID=America/Los_Angeles:20240124T090000
DTSTAMP:20240103T173109Z
CREATED:20240103T173109Z
LAST-MODIFIED:20240103T173109Z
UID:7496-1706083200-1706086800@marketingeda.com
SUMMARY:Comprehensive PCIe Verification Solution for bleeding edge and mission critical SoC & IP Designs
DESCRIPTION:Applications such as Data Centers\, High-Performance computing (HPC)\, artificial intelligence/machine learning (AI/ML)\, cloud computing\, military\, and aerospace\, automotive\, etc. are all extremely Bandwidth-hungry. To cater to such high demands of high speeds and bandwidth requires a breakthrough that HPC SoCs are constantly facing. High speed interfaces like PCI Express® (PCIe®) 5.0 and 6.0 show promising results for compute intensive applications. Every successive generation of PCIe has doubled the bandwidth of the previous generation for e.g. PCIe 6.0\, delivers double the bandwidth (64GT/s) of its predecessor i.e.\, PCIe 5.0 (32GT/s). \nCome join us to learn: \n1. How PCIe 6.0 can deliver such high data transfer rate of up to 64 GT/s per pin \n2. Design considerations for PCIe 5.0 and 6.0 design IPs \n3. Why verifying features such as Integrity and data encryption are critical. \n4. Why industry leading PCIe design IPs companies trust us and how stay ahead of the curve \n5. Reaching coverage closure faster through Compliance  Testsuites \n6. What’s next for PCIe. \nWe will also discuss how you can stay ahead in the market in verifying the most advanced and critical features of PCIe 6.0 and 5.0 for your design IPs. \n  \nWhat You Will Learn: \n\nOverview of PCIe Verification\nDesign and verification considerations when planning a new PCIe project specially around PCIe Gen5 or Gen6\nUnique features to Siemens Avery PCIe Verification IP and its Compliance Test Suite:\n\nTestbench Creation and easy bring-up. \nRun time Configurations. \nTraffic Generation \nError Injection \nDebug features \nVarious applications and use-cases \n\nChallenges involved in verifying advanced PCIe Generations\nTechnical Demonstration\n\nWho Should Attend: \n\nDesign & Verification Engineers\, Architects.\nManagers\, Directors\, Key Decision Makers.\n\n  \nWhat/Which Products are Covered:  \n\nVerification IP\, SV/UVM\, PCIe\, PCIe Compliance Test Suite\, QuestaSim & Visualizer\n\n\n\nSpeakers:\n\n\n\n\n\n\nLuis E. Rodriguez\nSiemens EDA\n\n\n\n\nLuis E. Rodriguez has worked on SoC and IP functional verification for over 17 years including developing and deploying PCIe\, CXL\, NVMe\, and UCIe Verification IPs. He has participated and contributed to several protocol workgroups like PCIe\, CCIX\, GENZ (Compliance Workgroup chair); and CXL\, where he helped define Compliance Testing for CXL 2.0.  At Siemens he is focused on the architecture of the UCIe Verification IP\, as well as participating in several cross functional teams focused on finding synergies between verification IP and other Siemens EDA tools. He received his master’s in computer science from National Taiwan University and is a fan of learning new languages. \n  \n\n\n\n\n\n\n\nJalaj Gupta\nVerification IP Product Engineer\, Siemens EDA\n\n\n\n\nJalaj Gupta is Verification IP Product Engineer at Siemens EDA. Jalaj is responsible for providing support for PCIe and UCIe Avery Verification IPs. He has 10 years of experience working in simulation and emulation domain\, from developing Verification IPs to transactor library development for Veloce to product engineering for leading edge Avery Verification IPs. He has worked on different protocols like USB\, Ethernet\, AMBA\, I2C and PCIe. He is based in Austin\, Texas.
URL:https://marketingeda.com/event/comprehensive-pcie-verification-solution-for-bleeding-edge-and-mission-critical-soc-ip-designs/
CATEGORIES:IP,Webinar
ATTACH;FMTTYPE=image/jpeg:https://marketingeda.com/wp-content/uploads/Siemens-January-24-2024.jpg
END:VEVENT
BEGIN:VEVENT
DTSTART;TZID=Europe/London:20240123T100000
DTEND;TZID=Europe/London:20240123T110000
DTSTAMP:20240104T173400Z
CREATED:20240104T173400Z
LAST-MODIFIED:20240104T173400Z
UID:7503-1706004000-1706007600@marketingeda.com
SUMMARY:Verisium SimAI: Coverage Gaps Meet Their Match
DESCRIPTION:Every project has some areas that seem impossible to cover. Various factors can cause these nearly impossible-to-hit coverage gaps\, including technical complexity\, lack of resources\, and shifting requirements. In constrained random environments\, simply running more random seeds may not always address these coverage gaps effectively. Overcoming these gaps requires creativity\, persistence\, and technical expertise. A much greater effort is needed to create tests that significantly increase “last mile” coverage\, and the “knee of the curve” that defines the last mile may occur anywhere from 70% to 95% for code and functional coverage. \nThis webinar will discuss addressing coverage gaps using new Verisium SimAI technology with the Cadence Xcelium Logic Simulator\, the ultimate breakthrough in accelerating verification closure. Verisium SimAI uses Machine learning to build a model to identify and eliminate redundancies in regressions\, generate optimized stimulus\, and automatically close coverage gaps. Users can also leverage the Jasper Coverage Unreachability (UNR) App in their flow to identify structural aspects that limit certain bins from getting hit\, further reducing the last-mile coverage gap. \nJoin us on January 23 to learn how a combination of Verisium\, Xcelium\, and Jasper Apps can quickly\, efficiently\, and automatically eliminate coverage holes and minimize the coverage closure gap.
URL:https://marketingeda.com/event/verisium-simai-coverage-gaps-meet-their-match/
CATEGORIES:EDA,Webinar
ATTACH;FMTTYPE=image/jpeg:https://marketingeda.com/wp-content/uploads/Cadence-January-23-2024.jpg
END:VEVENT
BEGIN:VEVENT
DTSTART;TZID=America/Los_Angeles:20240118T100000
DTEND;TZID=America/Los_Angeles:20240118T110000
DTSTAMP:20240103T221805Z
CREATED:20240103T221805Z
LAST-MODIFIED:20240103T221805Z
UID:7499-1705572000-1705575600@marketingeda.com
SUMMARY:Meet Advanced IC Package Design Schedule Challenges with In-Design Analysis
DESCRIPTION:The heterogeneous integration of chips/chiplets has added significant complexity to the IC package design process\, further compressing schedules for many design teams. Design teams must work more efficiently to meet quality and performance goals while maintaining schedule milestones. \n\nOne way to improve efficiency is to shift signal and power integrity (SI/PI) analysis to earlier in the design cycle. Instead of simply passing a completed design to SI/PI experts for inspection\, design teams can now run in-design analysis (IDA) using intuitive graphical feedback to improve design quality. This change in process saves multiple design re-spins and produces high-performance\, high-quality IC packages for even the most challenging schedules. \n\nThis webinar will educate IC package designers and their managers about Cadence in-design analysis software\, part of the market-leading Cadence IC package design technology. It will showcase the latest updates to the guided\, easy-to-use integrated design and analysis workflow that addresses the complexity of electrical challenges\, reduces design iterations\, and saves significant non-recurring engineering budget.
URL:https://marketingeda.com/event/meet-advanced-ic-package-design-schedule-challenges-with-in-design-analysis/
CATEGORIES:EDA,Webinar
ATTACH;FMTTYPE=image/jpeg:https://marketingeda.com/wp-content/uploads/cadence-January-18-2024.jpg
END:VEVENT
BEGIN:VEVENT
DTSTART;TZID=America/Chicago:20240116T100000
DTEND;TZID=America/Chicago:20240116T110000
DTSTAMP:20240110T172405Z
CREATED:20240110T172405Z
LAST-MODIFIED:20240110T172405Z
UID:7509-1705399200-1705402800@marketingeda.com
SUMMARY:PCB Design Best Practices: How to fully verify your Serdes-based designs before prototype manufacture
DESCRIPTION:“Right first time” is a goal we all aspire to\, but how often does it really happen? Even when we follow layout rules as closely as possible\, problems creep into the layout that cause issues during lab testing and result in costly\, time-consuming respins. \n‌ \nJoin our expert presenter Todd Westerhoff in this LinkedIn Live session where he will dive into why this happens and how to address it through a multifaceted approach that involves meticulous consideration of board fabrication nuances such as layer thickness and conductivity\, and ensuring simulations actually model the board as implemented (instead of the board as intended) by using automated post-layout verification that extracts\, models and analyzes all the design’s serial channels instead of only a select few. \n‌ \nTo learn more\, attend the upcoming LinkedIn Live on January 16\, 2023. 
URL:https://marketingeda.com/event/pcb-design-best-practices-how-to-fully-verify-your-serdes-based-designs-before-prototype-manufacture/
CATEGORIES:EDA,Webinar
ATTACH;FMTTYPE=image/jpeg:https://marketingeda.com/wp-content/uploads/Siemens-January-16-2024.jpg
END:VEVENT
BEGIN:VEVENT
DTSTART;TZID=America/Los_Angeles:20240116T080000
DTEND;TZID=America/Los_Angeles:20240116T090000
DTSTAMP:20231220T172444Z
CREATED:20231220T172444Z
LAST-MODIFIED:20231220T172444Z
UID:7201-1705392000-1705395600@marketingeda.com
SUMMARY:Speed Up Your Electronic Component Design with HPC ​
DESCRIPTION:About this Webinar\nElectronic components design and their integration on PCBs involve complex simulations to predict EM fields and forces accurately. These simulations can be computationally intensive and time-consuming. High-Performance Computing (HPC) capability built into Ansys Maxwell core technology significantly accelerates the electronic component design process\, enabling quick iteration\, optimization\, and validation. The ECAD capability of Maxwell allows modeling and simulation of the PCB along with its components and interdependencies. This system-level simulation enables faster identification and resolution of design challenges.​ \nWhat You Will Learn\n\nHigh-Performance Computing (HPC): provides knowledge to tackle efficiently complex EM computational problems\nParallel Computing: HPC breaks down complex tasks into smaller subtasks that can be executed concurrently\nScalability: Efficiently scale computational resources as the size of the problem increases is crucial in HPC\n\nWho Should Attend\nPCB Designers\, Consumer Electronics Engineers\, Systems Engineers\, Power Solutions Engineers\, SI/PI Engineers\, Product Design Engineers\, Power Module Engineers \nSpeaker\n\nMarius Rosu\nRyan Magargle
URL:https://marketingeda.com/event/speed-up-your-electronic-component-design-with-hpc/
CATEGORIES:EDA,Webinar
ATTACH;FMTTYPE=image/jpeg:https://marketingeda.com/wp-content/uploads/Ansys-January-16-2024.jpg
END:VEVENT
BEGIN:VEVENT
DTSTART;TZID=America/Los_Angeles:20231215T100000
DTEND;TZID=America/Los_Angeles:20231215T110000
DTSTAMP:20231211T212819Z
CREATED:20231211T212623Z
LAST-MODIFIED:20231211T212819Z
UID:7155-1702634400-1702638000@marketingeda.com
SUMMARY:Debugging SystemC with GDB
DESCRIPTION:Webinar Overview:\nThis webinar explores debugging SystemC code with basic tools\, including issues and strategies to make improvements. A large portion of the webinar includes a demonstration of a small design. Topics include single-stepping without getting lost and obtaining information about SystemC simulation status. The session concludes with ideas on how to simplify debugging and accelerate development. \nThe webinar is suitable for SystemC programmers of any level. It will cover: \n\nSystemC debug challenges\nTools\nDemo:\n\nConfiguring the code\n.gdbinit\n\n\nStrategies & Wrap-up\n\nThe webinar also features the Virtualizer Studio IDE from Synopsys for browsing\, editing and debug of SystemC source code. \nThe webinar is presented by David C Black\, Doulos Senior Member of Technical Staff and co-author of “SystemC: From the Ground Up”. \nAttendance is FREE! \n\n \nDavid C Black \, Doulos Senior Member Technical Staff will present this training webinar\, which will consist of a one-hour presentation with interactive Q&A available to attendees throughout. \n\nIf you have any queries\, please contact webinars@doulos.com
URL:https://marketingeda.com/event/debugging-systemc-with-gdb/
CATEGORIES:EDA,Webinar
ATTACH;FMTTYPE=image/jpeg:https://marketingeda.com/wp-content/uploads/Doulos-December-15-2023.jpg
ORGANIZER;CN="Doulos":MAILTO:webinars@duolos.com
END:VEVENT
BEGIN:VEVENT
DTSTART;TZID=America/Los_Angeles:20231214T100000
DTEND;TZID=America/Los_Angeles:20231214T110000
DTSTAMP:20231120T175241Z
CREATED:20231120T175241Z
LAST-MODIFIED:20231120T175241Z
UID:7114-1702548000-1702551600@marketingeda.com
SUMMARY:Automated Power Intent Management Pre-synthesis for Large SoC Designs
DESCRIPTION:With increasing chip design complexity\, power intent management is becoming a requirement by chip designers. Power intent (UPF) databases are getting more and more complex and difficult to handle by designers without a reasonable level of automation. Query UPF databases\, UPF creation and assembly are among the key capabilities to ease the implementation for complex SoC design projects and reach aggressive PPA requirements. \nDuring this webinar the Defacto technical experts will be presenting a complete flow on how to strengthen UPF Management before synthesis based on the Defacto’s SoC Compiler design solution. \nThe Defacto-based UPF management design solution is a clear addon to mainstream low-power checking and implementation flows presynthesis. To manage UPF Defacto’s SoC Compiler is non-intrusive and used as an API to query\, report and complete power intent information. Top level UPF can be easily built along with the RTL for design subsystems and SoC even if UPF views are not ready yet. \nLast but not least\, promoting UPF files to top level or demoting UPF files from top level to enable simulation and synthesis design tasks\, is provided as a press button capability by keeping customization possibilities to fit user design flows. \nDefacto’s power related capabilities are silicon proven and have been already successfully used on very large SoC design projects on many customer designs and the related flows will be presented during the webinar. \nSPEAKERS \n– Valentin Boyer: Product Manager \n– Adrien Lecardonnel: Product Expert \n– Chouki Aktouf: CTO
URL:https://marketingeda.com/event/automated-power-intent-management-pre-synthesis-for-large-soc-designs/
CATEGORIES:EDA,IP,Webinar
ATTACH;FMTTYPE=image/jpeg:https://marketingeda.com/wp-content/uploads/Defacto-December-14-2023.jpg
END:VEVENT
BEGIN:VEVENT
DTSTART;TZID=America/Los_Angeles:20231213T100000
DTEND;TZID=America/Los_Angeles:20231213T110000
DTSTAMP:20231211T211948Z
CREATED:20231211T211948Z
LAST-MODIFIED:20231211T211948Z
UID:7152-1702461600-1702465200@marketingeda.com
SUMMARY:CMOS Circuit Techniques for Wireline Transmitters Part III
DESCRIPTION:Synopsys Webinar – Part III \nIn this 3-part Synopsys webinar series\, we will present how hyperscale data centers are going through a paradigm shift with the advent of technologies like Artificial Intelligence (AI) and edge compute requiring hyperscale data centers to support exponential growth of data volume.  This volume of network traffic demands an increase in bandwidth to 400G\, which is now enabled by 112G Ethernet as the interconnect of choice\, with next generation architectures being designed to operate at 224Gbps supporting upcoming 800G/1.6T switches inside datacenters.  These data rates pose extreme challenges on the entire transceiver.  Attend this webinar series to find out about the challenges posed on the transmitter and a discussion on various techniques used in the different blocks to overcome the challenges of data transmission at 100s of Gbps. \nPart I: Wednesday\, November 8\, 2023 \n\nMotivation for SERDES\nTransmitter Requirements\nCurrent/Voltage Mode Drivers\n\nPart II: Wednesday\, November 29\, 2023 \n\nHigh Order Multiplexers\nFFE Equalization\nDSP-DAC Based TX Architectures\n1-UI Pulse Generation Circuits\n\nPart III: Wednesday\, December 13\, 2023 \n\nOutput Matching Network\nMeasurements and Simulation Techniques\n\n\n\n\n\n\n\n\n\n\n\nSpeaker\n\n\nListed below is the industry leader scheduled to speak. \n\n\n\n\n\n\n\n\n\n\n\n\n\n\n\n\n\n\n\n\n\n\n\n\n\n\nNoman Hai\n\n\nManager\, Analog & Mixed-Signal Circuit Design\nSynopsys\, Inc. \n\n\n\n\n\n\n\n\n\n\n\nNoman Hai received the B.E. degree from NED University\, Karachi\, Pakistan in 2002 and the M.Sc. degree in Electrical Engineering from Linkoping University\, Sweden in 2006 and the Ph.D. degree from University of Waterloo\, Canada\, in 2012. He has worked at Philips Semiconductors\, MACOM\, Movellus and Synopsys as an analog design engineer where he was involved in designing high speed analog circuits for wireline and A.I. applications. Currently he is an Analog Design Manager at Synopsys where he is involved in designing high speed interface IP circuits. His current interests include high speed I/O circuits\, design methodology and automation\, and mixed-signal circuits. He holds three U.S. patents.
URL:https://marketingeda.com/event/cmos-circuit-techniques-for-wireline-transmitters-part-iii/
CATEGORIES:EDA,IP,Webinar
ATTACH;FMTTYPE=image/jpeg:https://marketingeda.com/wp-content/uploads/Synopsys-December-13-2023.jpg
END:VEVENT
BEGIN:VEVENT
DTSTART;TZID=America/Los_Angeles:20231213T090000
DTEND;TZID=America/Los_Angeles:20231213T100000
DTSTAMP:20231204T224640Z
CREATED:20231204T224336Z
LAST-MODIFIED:20231204T224640Z
UID:7139-1702458000-1702461600@marketingeda.com
SUMMARY:Accelerating New Product Introduction with Integrated End-to-End Analytics
DESCRIPTION:Are you seeking to achieve dramatic gains in product time to market? This webinar will explore the combined solution of proteanTecs deep data analytics solutions and the PDF Solutions Exensio platform for rapid NPI.\nThis 30-minute program will include a presentation and a LIVE DEMO of the integration of PDF Solutions’ Exensio platform and proteanTecs’ deep data analytics platform. Our collaboration combines PDF Solutions’ semiconductor big data analytics solutions with proteanTecs’ deep data offering for chip and system lifecycle analytics to enable data-driven actionable insights for device centering\, design margin assessment\, yield limiter detection\, test tool debug and excursions correction. \nWe will cover how integrated end-to-end analytics can: \n\nAccelerate ​learning for NPI and early ramp​\nProvide drill-down diagnostics from lots to device subsystems​\nImprove test understanding for device characterization\n\nKey topics covered:  \n\nDesign validation visibility with Agents and analytics assessing chip health at every stage​\nAnalytics tool from fab through device testing\nDesign validation enabling data fusion for in-die visibility\, analytics and machine learning\nFaster validation by accelerated use of data\nActual use cases\n\nMeet Our Speakers \nTami Shlasky Nachalon is VP of Product Management at proteanTecs. Tami has 15 years of experience in various product positions in big data analytics B2B companies\, both startups & corporates. Prior to proteanTecs\, Tami was a Chief Product Planner in Optimal Plus\, which was acquired by National Instruments. Tami holds a B.Sc in Industrial Engineering & Management from Ben Gurion University\, and an MBA in Management & Entrepreneurship from Tel Aviv University. \n\nThomas Zanon is an Engagement Director at PDF Solutions with 15+ years in the semiconductor industry. He’s a technical lead for partner collaborations\, specializing in Bitmap\, DFI\, and yield ramp projects with IDMs and fabless companies. Thomas holds a Dipl. Ing. in Electrical Engineering and Information Technology from the Technical University in Munich and a Ph.D. in Electrical Engineering from Carnegie Mellon University in Pittsburgh\, PA.
URL:https://marketingeda.com/event/accelerating-new-product-introduction-with-integrated-end-to-end-analytics/
CATEGORIES:EDA,IP,Webinar
ATTACH;FMTTYPE=image/jpeg:https://marketingeda.com/wp-content/uploads/proteanTecs-December-13-2023.jpg
END:VEVENT
BEGIN:VEVENT
DTSTART;TZID=America/Los_Angeles:20231213T070000
DTEND;TZID=America/Los_Angeles:20231213T100000
DTSTAMP:20231110T200548Z
CREATED:20231110T200548Z
LAST-MODIFIED:20231110T200548Z
UID:7073-1702450800-1702461600@marketingeda.com
SUMMARY:RTL-to-GDSII Flow for ASIC Design Using Cadence Tools
DESCRIPTION:Would you like to know how to design a complete chip using the RTL-to-GDSII Flow? \nIn this free technical Training Webinar with Application Engineer Sai Srinivas Pamula\, we’ll teach you the essential steps in the RTL-to-GDSII design flow using a wide variety of industry-leading Cadence tools—such as the Xcelium Logic Simulator\, Modus DFT Software Solution\, Genus Synthesis Solution\, Conformal technologies\, Innovus Implementation System\, and Tempus Timing Solution—that provide great power\, performance\, and area (PPA). \nWe’ll explore topics like: \n\nWriting RTL code using Verilog or VHDL\nSynthesizing the RTL design into a gate-level netlist\nInserting scan chains into the netlist for testing and debugging\nPerforming logic equivalence checking to verify that the synthesized design is functionally equivalent to the original RTL design\nImplementing the netlist by performing floorplanning\, placement\, clock tree synthesis\, and routing\nPerforming timing signoff to verify that the design meets all of its timing requirements\nExtracting the GDSII file from the physical layout to manufacture the chip\n\nWebinar\nRTL-to-GDSII Flow for ASIC Design Using Cadence Tools \nDate and Time\nWednesday\, December 13\n07:00 PST San Jose / 10:00 EST New York / 15:00 GMT London / 16:00 CET Berlin / 17:00 IST Jerusalem / 20:30 IST Bangalore / 23:00 CST Beijing \n\nTo register for the RTL-to-GDSII Flow for ASIC Design Using Cadence Tools webinar\, sign in with your Cadence Support account (email ID and password) to log in to the Learning and Support System. Then select Enroll to register for the session. Once registered\, you’ll receive a confirmation email containing all login details. If you don’t have a Cadence Support account\, go to Registration Help or Cadence User Registration and complete the requested information.
URL:https://marketingeda.com/event/rtl-to-gdsii-flow-for-asic-design-using-cadence-tools/
CATEGORIES:EDA,Webinar
ATTACH;FMTTYPE=image/jpeg:https://marketingeda.com/wp-content/uploads/Cadence-December-13-2023.jpg
END:VEVENT
BEGIN:VEVENT
DTSTART;TZID=America/Los_Angeles:20231212T110000
DTEND;TZID=America/Los_Angeles:20231212T120000
DTSTAMP:20231120T173808Z
CREATED:20231120T173808Z
LAST-MODIFIED:20231120T173808Z
UID:7111-1702378800-1702382400@marketingeda.com
SUMMARY:Solve EM Fields and Forces in PCBs for Consumer Electronics ​
DESCRIPTION:This webinar will demonstrate how Ansys tools can improve PCB designs for higher performance and reliability. Ansys Maxwell simulates low-frequency (LF) EM fields to identify potential EMI/EMC issues for shielding and grounding purposes. Engineers can also predict electric currents distributed throughout the PCB power traces and study the EM forces generated by the magnetic field of the permanent magnets. Computed broadband forces are mapped to Ansys Mechanical for NVH analysis to reduce undesired mechanical vibrations.​ \nWhat You Will Learn\n\nDesign and development of electronic circuits and PCBs\nModel detailed printed circuit boards\nPerform electromagnetic analysis to import EM sources\nConduct mechanical analysis to identify noise sources\n\nWho Should Attend\nPCB Designers\, Consumer Electronics Engineers\, Systems Engineers\, Power Solutions Engineers\, SI/PI Engineers\, Product Design Engineers\, Power Module Engineers \nSpeaker\nTianze Kan and Marius Rosu
URL:https://marketingeda.com/event/solve-em-fields-and-forces-in-pcbs-for-consumer-electronics/
CATEGORIES:EDA,Webinar
ATTACH;FMTTYPE=image/jpeg:https://marketingeda.com/wp-content/uploads/Ansys-December-12-2023.jpg
END:VEVENT
BEGIN:VEVENT
DTSTART;TZID=America/Los_Angeles:20231207T090000
DTEND;TZID=America/Los_Angeles:20231207T100000
DTSTAMP:20231130T173639Z
CREATED:20231130T173639Z
LAST-MODIFIED:20231130T173639Z
UID:7136-1701939600-1701943200@marketingeda.com
SUMMARY:Avoiding Metastability in Hardware Software Interface (HSI) using CDC Techniques
DESCRIPTION:Various IP blocks within an SoC are often required to work in different clock domains in order to satisfy the power constraints. Clock domain crossing (CDC) challenges faced by design engineers include: \n– Speed and power requirements lead to designs with multiple asynchronous clock domains on different I/O interfaces and data being transferred from one clock domain to another. \n– Transferring signals between asynchronous clock domains may lead to setup or hold timing violations of the flip-flops in the receiving clock domain. \n– These violations may cause CDC signals to be metastable. \n– Metastability may also arise from jitter between asynchronous clock domains\, resulting in functional failures if the appropriate clock synchronizers are not present. \nThis webinar will examine the techniques used to avoid metastability as signals cross from one clock domain to another: \n– Mux Synchronizer \n– Two-Flip-Flop Synchronizer \n– Handshake Synchronization \n– Write operation \n– Read operation \n– Pulse \n– Reset Domain Crossing \n– Custom Synchronizer \nSpeaker Bio:  \nFreddy Nunez\, a Senior Application Engineer at Agnisys since 2021\, holds a degree in Computer Engineering from California State University\, Northridge. He’s been instrumental in Agnisys’ success\, leveraging his technical expertise to assist customers in navigating complex challenges and optimizing their systems. Freddy has experience with SystemRDL\, IP-XACT\, Verilog and SystemVerilog. \nThis webinar is in partnership with SemiWiki and Agnisys
URL:https://marketingeda.com/event/avoiding-metastability-in-hardware-software-interface-hsi-using-cdc-techniques/
CATEGORIES:EDA,Webinar
ATTACH;FMTTYPE=image/jpeg:https://marketingeda.com/wp-content/uploads/Agnisys-December-7-2023.jpg
END:VEVENT
BEGIN:VEVENT
DTSTART;TZID=America/Los_Angeles:20231207T080000
DTEND;TZID=America/Los_Angeles:20231207T090000
DTSTAMP:20231117T204354Z
CREATED:20231117T204354Z
LAST-MODIFIED:20231117T204354Z
UID:7107-1701936000-1701939600@marketingeda.com
SUMMARY:Multi-Die System Verification with Siemens Avery UCIe VIP
DESCRIPTION:Conventional monolithic SoCs are becoming a bottleneck for power\, performance\, and area (PPA)\, creating limitations for Data-intensive applications like high-performance computing (HPC)\, machine learning (ML) and artificial intelligence (AI)\, and for hyperscale data centers. These bottlenecks are challenging Moore’s law\, hindering the industry’s ability to continue scaling designs. Chiplets are rapidly becoming the means to overcome the slowing of Moore’s Law\, but the semiconductor industry needs standardized interconnects to allow scaling up these systems\, with 2D\, 2.5D and even 3D packaging technologies. \nUniversal Chiplet Interconnect express (UCIe) is a chiplet interconnect standard that enables seamless interoperation and connectivity between the chiplets/dies without impacting the overall performance. UCIe offers several benefits with lower power consumption\, improved performance with the same latency of the system. \nIn this online seminar\, we will introduce you to Siemens EDA’s Verification Portfolio and then deep dive into UCIe Verification IP\, discussing its key features such as dynamic block-level and SoC level testbench creation\, traffic generation\, error injection\, debug features\, and performance monitoring. Siemens Avery UCIe Verification IP is a leading solution in the market\, runs on all major simulators and is a native SystemVerilog/UVM class-based Verification IP. \n  \nWhat You Will Learn: \n\nWhat is the Universal Chiplet Interconnect Express (UCIe)\nWhy do we need UCIe in chiplet designs: its evolution and application.\nDesign and Verification considerations when planning a UCIe based design.\nSiemens Avery UCIe Verification IP’s unique features.\n\nTechnical Demonstration. \nEnvironment / Testbench Creation \nDynamic Configuration \nTraffic Generation \nError Injection \nDebug features \n\nTechnical Demonstration\n\nWho Should Attend: \n\nDesign\, Verification Engineers\, Managers and Architects working on or planning UCIe design projects\n\n  \nWhat/Which Products are Covered:  \n\nUCIe\nPCIe\nCXL\nChiplets\n\n\n\n\nSpeakers\n\n\n\n\nLuis E. Rodriguez\nSiemens EDA\n\n\nLuis E. Rodriguez has worked on SoC and IP functional verification for over 17 years including developing and deploying PCIe\, CXL\, NVMe\, and UCIe Verification IPs. He has participated and contributed to several protocol workgroups like PCIe\, CCIX\, GENZ (Compliance Workgroup chair); and CXL\, where he helped define Compliance Testing for CXL 2.0. At Siemens he is focused on the architecture of the UCIe Verification IP\, as well as participating in several cross functional teams focused on finding synergies between verification IP and other Siemens EDA tools. He received his Master’s in Computer Science from National Taiwan University and is a fan of learning new languages. \n  \n\n\n\n\n\nJustin Bunnell\nTechnical Product Manager\nSiemens EDA\n\n\nJustin Bunnell is a Technical Product Manager at Siemens EDA\, responsible for the architecture and development of Siemens Avery UCIe Verification IP solution along with several other custom VIPs. He has over 12 years of experience in hardware design verification and simulation software development and holds a Master of Engineering Degree in Computer Engineering from Iowa State University.
URL:https://marketingeda.com/event/multi-die-system-verification-with-siemens-avery-ucie-vip/
CATEGORIES:EDA,IP,Webinar
ATTACH;FMTTYPE=image/jpeg:https://marketingeda.com/wp-content/uploads/Siemens-December-7-2023.jpg
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BEGIN:VEVENT
DTSTART;TZID=America/Los_Angeles:20231205T100000
DTEND;TZID=America/Los_Angeles:20231205T110000
DTSTAMP:20231108T203535Z
CREATED:20231108T203535Z
LAST-MODIFIED:20231108T203535Z
UID:7061-1701770400-1701774000@marketingeda.com
SUMMARY:Rigid Flex PCB In-Design Electromagnetic Analysis Workflow
DESCRIPTION:Today’s electronic products increasingly use Rigid-Flex PCBs to compress form factors\, reduce weight\, and increase cost-effectiveness. For many commercially available 3D numerical solver technologies (FEM and FDTD)\, the electromagnetic (EM) analysis of rigid-flex PCBs has always been challenging due to the complexity of the 3D designs. Much of this complexity comes from bending the board into small spaces and keeping fidelity\, like hatched ground and power planes\, and attaching shielding mask layers. \n\nThis webinar will highlight the key challenges involved in the design and analysis of rigid-flex PCBs\, specifically 3D electromagnetic simulation. Attendees will learn how to set up and perform the Rigid-Flex bending analysis using the Cadence Clarity 3D EM Solver for S-parameter extraction and parameterize bending angles to mitigate EMC/EMI issues.
URL:https://marketingeda.com/event/rigid-flex-pcb-in-design-electromagnetic-analysis-workflow/
CATEGORIES:EDA,Webinar
ATTACH;FMTTYPE=image/jpeg:https://marketingeda.com/wp-content/uploads/Cadence-December-5-2023.jpg
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BEGIN:VEVENT
DTSTART;TZID=America/Los_Angeles:20231130T090000
DTEND;TZID=America/Los_Angeles:20231130T100000
DTSTAMP:20231115T181114Z
CREATED:20231115T181059Z
LAST-MODIFIED:20231115T181114Z
UID:7097-1701334800-1701338400@marketingeda.com
SUMMARY:Latest Innovations and Updates in ASICs with Efabless
DESCRIPTION:In this webinar Jeff DiCorpo & Matt Venn will delve into the latest ASIC developments\, including the game-changing OpenFrame – a new Caravel version expanding your design possibilities by 50%. \nTopics Include: \n\nOpenFrame – a new version of Caravel that gives 50% more area\nGPIO configuration questions\nThe new cocotb testing framework\nIPM – The new IP manager tool\nOpenLane design integration options\nGFMPW-1 sponsored by Google
URL:https://marketingeda.com/event/latest-innovations-and-updates-in-asics-with-efabless/
CATEGORIES:EDA,IP,Webinar
ATTACH;FMTTYPE=image/jpeg:https://marketingeda.com/wp-content/uploads/efabless-November-30-2023.jpg
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BEGIN:VEVENT
DTSTART;TZID=America/Los_Angeles:20231130T080000
DTEND;TZID=America/Los_Angeles:20231130T090000
DTSTAMP:20231108T203020Z
CREATED:20231108T203020Z
LAST-MODIFIED:20231108T203020Z
UID:7058-1701331200-1701334800@marketingeda.com
SUMMARY:Large Eddy CFD Simulation for Automotive Aerodynamics
DESCRIPTION:Wall-modeled large eddy simulations (WMLES) of complex vehicle geometries offer highly accurate results but can be challenging in terms of speed and cost. In this webinar\, learn how to maximize the throughput of these simulations with Fidelity CharLES and how the solver’s GPU acceleration lowers the cost of using WMLES in engineering design. \nWe will present the Fidelity CharLES workflow applied to automotive vehicle aerodynamics simulations\, built around the low-Mach isentropic formulation of the Fidelity CharLES flow solver. \nDiscover fully scriptable meshing and simulation and lightweight interactive visualization of simulation data as some of the main benefits. Fidelity CharLES produces time-dependent\, three-dimensional data from which a detailed analysis of flow physics can be performed\, and integrated quantities such as lift and drag coefficients are readily available. \n\nWhat you’ll learn: \n\nHow to build a WMLES-suitable Voronoi mesh of an automotive geometry in Stitch\nHow to set up a wind tunnel simulation of a vehicle in Fidelity CharLES\nHow to configure relevant post-processing quantities and interactively explore the 3D flow field
URL:https://marketingeda.com/event/large-eddy-cfd-simulation-for-automotive-aerodynamics/
CATEGORIES:CFD,Webinar
ATTACH;FMTTYPE=image/jpeg:https://marketingeda.com/wp-content/uploads/Cadence-November-30-2023.jpg
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BEGIN:VEVENT
DTSTART;TZID=America/Los_Angeles:20231129T100000
DTEND;TZID=America/Los_Angeles:20231129T110000
DTSTAMP:20231120T172317Z
CREATED:20231113T181552Z
LAST-MODIFIED:20231120T172317Z
UID:7076-1701252000-1701255600@marketingeda.com
SUMMARY:CMOS Circuit Techniques for Wireline Transmitters Part II
DESCRIPTION:Synopsys Webinar – Part II \nIn this 3-part Synopsys webinar series\, we will present how hyperscale data centers are going through a paradigm shift with the advent of technologies like Artificial Intelligence (AI) and edge compute requiring hyperscale data centers to support exponential growth of data volume.  This volume of network traffic demands an increase in bandwidth to 400G\, which is now enabled by 112G Ethernet as the interconnect of choice\, with next generation architectures being designed to operate at 224Gbps supporting upcoming 800G/1.6T switches inside datacenters.  These data rates pose extreme challenges on the entire transceiver.  Attend this webinar series to find out about the challenges posed on the transmitter and a discussion on various techniques used in the different blocks to overcome the challenges of data transmission at 100s of Gbps. \nPart I: Wednesday\, November 8\, 2023 \n\nMotivation for SERDES\nTransmitter Requirements\nCurrent/Voltage Mode Drivers\n\nPart II: Wednesday\, November 29\, 2023 \n\nHigh Order Multiplexers\nFFE Equalization\nDSP-DAC Based TX Architectures\n1-UI Pulse Generation Circuits\n\nPart III: Wednesday\, December 13\, 2023 \n\nOutput Matching Network\nMeasurements and Simulation Techniques\n\n\n\n\n\n\nSpeaker\n\n\nListed below is the industry leader scheduled to speak. \n\n\n\n\n\n\n\n\n\n\n\n\n\n\n\n\n\n\n\n\n\n\n\n\n\n\nNoman Hai\n\n\nManager\, Analog & Mixed-Signal Circuit Design\nSynopsys\, Inc. \n\n\n\n\n\n\n\n\n\n\n\nNoman Hai received the B.E. degree from NED University\, Karachi\, Pakistan in 2002 and the M.Sc. degree in Electrical Engineering from Linkoping University\, Sweden in 2006 and the Ph.D. degree from University of Waterloo\, Canada\, in 2012. He has worked at Philips Semiconductors\, MACOM\, Movellus and Synopsys as an analog design engineer where he was involved in designing high speed analog circuits for wireline and A.I. applications. Currently he is an Analog Design Manager at Synopsys where he is involved in designing high speed interface IP circuits. His current interests include high speed I/O circuits\, design methodology and automation\, and mixed-signal circuits. He holds three U.S. patents.
URL:https://marketingeda.com/event/cmos-circuit-techniques-for-wireline-transmitters-part-ii/
CATEGORIES:IP,Webinar
ATTACH;FMTTYPE=image/jpeg:https://marketingeda.com/wp-content/uploads/Synopsys-November-29-2023-1.jpg
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BEGIN:VEVENT
DTSTART;TZID=UTC:20231128T120000
DTEND;TZID=UTC:20231128T130000
DTSTAMP:20231103T162108Z
CREATED:20231103T162108Z
LAST-MODIFIED:20231103T162108Z
UID:7027-1701172800-1701176400@marketingeda.com
SUMMARY:Auto-generation of Verification Infrastructure for IP to SoC
DESCRIPTION:Agenda (BST):\n\n\n\n\n\n\n\nTime\nSession Description\nSlides\nVideos\n\n\n12.00 GMT\nWelcome and Introduction \nMike Bartley\,Tessolve\n\n\n\n\n12.00 GMT\nAgnisys\n\n\n\n\n12.30 GMT\nImperas\n\n\n\n\n12.45 GMT\nBreker\n\n\n\n\n13.00 GMT\n  \nClose\n\n\n\n\n\nAbout DVClub\n\n\n\n\nThe principal goal of each DVCLUB meeting is to have fun while helping build the European verification community through regular educational and networking events. Attendance at DVClub Europe meetings is free and is open to all non-service provider semiconductor professionals. Each meeting addresses a specific issue faced by the design and verification community and whatever your speciality provides an excellent opportunity for updating knowledge as well as share experiences\, insights and issues with other members of the verification community.
URL:https://marketingeda.com/event/auto-generation-of-verification-infrastructure-for-ip-to-soc/
CATEGORIES:EDA,Webinar
ATTACH;FMTTYPE=image/jpeg:https://marketingeda.com/wp-content/uploads/DVClub-November-28-2023.jpg
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