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DTSTART;TZID=America/Los_Angeles:20240124T080000
DTEND;TZID=America/Los_Angeles:20240124T090000
DTSTAMP:20240103T173109Z
CREATED:20240103T173109Z
LAST-MODIFIED:20240103T173109Z
UID:7496-1706083200-1706086800@marketingeda.com
SUMMARY:Comprehensive PCIe Verification Solution for bleeding edge and mission critical SoC & IP Designs
DESCRIPTION:Applications such as Data Centers\, High-Performance computing (HPC)\, artificial intelligence/machine learning (AI/ML)\, cloud computing\, military\, and aerospace\, automotive\, etc. are all extremely Bandwidth-hungry. To cater to such high demands of high speeds and bandwidth requires a breakthrough that HPC SoCs are constantly facing. High speed interfaces like PCI Express® (PCIe®) 5.0 and 6.0 show promising results for compute intensive applications. Every successive generation of PCIe has doubled the bandwidth of the previous generation for e.g. PCIe 6.0\, delivers double the bandwidth (64GT/s) of its predecessor i.e.\, PCIe 5.0 (32GT/s). \nCome join us to learn: \n1. How PCIe 6.0 can deliver such high data transfer rate of up to 64 GT/s per pin \n2. Design considerations for PCIe 5.0 and 6.0 design IPs \n3. Why verifying features such as Integrity and data encryption are critical. \n4. Why industry leading PCIe design IPs companies trust us and how stay ahead of the curve \n5. Reaching coverage closure faster through Compliance  Testsuites \n6. What’s next for PCIe. \nWe will also discuss how you can stay ahead in the market in verifying the most advanced and critical features of PCIe 6.0 and 5.0 for your design IPs. \n  \nWhat You Will Learn: \n\nOverview of PCIe Verification\nDesign and verification considerations when planning a new PCIe project specially around PCIe Gen5 or Gen6\nUnique features to Siemens Avery PCIe Verification IP and its Compliance Test Suite:\n\nTestbench Creation and easy bring-up. \nRun time Configurations. \nTraffic Generation \nError Injection \nDebug features \nVarious applications and use-cases \n\nChallenges involved in verifying advanced PCIe Generations\nTechnical Demonstration\n\nWho Should Attend: \n\nDesign & Verification Engineers\, Architects.\nManagers\, Directors\, Key Decision Makers.\n\n  \nWhat/Which Products are Covered:  \n\nVerification IP\, SV/UVM\, PCIe\, PCIe Compliance Test Suite\, QuestaSim & Visualizer\n\n\n\nSpeakers:\n\n\n\n\n\n\nLuis E. Rodriguez\nSiemens EDA\n\n\n\n\nLuis E. Rodriguez has worked on SoC and IP functional verification for over 17 years including developing and deploying PCIe\, CXL\, NVMe\, and UCIe Verification IPs. He has participated and contributed to several protocol workgroups like PCIe\, CCIX\, GENZ (Compliance Workgroup chair); and CXL\, where he helped define Compliance Testing for CXL 2.0.  At Siemens he is focused on the architecture of the UCIe Verification IP\, as well as participating in several cross functional teams focused on finding synergies between verification IP and other Siemens EDA tools. He received his master’s in computer science from National Taiwan University and is a fan of learning new languages. \n  \n\n\n\n\n\n\n\nJalaj Gupta\nVerification IP Product Engineer\, Siemens EDA\n\n\n\n\nJalaj Gupta is Verification IP Product Engineer at Siemens EDA. Jalaj is responsible for providing support for PCIe and UCIe Avery Verification IPs. He has 10 years of experience working in simulation and emulation domain\, from developing Verification IPs to transactor library development for Veloce to product engineering for leading edge Avery Verification IPs. He has worked on different protocols like USB\, Ethernet\, AMBA\, I2C and PCIe. He is based in Austin\, Texas.
URL:https://marketingeda.com/event/comprehensive-pcie-verification-solution-for-bleeding-edge-and-mission-critical-soc-ip-designs/
CATEGORIES:IP,Webinar
ATTACH;FMTTYPE=image/jpeg:https://marketingeda.com/wp-content/uploads/Siemens-January-24-2024.jpg
END:VEVENT
BEGIN:VEVENT
DTSTART;TZID=Europe/London:20240123T100000
DTEND;TZID=Europe/London:20240123T110000
DTSTAMP:20240104T173400Z
CREATED:20240104T173400Z
LAST-MODIFIED:20240104T173400Z
UID:7503-1706004000-1706007600@marketingeda.com
SUMMARY:Verisium SimAI: Coverage Gaps Meet Their Match
DESCRIPTION:Every project has some areas that seem impossible to cover. Various factors can cause these nearly impossible-to-hit coverage gaps\, including technical complexity\, lack of resources\, and shifting requirements. In constrained random environments\, simply running more random seeds may not always address these coverage gaps effectively. Overcoming these gaps requires creativity\, persistence\, and technical expertise. A much greater effort is needed to create tests that significantly increase “last mile” coverage\, and the “knee of the curve” that defines the last mile may occur anywhere from 70% to 95% for code and functional coverage. \nThis webinar will discuss addressing coverage gaps using new Verisium SimAI technology with the Cadence Xcelium Logic Simulator\, the ultimate breakthrough in accelerating verification closure. Verisium SimAI uses Machine learning to build a model to identify and eliminate redundancies in regressions\, generate optimized stimulus\, and automatically close coverage gaps. Users can also leverage the Jasper Coverage Unreachability (UNR) App in their flow to identify structural aspects that limit certain bins from getting hit\, further reducing the last-mile coverage gap. \nJoin us on January 23 to learn how a combination of Verisium\, Xcelium\, and Jasper Apps can quickly\, efficiently\, and automatically eliminate coverage holes and minimize the coverage closure gap.
URL:https://marketingeda.com/event/verisium-simai-coverage-gaps-meet-their-match/
CATEGORIES:EDA,Webinar
ATTACH;FMTTYPE=image/jpeg:https://marketingeda.com/wp-content/uploads/Cadence-January-23-2024.jpg
END:VEVENT
BEGIN:VEVENT
DTSTART;TZID=America/Los_Angeles:20240118T100000
DTEND;TZID=America/Los_Angeles:20240118T110000
DTSTAMP:20240103T221805Z
CREATED:20240103T221805Z
LAST-MODIFIED:20240103T221805Z
UID:7499-1705572000-1705575600@marketingeda.com
SUMMARY:Meet Advanced IC Package Design Schedule Challenges with In-Design Analysis
DESCRIPTION:The heterogeneous integration of chips/chiplets has added significant complexity to the IC package design process\, further compressing schedules for many design teams. Design teams must work more efficiently to meet quality and performance goals while maintaining schedule milestones. \n\nOne way to improve efficiency is to shift signal and power integrity (SI/PI) analysis to earlier in the design cycle. Instead of simply passing a completed design to SI/PI experts for inspection\, design teams can now run in-design analysis (IDA) using intuitive graphical feedback to improve design quality. This change in process saves multiple design re-spins and produces high-performance\, high-quality IC packages for even the most challenging schedules. \n\nThis webinar will educate IC package designers and their managers about Cadence in-design analysis software\, part of the market-leading Cadence IC package design technology. It will showcase the latest updates to the guided\, easy-to-use integrated design and analysis workflow that addresses the complexity of electrical challenges\, reduces design iterations\, and saves significant non-recurring engineering budget.
URL:https://marketingeda.com/event/meet-advanced-ic-package-design-schedule-challenges-with-in-design-analysis/
CATEGORIES:EDA,Webinar
ATTACH;FMTTYPE=image/jpeg:https://marketingeda.com/wp-content/uploads/cadence-January-18-2024.jpg
END:VEVENT
BEGIN:VEVENT
DTSTART;TZID=America/Chicago:20240116T100000
DTEND;TZID=America/Chicago:20240116T110000
DTSTAMP:20240110T172405Z
CREATED:20240110T172405Z
LAST-MODIFIED:20240110T172405Z
UID:7509-1705399200-1705402800@marketingeda.com
SUMMARY:PCB Design Best Practices: How to fully verify your Serdes-based designs before prototype manufacture
DESCRIPTION:“Right first time” is a goal we all aspire to\, but how often does it really happen? Even when we follow layout rules as closely as possible\, problems creep into the layout that cause issues during lab testing and result in costly\, time-consuming respins. \n‌ \nJoin our expert presenter Todd Westerhoff in this LinkedIn Live session where he will dive into why this happens and how to address it through a multifaceted approach that involves meticulous consideration of board fabrication nuances such as layer thickness and conductivity\, and ensuring simulations actually model the board as implemented (instead of the board as intended) by using automated post-layout verification that extracts\, models and analyzes all the design’s serial channels instead of only a select few. \n‌ \nTo learn more\, attend the upcoming LinkedIn Live on January 16\, 2023. 
URL:https://marketingeda.com/event/pcb-design-best-practices-how-to-fully-verify-your-serdes-based-designs-before-prototype-manufacture/
CATEGORIES:EDA,Webinar
ATTACH;FMTTYPE=image/jpeg:https://marketingeda.com/wp-content/uploads/Siemens-January-16-2024.jpg
END:VEVENT
BEGIN:VEVENT
DTSTART;TZID=America/Los_Angeles:20240116T080000
DTEND;TZID=America/Los_Angeles:20240116T090000
DTSTAMP:20231220T172444Z
CREATED:20231220T172444Z
LAST-MODIFIED:20231220T172444Z
UID:7201-1705392000-1705395600@marketingeda.com
SUMMARY:Speed Up Your Electronic Component Design with HPC ​
DESCRIPTION:About this Webinar\nElectronic components design and their integration on PCBs involve complex simulations to predict EM fields and forces accurately. These simulations can be computationally intensive and time-consuming. High-Performance Computing (HPC) capability built into Ansys Maxwell core technology significantly accelerates the electronic component design process\, enabling quick iteration\, optimization\, and validation. The ECAD capability of Maxwell allows modeling and simulation of the PCB along with its components and interdependencies. This system-level simulation enables faster identification and resolution of design challenges.​ \nWhat You Will Learn\n\nHigh-Performance Computing (HPC): provides knowledge to tackle efficiently complex EM computational problems\nParallel Computing: HPC breaks down complex tasks into smaller subtasks that can be executed concurrently\nScalability: Efficiently scale computational resources as the size of the problem increases is crucial in HPC\n\nWho Should Attend\nPCB Designers\, Consumer Electronics Engineers\, Systems Engineers\, Power Solutions Engineers\, SI/PI Engineers\, Product Design Engineers\, Power Module Engineers \nSpeaker\n\nMarius Rosu\nRyan Magargle
URL:https://marketingeda.com/event/speed-up-your-electronic-component-design-with-hpc/
CATEGORIES:EDA,Webinar
ATTACH;FMTTYPE=image/jpeg:https://marketingeda.com/wp-content/uploads/Ansys-January-16-2024.jpg
END:VEVENT
BEGIN:VEVENT
DTSTART;TZID=America/Los_Angeles:20231215T100000
DTEND;TZID=America/Los_Angeles:20231215T110000
DTSTAMP:20231211T212819Z
CREATED:20231211T212623Z
LAST-MODIFIED:20231211T212819Z
UID:7155-1702634400-1702638000@marketingeda.com
SUMMARY:Debugging SystemC with GDB
DESCRIPTION:Webinar Overview:\nThis webinar explores debugging SystemC code with basic tools\, including issues and strategies to make improvements. A large portion of the webinar includes a demonstration of a small design. Topics include single-stepping without getting lost and obtaining information about SystemC simulation status. The session concludes with ideas on how to simplify debugging and accelerate development. \nThe webinar is suitable for SystemC programmers of any level. It will cover: \n\nSystemC debug challenges\nTools\nDemo:\n\nConfiguring the code\n.gdbinit\n\n\nStrategies & Wrap-up\n\nThe webinar also features the Virtualizer Studio IDE from Synopsys for browsing\, editing and debug of SystemC source code. \nThe webinar is presented by David C Black\, Doulos Senior Member of Technical Staff and co-author of “SystemC: From the Ground Up”. \nAttendance is FREE! \n\n \nDavid C Black \, Doulos Senior Member Technical Staff will present this training webinar\, which will consist of a one-hour presentation with interactive Q&A available to attendees throughout. \n\nIf you have any queries\, please contact webinars@doulos.com
URL:https://marketingeda.com/event/debugging-systemc-with-gdb/
CATEGORIES:EDA,Webinar
ATTACH;FMTTYPE=image/jpeg:https://marketingeda.com/wp-content/uploads/Doulos-December-15-2023.jpg
ORGANIZER;CN="Doulos":MAILTO:webinars@duolos.com
END:VEVENT
BEGIN:VEVENT
DTSTART;TZID=America/Los_Angeles:20231214T100000
DTEND;TZID=America/Los_Angeles:20231214T110000
DTSTAMP:20231120T175241Z
CREATED:20231120T175241Z
LAST-MODIFIED:20231120T175241Z
UID:7114-1702548000-1702551600@marketingeda.com
SUMMARY:Automated Power Intent Management Pre-synthesis for Large SoC Designs
DESCRIPTION:With increasing chip design complexity\, power intent management is becoming a requirement by chip designers. Power intent (UPF) databases are getting more and more complex and difficult to handle by designers without a reasonable level of automation. Query UPF databases\, UPF creation and assembly are among the key capabilities to ease the implementation for complex SoC design projects and reach aggressive PPA requirements. \nDuring this webinar the Defacto technical experts will be presenting a complete flow on how to strengthen UPF Management before synthesis based on the Defacto’s SoC Compiler design solution. \nThe Defacto-based UPF management design solution is a clear addon to mainstream low-power checking and implementation flows presynthesis. To manage UPF Defacto’s SoC Compiler is non-intrusive and used as an API to query\, report and complete power intent information. Top level UPF can be easily built along with the RTL for design subsystems and SoC even if UPF views are not ready yet. \nLast but not least\, promoting UPF files to top level or demoting UPF files from top level to enable simulation and synthesis design tasks\, is provided as a press button capability by keeping customization possibilities to fit user design flows. \nDefacto’s power related capabilities are silicon proven and have been already successfully used on very large SoC design projects on many customer designs and the related flows will be presented during the webinar. \nSPEAKERS \n– Valentin Boyer: Product Manager \n– Adrien Lecardonnel: Product Expert \n– Chouki Aktouf: CTO
URL:https://marketingeda.com/event/automated-power-intent-management-pre-synthesis-for-large-soc-designs/
CATEGORIES:EDA,IP,Webinar
ATTACH;FMTTYPE=image/jpeg:https://marketingeda.com/wp-content/uploads/Defacto-December-14-2023.jpg
END:VEVENT
BEGIN:VEVENT
DTSTART;TZID=America/Los_Angeles:20231213T100000
DTEND;TZID=America/Los_Angeles:20231213T110000
DTSTAMP:20231211T211948Z
CREATED:20231211T211948Z
LAST-MODIFIED:20231211T211948Z
UID:7152-1702461600-1702465200@marketingeda.com
SUMMARY:CMOS Circuit Techniques for Wireline Transmitters Part III
DESCRIPTION:Synopsys Webinar – Part III \nIn this 3-part Synopsys webinar series\, we will present how hyperscale data centers are going through a paradigm shift with the advent of technologies like Artificial Intelligence (AI) and edge compute requiring hyperscale data centers to support exponential growth of data volume.  This volume of network traffic demands an increase in bandwidth to 400G\, which is now enabled by 112G Ethernet as the interconnect of choice\, with next generation architectures being designed to operate at 224Gbps supporting upcoming 800G/1.6T switches inside datacenters.  These data rates pose extreme challenges on the entire transceiver.  Attend this webinar series to find out about the challenges posed on the transmitter and a discussion on various techniques used in the different blocks to overcome the challenges of data transmission at 100s of Gbps. \nPart I: Wednesday\, November 8\, 2023 \n\nMotivation for SERDES\nTransmitter Requirements\nCurrent/Voltage Mode Drivers\n\nPart II: Wednesday\, November 29\, 2023 \n\nHigh Order Multiplexers\nFFE Equalization\nDSP-DAC Based TX Architectures\n1-UI Pulse Generation Circuits\n\nPart III: Wednesday\, December 13\, 2023 \n\nOutput Matching Network\nMeasurements and Simulation Techniques\n\n\n\n\n\n\n\n\n\n\n\nSpeaker\n\n\nListed below is the industry leader scheduled to speak. \n\n\n\n\n\n\n\n\n\n\n\n\n\n\n\n\n\n\n\n\n\n\n\n\n\n\nNoman Hai\n\n\nManager\, Analog & Mixed-Signal Circuit Design\nSynopsys\, Inc. \n\n\n\n\n\n\n\n\n\n\n\nNoman Hai received the B.E. degree from NED University\, Karachi\, Pakistan in 2002 and the M.Sc. degree in Electrical Engineering from Linkoping University\, Sweden in 2006 and the Ph.D. degree from University of Waterloo\, Canada\, in 2012. He has worked at Philips Semiconductors\, MACOM\, Movellus and Synopsys as an analog design engineer where he was involved in designing high speed analog circuits for wireline and A.I. applications. Currently he is an Analog Design Manager at Synopsys where he is involved in designing high speed interface IP circuits. His current interests include high speed I/O circuits\, design methodology and automation\, and mixed-signal circuits. He holds three U.S. patents.
URL:https://marketingeda.com/event/cmos-circuit-techniques-for-wireline-transmitters-part-iii/
CATEGORIES:EDA,IP,Webinar
ATTACH;FMTTYPE=image/jpeg:https://marketingeda.com/wp-content/uploads/Synopsys-December-13-2023.jpg
END:VEVENT
BEGIN:VEVENT
DTSTART;TZID=America/Los_Angeles:20231213T090000
DTEND;TZID=America/Los_Angeles:20231213T100000
DTSTAMP:20231204T224640Z
CREATED:20231204T224336Z
LAST-MODIFIED:20231204T224640Z
UID:7139-1702458000-1702461600@marketingeda.com
SUMMARY:Accelerating New Product Introduction with Integrated End-to-End Analytics
DESCRIPTION:Are you seeking to achieve dramatic gains in product time to market? This webinar will explore the combined solution of proteanTecs deep data analytics solutions and the PDF Solutions Exensio platform for rapid NPI.\nThis 30-minute program will include a presentation and a LIVE DEMO of the integration of PDF Solutions’ Exensio platform and proteanTecs’ deep data analytics platform. Our collaboration combines PDF Solutions’ semiconductor big data analytics solutions with proteanTecs’ deep data offering for chip and system lifecycle analytics to enable data-driven actionable insights for device centering\, design margin assessment\, yield limiter detection\, test tool debug and excursions correction. \nWe will cover how integrated end-to-end analytics can: \n\nAccelerate ​learning for NPI and early ramp​\nProvide drill-down diagnostics from lots to device subsystems​\nImprove test understanding for device characterization\n\nKey topics covered:  \n\nDesign validation visibility with Agents and analytics assessing chip health at every stage​\nAnalytics tool from fab through device testing\nDesign validation enabling data fusion for in-die visibility\, analytics and machine learning\nFaster validation by accelerated use of data\nActual use cases\n\nMeet Our Speakers \nTami Shlasky Nachalon is VP of Product Management at proteanTecs. Tami has 15 years of experience in various product positions in big data analytics B2B companies\, both startups & corporates. Prior to proteanTecs\, Tami was a Chief Product Planner in Optimal Plus\, which was acquired by National Instruments. Tami holds a B.Sc in Industrial Engineering & Management from Ben Gurion University\, and an MBA in Management & Entrepreneurship from Tel Aviv University. \n\nThomas Zanon is an Engagement Director at PDF Solutions with 15+ years in the semiconductor industry. He’s a technical lead for partner collaborations\, specializing in Bitmap\, DFI\, and yield ramp projects with IDMs and fabless companies. Thomas holds a Dipl. Ing. in Electrical Engineering and Information Technology from the Technical University in Munich and a Ph.D. in Electrical Engineering from Carnegie Mellon University in Pittsburgh\, PA.
URL:https://marketingeda.com/event/accelerating-new-product-introduction-with-integrated-end-to-end-analytics/
CATEGORIES:EDA,IP,Webinar
ATTACH;FMTTYPE=image/jpeg:https://marketingeda.com/wp-content/uploads/proteanTecs-December-13-2023.jpg
END:VEVENT
BEGIN:VEVENT
DTSTART;TZID=America/Los_Angeles:20231213T070000
DTEND;TZID=America/Los_Angeles:20231213T100000
DTSTAMP:20231110T200548Z
CREATED:20231110T200548Z
LAST-MODIFIED:20231110T200548Z
UID:7073-1702450800-1702461600@marketingeda.com
SUMMARY:RTL-to-GDSII Flow for ASIC Design Using Cadence Tools
DESCRIPTION:Would you like to know how to design a complete chip using the RTL-to-GDSII Flow? \nIn this free technical Training Webinar with Application Engineer Sai Srinivas Pamula\, we’ll teach you the essential steps in the RTL-to-GDSII design flow using a wide variety of industry-leading Cadence tools—such as the Xcelium Logic Simulator\, Modus DFT Software Solution\, Genus Synthesis Solution\, Conformal technologies\, Innovus Implementation System\, and Tempus Timing Solution—that provide great power\, performance\, and area (PPA). \nWe’ll explore topics like: \n\nWriting RTL code using Verilog or VHDL\nSynthesizing the RTL design into a gate-level netlist\nInserting scan chains into the netlist for testing and debugging\nPerforming logic equivalence checking to verify that the synthesized design is functionally equivalent to the original RTL design\nImplementing the netlist by performing floorplanning\, placement\, clock tree synthesis\, and routing\nPerforming timing signoff to verify that the design meets all of its timing requirements\nExtracting the GDSII file from the physical layout to manufacture the chip\n\nWebinar\nRTL-to-GDSII Flow for ASIC Design Using Cadence Tools \nDate and Time\nWednesday\, December 13\n07:00 PST San Jose / 10:00 EST New York / 15:00 GMT London / 16:00 CET Berlin / 17:00 IST Jerusalem / 20:30 IST Bangalore / 23:00 CST Beijing \n\nTo register for the RTL-to-GDSII Flow for ASIC Design Using Cadence Tools webinar\, sign in with your Cadence Support account (email ID and password) to log in to the Learning and Support System. Then select Enroll to register for the session. Once registered\, you’ll receive a confirmation email containing all login details. If you don’t have a Cadence Support account\, go to Registration Help or Cadence User Registration and complete the requested information.
URL:https://marketingeda.com/event/rtl-to-gdsii-flow-for-asic-design-using-cadence-tools/
CATEGORIES:EDA,Webinar
ATTACH;FMTTYPE=image/jpeg:https://marketingeda.com/wp-content/uploads/Cadence-December-13-2023.jpg
END:VEVENT
BEGIN:VEVENT
DTSTART;TZID=America/Los_Angeles:20231212T110000
DTEND;TZID=America/Los_Angeles:20231212T120000
DTSTAMP:20231120T173808Z
CREATED:20231120T173808Z
LAST-MODIFIED:20231120T173808Z
UID:7111-1702378800-1702382400@marketingeda.com
SUMMARY:Solve EM Fields and Forces in PCBs for Consumer Electronics ​
DESCRIPTION:This webinar will demonstrate how Ansys tools can improve PCB designs for higher performance and reliability. Ansys Maxwell simulates low-frequency (LF) EM fields to identify potential EMI/EMC issues for shielding and grounding purposes. Engineers can also predict electric currents distributed throughout the PCB power traces and study the EM forces generated by the magnetic field of the permanent magnets. Computed broadband forces are mapped to Ansys Mechanical for NVH analysis to reduce undesired mechanical vibrations.​ \nWhat You Will Learn\n\nDesign and development of electronic circuits and PCBs\nModel detailed printed circuit boards\nPerform electromagnetic analysis to import EM sources\nConduct mechanical analysis to identify noise sources\n\nWho Should Attend\nPCB Designers\, Consumer Electronics Engineers\, Systems Engineers\, Power Solutions Engineers\, SI/PI Engineers\, Product Design Engineers\, Power Module Engineers \nSpeaker\nTianze Kan and Marius Rosu
URL:https://marketingeda.com/event/solve-em-fields-and-forces-in-pcbs-for-consumer-electronics/
CATEGORIES:EDA,Webinar
ATTACH;FMTTYPE=image/jpeg:https://marketingeda.com/wp-content/uploads/Ansys-December-12-2023.jpg
END:VEVENT
BEGIN:VEVENT
DTSTART;TZID=America/Los_Angeles:20231207T090000
DTEND;TZID=America/Los_Angeles:20231207T100000
DTSTAMP:20231130T173639Z
CREATED:20231130T173639Z
LAST-MODIFIED:20231130T173639Z
UID:7136-1701939600-1701943200@marketingeda.com
SUMMARY:Avoiding Metastability in Hardware Software Interface (HSI) using CDC Techniques
DESCRIPTION:Various IP blocks within an SoC are often required to work in different clock domains in order to satisfy the power constraints. Clock domain crossing (CDC) challenges faced by design engineers include: \n– Speed and power requirements lead to designs with multiple asynchronous clock domains on different I/O interfaces and data being transferred from one clock domain to another. \n– Transferring signals between asynchronous clock domains may lead to setup or hold timing violations of the flip-flops in the receiving clock domain. \n– These violations may cause CDC signals to be metastable. \n– Metastability may also arise from jitter between asynchronous clock domains\, resulting in functional failures if the appropriate clock synchronizers are not present. \nThis webinar will examine the techniques used to avoid metastability as signals cross from one clock domain to another: \n– Mux Synchronizer \n– Two-Flip-Flop Synchronizer \n– Handshake Synchronization \n– Write operation \n– Read operation \n– Pulse \n– Reset Domain Crossing \n– Custom Synchronizer \nSpeaker Bio:  \nFreddy Nunez\, a Senior Application Engineer at Agnisys since 2021\, holds a degree in Computer Engineering from California State University\, Northridge. He’s been instrumental in Agnisys’ success\, leveraging his technical expertise to assist customers in navigating complex challenges and optimizing their systems. Freddy has experience with SystemRDL\, IP-XACT\, Verilog and SystemVerilog. \nThis webinar is in partnership with SemiWiki and Agnisys
URL:https://marketingeda.com/event/avoiding-metastability-in-hardware-software-interface-hsi-using-cdc-techniques/
CATEGORIES:EDA,Webinar
ATTACH;FMTTYPE=image/jpeg:https://marketingeda.com/wp-content/uploads/Agnisys-December-7-2023.jpg
END:VEVENT
BEGIN:VEVENT
DTSTART;TZID=America/Los_Angeles:20231207T080000
DTEND;TZID=America/Los_Angeles:20231207T090000
DTSTAMP:20231117T204354Z
CREATED:20231117T204354Z
LAST-MODIFIED:20231117T204354Z
UID:7107-1701936000-1701939600@marketingeda.com
SUMMARY:Multi-Die System Verification with Siemens Avery UCIe VIP
DESCRIPTION:Conventional monolithic SoCs are becoming a bottleneck for power\, performance\, and area (PPA)\, creating limitations for Data-intensive applications like high-performance computing (HPC)\, machine learning (ML) and artificial intelligence (AI)\, and for hyperscale data centers. These bottlenecks are challenging Moore’s law\, hindering the industry’s ability to continue scaling designs. Chiplets are rapidly becoming the means to overcome the slowing of Moore’s Law\, but the semiconductor industry needs standardized interconnects to allow scaling up these systems\, with 2D\, 2.5D and even 3D packaging technologies. \nUniversal Chiplet Interconnect express (UCIe) is a chiplet interconnect standard that enables seamless interoperation and connectivity between the chiplets/dies without impacting the overall performance. UCIe offers several benefits with lower power consumption\, improved performance with the same latency of the system. \nIn this online seminar\, we will introduce you to Siemens EDA’s Verification Portfolio and then deep dive into UCIe Verification IP\, discussing its key features such as dynamic block-level and SoC level testbench creation\, traffic generation\, error injection\, debug features\, and performance monitoring. Siemens Avery UCIe Verification IP is a leading solution in the market\, runs on all major simulators and is a native SystemVerilog/UVM class-based Verification IP. \n  \nWhat You Will Learn: \n\nWhat is the Universal Chiplet Interconnect Express (UCIe)\nWhy do we need UCIe in chiplet designs: its evolution and application.\nDesign and Verification considerations when planning a UCIe based design.\nSiemens Avery UCIe Verification IP’s unique features.\n\nTechnical Demonstration. \nEnvironment / Testbench Creation \nDynamic Configuration \nTraffic Generation \nError Injection \nDebug features \n\nTechnical Demonstration\n\nWho Should Attend: \n\nDesign\, Verification Engineers\, Managers and Architects working on or planning UCIe design projects\n\n  \nWhat/Which Products are Covered:  \n\nUCIe\nPCIe\nCXL\nChiplets\n\n\n\n\nSpeakers\n\n\n\n\nLuis E. Rodriguez\nSiemens EDA\n\n\nLuis E. Rodriguez has worked on SoC and IP functional verification for over 17 years including developing and deploying PCIe\, CXL\, NVMe\, and UCIe Verification IPs. He has participated and contributed to several protocol workgroups like PCIe\, CCIX\, GENZ (Compliance Workgroup chair); and CXL\, where he helped define Compliance Testing for CXL 2.0. At Siemens he is focused on the architecture of the UCIe Verification IP\, as well as participating in several cross functional teams focused on finding synergies between verification IP and other Siemens EDA tools. He received his Master’s in Computer Science from National Taiwan University and is a fan of learning new languages. \n  \n\n\n\n\n\nJustin Bunnell\nTechnical Product Manager\nSiemens EDA\n\n\nJustin Bunnell is a Technical Product Manager at Siemens EDA\, responsible for the architecture and development of Siemens Avery UCIe Verification IP solution along with several other custom VIPs. He has over 12 years of experience in hardware design verification and simulation software development and holds a Master of Engineering Degree in Computer Engineering from Iowa State University.
URL:https://marketingeda.com/event/multi-die-system-verification-with-siemens-avery-ucie-vip/
CATEGORIES:EDA,IP,Webinar
ATTACH;FMTTYPE=image/jpeg:https://marketingeda.com/wp-content/uploads/Siemens-December-7-2023.jpg
END:VEVENT
BEGIN:VEVENT
DTSTART;TZID=America/Los_Angeles:20231205T100000
DTEND;TZID=America/Los_Angeles:20231205T110000
DTSTAMP:20231108T203535Z
CREATED:20231108T203535Z
LAST-MODIFIED:20231108T203535Z
UID:7061-1701770400-1701774000@marketingeda.com
SUMMARY:Rigid Flex PCB In-Design Electromagnetic Analysis Workflow
DESCRIPTION:Today’s electronic products increasingly use Rigid-Flex PCBs to compress form factors\, reduce weight\, and increase cost-effectiveness. For many commercially available 3D numerical solver technologies (FEM and FDTD)\, the electromagnetic (EM) analysis of rigid-flex PCBs has always been challenging due to the complexity of the 3D designs. Much of this complexity comes from bending the board into small spaces and keeping fidelity\, like hatched ground and power planes\, and attaching shielding mask layers. \n\nThis webinar will highlight the key challenges involved in the design and analysis of rigid-flex PCBs\, specifically 3D electromagnetic simulation. Attendees will learn how to set up and perform the Rigid-Flex bending analysis using the Cadence Clarity 3D EM Solver for S-parameter extraction and parameterize bending angles to mitigate EMC/EMI issues.
URL:https://marketingeda.com/event/rigid-flex-pcb-in-design-electromagnetic-analysis-workflow/
CATEGORIES:EDA,Webinar
ATTACH;FMTTYPE=image/jpeg:https://marketingeda.com/wp-content/uploads/Cadence-December-5-2023.jpg
END:VEVENT
BEGIN:VEVENT
DTSTART;TZID=America/Los_Angeles:20231130T090000
DTEND;TZID=America/Los_Angeles:20231130T100000
DTSTAMP:20231115T181114Z
CREATED:20231115T181059Z
LAST-MODIFIED:20231115T181114Z
UID:7097-1701334800-1701338400@marketingeda.com
SUMMARY:Latest Innovations and Updates in ASICs with Efabless
DESCRIPTION:In this webinar Jeff DiCorpo & Matt Venn will delve into the latest ASIC developments\, including the game-changing OpenFrame – a new Caravel version expanding your design possibilities by 50%. \nTopics Include: \n\nOpenFrame – a new version of Caravel that gives 50% more area\nGPIO configuration questions\nThe new cocotb testing framework\nIPM – The new IP manager tool\nOpenLane design integration options\nGFMPW-1 sponsored by Google
URL:https://marketingeda.com/event/latest-innovations-and-updates-in-asics-with-efabless/
CATEGORIES:EDA,IP,Webinar
ATTACH;FMTTYPE=image/jpeg:https://marketingeda.com/wp-content/uploads/efabless-November-30-2023.jpg
END:VEVENT
BEGIN:VEVENT
DTSTART;TZID=America/Los_Angeles:20231130T080000
DTEND;TZID=America/Los_Angeles:20231130T090000
DTSTAMP:20231108T203020Z
CREATED:20231108T203020Z
LAST-MODIFIED:20231108T203020Z
UID:7058-1701331200-1701334800@marketingeda.com
SUMMARY:Large Eddy CFD Simulation for Automotive Aerodynamics
DESCRIPTION:Wall-modeled large eddy simulations (WMLES) of complex vehicle geometries offer highly accurate results but can be challenging in terms of speed and cost. In this webinar\, learn how to maximize the throughput of these simulations with Fidelity CharLES and how the solver’s GPU acceleration lowers the cost of using WMLES in engineering design. \nWe will present the Fidelity CharLES workflow applied to automotive vehicle aerodynamics simulations\, built around the low-Mach isentropic formulation of the Fidelity CharLES flow solver. \nDiscover fully scriptable meshing and simulation and lightweight interactive visualization of simulation data as some of the main benefits. Fidelity CharLES produces time-dependent\, three-dimensional data from which a detailed analysis of flow physics can be performed\, and integrated quantities such as lift and drag coefficients are readily available. \n\nWhat you’ll learn: \n\nHow to build a WMLES-suitable Voronoi mesh of an automotive geometry in Stitch\nHow to set up a wind tunnel simulation of a vehicle in Fidelity CharLES\nHow to configure relevant post-processing quantities and interactively explore the 3D flow field
URL:https://marketingeda.com/event/large-eddy-cfd-simulation-for-automotive-aerodynamics/
CATEGORIES:CFD,Webinar
ATTACH;FMTTYPE=image/jpeg:https://marketingeda.com/wp-content/uploads/Cadence-November-30-2023.jpg
END:VEVENT
BEGIN:VEVENT
DTSTART;TZID=America/Los_Angeles:20231129T100000
DTEND;TZID=America/Los_Angeles:20231129T110000
DTSTAMP:20231120T172317Z
CREATED:20231113T181552Z
LAST-MODIFIED:20231120T172317Z
UID:7076-1701252000-1701255600@marketingeda.com
SUMMARY:CMOS Circuit Techniques for Wireline Transmitters Part II
DESCRIPTION:Synopsys Webinar – Part II \nIn this 3-part Synopsys webinar series\, we will present how hyperscale data centers are going through a paradigm shift with the advent of technologies like Artificial Intelligence (AI) and edge compute requiring hyperscale data centers to support exponential growth of data volume.  This volume of network traffic demands an increase in bandwidth to 400G\, which is now enabled by 112G Ethernet as the interconnect of choice\, with next generation architectures being designed to operate at 224Gbps supporting upcoming 800G/1.6T switches inside datacenters.  These data rates pose extreme challenges on the entire transceiver.  Attend this webinar series to find out about the challenges posed on the transmitter and a discussion on various techniques used in the different blocks to overcome the challenges of data transmission at 100s of Gbps. \nPart I: Wednesday\, November 8\, 2023 \n\nMotivation for SERDES\nTransmitter Requirements\nCurrent/Voltage Mode Drivers\n\nPart II: Wednesday\, November 29\, 2023 \n\nHigh Order Multiplexers\nFFE Equalization\nDSP-DAC Based TX Architectures\n1-UI Pulse Generation Circuits\n\nPart III: Wednesday\, December 13\, 2023 \n\nOutput Matching Network\nMeasurements and Simulation Techniques\n\n\n\n\n\n\nSpeaker\n\n\nListed below is the industry leader scheduled to speak. \n\n\n\n\n\n\n\n\n\n\n\n\n\n\n\n\n\n\n\n\n\n\n\n\n\n\nNoman Hai\n\n\nManager\, Analog & Mixed-Signal Circuit Design\nSynopsys\, Inc. \n\n\n\n\n\n\n\n\n\n\n\nNoman Hai received the B.E. degree from NED University\, Karachi\, Pakistan in 2002 and the M.Sc. degree in Electrical Engineering from Linkoping University\, Sweden in 2006 and the Ph.D. degree from University of Waterloo\, Canada\, in 2012. He has worked at Philips Semiconductors\, MACOM\, Movellus and Synopsys as an analog design engineer where he was involved in designing high speed analog circuits for wireline and A.I. applications. Currently he is an Analog Design Manager at Synopsys where he is involved in designing high speed interface IP circuits. His current interests include high speed I/O circuits\, design methodology and automation\, and mixed-signal circuits. He holds three U.S. patents.
URL:https://marketingeda.com/event/cmos-circuit-techniques-for-wireline-transmitters-part-ii/
CATEGORIES:IP,Webinar
ATTACH;FMTTYPE=image/jpeg:https://marketingeda.com/wp-content/uploads/Synopsys-November-29-2023-1.jpg
END:VEVENT
BEGIN:VEVENT
DTSTART;TZID=UTC:20231128T120000
DTEND;TZID=UTC:20231128T130000
DTSTAMP:20231103T162108Z
CREATED:20231103T162108Z
LAST-MODIFIED:20231103T162108Z
UID:7027-1701172800-1701176400@marketingeda.com
SUMMARY:Auto-generation of Verification Infrastructure for IP to SoC
DESCRIPTION:Agenda (BST):\n\n\n\n\n\n\n\nTime\nSession Description\nSlides\nVideos\n\n\n12.00 GMT\nWelcome and Introduction \nMike Bartley\,Tessolve\n\n\n\n\n12.00 GMT\nAgnisys\n\n\n\n\n12.30 GMT\nImperas\n\n\n\n\n12.45 GMT\nBreker\n\n\n\n\n13.00 GMT\n  \nClose\n\n\n\n\n\nAbout DVClub\n\n\n\n\nThe principal goal of each DVCLUB meeting is to have fun while helping build the European verification community through regular educational and networking events. Attendance at DVClub Europe meetings is free and is open to all non-service provider semiconductor professionals. Each meeting addresses a specific issue faced by the design and verification community and whatever your speciality provides an excellent opportunity for updating knowledge as well as share experiences\, insights and issues with other members of the verification community.
URL:https://marketingeda.com/event/auto-generation-of-verification-infrastructure-for-ip-to-soc/
CATEGORIES:EDA,Webinar
ATTACH;FMTTYPE=image/jpeg:https://marketingeda.com/wp-content/uploads/DVClub-November-28-2023.jpg
END:VEVENT
BEGIN:VEVENT
DTSTART;TZID=America/Los_Angeles:20231128T100000
DTEND;TZID=America/Los_Angeles:20231128T110000
DTSTAMP:20231115T211609Z
CREATED:20231115T211609Z
LAST-MODIFIED:20231115T211609Z
UID:7101-1701165600-1701169200@marketingeda.com
SUMMARY:Making the Right Connections - Taking the Guess Work out of DFT Connectivity Validation
DESCRIPTION:System-on-Chip (SoC) designs continue to grow in both size and complexity in order to meet the ever-growing performance and power demands associated with modern technology. To keep up with this fast-paced evolution\, the corresponding design-for-test (DFT) logic required for manufacturing tests has also become more complex. Increasing transistor density\, combined with a growing mix of both internally developed and third-party IP present multiple challenges related to validating DFT connections. These include multiple power and clock domains\, complex fault models\, and pressure to achieve low DPPM and high coverage. Detecting and fixing these DFT connectivity issues early in the design flow is critical to ensure that there are no connectivity verification escapes occur later in the design process as these can cause ECOs close to tape-out. Furthermore\, it is becoming increasingly important to keep the approach design agnostic so that the same technique can be deployed on any IP / block\, including those from third party vendors. \nThis Synopsys webinar explores techniques for addressing these connectivity challenges using the capabilities available in Synopsys TestMAX™ Advisor. The presentation will examine the main characteristics of effective and robust connectivity checks and cover topics including basic customizable connectivity checks\, the use of dynamic defined conditional connectivity macros and showcase the latest GUI analysis and debug capabilities. As well as being well suited to dealing with DFT connection challenges the tools and techniques highlighted in this webinar are also equally effective for detecting functional connectivity issues. \n  \n\n\n\n\n\n\n\n\n\nSpeakers\n\n\nListed below are the industry leaders scheduled to speak. \n\n\n\n\n\n\n\n\n\n\n\n\n\n\n\n\n\n\n\n\n\n\n\n\n\n\nRamsay Allen\n\n\nProduct Management\, Manager\nSynopsys\, Inc. \n\n\n\n\n\n\n\n\n\n\n\nRamsay is a Senior Product Manager in the Synopsys EDA Group (EDAG). Before joining Synopsys he was the Marketing Manager at Moortec Semiconductor Ltd\, who were global leaders for advanced node embedded in-chip monitoring solutions. Moortec were acquired by Synopsys in November 2020 and the well-established monitoring IP now forms part of the foundation of the Synopsys SLM platform. \n\n\n\n\n\n\n\n\n\n\n\n\n\n\n\n\n\n\n\n\n\n\n\n\n\n\n\n\n\n\n\nTushar Jeevan\n\n\nManager\, R&D\nSynopsys\, Inc. \n\n\n\n\n\n\n\n\n\n\n\nTushar Jeevan is an R&D Manager in the Hardware Analytics and Test Group at Synopsys. He joined Synopsys in 2015 through the acquisition of Atrenta. He has been working in the EDA industry for the last 9 years focused in the areas of software-driven automation technologies. Tushar has a bachelor’s degree in Electronics and Communication from Delhi College of Engineering.
URL:https://marketingeda.com/event/making-the-right-connections-taking-the-guess-work-out-of-dft-connectivity-validation/
CATEGORIES:EDA,Webinar
ATTACH;FMTTYPE=image/jpeg:https://marketingeda.com/wp-content/uploads/Synopsys-NOvember-28-2023.jpg
END:VEVENT
BEGIN:VEVENT
DTSTART;TZID=America/Los_Angeles:20231121T080000
DTEND;TZID=America/Los_Angeles:20231121T100000
DTSTAMP:20231022T002710Z
CREATED:20231022T002710Z
LAST-MODIFIED:20231022T002710Z
UID:6981-1700553600-1700560800@marketingeda.com
SUMMARY:RTL Power Optimization: Applying Best Practices to Overcome Low-Power Design Challenges
DESCRIPTION:Designers face enormous challenges for low-power designs. Whether it is IoT at the edge\, AI in the datacenter\, robotics or ADAS\, the demand for increased functionality in SoCs is rapidly outpacing the power budget. Power must be considered at every stage of chip design including performance\, reliability and packaging. Waiting to address power until late in the design cycle – post-netlist or during physical implementation – can be extremely costly. The design may overrun the power budget\, overheat\, or have long term reliability issues that cannot be addressed at the gate level\, layout or package selection. The best point in the design cycle to address power is at the beginning during the architectural and RTL stages. The earlier power analysis and optimization starts\, the more likely a chip will meet its power objectives. \nIn this virtual seminar\, you will learn the best practices for applying RTL power optimization. These practices are essential for realizing low-power\, energy efficient designs and can help you meet power budgets\, mitigate potential reliability issues arising out of power and discover thermal issues early to take corrective action. NXP will present their perspective on applying these techniques. You will learn how Siemens EDA’s PowerPro low-power design platform helps simplify low-power design for RTL designers and allows coarse as well as fine grain power analysis and optimization to achieve truly low-power\, energy efficient designs. \n  \nSpeakers:\n\n\n\n\n\nQazi Faheem Ahmed\nPrincipal Product Manager for PowerPro\, Siemens EDA\n\n\nQazi is the Principal Product Manager for PowerPro low-power platform at Siemens EDA. He has over 18 years of experience spanning across ASIC/FPGA design and EDA. \n\n\n\nVasundhra Kaushal\nFront-end ASIC Designer\, NXP\n\n\nVasundhra has worked in the field of front-end ASIC design for more than 6 years. Prior to working with NXP\, Vasundhra has worked with Intel for around 5 yrs in frontend RTL design\, DFT. She has also owned frontend design power with owning UPF. Most recently\, Vasundhra has been working in NXP for the last 1.5 years\, owning the complete RTL to GDS power flow. \nVasundhra holds a Master’s degree in VLSI from Vellore Institute of Technology.
URL:https://marketingeda.com/event/rtl-power-optimization-applying-best-practices-to-overcome-low-power-design-challenges/
CATEGORIES:EDA,Webinar
ATTACH;FMTTYPE=image/jpeg:https://marketingeda.com/wp-content/uploads/Siemens-November-21-2023.jpg
END:VEVENT
BEGIN:VEVENT
DTSTART;TZID=America/Los_Angeles:20231116T170000
DTEND;TZID=America/Los_Angeles:20231116T170000
DTSTAMP:20231108T222010Z
CREATED:20231108T222010Z
LAST-MODIFIED:20231108T222010Z
UID:7064-1700154000-1700154000@marketingeda.com
SUMMARY:Latest Innovations and Updates in ASICs
DESCRIPTION:In this webinar Jeff DiCorpo & Matt Venn will delve into the latest ASIC developments\, including the game-changing OpenFrame – a new Caravel version expanding your design possibilities by 50%. \nTopics Include: \n– OpenFrame – a new version of Caravel that gives 50% more area \n– GPIO configuration questions \n– The new cocotb testing framework \n– IPM – The new IP manager tool \n– OpenLane design integration options \n– GFMPW-1 sponsored by Google
URL:https://marketingeda.com/event/latest-innovations-and-updates-in-asics/
CATEGORIES:EDA,IP,Webinar
ATTACH;FMTTYPE=image/jpeg:https://marketingeda.com/wp-content/uploads/efabless-November-16-2023.jpg
END:VEVENT
BEGIN:VEVENT
DTSTART;TZID=America/Los_Angeles:20231116T110000
DTEND;TZID=America/Los_Angeles:20231116T120000
DTSTAMP:20231009T172654Z
CREATED:20231009T172654Z
LAST-MODIFIED:20231009T172654Z
UID:6930-1700132400-1700136000@marketingeda.com
SUMMARY:System Simulation of Versal ACAP Designs
DESCRIPTION:AVersal ACAP\, developed by Xilinx/AMD\, is a groundbreaking adaptable platform composed of AI Engine (AIE)\, Processing System (PS)\, Programmable Logic (PL)\, Network on Chip (NoC) and a wide range of hardened domain-specific IPs. Versal ACAP enables the efficient execution of complex algorithms and accelerates workloads\, including machine learning\, embedded computing\, and high-performance computing. \nIn this webinar\, we will introduce Versal ACAP (and discuss the different types of simulation flows and models available) and QEMU (the open-source system emulator) and its co-simulation interface with Riviera-PRO. We will also show how to run a system simulation of a Versal example design. \nRiviera-PRO supports system simulation of Versal ACAP designs based on the Vitis™ hardware emulation flow for testing the interactions between PL\, PS and AIE. The entire hardware emulation setup and system integration is done within the Vitis environment. It runs the AIE simulator for the graph application\, Riviera-PRO’s simulator for the PL kernels\, and  QEMU for the PS host application. SystemC models are also available for the AIE and NoC\, which can also be simulated in Riviera-PRO. \n  \nAgenda:\n\nVersal ACAP Overview\nVersal Simulation Flows and Simulation Models\nIntroduction to QEMU\nHardware Emulation (System Simulation)\nDemo\nConclusions\nQ&A\n\nWebinar Duration\n\n45 min presentation/live demo\n15 min Q&A\n\nPresenter Bio: \n \nLouie De Luna is Aldec’s Director of Marketing with 20+ years’ experience in FPGA/SoC design verification and EDA tools. He currently directs the overall product and technical marketing of Aldec’s design verification solutions. He earned his B.S. in Computer Engineering from University of Nevada\, Las Vegas\, in 2001.  His practical engineering experience includes simulation-based verification\, linting\, CDC analysis\, and hardware-assisted verification.
URL:https://marketingeda.com/event/system-simulation-of-versal-acap-designs/
CATEGORIES:EDA,IP,Webinar
ATTACH;FMTTYPE=image/jpeg:https://marketingeda.com/wp-content/uploads/Aldec-November-16-2023.jpg
END:VEVENT
BEGIN:VEVENT
DTSTART;TZID=America/Los_Angeles:20231116T100000
DTEND;TZID=America/Los_Angeles:20231116T110000
DTSTAMP:20231113T182451Z
CREATED:20231113T182330Z
LAST-MODIFIED:20231113T182451Z
UID:7079-1700128800-1700132400@marketingeda.com
SUMMARY:Webinar Series | RISC-V Ready for Prime Time?
DESCRIPTION:Join us for session II of our webinar series where we delve into the intricacies of RISC-V core integration and explore strategies to overcome the unique verification challenges that design and verification engineers encounter along the way. \nWhether you’re an engineer looking to enhance your understanding of RISC-V or a technology enthusiast keen on staying at the forefront of innovation\, this webinar will provide invaluable insights\, practical strategies\, and real-world examples to help you conquer the verification hurdles associated with RISC-V integration. \nSign Up Here to Get the Zoom Link – https://www.impare.cloud/webinar/session-2 \n  \nAGENDA\n\nIntroduction to RISC-V: Understanding the modularity and appeal of RISC-V.\nCore Integration Challenges: Exploring the intricacies of integrating RISC-V cores into SoCs\, ASICs\, and FPGAs.\nVerification Strategies: Unveiling the tools and methodologies to address power\, performance\, concurrency\, inter-core communication\, synchronization\, security\, and safety concerns.\nReal-World Examples: Learning from practical case studies to navigate RISC-V core integration successfully.\nQ&A Session: An opportunity to get your questions answered by our experts.
URL:https://marketingeda.com/event/webinar-series-risc-v-ready-for-prime-time/
CATEGORIES:IP,Webinar
ATTACH;FMTTYPE=image/jpeg:https://marketingeda.com/wp-content/uploads/Impare-November-16-2023.jpg
END:VEVENT
BEGIN:VEVENT
DTSTART;TZID=America/Los_Angeles:20231116T100000
DTEND;TZID=America/Los_Angeles:20231116T110000
DTSTAMP:20231101T172710Z
CREATED:20231101T172710Z
LAST-MODIFIED:20231101T172710Z
UID:7019-1700128800-1700132400@marketingeda.com
SUMMARY:Enabling Electromagnetic Simulations with Encrypted Components
DESCRIPTION:High-fidelity simulations in the ever-widening realm of complete systems analysis requires incorporating vendor-supplied models for accuracy. However\, vendors are reluctant to share their proprietary intellectual property. Cadence enables the ecosystem and supports model creators by allowing them to encrypt their geometries and protect their IP while sharing them with their customers for simulation. \n\nThis webinar will demonstrate the use of these models for complete system designs and showcase some of Cadence’s Clarity encrypted models that are part of a library developed by Modelithics.
URL:https://marketingeda.com/event/enabling-electromagnetic-simulations-with-encrypted-components/
CATEGORIES:EDA,Webinar
ATTACH;FMTTYPE=image/jpeg:https://marketingeda.com/wp-content/uploads/Cadence-November-16-2023.jpg
END:VEVENT
BEGIN:VEVENT
DTSTART;TZID=America/Los_Angeles:20231116T090000
DTEND;TZID=America/Los_Angeles:20231116T100000
DTSTAMP:20231115T180404Z
CREATED:20231115T180404Z
LAST-MODIFIED:20231115T180404Z
UID:7094-1700125200-1700128800@marketingeda.com
SUMMARY:Boost SoC debug and analytics with embedded software and smart monitors
DESCRIPTION:On-chip monitors and debug structures can dramatically simplify debug\, validation\, analytics\, and optimization of complex SoCs. Such monitors are often accessed by software executing on an external host or debugger via USB or JTAG.  In this webinar\, we will demonstrate how embedded software running on the target silicon for many use cases provides a superior alternative to extract even more insights out of your on-chip monitors and debug structures for analytics and optimization\, and to create a self-contained on-chip monitoring system. \nWe will explore how the Tessent Embedded SDK can be used to build embedded software applications to orchestrate Tessent Embedded Analytics on-chip smart monitors. With the combination of embedded software and a complete on-chip monitoring solution\, you can perform non-intrusive real-time logging\, cache more data for later analysis\, enable real-time performance analysis and anomaly detection. \n  \nWhat you will learn: \n\nDiscover the Tessent Embedded Software Development Kit (Embedded SDK)\, a suite of software utilities that allows SoCs to be equipped with self-contained monitoring and analytics capabilities\nExplore which debug\, optimization and monitoring tasks can be simplified using embedded software.\nLearn how to develop embedded applications using the Tessent Embedded SDK\n\n  \nWho Should Attend: \n\nEmbedded SW Engineers\nSilicon bring-up engineers\nSoC architects\n\n  \nSpeaker\n \nNaga Nagarajan \nSoftware Engineer \nSiemens EDA \n  \nNaga Nagarajan is a software engineer at Siemens EDA. Naga began his career with UltraSoC (acquired by Mentor Graphics which is now Siemens EDA) where he focused on improving the host-based analytics software product known as SystemInsight. Naga now focuses on the development of the Tessent Embedded SDK products\, including the entire implementation of critical features such as in-life\, real-time performance monitoring and analytics. Naga holds an MEng in Electrical and Electronic Engineering.
URL:https://marketingeda.com/event/boost-soc-debug-and-analytics-with-embedded-software-and-smart-monitors/
CATEGORIES:EDA,IP,Webinar
ATTACH;FMTTYPE=image/jpeg:https://marketingeda.com/wp-content/uploads/Siemens-November-16-2023.jpg
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BEGIN:VEVENT
DTSTART;TZID=Asia/Jerusalem:20231115T170000
DTEND;TZID=Asia/Jerusalem:20231115T180000
DTSTAMP:20231109T174407Z
CREATED:20231109T174407Z
LAST-MODIFIED:20231109T174407Z
UID:7067-1700067600-1700071200@marketingeda.com
SUMMARY:ParagonX - Intelligent analysis\, visualization and debugging tool for IC layout parasitics
DESCRIPTION:I would like to invite you to Ansys Paragon X webinar that we are hosting on Wednesday\, November 15th 17:00 PM (Israel time). \nParagonX intended for analyzing\, simulating\, debugging\, visualizing\, and improving IC layout parasitics. It helps analog designers and layout engineers to immediately understand the parasitics and allows to reduce parasitics debugging time from days\, weeks\, and months down to minutes or hours. \nSpeaker: Maxim Ershov\, Senior Director R&D\, Ansys and formerly CEO and CTO at Diakopto
URL:https://marketingeda.com/event/paragonx-intelligent-analysis-visualization-and-debugging-tool-for-ic-layout-parasitics/
CATEGORIES:EDA,Webinar
ATTACH;FMTTYPE=image/jpeg:https://marketingeda.com/wp-content/uploads/Ansys-November-15-2023-.jpg
END:VEVENT
BEGIN:VEVENT
DTSTART;TZID=America/New_York:20231115T090000
DTEND;TZID=America/New_York:20231115T170000
DTSTAMP:20231018T180605Z
CREATED:20231018T180605Z
LAST-MODIFIED:20231018T180605Z
UID:6969-1700038800-1700067600@marketingeda.com
SUMMARY:ASIP University Day 2023
DESCRIPTION:ASIP University Day: Domain-Specific Processor Design using ASIP Designer\n\n\nApplication-specific instruction set processors (ASIPs) have established themselves as an important implementation option for modern SoCs\, i.e. when standard processor IP cannot meet challenging application-specific requirements\, and fixed hardware is not flexible enough.  Heterogeneous multicore systems including ASIPs are now becoming more mainstream. Domains such as artificial intelligence\, image and video processing or automated driving assistance have fueled the development of such ASIPs\, and triggered many university projects.  Processor design projects such as the RISC-V initiative also initiated a lot of interest.  With all the commercial activity around RISC-V these days\, it has outgrown UC Berkeley. \nSynopsys ASIP Designer is the market leading tool for ASIP design\, verification\, and programming. It is used by leading companies around the globe with hundreds of successful projects to date. \nAt this informal event\, leading university teams will present results from their ongoing ASIP projects in a variety of application domains. Synopsys will share insight on market trends\, and provide a technical update on ASIP Designer along with reference examples.
URL:https://marketingeda.com/event/asip-university-day-2023/
CATEGORIES:EDA,IP,Webinar
ATTACH;FMTTYPE=image/jpeg:https://marketingeda.com/wp-content/uploads/Synopsys-November-15-2023.jpg
END:VEVENT
BEGIN:VEVENT
DTSTART;TZID=America/Los_Angeles:20231115T090000
DTEND;TZID=America/Los_Angeles:20231115T100000
DTSTAMP:20231103T171645Z
CREATED:20231103T171645Z
LAST-MODIFIED:20231103T171645Z
UID:7033-1700038800-1700042400@marketingeda.com
SUMMARY:Achieve 95% Accurate Power Measurement during Architectural Exploration
DESCRIPTION:Are you in the conceptualization and architectural exploration phases\, where assessing the power budget is of paramount importance? If you’re looking to achieve precise power measurement for critical aspects like embedded software\, power management algorithms\, hardware configurations\, and more\, this webinar is tailor-made for you. \n  \nWebinar: How to achieve 95%+ Accurate Power Measurement during Architecture Exploration? \n\nRegister now to secure your spot for Wednesday\, November 15th\, 2023 \n\nSession 1: For Asia & Europe: https://bit.ly/40cR4ek \nTime:  5:00PM Japan/Korea\, 4:00PM China\, 1:30PM India and 9:00 AM CEST. \n\nSession 2: For US & Canada: https://bit.ly/3Mhwzrf \nTime: 9AM PST\, 12PM EST \n  \nDuring this webinar\, we will introduce you to VisualSim System-level Power 2.0\, the only system-level\, power modeling solution that support measurements from IP to SoC and Systems; generate a Digital Twin for early validation\, and support for the entire power chain from generation\, battery\, consumption and conservation. \n\nWould you like to accurately measure the:  \n\n\nPower consumed for a proposed embedded software or firmware? \nSavings of a Power Management Algorithm prior to development? \nPower impact of hardware configuration change? \nTrade-off between Power and Performance? \nTemperature\, heat\, peak power and cumulative power? \n\n\nRegister now to secure your spot for Wednesday\, November 15th\, 2023 and find answers to many such questions!  \n  \nWho should attend? This webinar is tailored for power architects\, systems engineers\, software designers\, systems integrators\, and thermal engineers. \n  \nDon’t miss out on this invaluable opportunity to gain deep insights into achieving 95%+ accurate power measurement during architecture exploration.  \n\nSession 1: For Asia & Europe: https://bit.ly/40cR4ek \nTime:  5:00PM Japan/Korea\, 4:00PM China\, 1:30PM India and 9:00 AM CEST. \n\nSession 2: For US & Canada: https://bit.ly/3Mhwzrf \nTime: 9AM PST\, 12PM EST \n  \nWe look forward to having you with us on 15th Nov’23 at your preferred time.Together\, we’ll explore the power of VisualSim and its role in shaping your architectural decisions. \n  \nBest regards\, \nTeam Mirabilis Design
URL:https://marketingeda.com/event/achieve-95-accurate-power-measurement-during-architectural-exploration/
CATEGORIES:EDA,Webinar
ATTACH;FMTTYPE=image/jpeg:https://marketingeda.com/wp-content/uploads/Mirabilis-November-15-2023.jpg
END:VEVENT
BEGIN:VEVENT
DTSTART;TZID=America/Los_Angeles:20231115T080000
DTEND;TZID=America/Los_Angeles:20231115T090000
DTSTAMP:20231103T163102Z
CREATED:20231103T163102Z
LAST-MODIFIED:20231103T163102Z
UID:7030-1700035200-1700038800@marketingeda.com
SUMMARY:Fail-safe Electronics for Automotive
DESCRIPTION:I would like to invite you to attend our upcoming webinar on Wednesday\, November 15 at 8 a.m. PST. This 1-hour panel will feature SoC experts from CARIAD\, Infineon\, NXP and proteanTecs\, who bridge both the semiconductor and automotive worlds. The discussion will revolve around “Fail-Safe Electronics for Automotive\,” a topic of paramount importance in today’s technology-driven automotive industry. \n\n\n\n\n\n\nPanelists: \n\nHeinz Wagensonner\, Senior SoC Designer\, CARIAD\nJens Rosenbusch\, Sr. Principal Engineer\, SoC Safety Architecture\, Infineon\nXiankun “Robert” Jin\, Automotive SoC Safety Architect\, NXP\nGal Carmel\, Executive VP\, GM Automotive\, proteanTecs\n\nModerated by Circulor’s Chief External Affairs Officer\, Ellen Carey. \n\n\n\n\n\n\n\n\n\n\n\n\nTopics covered:\n\nFail-safe system architectures\nDecoupling of hardware/ software\nSoC and ECU lifetime monitoring solutions\nTradeoffs between reliability\, performance and costs
URL:https://marketingeda.com/event/fail-safe-electronics-for-automotive/
CATEGORIES:EDA,Webinar
ATTACH;FMTTYPE=image/jpeg:https://marketingeda.com/wp-content/uploads/proteanTecs-November-15-2023.jpg
END:VEVENT
BEGIN:VEVENT
DTSTART;TZID=America/Los_Angeles:20231114T110000
DTEND;TZID=America/Los_Angeles:20231114T120000
DTSTAMP:20231103T204425Z
CREATED:20231103T204425Z
LAST-MODIFIED:20231103T204425Z
UID:7040-1699959600-1699963200@marketingeda.com
SUMMARY:Why Chiplets with UCIe are the Next Big Thing
DESCRIPTION:Artificial intelligence (AI) and virtual reality (VR) require fast\, efficient\, low-power technologies. Transistors are becoming harder and harder to shrink\, so chiplets are a promising alternative. Chiplets are small\, modular dies that use UCIe\, an open industry standard\, to communicate with each other. Combined in a Systems-on-Package (SoP)\, they provide superior performance\, reduced power consumption\, and increased design flexibility for customized applications such as cell phones\, autonomous vehicles\, etc. In this panel session\, signal and power integrity experts will discuss: \n  \n\nIndustry trends and why chiplets with UCIe are the next big thing.\nSignal and power integrity considerations when integrating chiplets and UCIe interfaces.\nEDA tools evolved\, and how to streamline chiplets integration into the design workflow.\n\nSpeakers:\n\n\n\nHeeSoo Lee\nSerDes/DDR Product Owner\, Keysight Technologies\n\n\nHeeSoo Lee is the SerDes/DDR product owner in the EDA Software group of Keysight Technologies DES division\, located in Santa Rosa\, Calif. He has held several positions in Keysight Technologies\, Agilent Technologies and Hewlett-Packard\, including consulting business manager\, technical marketing lead and field applications engineer since 1989. Prior to these positions\, he worked for Daeryung Ind. Inc. as an RF/MW circuit design engineer. He has over 30 years of design and simulation experience in RF\, microwave and high-speed digital designs. He graduated with a BSEE from Hankuk Aviation University\, South Korea. \n\nHeidi Barnes\nSenior Application Engineer and Power Integrity Product Owner\, Keysight Technologies\n\n\nHeidi Barnes is a Senior Application Engineer and Power Integrity Product Owner at Keysight\, specializing in High-Speed Digital applications. With 26+ years of experience in the field of electronic design automation\, her recent activities include the application of electromagnetic\, transient\, and channel simulators to solve signal and power integrity challenges. She contributed to the IEEE-370 Standard on fixture removal for high-frequency interconnects and is Co-Chair for the IEEE EPS EDMS Packaging Benchmark Sub-Committee. Heidi holds five patents and was awarded the DesignCon Engineer of the Year in 2017. \n\nRandy White\nMemory Solutions Program Manager\, Keysight Technologies\n\n\nRandy White is the Memory Solutions Program Manager for Keysight Technologies. He is focused on test methodologies for emerging memory technologies in server\, mobile\, and embedded applications. Randy has spent the last 20 years investigating signal integrity measurement techniques\, including de-embedding algorithms\, measurement/model correlation\, high-speed measurements for real-time & sampling oscilloscopes\, and BERTs & AWGs. He has participated on many standards committees\, including PCI-SIG\, USB-IF\, SATA-IO\, and JEDEC\, to help define new test methodologies. He is currently the chair of the JEDEC JC40.5 Logic Validation subcommittee. He graduated with a BSEE from Oregon State University.
URL:https://marketingeda.com/event/why-chiplets-with-ucie-are-the-next-big-thing/
CATEGORIES:EDA,IP,Webinar
ATTACH;FMTTYPE=image/jpeg:https://marketingeda.com/wp-content/uploads/Keysight-November-14-2023.jpg
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END:VCALENDAR