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BEGIN:VEVENT
DTSTART;TZID=America/Los_Angeles:20231207T080000
DTEND;TZID=America/Los_Angeles:20231207T090000
DTSTAMP:20231117T204354Z
CREATED:20231117T204354Z
LAST-MODIFIED:20231117T204354Z
UID:7107-1701936000-1701939600@marketingeda.com
SUMMARY:Multi-Die System Verification with Siemens Avery UCIe VIP
DESCRIPTION:Conventional monolithic SoCs are becoming a bottleneck for power\, performance\, and area (PPA)\, creating limitations for Data-intensive applications like high-performance computing (HPC)\, machine learning (ML) and artificial intelligence (AI)\, and for hyperscale data centers. These bottlenecks are challenging Moore’s law\, hindering the industry’s ability to continue scaling designs. Chiplets are rapidly becoming the means to overcome the slowing of Moore’s Law\, but the semiconductor industry needs standardized interconnects to allow scaling up these systems\, with 2D\, 2.5D and even 3D packaging technologies. \nUniversal Chiplet Interconnect express (UCIe) is a chiplet interconnect standard that enables seamless interoperation and connectivity between the chiplets/dies without impacting the overall performance. UCIe offers several benefits with lower power consumption\, improved performance with the same latency of the system. \nIn this online seminar\, we will introduce you to Siemens EDA’s Verification Portfolio and then deep dive into UCIe Verification IP\, discussing its key features such as dynamic block-level and SoC level testbench creation\, traffic generation\, error injection\, debug features\, and performance monitoring. Siemens Avery UCIe Verification IP is a leading solution in the market\, runs on all major simulators and is a native SystemVerilog/UVM class-based Verification IP. \n  \nWhat You Will Learn: \n\nWhat is the Universal Chiplet Interconnect Express (UCIe)\nWhy do we need UCIe in chiplet designs: its evolution and application.\nDesign and Verification considerations when planning a UCIe based design.\nSiemens Avery UCIe Verification IP’s unique features.\n\nTechnical Demonstration. \nEnvironment / Testbench Creation \nDynamic Configuration \nTraffic Generation \nError Injection \nDebug features \n\nTechnical Demonstration\n\nWho Should Attend: \n\nDesign\, Verification Engineers\, Managers and Architects working on or planning UCIe design projects\n\n  \nWhat/Which Products are Covered:  \n\nUCIe\nPCIe\nCXL\nChiplets\n\n\n\n\nSpeakers\n\n\n\n\nLuis E. Rodriguez\nSiemens EDA\n\n\nLuis E. Rodriguez has worked on SoC and IP functional verification for over 17 years including developing and deploying PCIe\, CXL\, NVMe\, and UCIe Verification IPs. He has participated and contributed to several protocol workgroups like PCIe\, CCIX\, GENZ (Compliance Workgroup chair); and CXL\, where he helped define Compliance Testing for CXL 2.0. At Siemens he is focused on the architecture of the UCIe Verification IP\, as well as participating in several cross functional teams focused on finding synergies between verification IP and other Siemens EDA tools. He received his Master’s in Computer Science from National Taiwan University and is a fan of learning new languages. \n  \n\n\n\n\n\nJustin Bunnell\nTechnical Product Manager\nSiemens EDA\n\n\nJustin Bunnell is a Technical Product Manager at Siemens EDA\, responsible for the architecture and development of Siemens Avery UCIe Verification IP solution along with several other custom VIPs. He has over 12 years of experience in hardware design verification and simulation software development and holds a Master of Engineering Degree in Computer Engineering from Iowa State University.
URL:https://marketingeda.com/event/multi-die-system-verification-with-siemens-avery-ucie-vip/
CATEGORIES:EDA,IP,Webinar
ATTACH;FMTTYPE=image/jpeg:https://marketingeda.com/wp-content/uploads/Siemens-December-7-2023.jpg
END:VEVENT
BEGIN:VEVENT
DTSTART;TZID=America/Los_Angeles:20231205T100000
DTEND;TZID=America/Los_Angeles:20231205T110000
DTSTAMP:20231108T203535Z
CREATED:20231108T203535Z
LAST-MODIFIED:20231108T203535Z
UID:7061-1701770400-1701774000@marketingeda.com
SUMMARY:Rigid Flex PCB In-Design Electromagnetic Analysis Workflow
DESCRIPTION:Today’s electronic products increasingly use Rigid-Flex PCBs to compress form factors\, reduce weight\, and increase cost-effectiveness. For many commercially available 3D numerical solver technologies (FEM and FDTD)\, the electromagnetic (EM) analysis of rigid-flex PCBs has always been challenging due to the complexity of the 3D designs. Much of this complexity comes from bending the board into small spaces and keeping fidelity\, like hatched ground and power planes\, and attaching shielding mask layers. \n\nThis webinar will highlight the key challenges involved in the design and analysis of rigid-flex PCBs\, specifically 3D electromagnetic simulation. Attendees will learn how to set up and perform the Rigid-Flex bending analysis using the Cadence Clarity 3D EM Solver for S-parameter extraction and parameterize bending angles to mitigate EMC/EMI issues.
URL:https://marketingeda.com/event/rigid-flex-pcb-in-design-electromagnetic-analysis-workflow/
CATEGORIES:EDA,Webinar
ATTACH;FMTTYPE=image/jpeg:https://marketingeda.com/wp-content/uploads/Cadence-December-5-2023.jpg
END:VEVENT
BEGIN:VEVENT
DTSTART;TZID=America/Los_Angeles:20231130T090000
DTEND;TZID=America/Los_Angeles:20231130T100000
DTSTAMP:20231115T181114Z
CREATED:20231115T181059Z
LAST-MODIFIED:20231115T181114Z
UID:7097-1701334800-1701338400@marketingeda.com
SUMMARY:Latest Innovations and Updates in ASICs with Efabless
DESCRIPTION:In this webinar Jeff DiCorpo & Matt Venn will delve into the latest ASIC developments\, including the game-changing OpenFrame – a new Caravel version expanding your design possibilities by 50%. \nTopics Include: \n\nOpenFrame – a new version of Caravel that gives 50% more area\nGPIO configuration questions\nThe new cocotb testing framework\nIPM – The new IP manager tool\nOpenLane design integration options\nGFMPW-1 sponsored by Google
URL:https://marketingeda.com/event/latest-innovations-and-updates-in-asics-with-efabless/
CATEGORIES:EDA,IP,Webinar
ATTACH;FMTTYPE=image/jpeg:https://marketingeda.com/wp-content/uploads/efabless-November-30-2023.jpg
END:VEVENT
BEGIN:VEVENT
DTSTART;TZID=America/Los_Angeles:20231130T080000
DTEND;TZID=America/Los_Angeles:20231130T090000
DTSTAMP:20231108T203020Z
CREATED:20231108T203020Z
LAST-MODIFIED:20231108T203020Z
UID:7058-1701331200-1701334800@marketingeda.com
SUMMARY:Large Eddy CFD Simulation for Automotive Aerodynamics
DESCRIPTION:Wall-modeled large eddy simulations (WMLES) of complex vehicle geometries offer highly accurate results but can be challenging in terms of speed and cost. In this webinar\, learn how to maximize the throughput of these simulations with Fidelity CharLES and how the solver’s GPU acceleration lowers the cost of using WMLES in engineering design. \nWe will present the Fidelity CharLES workflow applied to automotive vehicle aerodynamics simulations\, built around the low-Mach isentropic formulation of the Fidelity CharLES flow solver. \nDiscover fully scriptable meshing and simulation and lightweight interactive visualization of simulation data as some of the main benefits. Fidelity CharLES produces time-dependent\, three-dimensional data from which a detailed analysis of flow physics can be performed\, and integrated quantities such as lift and drag coefficients are readily available. \n\nWhat you’ll learn: \n\nHow to build a WMLES-suitable Voronoi mesh of an automotive geometry in Stitch\nHow to set up a wind tunnel simulation of a vehicle in Fidelity CharLES\nHow to configure relevant post-processing quantities and interactively explore the 3D flow field
URL:https://marketingeda.com/event/large-eddy-cfd-simulation-for-automotive-aerodynamics/
CATEGORIES:CFD,Webinar
ATTACH;FMTTYPE=image/jpeg:https://marketingeda.com/wp-content/uploads/Cadence-November-30-2023.jpg
END:VEVENT
BEGIN:VEVENT
DTSTART;TZID=America/Los_Angeles:20231129T100000
DTEND;TZID=America/Los_Angeles:20231129T110000
DTSTAMP:20231120T172317Z
CREATED:20231113T181552Z
LAST-MODIFIED:20231120T172317Z
UID:7076-1701252000-1701255600@marketingeda.com
SUMMARY:CMOS Circuit Techniques for Wireline Transmitters Part II
DESCRIPTION:Synopsys Webinar – Part II \nIn this 3-part Synopsys webinar series\, we will present how hyperscale data centers are going through a paradigm shift with the advent of technologies like Artificial Intelligence (AI) and edge compute requiring hyperscale data centers to support exponential growth of data volume.  This volume of network traffic demands an increase in bandwidth to 400G\, which is now enabled by 112G Ethernet as the interconnect of choice\, with next generation architectures being designed to operate at 224Gbps supporting upcoming 800G/1.6T switches inside datacenters.  These data rates pose extreme challenges on the entire transceiver.  Attend this webinar series to find out about the challenges posed on the transmitter and a discussion on various techniques used in the different blocks to overcome the challenges of data transmission at 100s of Gbps. \nPart I: Wednesday\, November 8\, 2023 \n\nMotivation for SERDES\nTransmitter Requirements\nCurrent/Voltage Mode Drivers\n\nPart II: Wednesday\, November 29\, 2023 \n\nHigh Order Multiplexers\nFFE Equalization\nDSP-DAC Based TX Architectures\n1-UI Pulse Generation Circuits\n\nPart III: Wednesday\, December 13\, 2023 \n\nOutput Matching Network\nMeasurements and Simulation Techniques\n\n\n\n\n\n\nSpeaker\n\n\nListed below is the industry leader scheduled to speak. \n\n\n\n\n\n\n\n\n\n\n\n\n\n\n\n\n\n\n\n\n\n\n\n\n\n\nNoman Hai\n\n\nManager\, Analog & Mixed-Signal Circuit Design\nSynopsys\, Inc. \n\n\n\n\n\n\n\n\n\n\n\nNoman Hai received the B.E. degree from NED University\, Karachi\, Pakistan in 2002 and the M.Sc. degree in Electrical Engineering from Linkoping University\, Sweden in 2006 and the Ph.D. degree from University of Waterloo\, Canada\, in 2012. He has worked at Philips Semiconductors\, MACOM\, Movellus and Synopsys as an analog design engineer where he was involved in designing high speed analog circuits for wireline and A.I. applications. Currently he is an Analog Design Manager at Synopsys where he is involved in designing high speed interface IP circuits. His current interests include high speed I/O circuits\, design methodology and automation\, and mixed-signal circuits. He holds three U.S. patents.
URL:https://marketingeda.com/event/cmos-circuit-techniques-for-wireline-transmitters-part-ii/
CATEGORIES:IP,Webinar
ATTACH;FMTTYPE=image/jpeg:https://marketingeda.com/wp-content/uploads/Synopsys-November-29-2023-1.jpg
END:VEVENT
BEGIN:VEVENT
DTSTART;TZID=UTC:20231128T120000
DTEND;TZID=UTC:20231128T130000
DTSTAMP:20231103T162108Z
CREATED:20231103T162108Z
LAST-MODIFIED:20231103T162108Z
UID:7027-1701172800-1701176400@marketingeda.com
SUMMARY:Auto-generation of Verification Infrastructure for IP to SoC
DESCRIPTION:Agenda (BST):\n\n\n\n\n\n\n\nTime\nSession Description\nSlides\nVideos\n\n\n12.00 GMT\nWelcome and Introduction \nMike Bartley\,Tessolve\n\n\n\n\n12.00 GMT\nAgnisys\n\n\n\n\n12.30 GMT\nImperas\n\n\n\n\n12.45 GMT\nBreker\n\n\n\n\n13.00 GMT\n  \nClose\n\n\n\n\n\nAbout DVClub\n\n\n\n\nThe principal goal of each DVCLUB meeting is to have fun while helping build the European verification community through regular educational and networking events. Attendance at DVClub Europe meetings is free and is open to all non-service provider semiconductor professionals. Each meeting addresses a specific issue faced by the design and verification community and whatever your speciality provides an excellent opportunity for updating knowledge as well as share experiences\, insights and issues with other members of the verification community.
URL:https://marketingeda.com/event/auto-generation-of-verification-infrastructure-for-ip-to-soc/
CATEGORIES:EDA,Webinar
ATTACH;FMTTYPE=image/jpeg:https://marketingeda.com/wp-content/uploads/DVClub-November-28-2023.jpg
END:VEVENT
BEGIN:VEVENT
DTSTART;TZID=America/Los_Angeles:20231128T100000
DTEND;TZID=America/Los_Angeles:20231128T110000
DTSTAMP:20231115T211609Z
CREATED:20231115T211609Z
LAST-MODIFIED:20231115T211609Z
UID:7101-1701165600-1701169200@marketingeda.com
SUMMARY:Making the Right Connections - Taking the Guess Work out of DFT Connectivity Validation
DESCRIPTION:System-on-Chip (SoC) designs continue to grow in both size and complexity in order to meet the ever-growing performance and power demands associated with modern technology. To keep up with this fast-paced evolution\, the corresponding design-for-test (DFT) logic required for manufacturing tests has also become more complex. Increasing transistor density\, combined with a growing mix of both internally developed and third-party IP present multiple challenges related to validating DFT connections. These include multiple power and clock domains\, complex fault models\, and pressure to achieve low DPPM and high coverage. Detecting and fixing these DFT connectivity issues early in the design flow is critical to ensure that there are no connectivity verification escapes occur later in the design process as these can cause ECOs close to tape-out. Furthermore\, it is becoming increasingly important to keep the approach design agnostic so that the same technique can be deployed on any IP / block\, including those from third party vendors. \nThis Synopsys webinar explores techniques for addressing these connectivity challenges using the capabilities available in Synopsys TestMAX™ Advisor. The presentation will examine the main characteristics of effective and robust connectivity checks and cover topics including basic customizable connectivity checks\, the use of dynamic defined conditional connectivity macros and showcase the latest GUI analysis and debug capabilities. As well as being well suited to dealing with DFT connection challenges the tools and techniques highlighted in this webinar are also equally effective for detecting functional connectivity issues. \n  \n\n\n\n\n\n\n\n\n\nSpeakers\n\n\nListed below are the industry leaders scheduled to speak. \n\n\n\n\n\n\n\n\n\n\n\n\n\n\n\n\n\n\n\n\n\n\n\n\n\n\nRamsay Allen\n\n\nProduct Management\, Manager\nSynopsys\, Inc. \n\n\n\n\n\n\n\n\n\n\n\nRamsay is a Senior Product Manager in the Synopsys EDA Group (EDAG). Before joining Synopsys he was the Marketing Manager at Moortec Semiconductor Ltd\, who were global leaders for advanced node embedded in-chip monitoring solutions. Moortec were acquired by Synopsys in November 2020 and the well-established monitoring IP now forms part of the foundation of the Synopsys SLM platform. \n\n\n\n\n\n\n\n\n\n\n\n\n\n\n\n\n\n\n\n\n\n\n\n\n\n\n\n\n\n\n\nTushar Jeevan\n\n\nManager\, R&D\nSynopsys\, Inc. \n\n\n\n\n\n\n\n\n\n\n\nTushar Jeevan is an R&D Manager in the Hardware Analytics and Test Group at Synopsys. He joined Synopsys in 2015 through the acquisition of Atrenta. He has been working in the EDA industry for the last 9 years focused in the areas of software-driven automation technologies. Tushar has a bachelor’s degree in Electronics and Communication from Delhi College of Engineering.
URL:https://marketingeda.com/event/making-the-right-connections-taking-the-guess-work-out-of-dft-connectivity-validation/
CATEGORIES:EDA,Webinar
ATTACH;FMTTYPE=image/jpeg:https://marketingeda.com/wp-content/uploads/Synopsys-NOvember-28-2023.jpg
END:VEVENT
BEGIN:VEVENT
DTSTART;TZID=America/Los_Angeles:20231121T080000
DTEND;TZID=America/Los_Angeles:20231121T100000
DTSTAMP:20231022T002710Z
CREATED:20231022T002710Z
LAST-MODIFIED:20231022T002710Z
UID:6981-1700553600-1700560800@marketingeda.com
SUMMARY:RTL Power Optimization: Applying Best Practices to Overcome Low-Power Design Challenges
DESCRIPTION:Designers face enormous challenges for low-power designs. Whether it is IoT at the edge\, AI in the datacenter\, robotics or ADAS\, the demand for increased functionality in SoCs is rapidly outpacing the power budget. Power must be considered at every stage of chip design including performance\, reliability and packaging. Waiting to address power until late in the design cycle – post-netlist or during physical implementation – can be extremely costly. The design may overrun the power budget\, overheat\, or have long term reliability issues that cannot be addressed at the gate level\, layout or package selection. The best point in the design cycle to address power is at the beginning during the architectural and RTL stages. The earlier power analysis and optimization starts\, the more likely a chip will meet its power objectives. \nIn this virtual seminar\, you will learn the best practices for applying RTL power optimization. These practices are essential for realizing low-power\, energy efficient designs and can help you meet power budgets\, mitigate potential reliability issues arising out of power and discover thermal issues early to take corrective action. NXP will present their perspective on applying these techniques. You will learn how Siemens EDA’s PowerPro low-power design platform helps simplify low-power design for RTL designers and allows coarse as well as fine grain power analysis and optimization to achieve truly low-power\, energy efficient designs. \n  \nSpeakers:\n\n\n\n\n\nQazi Faheem Ahmed\nPrincipal Product Manager for PowerPro\, Siemens EDA\n\n\nQazi is the Principal Product Manager for PowerPro low-power platform at Siemens EDA. He has over 18 years of experience spanning across ASIC/FPGA design and EDA. \n\n\n\nVasundhra Kaushal\nFront-end ASIC Designer\, NXP\n\n\nVasundhra has worked in the field of front-end ASIC design for more than 6 years. Prior to working with NXP\, Vasundhra has worked with Intel for around 5 yrs in frontend RTL design\, DFT. She has also owned frontend design power with owning UPF. Most recently\, Vasundhra has been working in NXP for the last 1.5 years\, owning the complete RTL to GDS power flow. \nVasundhra holds a Master’s degree in VLSI from Vellore Institute of Technology.
URL:https://marketingeda.com/event/rtl-power-optimization-applying-best-practices-to-overcome-low-power-design-challenges/
CATEGORIES:EDA,Webinar
ATTACH;FMTTYPE=image/jpeg:https://marketingeda.com/wp-content/uploads/Siemens-November-21-2023.jpg
END:VEVENT
BEGIN:VEVENT
DTSTART;TZID=America/Los_Angeles:20231116T170000
DTEND;TZID=America/Los_Angeles:20231116T170000
DTSTAMP:20231108T222010Z
CREATED:20231108T222010Z
LAST-MODIFIED:20231108T222010Z
UID:7064-1700154000-1700154000@marketingeda.com
SUMMARY:Latest Innovations and Updates in ASICs
DESCRIPTION:In this webinar Jeff DiCorpo & Matt Venn will delve into the latest ASIC developments\, including the game-changing OpenFrame – a new Caravel version expanding your design possibilities by 50%. \nTopics Include: \n– OpenFrame – a new version of Caravel that gives 50% more area \n– GPIO configuration questions \n– The new cocotb testing framework \n– IPM – The new IP manager tool \n– OpenLane design integration options \n– GFMPW-1 sponsored by Google
URL:https://marketingeda.com/event/latest-innovations-and-updates-in-asics/
CATEGORIES:EDA,IP,Webinar
ATTACH;FMTTYPE=image/jpeg:https://marketingeda.com/wp-content/uploads/efabless-November-16-2023.jpg
END:VEVENT
BEGIN:VEVENT
DTSTART;TZID=America/Los_Angeles:20231116T110000
DTEND;TZID=America/Los_Angeles:20231116T120000
DTSTAMP:20231009T172654Z
CREATED:20231009T172654Z
LAST-MODIFIED:20231009T172654Z
UID:6930-1700132400-1700136000@marketingeda.com
SUMMARY:System Simulation of Versal ACAP Designs
DESCRIPTION:AVersal ACAP\, developed by Xilinx/AMD\, is a groundbreaking adaptable platform composed of AI Engine (AIE)\, Processing System (PS)\, Programmable Logic (PL)\, Network on Chip (NoC) and a wide range of hardened domain-specific IPs. Versal ACAP enables the efficient execution of complex algorithms and accelerates workloads\, including machine learning\, embedded computing\, and high-performance computing. \nIn this webinar\, we will introduce Versal ACAP (and discuss the different types of simulation flows and models available) and QEMU (the open-source system emulator) and its co-simulation interface with Riviera-PRO. We will also show how to run a system simulation of a Versal example design. \nRiviera-PRO supports system simulation of Versal ACAP designs based on the Vitis™ hardware emulation flow for testing the interactions between PL\, PS and AIE. The entire hardware emulation setup and system integration is done within the Vitis environment. It runs the AIE simulator for the graph application\, Riviera-PRO’s simulator for the PL kernels\, and  QEMU for the PS host application. SystemC models are also available for the AIE and NoC\, which can also be simulated in Riviera-PRO. \n  \nAgenda:\n\nVersal ACAP Overview\nVersal Simulation Flows and Simulation Models\nIntroduction to QEMU\nHardware Emulation (System Simulation)\nDemo\nConclusions\nQ&A\n\nWebinar Duration\n\n45 min presentation/live demo\n15 min Q&A\n\nPresenter Bio: \n \nLouie De Luna is Aldec’s Director of Marketing with 20+ years’ experience in FPGA/SoC design verification and EDA tools. He currently directs the overall product and technical marketing of Aldec’s design verification solutions. He earned his B.S. in Computer Engineering from University of Nevada\, Las Vegas\, in 2001.  His practical engineering experience includes simulation-based verification\, linting\, CDC analysis\, and hardware-assisted verification.
URL:https://marketingeda.com/event/system-simulation-of-versal-acap-designs/
CATEGORIES:EDA,IP,Webinar
ATTACH;FMTTYPE=image/jpeg:https://marketingeda.com/wp-content/uploads/Aldec-November-16-2023.jpg
END:VEVENT
BEGIN:VEVENT
DTSTART;TZID=America/Los_Angeles:20231116T100000
DTEND;TZID=America/Los_Angeles:20231116T110000
DTSTAMP:20231113T182451Z
CREATED:20231113T182330Z
LAST-MODIFIED:20231113T182451Z
UID:7079-1700128800-1700132400@marketingeda.com
SUMMARY:Webinar Series | RISC-V Ready for Prime Time?
DESCRIPTION:Join us for session II of our webinar series where we delve into the intricacies of RISC-V core integration and explore strategies to overcome the unique verification challenges that design and verification engineers encounter along the way. \nWhether you’re an engineer looking to enhance your understanding of RISC-V or a technology enthusiast keen on staying at the forefront of innovation\, this webinar will provide invaluable insights\, practical strategies\, and real-world examples to help you conquer the verification hurdles associated with RISC-V integration. \nSign Up Here to Get the Zoom Link – https://www.impare.cloud/webinar/session-2 \n  \nAGENDA\n\nIntroduction to RISC-V: Understanding the modularity and appeal of RISC-V.\nCore Integration Challenges: Exploring the intricacies of integrating RISC-V cores into SoCs\, ASICs\, and FPGAs.\nVerification Strategies: Unveiling the tools and methodologies to address power\, performance\, concurrency\, inter-core communication\, synchronization\, security\, and safety concerns.\nReal-World Examples: Learning from practical case studies to navigate RISC-V core integration successfully.\nQ&A Session: An opportunity to get your questions answered by our experts.
URL:https://marketingeda.com/event/webinar-series-risc-v-ready-for-prime-time/
CATEGORIES:IP,Webinar
ATTACH;FMTTYPE=image/jpeg:https://marketingeda.com/wp-content/uploads/Impare-November-16-2023.jpg
END:VEVENT
BEGIN:VEVENT
DTSTART;TZID=America/Los_Angeles:20231116T100000
DTEND;TZID=America/Los_Angeles:20231116T110000
DTSTAMP:20231101T172710Z
CREATED:20231101T172710Z
LAST-MODIFIED:20231101T172710Z
UID:7019-1700128800-1700132400@marketingeda.com
SUMMARY:Enabling Electromagnetic Simulations with Encrypted Components
DESCRIPTION:High-fidelity simulations in the ever-widening realm of complete systems analysis requires incorporating vendor-supplied models for accuracy. However\, vendors are reluctant to share their proprietary intellectual property. Cadence enables the ecosystem and supports model creators by allowing them to encrypt their geometries and protect their IP while sharing them with their customers for simulation. \n\nThis webinar will demonstrate the use of these models for complete system designs and showcase some of Cadence’s Clarity encrypted models that are part of a library developed by Modelithics.
URL:https://marketingeda.com/event/enabling-electromagnetic-simulations-with-encrypted-components/
CATEGORIES:EDA,Webinar
ATTACH;FMTTYPE=image/jpeg:https://marketingeda.com/wp-content/uploads/Cadence-November-16-2023.jpg
END:VEVENT
BEGIN:VEVENT
DTSTART;TZID=America/Los_Angeles:20231116T090000
DTEND;TZID=America/Los_Angeles:20231116T100000
DTSTAMP:20231115T180404Z
CREATED:20231115T180404Z
LAST-MODIFIED:20231115T180404Z
UID:7094-1700125200-1700128800@marketingeda.com
SUMMARY:Boost SoC debug and analytics with embedded software and smart monitors
DESCRIPTION:On-chip monitors and debug structures can dramatically simplify debug\, validation\, analytics\, and optimization of complex SoCs. Such monitors are often accessed by software executing on an external host or debugger via USB or JTAG.  In this webinar\, we will demonstrate how embedded software running on the target silicon for many use cases provides a superior alternative to extract even more insights out of your on-chip monitors and debug structures for analytics and optimization\, and to create a self-contained on-chip monitoring system. \nWe will explore how the Tessent Embedded SDK can be used to build embedded software applications to orchestrate Tessent Embedded Analytics on-chip smart monitors. With the combination of embedded software and a complete on-chip monitoring solution\, you can perform non-intrusive real-time logging\, cache more data for later analysis\, enable real-time performance analysis and anomaly detection. \n  \nWhat you will learn: \n\nDiscover the Tessent Embedded Software Development Kit (Embedded SDK)\, a suite of software utilities that allows SoCs to be equipped with self-contained monitoring and analytics capabilities\nExplore which debug\, optimization and monitoring tasks can be simplified using embedded software.\nLearn how to develop embedded applications using the Tessent Embedded SDK\n\n  \nWho Should Attend: \n\nEmbedded SW Engineers\nSilicon bring-up engineers\nSoC architects\n\n  \nSpeaker\n \nNaga Nagarajan \nSoftware Engineer \nSiemens EDA \n  \nNaga Nagarajan is a software engineer at Siemens EDA. Naga began his career with UltraSoC (acquired by Mentor Graphics which is now Siemens EDA) where he focused on improving the host-based analytics software product known as SystemInsight. Naga now focuses on the development of the Tessent Embedded SDK products\, including the entire implementation of critical features such as in-life\, real-time performance monitoring and analytics. Naga holds an MEng in Electrical and Electronic Engineering.
URL:https://marketingeda.com/event/boost-soc-debug-and-analytics-with-embedded-software-and-smart-monitors/
CATEGORIES:EDA,IP,Webinar
ATTACH;FMTTYPE=image/jpeg:https://marketingeda.com/wp-content/uploads/Siemens-November-16-2023.jpg
END:VEVENT
BEGIN:VEVENT
DTSTART;TZID=Asia/Jerusalem:20231115T170000
DTEND;TZID=Asia/Jerusalem:20231115T180000
DTSTAMP:20231109T174407Z
CREATED:20231109T174407Z
LAST-MODIFIED:20231109T174407Z
UID:7067-1700067600-1700071200@marketingeda.com
SUMMARY:ParagonX - Intelligent analysis\, visualization and debugging tool for IC layout parasitics
DESCRIPTION:I would like to invite you to Ansys Paragon X webinar that we are hosting on Wednesday\, November 15th 17:00 PM (Israel time). \nParagonX intended for analyzing\, simulating\, debugging\, visualizing\, and improving IC layout parasitics. It helps analog designers and layout engineers to immediately understand the parasitics and allows to reduce parasitics debugging time from days\, weeks\, and months down to minutes or hours. \nSpeaker: Maxim Ershov\, Senior Director R&D\, Ansys and formerly CEO and CTO at Diakopto
URL:https://marketingeda.com/event/paragonx-intelligent-analysis-visualization-and-debugging-tool-for-ic-layout-parasitics/
CATEGORIES:EDA,Webinar
ATTACH;FMTTYPE=image/jpeg:https://marketingeda.com/wp-content/uploads/Ansys-November-15-2023-.jpg
END:VEVENT
BEGIN:VEVENT
DTSTART;TZID=America/New_York:20231115T090000
DTEND;TZID=America/New_York:20231115T170000
DTSTAMP:20231018T180605Z
CREATED:20231018T180605Z
LAST-MODIFIED:20231018T180605Z
UID:6969-1700038800-1700067600@marketingeda.com
SUMMARY:ASIP University Day 2023
DESCRIPTION:ASIP University Day: Domain-Specific Processor Design using ASIP Designer\n\n\nApplication-specific instruction set processors (ASIPs) have established themselves as an important implementation option for modern SoCs\, i.e. when standard processor IP cannot meet challenging application-specific requirements\, and fixed hardware is not flexible enough.  Heterogeneous multicore systems including ASIPs are now becoming more mainstream. Domains such as artificial intelligence\, image and video processing or automated driving assistance have fueled the development of such ASIPs\, and triggered many university projects.  Processor design projects such as the RISC-V initiative also initiated a lot of interest.  With all the commercial activity around RISC-V these days\, it has outgrown UC Berkeley. \nSynopsys ASIP Designer is the market leading tool for ASIP design\, verification\, and programming. It is used by leading companies around the globe with hundreds of successful projects to date. \nAt this informal event\, leading university teams will present results from their ongoing ASIP projects in a variety of application domains. Synopsys will share insight on market trends\, and provide a technical update on ASIP Designer along with reference examples.
URL:https://marketingeda.com/event/asip-university-day-2023/
CATEGORIES:EDA,IP,Webinar
ATTACH;FMTTYPE=image/jpeg:https://marketingeda.com/wp-content/uploads/Synopsys-November-15-2023.jpg
END:VEVENT
BEGIN:VEVENT
DTSTART;TZID=America/Los_Angeles:20231115T090000
DTEND;TZID=America/Los_Angeles:20231115T100000
DTSTAMP:20231103T171645Z
CREATED:20231103T171645Z
LAST-MODIFIED:20231103T171645Z
UID:7033-1700038800-1700042400@marketingeda.com
SUMMARY:Achieve 95% Accurate Power Measurement during Architectural Exploration
DESCRIPTION:Are you in the conceptualization and architectural exploration phases\, where assessing the power budget is of paramount importance? If you’re looking to achieve precise power measurement for critical aspects like embedded software\, power management algorithms\, hardware configurations\, and more\, this webinar is tailor-made for you. \n  \nWebinar: How to achieve 95%+ Accurate Power Measurement during Architecture Exploration? \n\nRegister now to secure your spot for Wednesday\, November 15th\, 2023 \n\nSession 1: For Asia & Europe: https://bit.ly/40cR4ek \nTime:  5:00PM Japan/Korea\, 4:00PM China\, 1:30PM India and 9:00 AM CEST. \n\nSession 2: For US & Canada: https://bit.ly/3Mhwzrf \nTime: 9AM PST\, 12PM EST \n  \nDuring this webinar\, we will introduce you to VisualSim System-level Power 2.0\, the only system-level\, power modeling solution that support measurements from IP to SoC and Systems; generate a Digital Twin for early validation\, and support for the entire power chain from generation\, battery\, consumption and conservation. \n\nWould you like to accurately measure the:  \n\n\nPower consumed for a proposed embedded software or firmware? \nSavings of a Power Management Algorithm prior to development? \nPower impact of hardware configuration change? \nTrade-off between Power and Performance? \nTemperature\, heat\, peak power and cumulative power? \n\n\nRegister now to secure your spot for Wednesday\, November 15th\, 2023 and find answers to many such questions!  \n  \nWho should attend? This webinar is tailored for power architects\, systems engineers\, software designers\, systems integrators\, and thermal engineers. \n  \nDon’t miss out on this invaluable opportunity to gain deep insights into achieving 95%+ accurate power measurement during architecture exploration.  \n\nSession 1: For Asia & Europe: https://bit.ly/40cR4ek \nTime:  5:00PM Japan/Korea\, 4:00PM China\, 1:30PM India and 9:00 AM CEST. \n\nSession 2: For US & Canada: https://bit.ly/3Mhwzrf \nTime: 9AM PST\, 12PM EST \n  \nWe look forward to having you with us on 15th Nov’23 at your preferred time.Together\, we’ll explore the power of VisualSim and its role in shaping your architectural decisions. \n  \nBest regards\, \nTeam Mirabilis Design
URL:https://marketingeda.com/event/achieve-95-accurate-power-measurement-during-architectural-exploration/
CATEGORIES:EDA,Webinar
ATTACH;FMTTYPE=image/jpeg:https://marketingeda.com/wp-content/uploads/Mirabilis-November-15-2023.jpg
END:VEVENT
BEGIN:VEVENT
DTSTART;TZID=America/Los_Angeles:20231115T080000
DTEND;TZID=America/Los_Angeles:20231115T090000
DTSTAMP:20231103T163102Z
CREATED:20231103T163102Z
LAST-MODIFIED:20231103T163102Z
UID:7030-1700035200-1700038800@marketingeda.com
SUMMARY:Fail-safe Electronics for Automotive
DESCRIPTION:I would like to invite you to attend our upcoming webinar on Wednesday\, November 15 at 8 a.m. PST. This 1-hour panel will feature SoC experts from CARIAD\, Infineon\, NXP and proteanTecs\, who bridge both the semiconductor and automotive worlds. The discussion will revolve around “Fail-Safe Electronics for Automotive\,” a topic of paramount importance in today’s technology-driven automotive industry. \n\n\n\n\n\n\nPanelists: \n\nHeinz Wagensonner\, Senior SoC Designer\, CARIAD\nJens Rosenbusch\, Sr. Principal Engineer\, SoC Safety Architecture\, Infineon\nXiankun “Robert” Jin\, Automotive SoC Safety Architect\, NXP\nGal Carmel\, Executive VP\, GM Automotive\, proteanTecs\n\nModerated by Circulor’s Chief External Affairs Officer\, Ellen Carey. \n\n\n\n\n\n\n\n\n\n\n\n\nTopics covered:\n\nFail-safe system architectures\nDecoupling of hardware/ software\nSoC and ECU lifetime monitoring solutions\nTradeoffs between reliability\, performance and costs
URL:https://marketingeda.com/event/fail-safe-electronics-for-automotive/
CATEGORIES:EDA,Webinar
ATTACH;FMTTYPE=image/jpeg:https://marketingeda.com/wp-content/uploads/proteanTecs-November-15-2023.jpg
END:VEVENT
BEGIN:VEVENT
DTSTART;TZID=America/Los_Angeles:20231114T110000
DTEND;TZID=America/Los_Angeles:20231114T120000
DTSTAMP:20231103T204425Z
CREATED:20231103T204425Z
LAST-MODIFIED:20231103T204425Z
UID:7040-1699959600-1699963200@marketingeda.com
SUMMARY:Why Chiplets with UCIe are the Next Big Thing
DESCRIPTION:Artificial intelligence (AI) and virtual reality (VR) require fast\, efficient\, low-power technologies. Transistors are becoming harder and harder to shrink\, so chiplets are a promising alternative. Chiplets are small\, modular dies that use UCIe\, an open industry standard\, to communicate with each other. Combined in a Systems-on-Package (SoP)\, they provide superior performance\, reduced power consumption\, and increased design flexibility for customized applications such as cell phones\, autonomous vehicles\, etc. In this panel session\, signal and power integrity experts will discuss: \n  \n\nIndustry trends and why chiplets with UCIe are the next big thing.\nSignal and power integrity considerations when integrating chiplets and UCIe interfaces.\nEDA tools evolved\, and how to streamline chiplets integration into the design workflow.\n\nSpeakers:\n\n\n\nHeeSoo Lee\nSerDes/DDR Product Owner\, Keysight Technologies\n\n\nHeeSoo Lee is the SerDes/DDR product owner in the EDA Software group of Keysight Technologies DES division\, located in Santa Rosa\, Calif. He has held several positions in Keysight Technologies\, Agilent Technologies and Hewlett-Packard\, including consulting business manager\, technical marketing lead and field applications engineer since 1989. Prior to these positions\, he worked for Daeryung Ind. Inc. as an RF/MW circuit design engineer. He has over 30 years of design and simulation experience in RF\, microwave and high-speed digital designs. He graduated with a BSEE from Hankuk Aviation University\, South Korea. \n\nHeidi Barnes\nSenior Application Engineer and Power Integrity Product Owner\, Keysight Technologies\n\n\nHeidi Barnes is a Senior Application Engineer and Power Integrity Product Owner at Keysight\, specializing in High-Speed Digital applications. With 26+ years of experience in the field of electronic design automation\, her recent activities include the application of electromagnetic\, transient\, and channel simulators to solve signal and power integrity challenges. She contributed to the IEEE-370 Standard on fixture removal for high-frequency interconnects and is Co-Chair for the IEEE EPS EDMS Packaging Benchmark Sub-Committee. Heidi holds five patents and was awarded the DesignCon Engineer of the Year in 2017. \n\nRandy White\nMemory Solutions Program Manager\, Keysight Technologies\n\n\nRandy White is the Memory Solutions Program Manager for Keysight Technologies. He is focused on test methodologies for emerging memory technologies in server\, mobile\, and embedded applications. Randy has spent the last 20 years investigating signal integrity measurement techniques\, including de-embedding algorithms\, measurement/model correlation\, high-speed measurements for real-time & sampling oscilloscopes\, and BERTs & AWGs. He has participated on many standards committees\, including PCI-SIG\, USB-IF\, SATA-IO\, and JEDEC\, to help define new test methodologies. He is currently the chair of the JEDEC JC40.5 Logic Validation subcommittee. He graduated with a BSEE from Oregon State University.
URL:https://marketingeda.com/event/why-chiplets-with-ucie-are-the-next-big-thing/
CATEGORIES:EDA,IP,Webinar
ATTACH;FMTTYPE=image/jpeg:https://marketingeda.com/wp-content/uploads/Keysight-November-14-2023.jpg
END:VEVENT
BEGIN:VEVENT
DTSTART;TZID=America/Los_Angeles:20231114T100000
DTEND;TZID=America/Los_Angeles:20231114T110000
DTSTAMP:20231110T193817Z
CREATED:20231110T193817Z
LAST-MODIFIED:20231110T193817Z
UID:7070-1699956000-1699959600@marketingeda.com
SUMMARY:Leverage Certified RISC-V IP to Craft ASIL ISO 26262 Grade Automotive Chips
DESCRIPTION:As semiconductor industry leaders\, Bosch\, Infineon\, Nordic Semiconductor\, NXP\, and Qualcomm collaborate to drive the acceleration of automotive RISC-V semiconductors\, join us for an insightful webinar on how you too can unlock the full potential of RISC-V within your automotive SoC. Featuring Andes Technology and Green Hills Software\, this webinar will offer key insights into developing your own ISO 26262-grade\, Certified ASIL RISC-V automotive chip solution. Don’t miss this opportunity to stay ahead in the evolving semiconductor landscape. \nSpeakers: \nMarvin Chao\, Andes Technology Director of Solution Architecture\, will provide insights into the functionality and capabilities of the ISO 26262-certified AndesCore N25F-SE CPU IP. Learn how this new open-source CPU ISA is addressing the unique demands of automotive applications\, ensuring safety\, reliability\, and performance. \nChuck Brokish\, Green Hills Software Director of Automotive Business Development\, will demonstrate how Green Hills’ MULTI and TimeMachine Software Development Tools\, µ-velOSity Real-Time Operating System\, and Hardware Debugging and Trace Probes can be effectively used to write and debug ISO 26262-certified software that runs efficiently on the N25F-SE CPU IP. \n*This webinar is in partnership with SemiWiki\, Andes\, and Green Hills Software*
URL:https://marketingeda.com/event/leverage-certified-risc-v-ip-to-craft-asil-iso-26262-grade-automotive-chips/
CATEGORIES:IP,Webinar
ATTACH;FMTTYPE=image/jpeg:https://marketingeda.com/wp-content/uploads/Andes-November-14-2023.jpg
END:VEVENT
BEGIN:VEVENT
DTSTART;TZID=America/Los_Angeles:20231114T100000
DTEND;TZID=America/Los_Angeles:20231114T110000
DTSTAMP:20231106T182805Z
CREATED:20231106T182805Z
LAST-MODIFIED:20231106T182805Z
UID:7044-1699956000-1699959600@marketingeda.com
SUMMARY:Automated Constraints Promotion Methodology from IP to SoC for Complex Designs
DESCRIPTION:IP cores require integration into top-level subsystems and/or SoCs. Writing constraints manually for top level design is prone to errors and difficult to verify and manage. This Synopsys webinar will cover how automated SDC constraints promotion from the IP to SoC level provides high-quality SDC using Synopsys Timing Constraints Manager relative to manual time-consuming approaches. We will demonstrate the approach taken and benefits observed using automated constraints promotion and generation on an early PCIe® Gen 6 design resulting in shorter TAT and improved PPA. Lastly\, this webinar will illustrate how designers can ensure constraints correctness is maintained or bettered during the constraints promotion effort. \n\n\n\n\n\n\n\n\n\n\nSpeakers\n\n\nListed below are the industry leaders scheduled to speak. \n\n\n\n\n\n\n\n\n\n\n\n\n\n\n\n\n\n\n\n\n\n\n\n\n\n\nAjay Daga\n\n\nGroup Director\, R&D\nSynopsys \n\n\n\n\n\n\n\n\n\n\n\nAjay Daga is an R&D Group Director at Synopsys where he is responsible for Synopsys’ SDC constraints solutions. Prior to Synopsys he founded and led FishTail Design Automation\, Inc. for 20 years. FishTail focused on solutions for SDC verification\, management and generation and was acquired by Synopsys in 2022. Ajay has a PhD in Computer Engineering from the University of Michigan. \n\n\n\n\n\n\n\n\n\n\n\n\n\n\n\n\n\n\n\n\n\n\n\n\n\n\n\n\n\n\n\nMallik Devulapalli\n\n\nSolutions Engineer\, Principal\nSynopsys \n\n\n\n\n\n\n\n\n\n\n\nMallik has over 25 years of experience in the RTL2GDS implementation\, with experience in CPU\, GPU\, DSP\, networking SoC and Interface IP class of SoC design. He has delivered best in class Implementation & signoff methodologies for the most complex SoC in advanced nodes. He holds a Masters degree in Telecommunications management from California State University. Prior to joining Synopsys he has worked in Fujitsu specializing in Sparc64 CPU design.
URL:https://marketingeda.com/event/automated-constraints-promotion-methodology-from-ip-to-soc-for-complex-designs/
CATEGORIES:EDA,Webinar
ATTACH;FMTTYPE=image/jpeg:https://marketingeda.com/wp-content/uploads/Synopsys-November-14-2023.jpg
END:VEVENT
BEGIN:VEVENT
DTSTART;TZID=America/Los_Angeles:20231114T080000
DTEND;TZID=America/Los_Angeles:20231114T090000
DTSTAMP:20231113T183631Z
CREATED:20231113T183631Z
LAST-MODIFIED:20231113T183631Z
UID:7085-1699948800-1699952400@marketingeda.com
SUMMARY:PCB Design Best Practices: Design Automation
DESCRIPTION:re you harnessing the full power of your PCB design software? In this live discussion\, experts Stephen Chavez and Ray Macias will discuss the benefits of using PCB design automation\, and show how certain capabilities such as component placement\, trace routing\, and generating manufacturing outputs to include intelligent data formats can improve your design cycle times. They’ll offer practical guidance on how to utilize the incredible horsepower of your PCB design tool to make your daily work easier and more efficient.
URL:https://marketingeda.com/event/pcb-design-best-practices-design-automation/
CATEGORIES:EDA,Webinar
ATTACH;FMTTYPE=image/jpeg:https://marketingeda.com/wp-content/uploads/Siemens-November-14-2023.jpg
END:VEVENT
BEGIN:VEVENT
DTSTART;TZID=America/New_York:20231109T130000
DTEND;TZID=America/New_York:20231109T140000
DTSTAMP:20231030T181412Z
CREATED:20231030T181412Z
LAST-MODIFIED:20231030T181412Z
UID:7012-1699534800-1699538400@marketingeda.com
SUMMARY:Tackling Challenges in 3D Heterogenous Integrated (3DHI) Microelectronics for Aerospace\, Government\, and Defense Systems
DESCRIPTION:Join industry experts from aerospace\, government\, and defense as they discuss the complexities of 3D Heterogeneous Integration (3DHI)\, highlighting some of the technological\, manufacturing\, and economic complexities as well as security\, reliability\, and safety challenges.  The panelists will also share their insights on chiplets and interface compatibility in addition to how DARPA’s NGMM (Next-Generation Microelectronics Manufacturing research program plans to grow the 3DHI R&D ecosystem. Whether you are an engineer or a policymaker looking to deepen your 3DHI knowledge\, this panel offers insightful discussions to help anticipate and address future microelectronics design challenges for aerospace\, government\, and defense systems. \nSpeakers\nIan Land\nSynopsys\nSenior Director\, Security\, Government and Aerospace Solutions\nModerator \nDr. Carl McCants\nSpecial Assistant to the DARPA Director \nDr. Josh Fryman\nIntel Corporation\nFellow \nRob Aitken\nSynopsys\nDistinguished Architect
URL:https://marketingeda.com/event/tackling-challenges-in-3d-heterogenous-integrated-3dhi-microelectronics-for-aerospace-government-and-defense-systems/
CATEGORIES:EDA,IP,Webinar
ATTACH;FMTTYPE=image/jpeg:https://marketingeda.com/wp-content/uploads/Synopsys-November-9-2023.jpg
END:VEVENT
BEGIN:VEVENT
DTSTART;TZID=America/New_York:20231109T110000
DTEND;TZID=America/New_York:20231109T120000
DTSTAMP:20231030T174714Z
CREATED:20231030T174714Z
LAST-MODIFIED:20231030T174714Z
UID:7006-1699527600-1699531200@marketingeda.com
SUMMARY:Elevating Consumer Electronics Design Through Cloud-Based Simulation
DESCRIPTION:Electronics design engineering teams are under incredible pressure to quickly deliver innovative new product designs to meet skyrocketing market demand. Sign up for this webinar to learn more about designing better consumer electronics products thanks to simulation in the cloud. \nAbout this Webinar\nConsumer electronic devices are part of our daily lives and include phones\, tablets\, smartwatches\, and their accessories\, such as earbuds\, power supplies\, wireless chargers\, and more. Electronics design engineering teams are under incredible pressure to quickly deliver innovative new product designs to meet skyrocketing market demand. That means modeling and solving significant problems at scale with speed\, verifiable high accuracy\, and confidence. \nMany design challenges will face these engineering teams to ensure they can design optimized products\, avoid noise vibration and mechanical reliability issues\, and optimize the charge’s efficiency to reduce charging time or the material selection to achieve a desired magnetic force. \nThese challenges are solvable by using simulation to avoid producing a physical prototype. These intensive use cases call for different physics (electronics and mechanics) in parallel work streams. \nElectronics engineers require a solution that accelerates issue resolution\, reducing time-to-market. That’s why Ansys has partnered with Amazon Web Services (AWS) to provide the complete electronics solver suite through Ansys Gateway powered by AWS\, accessible on the AWS Marketplace. This solution offers flexible\, secure cloud computing capacity with pre-configured settings tailored to unique design project simulation needs. \nWhat You Will Learn\n\nConsumer electronics industry’s top trends\nChallenges that electronics engineers face in this industry\nLow-frequency and high-frequency use cases for consumer electronics\nHow cloud and HPC help achieve simulation at the best cost/performance ratio\n\nWho Should Attend\nPCB Designers\, Thermal Engineers\, PCB Reliability Engineers\, Electronics Engineers\, Consumer Electronics Engineers\, Head of R&D \, R&D Specialist etc. \nSpeakers\n\nJJ Jones\nLaila Salman\nMarius Rosu
URL:https://marketingeda.com/event/elevating-consumer-electronics-design-through-cloud-based-simulation/
CATEGORIES:EDA,Webinar
ATTACH;FMTTYPE=image/jpeg:https://marketingeda.com/wp-content/uploads/Ansys-November-9-2023.jpg
END:VEVENT
BEGIN:VEVENT
DTSTART;TZID=America/Los_Angeles:20231109T110000
DTEND;TZID=America/Los_Angeles:20231109T120000
DTSTAMP:20231024T171328Z
CREATED:20231024T164155Z
LAST-MODIFIED:20231024T171328Z
UID:6987-1699527600-1699531200@marketingeda.com
SUMMARY:Ways to run cocotb: makefiles\, cocotb-test\, or your custom setup
DESCRIPTION:cocotb enables Python-based hardware verification\, and it integrates into your simulator of choice\, such as Aldec’s Riviera-PRO and executes Python testbenches in that context. In this webinar\, we will look at ways to invoke your simulator of choice in a way that also starts with cocotb. We will show ways to extend the setup to make it suitable for your design\, and discuss trade-offs between the different approaches. \nWe will assume basic cocotb knowledge during this webinar. If you have never heard of cocotb\, have a look at previous Aldec Webinars or other online resources for an introduction to cocotb. \nAgenda:\n\nRunning cocotb tests: your options\nUsing Makefiles to run cocotb tests\nA closer look at cocotb runner\nQ&A: bring your questions!\n\nWebinar Duration\n\n45 min presentation/live demo\n15 min Q&A\n\nPresenter\nPhilipp Wagner\nBio: \nPhilipp Wagner is co-maintainer of cocotb and Hardware/Software Engineer at lowRISC in Cambridge\, UK\, where he is involved in OpenTitan\, the first Open Source Root of Trust chip. For many years Philipp has been working on the intersection of digital hardware\, software and open source. He is passionate about developer productivity\, communities\, and bridging the gap between hardware and software development methodologies. Philipp is Founding Director of the Free and Open Source Silicon Foundation\, and has received a M.Sc. and PhD (Dr.-Ing.) degree in Electrical Engineering from Technical University Munich\, Germany.
URL:https://marketingeda.com/event/ways-to-run-cocotb-makefiles-cocotb-test-or-your-custom-setup/
CATEGORIES:EDA,Webinar
ATTACH;FMTTYPE=image/jpeg:https://marketingeda.com/wp-content/uploads/Aldec-November-9-2023.jpg
END:VEVENT
BEGIN:VEVENT
DTSTART;TZID=America/Los_Angeles:20231108T100000
DTEND;TZID=America/Los_Angeles:20231108T110000
DTSTAMP:20231030T180110Z
CREATED:20231030T175759Z
LAST-MODIFIED:20231030T180110Z
UID:7009-1699437600-1699441200@marketingeda.com
SUMMARY:CMOS Circuit Techniques for Wireline Transmitters Part I
DESCRIPTION:Synopsys Webinar – Part I  \nIn this 3-part Synopsys webinar series\, we will present how hyperscale data centers are going through a paradigm shift with the advent of technologies like Artificial Intelligence (AI) and edge compute requiring hyperscale data centers to support exponential growth of data volume.  This volume of network traffic demands an increase in bandwidth to 400G\, which is now enabled by 112G Ethernet as the interconnect of choice\, with next generation architectures being designed to operate at 224Gbps supporting upcoming 800G/1.6T switches inside datacenters.  These data rates pose extreme challenges on the entire transceiver.  Attend this webinar series to find out about the challenges posed on the transmitter and a discussion on various techniques used in the different blocks to overcome the challenges of data transmission at 100s of Gbps. \nPart I: Wednesday\, November 8\, 2023 \n\nMotivation for SERDES\nTransmitter Requirements\nCurrent/Voltage Mode Drivers\n\nPart II: Wednesday\, November 29\, 2023 \n\nHigh Order Multiplexers\nFFE Equalization\nDSP-DAC Based TX Architectures\n1-UI Pulse Generation Circuits\n\nPart III: Wednesday\, December 13\, 2023 \n\nOutput Matching Network\nMeasurements and Simulation Techniques\n\n\n\n\n\n\n\n\n\n\n\nSpeaker\n\n\nListed below is the industry leader scheduled to speak. \n\n\n\n\n\n\n\n\n\n\n\n\n\n\n\n\n\n\n\n\n\n\n\n\n\n\nNoman Hai\n\n\nManager\, Analog & Mixed-Signal Circuit Design\nSynopsys\, Inc. \n\n\n\n\n\n\n\n\nNoman Hai received the B.E. degree from NED University\, Karachi\, Pakistan in 2002 and the M.Sc. degree in Electrical Engineering from Linkoping University\, Sweden in 2006 and the Ph.D. degree from University of Waterloo\, Canada\, in 2012. He has worked at Philips Semiconductors\, MACOM\, Movellus and Synopsys as an analog design engineer where he was involved in designing high speed analog circuits for wireline and A.I. applications. Currently he is an Analog Design Manager at Synopsys where he is involved in designing high speed interface IP circuits. His current interests include high speed I/O circuits\, design methodology and automation\, and mixed-signal circuits. He holds three U.S. patents
URL:https://marketingeda.com/event/cmos-circuit-techniques-for-wireline-transmitters-part-i/
CATEGORIES:IP,Webinar
ATTACH;FMTTYPE=image/jpeg:https://marketingeda.com/wp-content/uploads/Synopsys-November-8-2023.jpg
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BEGIN:VEVENT
DTSTART;TZID=America/Los_Angeles:20231108T100000
DTEND;TZID=America/Los_Angeles:20231108T110000
DTSTAMP:20231018T175638Z
CREATED:20231018T175638Z
LAST-MODIFIED:20231018T175638Z
UID:6966-1699437600-1699441200@marketingeda.com
SUMMARY:Deep Dive into the UVM Register Layer: User-Defined Doors\, Predictors\, and Callbacks
DESCRIPTION:This webinar focuses on three specific aspects of the UVM register layer that will help you to model in UVM some of the less obvious ways in which registers can behave\, such as non-linear addressing\, burst access mode\, registers accessed through an embedded CPU\, and quirky registers. \nIt will cover the following topics: \n\nUsing user-defined front and back doors to extend the capabilities of the register layer beyond sending simple request and response transactions to the DUT\nUnderstanding the role played by the predictor in updating the register model and using the predictor in the presence of user-defined front doors • Using register callbacks to model quirky register behaviors\, the side-effects of register reads and writes\, and aliased registers.\nExactly what changes you can and cannot make to UVM code without disturbing the random stimulus generation\n\nTogether\, these topics provide an important set of mechanisms for extending the capabilities of the register layer in many useful ways. \nWe will show code examples that can be run in the Cadence Xcelium Parallel Simulator. \nJohn Aynsley is Doulos Co-Founder and Technical Fellow. John will present this webinar\, consisting of a one-hour broadcast with interactive Q&A available to attendees throughout. \nAttendance is free of charge.\nIf you have any queries\, please contact webinars@doulos.com
URL:https://marketingeda.com/event/deep-dive-into-the-uvm-register-layer-user-defined-doors-predictors-and-callbacks/
CATEGORIES:EDA,Webinar
ATTACH;FMTTYPE=image/jpeg:https://marketingeda.com/wp-content/uploads/Cadence-November-8-2023.jpg
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BEGIN:VEVENT
DTSTART;TZID=America/Los_Angeles:20231107T100000
DTEND;TZID=America/Los_Angeles:20231107T110000
DTSTAMP:20231010T195132Z
CREATED:20231010T195132Z
LAST-MODIFIED:20231010T195132Z
UID:6937-1699351200-1699354800@marketingeda.com
SUMMARY:Proactive Data Center Management with Insight Platform
DESCRIPTION:The DataCenter Insight Platform is an enterprise software solution that simplifies data center capacity management by making it proactive\, rather than reactive. The platform is a database of data center “digital twins”—virtual models reflecting the aggregate of an organization’s toolsets and add/move/change workflows. \nBy bringing together data that is typically siloed and using predictive computational fluid dynamics (CFD) simulation to answer all the “what-ifs\,” digital twins provide actionable insights that would otherwise go unrealized. Fortune 500 companies are using Insight Platform to standardize their deployment processes and make fast and effective capacity planning decisions. \nThis webinar will describe how digital twins are deployed at scale via integration and automated workflows and provide a software demonstration of the proactive capacity planning toolset.
URL:https://marketingeda.com/event/proactive-data-center-management-with-insight-platform/
CATEGORIES:EDA,Webinar
ATTACH;FMTTYPE=image/jpeg:https://marketingeda.com/wp-content/uploads/Cadence-November-7-2023.jpg
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BEGIN:VEVENT
DTSTART;TZID=America/Los_Angeles:20231101T110000
DTEND;TZID=America/Los_Angeles:20231101T120000
DTSTAMP:20231019T170231Z
CREATED:20231019T170231Z
LAST-MODIFIED:20231019T170231Z
UID:6977-1698836400-1698840000@marketingeda.com
SUMMARY:Warp Speed Gate-Level Simulations with the Xcelium Multi-Core App
DESCRIPTION:Are you ready to lead the way in gate-level digital simulations (GLS)? Dive into Cadence’s exclusive webinar and uncover the revolutionary Xcelium Multi-Core (MC) App—a game changer for GLS\, allowing you to parallelize and expedite simulations like never before. \nWhat You’ll Gain:\nInsight: Understand why the Xcelium MC App is crucial for DV engineers looking to speed up GLS.\nKnowledge: Learn how to deploy the full potential of the Xcelium MC App.\nBest Practices: Discover optimal utilization practices to maximize the efficiency of your gate-level simulations.\nExamples: See the application of the Xcelium MC App\, showcasing how you can simulate GLS at warp speed! \nBenefits: \n\nAchieve 10X faster simulations\, accelerate your aggressive project schedules\nTackle complex billion gate designs with ease\nFully leverage the capacities of modern multi-core CPUs in your server farm\n\nDon’t be left behind! Join us and catapult your GLS to warp speed\, ensuring your projects are not stalled by long pole tests but mastered with precision and efficiency.
URL:https://marketingeda.com/event/warp-speed-gate-level-simulations-with-the-xcelium-multi-core-app/
CATEGORIES:EDA,Webinar
ATTACH;FMTTYPE=image/jpeg:https://marketingeda.com/wp-content/uploads/Cadence-November-1-2023.jpg
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BEGIN:VEVENT
DTSTART;TZID=America/Los_Angeles:20231101T100000
DTEND;TZID=America/Los_Angeles:20231101T103000
DTSTAMP:20231003T172423Z
CREATED:20231003T172423Z
LAST-MODIFIED:20231003T172423Z
UID:6910-1698832800-1698834600@marketingeda.com
SUMMARY:Mastering the Art of Managing IP\, Chiplets\, and Design Data
DESCRIPTION:Join us on Wednesday\, November 1st\, for an eye-opening exploration of the inadequacy of common design data and IP management capabilities in the face of today’s intricate semiconductor chip designs. Discover the keys to unlocking unparalleled success in your upcoming designs through cutting-edge capabilities and strategies that are reshaping the industry. Don’t miss this exclusive opportunity to revolutionize your approach to semiconductor chip design. \n  \nHere’s what you can learn:\n\nBest practices for efficient chip design data and IP handling.\nCutting-edge IP management strategies for reuse\, security\, and compliance.\nData integration and design flow techniques to enhance collaboration.\n\n  \nBONUS: Design Data and IP Management Best Practices eBook for All Participants! \n  \nWho should attend:\n\nSemiconductor Design and Verification Engineers\nIP Managers and Administrators\nData and tech enthusiasts\nInnovators seeking an edge\nAnyone passionate about chip design excellence\n\nDon’t miss out on this chance to gain a competitive edge in the dynamic world of semiconductor chip design. See you at the webinar!
URL:https://marketingeda.com/event/mastering-the-art-of-managing-ip-chiplets-and-design-data/
CATEGORIES:EDA,IP,Webinar
ATTACH;FMTTYPE=image/jpeg:https://marketingeda.com/wp-content/uploads/Keysight-November-1-2023.jpg
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BEGIN:VEVENT
DTSTART;TZID=America/Los_Angeles:20231031T100000
DTEND;TZID=America/Los_Angeles:20231031T110000
DTSTAMP:20231013T183201Z
CREATED:20231013T183201Z
LAST-MODIFIED:20231013T183201Z
UID:6956-1698746400-1698750000@marketingeda.com
SUMMARY:Enhance Verification Quality with the Xcelium Mixed-Signal App
DESCRIPTION:The comprehensive verification of analog mixed-signal (AMS) designs has challenges in schedules and implementations due to the vast divergence in design flows of the analog and digital portions of the SoC. These discrepancies include priorities in simulation cycles (accuracy versus performance)\, design methodologies\, and verification of functionality. \nOver multiple decades\, design verification (DV) has evolved towards catching bugs earlier in the design cycles\, allowing an exponential increase in the functionality of SoCs. Extending those improvements to mixed signal is critical for continuous growth. This CadenceTECHTALK goes over many of the silicon-proven approaches enabling it\, and DV engineers will find immense value in the contents. Specifically\, it covers solutions to those challenges in mixed-signal verification (MSV) using the capabilities of the Xcelium Mixed-Signal App. \nWhat attendees will learn: \n\nDevelopment of analog modeling in SystemVerilog using real number modeling (RNM)\nMSV co-sim testbench architecture to allow swapping of models and netlists\nEnhancements of DV regression setup with a hybrid flow that allows for both RNM and co-sim
URL:https://marketingeda.com/event/enhance-verification-quality-with-the-xcelium-mixed-signal-app/
CATEGORIES:EDA,Webinar
ATTACH;FMTTYPE=image/jpeg:https://marketingeda.com/wp-content/uploads/Cadence-October-31-2023.jpg
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