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BEGIN:VEVENT
DTSTART;TZID=America/Los_Angeles:20231116T090000
DTEND;TZID=America/Los_Angeles:20231116T100000
DTSTAMP:20231115T180404Z
CREATED:20231115T180404Z
LAST-MODIFIED:20231115T180404Z
UID:7094-1700125200-1700128800@marketingeda.com
SUMMARY:Boost SoC debug and analytics with embedded software and smart monitors
DESCRIPTION:On-chip monitors and debug structures can dramatically simplify debug\, validation\, analytics\, and optimization of complex SoCs. Such monitors are often accessed by software executing on an external host or debugger via USB or JTAG.  In this webinar\, we will demonstrate how embedded software running on the target silicon for many use cases provides a superior alternative to extract even more insights out of your on-chip monitors and debug structures for analytics and optimization\, and to create a self-contained on-chip monitoring system. \nWe will explore how the Tessent Embedded SDK can be used to build embedded software applications to orchestrate Tessent Embedded Analytics on-chip smart monitors. With the combination of embedded software and a complete on-chip monitoring solution\, you can perform non-intrusive real-time logging\, cache more data for later analysis\, enable real-time performance analysis and anomaly detection. \n  \nWhat you will learn: \n\nDiscover the Tessent Embedded Software Development Kit (Embedded SDK)\, a suite of software utilities that allows SoCs to be equipped with self-contained monitoring and analytics capabilities\nExplore which debug\, optimization and monitoring tasks can be simplified using embedded software.\nLearn how to develop embedded applications using the Tessent Embedded SDK\n\n  \nWho Should Attend: \n\nEmbedded SW Engineers\nSilicon bring-up engineers\nSoC architects\n\n  \nSpeaker\n \nNaga Nagarajan \nSoftware Engineer \nSiemens EDA \n  \nNaga Nagarajan is a software engineer at Siemens EDA. Naga began his career with UltraSoC (acquired by Mentor Graphics which is now Siemens EDA) where he focused on improving the host-based analytics software product known as SystemInsight. Naga now focuses on the development of the Tessent Embedded SDK products\, including the entire implementation of critical features such as in-life\, real-time performance monitoring and analytics. Naga holds an MEng in Electrical and Electronic Engineering.
URL:https://marketingeda.com/event/boost-soc-debug-and-analytics-with-embedded-software-and-smart-monitors/
CATEGORIES:EDA,IP,Webinar
ATTACH;FMTTYPE=image/jpeg:https://marketingeda.com/wp-content/uploads/Siemens-November-16-2023.jpg
END:VEVENT
BEGIN:VEVENT
DTSTART;TZID=Asia/Jerusalem:20231115T170000
DTEND;TZID=Asia/Jerusalem:20231115T180000
DTSTAMP:20231109T174407Z
CREATED:20231109T174407Z
LAST-MODIFIED:20231109T174407Z
UID:7067-1700067600-1700071200@marketingeda.com
SUMMARY:ParagonX - Intelligent analysis\, visualization and debugging tool for IC layout parasitics
DESCRIPTION:I would like to invite you to Ansys Paragon X webinar that we are hosting on Wednesday\, November 15th 17:00 PM (Israel time). \nParagonX intended for analyzing\, simulating\, debugging\, visualizing\, and improving IC layout parasitics. It helps analog designers and layout engineers to immediately understand the parasitics and allows to reduce parasitics debugging time from days\, weeks\, and months down to minutes or hours. \nSpeaker: Maxim Ershov\, Senior Director R&D\, Ansys and formerly CEO and CTO at Diakopto
URL:https://marketingeda.com/event/paragonx-intelligent-analysis-visualization-and-debugging-tool-for-ic-layout-parasitics/
CATEGORIES:EDA,Webinar
ATTACH;FMTTYPE=image/jpeg:https://marketingeda.com/wp-content/uploads/Ansys-November-15-2023-.jpg
END:VEVENT
BEGIN:VEVENT
DTSTART;TZID=America/New_York:20231115T090000
DTEND;TZID=America/New_York:20231115T170000
DTSTAMP:20231018T180605Z
CREATED:20231018T180605Z
LAST-MODIFIED:20231018T180605Z
UID:6969-1700038800-1700067600@marketingeda.com
SUMMARY:ASIP University Day 2023
DESCRIPTION:ASIP University Day: Domain-Specific Processor Design using ASIP Designer\n\n\nApplication-specific instruction set processors (ASIPs) have established themselves as an important implementation option for modern SoCs\, i.e. when standard processor IP cannot meet challenging application-specific requirements\, and fixed hardware is not flexible enough.  Heterogeneous multicore systems including ASIPs are now becoming more mainstream. Domains such as artificial intelligence\, image and video processing or automated driving assistance have fueled the development of such ASIPs\, and triggered many university projects.  Processor design projects such as the RISC-V initiative also initiated a lot of interest.  With all the commercial activity around RISC-V these days\, it has outgrown UC Berkeley. \nSynopsys ASIP Designer is the market leading tool for ASIP design\, verification\, and programming. It is used by leading companies around the globe with hundreds of successful projects to date. \nAt this informal event\, leading university teams will present results from their ongoing ASIP projects in a variety of application domains. Synopsys will share insight on market trends\, and provide a technical update on ASIP Designer along with reference examples.
URL:https://marketingeda.com/event/asip-university-day-2023/
CATEGORIES:EDA,IP,Webinar
ATTACH;FMTTYPE=image/jpeg:https://marketingeda.com/wp-content/uploads/Synopsys-November-15-2023.jpg
END:VEVENT
BEGIN:VEVENT
DTSTART;TZID=America/Los_Angeles:20231115T090000
DTEND;TZID=America/Los_Angeles:20231115T100000
DTSTAMP:20231103T171645Z
CREATED:20231103T171645Z
LAST-MODIFIED:20231103T171645Z
UID:7033-1700038800-1700042400@marketingeda.com
SUMMARY:Achieve 95% Accurate Power Measurement during Architectural Exploration
DESCRIPTION:Are you in the conceptualization and architectural exploration phases\, where assessing the power budget is of paramount importance? If you’re looking to achieve precise power measurement for critical aspects like embedded software\, power management algorithms\, hardware configurations\, and more\, this webinar is tailor-made for you. \n  \nWebinar: How to achieve 95%+ Accurate Power Measurement during Architecture Exploration? \n\nRegister now to secure your spot for Wednesday\, November 15th\, 2023 \n\nSession 1: For Asia & Europe: https://bit.ly/40cR4ek \nTime:  5:00PM Japan/Korea\, 4:00PM China\, 1:30PM India and 9:00 AM CEST. \n\nSession 2: For US & Canada: https://bit.ly/3Mhwzrf \nTime: 9AM PST\, 12PM EST \n  \nDuring this webinar\, we will introduce you to VisualSim System-level Power 2.0\, the only system-level\, power modeling solution that support measurements from IP to SoC and Systems; generate a Digital Twin for early validation\, and support for the entire power chain from generation\, battery\, consumption and conservation. \n\nWould you like to accurately measure the:  \n\n\nPower consumed for a proposed embedded software or firmware? \nSavings of a Power Management Algorithm prior to development? \nPower impact of hardware configuration change? \nTrade-off between Power and Performance? \nTemperature\, heat\, peak power and cumulative power? \n\n\nRegister now to secure your spot for Wednesday\, November 15th\, 2023 and find answers to many such questions!  \n  \nWho should attend? This webinar is tailored for power architects\, systems engineers\, software designers\, systems integrators\, and thermal engineers. \n  \nDon’t miss out on this invaluable opportunity to gain deep insights into achieving 95%+ accurate power measurement during architecture exploration.  \n\nSession 1: For Asia & Europe: https://bit.ly/40cR4ek \nTime:  5:00PM Japan/Korea\, 4:00PM China\, 1:30PM India and 9:00 AM CEST. \n\nSession 2: For US & Canada: https://bit.ly/3Mhwzrf \nTime: 9AM PST\, 12PM EST \n  \nWe look forward to having you with us on 15th Nov’23 at your preferred time.Together\, we’ll explore the power of VisualSim and its role in shaping your architectural decisions. \n  \nBest regards\, \nTeam Mirabilis Design
URL:https://marketingeda.com/event/achieve-95-accurate-power-measurement-during-architectural-exploration/
CATEGORIES:EDA,Webinar
ATTACH;FMTTYPE=image/jpeg:https://marketingeda.com/wp-content/uploads/Mirabilis-November-15-2023.jpg
END:VEVENT
BEGIN:VEVENT
DTSTART;TZID=America/Los_Angeles:20231115T080000
DTEND;TZID=America/Los_Angeles:20231115T090000
DTSTAMP:20231103T163102Z
CREATED:20231103T163102Z
LAST-MODIFIED:20231103T163102Z
UID:7030-1700035200-1700038800@marketingeda.com
SUMMARY:Fail-safe Electronics for Automotive
DESCRIPTION:I would like to invite you to attend our upcoming webinar on Wednesday\, November 15 at 8 a.m. PST. This 1-hour panel will feature SoC experts from CARIAD\, Infineon\, NXP and proteanTecs\, who bridge both the semiconductor and automotive worlds. The discussion will revolve around “Fail-Safe Electronics for Automotive\,” a topic of paramount importance in today’s technology-driven automotive industry. \n\n\n\n\n\n\nPanelists: \n\nHeinz Wagensonner\, Senior SoC Designer\, CARIAD\nJens Rosenbusch\, Sr. Principal Engineer\, SoC Safety Architecture\, Infineon\nXiankun “Robert” Jin\, Automotive SoC Safety Architect\, NXP\nGal Carmel\, Executive VP\, GM Automotive\, proteanTecs\n\nModerated by Circulor’s Chief External Affairs Officer\, Ellen Carey. \n\n\n\n\n\n\n\n\n\n\n\n\nTopics covered:\n\nFail-safe system architectures\nDecoupling of hardware/ software\nSoC and ECU lifetime monitoring solutions\nTradeoffs between reliability\, performance and costs
URL:https://marketingeda.com/event/fail-safe-electronics-for-automotive/
CATEGORIES:EDA,Webinar
ATTACH;FMTTYPE=image/jpeg:https://marketingeda.com/wp-content/uploads/proteanTecs-November-15-2023.jpg
END:VEVENT
BEGIN:VEVENT
DTSTART;TZID=America/Los_Angeles:20231114T110000
DTEND;TZID=America/Los_Angeles:20231114T120000
DTSTAMP:20231103T204425Z
CREATED:20231103T204425Z
LAST-MODIFIED:20231103T204425Z
UID:7040-1699959600-1699963200@marketingeda.com
SUMMARY:Why Chiplets with UCIe are the Next Big Thing
DESCRIPTION:Artificial intelligence (AI) and virtual reality (VR) require fast\, efficient\, low-power technologies. Transistors are becoming harder and harder to shrink\, so chiplets are a promising alternative. Chiplets are small\, modular dies that use UCIe\, an open industry standard\, to communicate with each other. Combined in a Systems-on-Package (SoP)\, they provide superior performance\, reduced power consumption\, and increased design flexibility for customized applications such as cell phones\, autonomous vehicles\, etc. In this panel session\, signal and power integrity experts will discuss: \n  \n\nIndustry trends and why chiplets with UCIe are the next big thing.\nSignal and power integrity considerations when integrating chiplets and UCIe interfaces.\nEDA tools evolved\, and how to streamline chiplets integration into the design workflow.\n\nSpeakers:\n\n\n\nHeeSoo Lee\nSerDes/DDR Product Owner\, Keysight Technologies\n\n\nHeeSoo Lee is the SerDes/DDR product owner in the EDA Software group of Keysight Technologies DES division\, located in Santa Rosa\, Calif. He has held several positions in Keysight Technologies\, Agilent Technologies and Hewlett-Packard\, including consulting business manager\, technical marketing lead and field applications engineer since 1989. Prior to these positions\, he worked for Daeryung Ind. Inc. as an RF/MW circuit design engineer. He has over 30 years of design and simulation experience in RF\, microwave and high-speed digital designs. He graduated with a BSEE from Hankuk Aviation University\, South Korea. \n\nHeidi Barnes\nSenior Application Engineer and Power Integrity Product Owner\, Keysight Technologies\n\n\nHeidi Barnes is a Senior Application Engineer and Power Integrity Product Owner at Keysight\, specializing in High-Speed Digital applications. With 26+ years of experience in the field of electronic design automation\, her recent activities include the application of electromagnetic\, transient\, and channel simulators to solve signal and power integrity challenges. She contributed to the IEEE-370 Standard on fixture removal for high-frequency interconnects and is Co-Chair for the IEEE EPS EDMS Packaging Benchmark Sub-Committee. Heidi holds five patents and was awarded the DesignCon Engineer of the Year in 2017. \n\nRandy White\nMemory Solutions Program Manager\, Keysight Technologies\n\n\nRandy White is the Memory Solutions Program Manager for Keysight Technologies. He is focused on test methodologies for emerging memory technologies in server\, mobile\, and embedded applications. Randy has spent the last 20 years investigating signal integrity measurement techniques\, including de-embedding algorithms\, measurement/model correlation\, high-speed measurements for real-time & sampling oscilloscopes\, and BERTs & AWGs. He has participated on many standards committees\, including PCI-SIG\, USB-IF\, SATA-IO\, and JEDEC\, to help define new test methodologies. He is currently the chair of the JEDEC JC40.5 Logic Validation subcommittee. He graduated with a BSEE from Oregon State University.
URL:https://marketingeda.com/event/why-chiplets-with-ucie-are-the-next-big-thing/
CATEGORIES:EDA,IP,Webinar
ATTACH;FMTTYPE=image/jpeg:https://marketingeda.com/wp-content/uploads/Keysight-November-14-2023.jpg
END:VEVENT
BEGIN:VEVENT
DTSTART;TZID=America/Los_Angeles:20231114T100000
DTEND;TZID=America/Los_Angeles:20231114T110000
DTSTAMP:20231110T193817Z
CREATED:20231110T193817Z
LAST-MODIFIED:20231110T193817Z
UID:7070-1699956000-1699959600@marketingeda.com
SUMMARY:Leverage Certified RISC-V IP to Craft ASIL ISO 26262 Grade Automotive Chips
DESCRIPTION:As semiconductor industry leaders\, Bosch\, Infineon\, Nordic Semiconductor\, NXP\, and Qualcomm collaborate to drive the acceleration of automotive RISC-V semiconductors\, join us for an insightful webinar on how you too can unlock the full potential of RISC-V within your automotive SoC. Featuring Andes Technology and Green Hills Software\, this webinar will offer key insights into developing your own ISO 26262-grade\, Certified ASIL RISC-V automotive chip solution. Don’t miss this opportunity to stay ahead in the evolving semiconductor landscape. \nSpeakers: \nMarvin Chao\, Andes Technology Director of Solution Architecture\, will provide insights into the functionality and capabilities of the ISO 26262-certified AndesCore N25F-SE CPU IP. Learn how this new open-source CPU ISA is addressing the unique demands of automotive applications\, ensuring safety\, reliability\, and performance. \nChuck Brokish\, Green Hills Software Director of Automotive Business Development\, will demonstrate how Green Hills’ MULTI and TimeMachine Software Development Tools\, µ-velOSity Real-Time Operating System\, and Hardware Debugging and Trace Probes can be effectively used to write and debug ISO 26262-certified software that runs efficiently on the N25F-SE CPU IP. \n*This webinar is in partnership with SemiWiki\, Andes\, and Green Hills Software*
URL:https://marketingeda.com/event/leverage-certified-risc-v-ip-to-craft-asil-iso-26262-grade-automotive-chips/
CATEGORIES:IP,Webinar
ATTACH;FMTTYPE=image/jpeg:https://marketingeda.com/wp-content/uploads/Andes-November-14-2023.jpg
END:VEVENT
BEGIN:VEVENT
DTSTART;TZID=America/Los_Angeles:20231114T100000
DTEND;TZID=America/Los_Angeles:20231114T110000
DTSTAMP:20231106T182805Z
CREATED:20231106T182805Z
LAST-MODIFIED:20231106T182805Z
UID:7044-1699956000-1699959600@marketingeda.com
SUMMARY:Automated Constraints Promotion Methodology from IP to SoC for Complex Designs
DESCRIPTION:IP cores require integration into top-level subsystems and/or SoCs. Writing constraints manually for top level design is prone to errors and difficult to verify and manage. This Synopsys webinar will cover how automated SDC constraints promotion from the IP to SoC level provides high-quality SDC using Synopsys Timing Constraints Manager relative to manual time-consuming approaches. We will demonstrate the approach taken and benefits observed using automated constraints promotion and generation on an early PCIe® Gen 6 design resulting in shorter TAT and improved PPA. Lastly\, this webinar will illustrate how designers can ensure constraints correctness is maintained or bettered during the constraints promotion effort. \n\n\n\n\n\n\n\n\n\n\nSpeakers\n\n\nListed below are the industry leaders scheduled to speak. \n\n\n\n\n\n\n\n\n\n\n\n\n\n\n\n\n\n\n\n\n\n\n\n\n\n\nAjay Daga\n\n\nGroup Director\, R&D\nSynopsys \n\n\n\n\n\n\n\n\n\n\n\nAjay Daga is an R&D Group Director at Synopsys where he is responsible for Synopsys’ SDC constraints solutions. Prior to Synopsys he founded and led FishTail Design Automation\, Inc. for 20 years. FishTail focused on solutions for SDC verification\, management and generation and was acquired by Synopsys in 2022. Ajay has a PhD in Computer Engineering from the University of Michigan. \n\n\n\n\n\n\n\n\n\n\n\n\n\n\n\n\n\n\n\n\n\n\n\n\n\n\n\n\n\n\n\nMallik Devulapalli\n\n\nSolutions Engineer\, Principal\nSynopsys \n\n\n\n\n\n\n\n\n\n\n\nMallik has over 25 years of experience in the RTL2GDS implementation\, with experience in CPU\, GPU\, DSP\, networking SoC and Interface IP class of SoC design. He has delivered best in class Implementation & signoff methodologies for the most complex SoC in advanced nodes. He holds a Masters degree in Telecommunications management from California State University. Prior to joining Synopsys he has worked in Fujitsu specializing in Sparc64 CPU design.
URL:https://marketingeda.com/event/automated-constraints-promotion-methodology-from-ip-to-soc-for-complex-designs/
CATEGORIES:EDA,Webinar
ATTACH;FMTTYPE=image/jpeg:https://marketingeda.com/wp-content/uploads/Synopsys-November-14-2023.jpg
END:VEVENT
BEGIN:VEVENT
DTSTART;TZID=America/Los_Angeles:20231114T080000
DTEND;TZID=America/Los_Angeles:20231114T090000
DTSTAMP:20231113T183631Z
CREATED:20231113T183631Z
LAST-MODIFIED:20231113T183631Z
UID:7085-1699948800-1699952400@marketingeda.com
SUMMARY:PCB Design Best Practices: Design Automation
DESCRIPTION:re you harnessing the full power of your PCB design software? In this live discussion\, experts Stephen Chavez and Ray Macias will discuss the benefits of using PCB design automation\, and show how certain capabilities such as component placement\, trace routing\, and generating manufacturing outputs to include intelligent data formats can improve your design cycle times. They’ll offer practical guidance on how to utilize the incredible horsepower of your PCB design tool to make your daily work easier and more efficient.
URL:https://marketingeda.com/event/pcb-design-best-practices-design-automation/
CATEGORIES:EDA,Webinar
ATTACH;FMTTYPE=image/jpeg:https://marketingeda.com/wp-content/uploads/Siemens-November-14-2023.jpg
END:VEVENT
BEGIN:VEVENT
DTSTART;TZID=America/New_York:20231109T130000
DTEND;TZID=America/New_York:20231109T140000
DTSTAMP:20231030T181412Z
CREATED:20231030T181412Z
LAST-MODIFIED:20231030T181412Z
UID:7012-1699534800-1699538400@marketingeda.com
SUMMARY:Tackling Challenges in 3D Heterogenous Integrated (3DHI) Microelectronics for Aerospace\, Government\, and Defense Systems
DESCRIPTION:Join industry experts from aerospace\, government\, and defense as they discuss the complexities of 3D Heterogeneous Integration (3DHI)\, highlighting some of the technological\, manufacturing\, and economic complexities as well as security\, reliability\, and safety challenges.  The panelists will also share their insights on chiplets and interface compatibility in addition to how DARPA’s NGMM (Next-Generation Microelectronics Manufacturing research program plans to grow the 3DHI R&D ecosystem. Whether you are an engineer or a policymaker looking to deepen your 3DHI knowledge\, this panel offers insightful discussions to help anticipate and address future microelectronics design challenges for aerospace\, government\, and defense systems. \nSpeakers\nIan Land\nSynopsys\nSenior Director\, Security\, Government and Aerospace Solutions\nModerator \nDr. Carl McCants\nSpecial Assistant to the DARPA Director \nDr. Josh Fryman\nIntel Corporation\nFellow \nRob Aitken\nSynopsys\nDistinguished Architect
URL:https://marketingeda.com/event/tackling-challenges-in-3d-heterogenous-integrated-3dhi-microelectronics-for-aerospace-government-and-defense-systems/
CATEGORIES:EDA,IP,Webinar
ATTACH;FMTTYPE=image/jpeg:https://marketingeda.com/wp-content/uploads/Synopsys-November-9-2023.jpg
END:VEVENT
BEGIN:VEVENT
DTSTART;TZID=America/New_York:20231109T110000
DTEND;TZID=America/New_York:20231109T120000
DTSTAMP:20231030T174714Z
CREATED:20231030T174714Z
LAST-MODIFIED:20231030T174714Z
UID:7006-1699527600-1699531200@marketingeda.com
SUMMARY:Elevating Consumer Electronics Design Through Cloud-Based Simulation
DESCRIPTION:Electronics design engineering teams are under incredible pressure to quickly deliver innovative new product designs to meet skyrocketing market demand. Sign up for this webinar to learn more about designing better consumer electronics products thanks to simulation in the cloud. \nAbout this Webinar\nConsumer electronic devices are part of our daily lives and include phones\, tablets\, smartwatches\, and their accessories\, such as earbuds\, power supplies\, wireless chargers\, and more. Electronics design engineering teams are under incredible pressure to quickly deliver innovative new product designs to meet skyrocketing market demand. That means modeling and solving significant problems at scale with speed\, verifiable high accuracy\, and confidence. \nMany design challenges will face these engineering teams to ensure they can design optimized products\, avoid noise vibration and mechanical reliability issues\, and optimize the charge’s efficiency to reduce charging time or the material selection to achieve a desired magnetic force. \nThese challenges are solvable by using simulation to avoid producing a physical prototype. These intensive use cases call for different physics (electronics and mechanics) in parallel work streams. \nElectronics engineers require a solution that accelerates issue resolution\, reducing time-to-market. That’s why Ansys has partnered with Amazon Web Services (AWS) to provide the complete electronics solver suite through Ansys Gateway powered by AWS\, accessible on the AWS Marketplace. This solution offers flexible\, secure cloud computing capacity with pre-configured settings tailored to unique design project simulation needs. \nWhat You Will Learn\n\nConsumer electronics industry’s top trends\nChallenges that electronics engineers face in this industry\nLow-frequency and high-frequency use cases for consumer electronics\nHow cloud and HPC help achieve simulation at the best cost/performance ratio\n\nWho Should Attend\nPCB Designers\, Thermal Engineers\, PCB Reliability Engineers\, Electronics Engineers\, Consumer Electronics Engineers\, Head of R&D \, R&D Specialist etc. \nSpeakers\n\nJJ Jones\nLaila Salman\nMarius Rosu
URL:https://marketingeda.com/event/elevating-consumer-electronics-design-through-cloud-based-simulation/
CATEGORIES:EDA,Webinar
ATTACH;FMTTYPE=image/jpeg:https://marketingeda.com/wp-content/uploads/Ansys-November-9-2023.jpg
END:VEVENT
BEGIN:VEVENT
DTSTART;TZID=America/Los_Angeles:20231109T110000
DTEND;TZID=America/Los_Angeles:20231109T120000
DTSTAMP:20231024T171328Z
CREATED:20231024T164155Z
LAST-MODIFIED:20231024T171328Z
UID:6987-1699527600-1699531200@marketingeda.com
SUMMARY:Ways to run cocotb: makefiles\, cocotb-test\, or your custom setup
DESCRIPTION:cocotb enables Python-based hardware verification\, and it integrates into your simulator of choice\, such as Aldec’s Riviera-PRO and executes Python testbenches in that context. In this webinar\, we will look at ways to invoke your simulator of choice in a way that also starts with cocotb. We will show ways to extend the setup to make it suitable for your design\, and discuss trade-offs between the different approaches. \nWe will assume basic cocotb knowledge during this webinar. If you have never heard of cocotb\, have a look at previous Aldec Webinars or other online resources for an introduction to cocotb. \nAgenda:\n\nRunning cocotb tests: your options\nUsing Makefiles to run cocotb tests\nA closer look at cocotb runner\nQ&A: bring your questions!\n\nWebinar Duration\n\n45 min presentation/live demo\n15 min Q&A\n\nPresenter\nPhilipp Wagner\nBio: \nPhilipp Wagner is co-maintainer of cocotb and Hardware/Software Engineer at lowRISC in Cambridge\, UK\, where he is involved in OpenTitan\, the first Open Source Root of Trust chip. For many years Philipp has been working on the intersection of digital hardware\, software and open source. He is passionate about developer productivity\, communities\, and bridging the gap between hardware and software development methodologies. Philipp is Founding Director of the Free and Open Source Silicon Foundation\, and has received a M.Sc. and PhD (Dr.-Ing.) degree in Electrical Engineering from Technical University Munich\, Germany.
URL:https://marketingeda.com/event/ways-to-run-cocotb-makefiles-cocotb-test-or-your-custom-setup/
CATEGORIES:EDA,Webinar
ATTACH;FMTTYPE=image/jpeg:https://marketingeda.com/wp-content/uploads/Aldec-November-9-2023.jpg
END:VEVENT
BEGIN:VEVENT
DTSTART;TZID=America/Los_Angeles:20231108T100000
DTEND;TZID=America/Los_Angeles:20231108T110000
DTSTAMP:20231030T180110Z
CREATED:20231030T175759Z
LAST-MODIFIED:20231030T180110Z
UID:7009-1699437600-1699441200@marketingeda.com
SUMMARY:CMOS Circuit Techniques for Wireline Transmitters Part I
DESCRIPTION:Synopsys Webinar – Part I  \nIn this 3-part Synopsys webinar series\, we will present how hyperscale data centers are going through a paradigm shift with the advent of technologies like Artificial Intelligence (AI) and edge compute requiring hyperscale data centers to support exponential growth of data volume.  This volume of network traffic demands an increase in bandwidth to 400G\, which is now enabled by 112G Ethernet as the interconnect of choice\, with next generation architectures being designed to operate at 224Gbps supporting upcoming 800G/1.6T switches inside datacenters.  These data rates pose extreme challenges on the entire transceiver.  Attend this webinar series to find out about the challenges posed on the transmitter and a discussion on various techniques used in the different blocks to overcome the challenges of data transmission at 100s of Gbps. \nPart I: Wednesday\, November 8\, 2023 \n\nMotivation for SERDES\nTransmitter Requirements\nCurrent/Voltage Mode Drivers\n\nPart II: Wednesday\, November 29\, 2023 \n\nHigh Order Multiplexers\nFFE Equalization\nDSP-DAC Based TX Architectures\n1-UI Pulse Generation Circuits\n\nPart III: Wednesday\, December 13\, 2023 \n\nOutput Matching Network\nMeasurements and Simulation Techniques\n\n\n\n\n\n\n\n\n\n\n\nSpeaker\n\n\nListed below is the industry leader scheduled to speak. \n\n\n\n\n\n\n\n\n\n\n\n\n\n\n\n\n\n\n\n\n\n\n\n\n\n\nNoman Hai\n\n\nManager\, Analog & Mixed-Signal Circuit Design\nSynopsys\, Inc. \n\n\n\n\n\n\n\n\nNoman Hai received the B.E. degree from NED University\, Karachi\, Pakistan in 2002 and the M.Sc. degree in Electrical Engineering from Linkoping University\, Sweden in 2006 and the Ph.D. degree from University of Waterloo\, Canada\, in 2012. He has worked at Philips Semiconductors\, MACOM\, Movellus and Synopsys as an analog design engineer where he was involved in designing high speed analog circuits for wireline and A.I. applications. Currently he is an Analog Design Manager at Synopsys where he is involved in designing high speed interface IP circuits. His current interests include high speed I/O circuits\, design methodology and automation\, and mixed-signal circuits. He holds three U.S. patents
URL:https://marketingeda.com/event/cmos-circuit-techniques-for-wireline-transmitters-part-i/
CATEGORIES:IP,Webinar
ATTACH;FMTTYPE=image/jpeg:https://marketingeda.com/wp-content/uploads/Synopsys-November-8-2023.jpg
END:VEVENT
BEGIN:VEVENT
DTSTART;TZID=America/Los_Angeles:20231108T100000
DTEND;TZID=America/Los_Angeles:20231108T110000
DTSTAMP:20231018T175638Z
CREATED:20231018T175638Z
LAST-MODIFIED:20231018T175638Z
UID:6966-1699437600-1699441200@marketingeda.com
SUMMARY:Deep Dive into the UVM Register Layer: User-Defined Doors\, Predictors\, and Callbacks
DESCRIPTION:This webinar focuses on three specific aspects of the UVM register layer that will help you to model in UVM some of the less obvious ways in which registers can behave\, such as non-linear addressing\, burst access mode\, registers accessed through an embedded CPU\, and quirky registers. \nIt will cover the following topics: \n\nUsing user-defined front and back doors to extend the capabilities of the register layer beyond sending simple request and response transactions to the DUT\nUnderstanding the role played by the predictor in updating the register model and using the predictor in the presence of user-defined front doors • Using register callbacks to model quirky register behaviors\, the side-effects of register reads and writes\, and aliased registers.\nExactly what changes you can and cannot make to UVM code without disturbing the random stimulus generation\n\nTogether\, these topics provide an important set of mechanisms for extending the capabilities of the register layer in many useful ways. \nWe will show code examples that can be run in the Cadence Xcelium Parallel Simulator. \nJohn Aynsley is Doulos Co-Founder and Technical Fellow. John will present this webinar\, consisting of a one-hour broadcast with interactive Q&A available to attendees throughout. \nAttendance is free of charge.\nIf you have any queries\, please contact webinars@doulos.com
URL:https://marketingeda.com/event/deep-dive-into-the-uvm-register-layer-user-defined-doors-predictors-and-callbacks/
CATEGORIES:EDA,Webinar
ATTACH;FMTTYPE=image/jpeg:https://marketingeda.com/wp-content/uploads/Cadence-November-8-2023.jpg
END:VEVENT
BEGIN:VEVENT
DTSTART;TZID=America/Los_Angeles:20231107T100000
DTEND;TZID=America/Los_Angeles:20231107T110000
DTSTAMP:20231010T195132Z
CREATED:20231010T195132Z
LAST-MODIFIED:20231010T195132Z
UID:6937-1699351200-1699354800@marketingeda.com
SUMMARY:Proactive Data Center Management with Insight Platform
DESCRIPTION:The DataCenter Insight Platform is an enterprise software solution that simplifies data center capacity management by making it proactive\, rather than reactive. The platform is a database of data center “digital twins”—virtual models reflecting the aggregate of an organization’s toolsets and add/move/change workflows. \nBy bringing together data that is typically siloed and using predictive computational fluid dynamics (CFD) simulation to answer all the “what-ifs\,” digital twins provide actionable insights that would otherwise go unrealized. Fortune 500 companies are using Insight Platform to standardize their deployment processes and make fast and effective capacity planning decisions. \nThis webinar will describe how digital twins are deployed at scale via integration and automated workflows and provide a software demonstration of the proactive capacity planning toolset.
URL:https://marketingeda.com/event/proactive-data-center-management-with-insight-platform/
CATEGORIES:EDA,Webinar
ATTACH;FMTTYPE=image/jpeg:https://marketingeda.com/wp-content/uploads/Cadence-November-7-2023.jpg
END:VEVENT
BEGIN:VEVENT
DTSTART;TZID=America/Los_Angeles:20231101T110000
DTEND;TZID=America/Los_Angeles:20231101T120000
DTSTAMP:20231019T170231Z
CREATED:20231019T170231Z
LAST-MODIFIED:20231019T170231Z
UID:6977-1698836400-1698840000@marketingeda.com
SUMMARY:Warp Speed Gate-Level Simulations with the Xcelium Multi-Core App
DESCRIPTION:Are you ready to lead the way in gate-level digital simulations (GLS)? Dive into Cadence’s exclusive webinar and uncover the revolutionary Xcelium Multi-Core (MC) App—a game changer for GLS\, allowing you to parallelize and expedite simulations like never before. \nWhat You’ll Gain:\nInsight: Understand why the Xcelium MC App is crucial for DV engineers looking to speed up GLS.\nKnowledge: Learn how to deploy the full potential of the Xcelium MC App.\nBest Practices: Discover optimal utilization practices to maximize the efficiency of your gate-level simulations.\nExamples: See the application of the Xcelium MC App\, showcasing how you can simulate GLS at warp speed! \nBenefits: \n\nAchieve 10X faster simulations\, accelerate your aggressive project schedules\nTackle complex billion gate designs with ease\nFully leverage the capacities of modern multi-core CPUs in your server farm\n\nDon’t be left behind! Join us and catapult your GLS to warp speed\, ensuring your projects are not stalled by long pole tests but mastered with precision and efficiency.
URL:https://marketingeda.com/event/warp-speed-gate-level-simulations-with-the-xcelium-multi-core-app/
CATEGORIES:EDA,Webinar
ATTACH;FMTTYPE=image/jpeg:https://marketingeda.com/wp-content/uploads/Cadence-November-1-2023.jpg
END:VEVENT
BEGIN:VEVENT
DTSTART;TZID=America/Los_Angeles:20231101T100000
DTEND;TZID=America/Los_Angeles:20231101T103000
DTSTAMP:20231003T172423Z
CREATED:20231003T172423Z
LAST-MODIFIED:20231003T172423Z
UID:6910-1698832800-1698834600@marketingeda.com
SUMMARY:Mastering the Art of Managing IP\, Chiplets\, and Design Data
DESCRIPTION:Join us on Wednesday\, November 1st\, for an eye-opening exploration of the inadequacy of common design data and IP management capabilities in the face of today’s intricate semiconductor chip designs. Discover the keys to unlocking unparalleled success in your upcoming designs through cutting-edge capabilities and strategies that are reshaping the industry. Don’t miss this exclusive opportunity to revolutionize your approach to semiconductor chip design. \n  \nHere’s what you can learn:\n\nBest practices for efficient chip design data and IP handling.\nCutting-edge IP management strategies for reuse\, security\, and compliance.\nData integration and design flow techniques to enhance collaboration.\n\n  \nBONUS: Design Data and IP Management Best Practices eBook for All Participants! \n  \nWho should attend:\n\nSemiconductor Design and Verification Engineers\nIP Managers and Administrators\nData and tech enthusiasts\nInnovators seeking an edge\nAnyone passionate about chip design excellence\n\nDon’t miss out on this chance to gain a competitive edge in the dynamic world of semiconductor chip design. See you at the webinar!
URL:https://marketingeda.com/event/mastering-the-art-of-managing-ip-chiplets-and-design-data/
CATEGORIES:EDA,IP,Webinar
ATTACH;FMTTYPE=image/jpeg:https://marketingeda.com/wp-content/uploads/Keysight-November-1-2023.jpg
END:VEVENT
BEGIN:VEVENT
DTSTART;TZID=America/Los_Angeles:20231031T100000
DTEND;TZID=America/Los_Angeles:20231031T110000
DTSTAMP:20231013T183201Z
CREATED:20231013T183201Z
LAST-MODIFIED:20231013T183201Z
UID:6956-1698746400-1698750000@marketingeda.com
SUMMARY:Enhance Verification Quality with the Xcelium Mixed-Signal App
DESCRIPTION:The comprehensive verification of analog mixed-signal (AMS) designs has challenges in schedules and implementations due to the vast divergence in design flows of the analog and digital portions of the SoC. These discrepancies include priorities in simulation cycles (accuracy versus performance)\, design methodologies\, and verification of functionality. \nOver multiple decades\, design verification (DV) has evolved towards catching bugs earlier in the design cycles\, allowing an exponential increase in the functionality of SoCs. Extending those improvements to mixed signal is critical for continuous growth. This CadenceTECHTALK goes over many of the silicon-proven approaches enabling it\, and DV engineers will find immense value in the contents. Specifically\, it covers solutions to those challenges in mixed-signal verification (MSV) using the capabilities of the Xcelium Mixed-Signal App. \nWhat attendees will learn: \n\nDevelopment of analog modeling in SystemVerilog using real number modeling (RNM)\nMSV co-sim testbench architecture to allow swapping of models and netlists\nEnhancements of DV regression setup with a hybrid flow that allows for both RNM and co-sim
URL:https://marketingeda.com/event/enhance-verification-quality-with-the-xcelium-mixed-signal-app/
CATEGORIES:EDA,Webinar
ATTACH;FMTTYPE=image/jpeg:https://marketingeda.com/wp-content/uploads/Cadence-October-31-2023.jpg
END:VEVENT
BEGIN:VEVENT
DTSTART;TZID=America/Los_Angeles:20231019T100000
DTEND;TZID=America/Los_Angeles:20231019T110000
DTSTAMP:20231009T170426Z
CREATED:20231009T170426Z
LAST-MODIFIED:20231009T170426Z
UID:6927-1697709600-1697713200@marketingeda.com
SUMMARY:High Reliability and Functional Safety Applications for FPGA
DESCRIPTION:When designing any new system\, safety and reliability are key factors in determining if a system is safe for real-world deployment and if there are sufficient contingency plans for worst case scenarios. This is no different for the designs targeted for FPGAs based deployments. Today\, FPGA based designs are utilized in many safety critical systems in the military\, aerospace\, medical\, industrial\, robotics\, and automotive industries. These systems require meeting stringent safety regulations such as defined by ISO 26262 standard for automotive and the IEC 61508 standard for industrial applications. \nTo address this need\, Synopsys provides a comprehensive family of integrated FPGA verification products. For FPGA synthesis\, Synplify provides the state of the art and most ease-of-use automated features for functional safety and high reliability for FPGA designs. Synplify Synthesis tool can automate design logic insertion at module to register level and as well as provide full features for functional testing and debugging. This includes features such as logic duplication\, triplication\, error flag insertion and fault injection. \nIn this webinar\, we will cover and demonstrate\, how Synplify and Synopsys family of verification products enable users to meet their functional safety and high reliability needs for FPGA based designs. \n\n\n\n\n\n\n\n\n\n\nSpeakers\n\n\nListed below are the industry leaders scheduled to speak. \n\n\n\n\n\n\n\n\n\n\n\n\n\n\n\n\n\n\n\n\n\n\n\n\n\n\nKhalid Khan\n\n\nSenior Staff Applications Engineer\nSynopsys Inc \n\n\n\n\n\n\n\n\n\n\n\nKhalid Khan is a Senior Staff Application Engineer with Synopsys System Design Group based out of Synopsys HQ in Sunnyvale\, CA. He has 20+ years of experience in FPGA Synthesis\, Verification and ASIC Prototyping fields. He is currently the overall lead for the Synplify FPGA synthesis product for field application engineering team in helping define the product road map and strategy. \nHe also helps support many of the major FPGA Synthesis and Prototyping customers in the Silicon Valley region. \n\n\n\n\n\n\n\n\n\n\n\n\n\n\n\n\n\n\n\n\n\n\n\n\n\n\n\n\n\n\n\nDeAndre Hoskins\n\n\nStaff Applications Engineer\nSynopsys Inc \n\n\n\n\n\n\n\n\n\n\n\nDeAndre Hopkins is a Staff Application Engineer based in San Diego\, CA. \nHe has 15+ of experience in FPGA Synthesis and Verification flows. He has extensive background working with Military/Aerospace customers using VHDL and FPGA synthesis flows. He is based out of San Diego\, CA and supports major FPGA accounts in southern CA\, AZ\, NM\, TX regions. \n\n\n\n\n\n\n\n\n\n\n\n\n\n\n\n\n\n\n\n\n\n\n\n\n\n\n\n\n\n\n\nBobby Zuiss\n\n\nSenior Applications Engineer\nSynopsys Inc \n\n\n\n\n\n\n\n\n\n\n\nBobby Zuiss is a Senior Applications Engineer with the Synopsys System Design Group. He has 10+ years of experience with FPGA Synthesis products. He is based out of Los Angeles\, CA. He has experience working with FPGAs in both Defense and High Speed Trading industries. He supports major Military/Aerospace accounts in Southern CA\, CO\, & UT.
URL:https://marketingeda.com/event/high-reliability-and-functional-safety-applications-for-fpga/
CATEGORIES:EDA,Webinar
ATTACH;FMTTYPE=image/jpeg:https://marketingeda.com/wp-content/uploads/Synopsys-October-19-2023.jpg
END:VEVENT
BEGIN:VEVENT
DTSTART;TZID=America/New_York:20231018T100000
DTEND;TZID=America/New_York:20231018T104500
DTSTAMP:20231008T235227Z
CREATED:20231008T235227Z
LAST-MODIFIED:20231008T235227Z
UID:6922-1697623200-1697625900@marketingeda.com
SUMMARY:System-Level Thermal Signoff from Chips Through to Racks
DESCRIPTION:Today’s modern electronic designs require ever more functionality and performance to meet consumer demand. These challenges become more critical and complex when resistive losses in PCB and package structures are significant since resistive losses are temperature dependent. In this webinar\, we will look at an electrothermal co-simulation solution for the full hierarchy of electronic systems from ICs to physical enclosures using Cadence’s Celsius technologies. By combining finite-element analysis (FEA) for solid structures with computational fluid dynamics (CFD) for both liquid and gas\, as well as airflow\, designers can perform complete system analysis in a single tool. The combined workflow that ties the Celsius Thermal Solver with the Celsius EC electronic cooling solver provides even higher accuracy and faster simulation time in the modeling of electronics equipment.  \n\n\n\nSpeakers\n\n\n\n\nDr. Melika Roshandell\nProduct Marketing Director\nCadence\n\n\nDr. Melika Roshandell is product marketing director for Celsius Thermal Solver software at Cadence. Prior to Cadence she held positions as a system on chip (SoC) thermal engineer at Qualcomm for nine years and thermal engineer at Broadcom for two years. Dr. Roshandell earned her BS in mechanical engineering at the University of California\, San Diego\, and her MS and PhD in mechanical engineering at the University of California\, Irvine. \n\n\n\n\n\nKarthick Gopalakrishnan\nProduct Engineer\nCadence\n\n\nKarthick Gopalakrishnan is a product engineer at Cadence supporting the Celsius line of electrothermal analysis products. Prior to joining Cadence\, he was a thermal/CFD application engineer at Mentor Graphics. Karthick holds an MS in mechanical engineering from the North Carolina State University\, where he specialized in thermal and fluid sciences.
URL:https://marketingeda.com/event/system-level-thermal-signoff-from-chips-through-to-racks/
CATEGORIES:EDA,Webinar
ATTACH;FMTTYPE=image/jpeg:https://marketingeda.com/wp-content/uploads/Cadence-October-18-2023-1.jpg
END:VEVENT
BEGIN:VEVENT
DTSTART;TZID=America/Los_Angeles:20231018T083000
DTEND;TZID=America/Los_Angeles:20231018T091500
DTSTAMP:20230928T182610Z
CREATED:20230928T182610Z
LAST-MODIFIED:20230928T182610Z
UID:6900-1697617800-1697620500@marketingeda.com
SUMMARY:Soar to New Heights of Productivity using Cadence Managed Cloud Services
DESCRIPTION:Date: Wednesday\, October 18\, 2023 \nTime: 8:30am PT | 10:30am CT | 11:30am ET \n\n\n\n\n\n\n\n\n\n\n\n\nJoin us for this 45-minute webinar to learn how the Cadence-managed\, EDA-optimized\, ready-to-use\, and secure ISO-certified cloud platform delivers a fully integrated and proven environment to jump-start product design\, verification\, and implementation. See the platform in action as we demo the productivity features of Cadence’s digital and analog design flows. \n\n\n\n\n\n\n\n\n\n\n\n\nWhat You Will Learn \n\n\n\n\n\n\n\n\n\n\n\n\n\nHow hundreds of customers have accelerated their design\, verification\, and implementation projects\, whether for full or partial design flow in the cloud\nHow the cloud can solve your peak capacity needs\, driving faster tapeouts and time-to-market\nHow to request compute hosts and access Rapid Adoption Kits (RAKs) in the cloud for interactive and batch jobs utilizing Virtuoso and Xcelium\nHow to request a free 30-day evaluation of the environment\n\n\n\n\n\n\n\n\n\n\n\n\n\nWho Should Attend \n\n\n\n\n\n\n\n\n\n\n\n\nThis webinar will be useful for: \n\nDesign/Verification engineers\nIT/Cloud Architects\nTechnical/Business Decision Makers\n\n\n\n\n\n\n\n\n\n\n\n\n\nSpeakers: \n\n\n\n\n\n\n\nKetan Joshi\nSr. Group Director\, Cloud Team\, Cadence \n\n\n\n\n\n\n\n\n\n\n\n\nMike Stanton\nGroup Director\, IT\, Cadence
URL:https://marketingeda.com/event/soar-to-new-heights-of-productivity-using-cadence-managed-cloud-services/
CATEGORIES:EDA,Webinar
ATTACH;FMTTYPE=image/jpeg:https://marketingeda.com/wp-content/uploads/Cadence-cloud-October-18-2023.jpg
END:VEVENT
BEGIN:VEVENT
DTSTART;TZID=Europe/London:20231017T120000
DTEND;TZID=Europe/London:20231017T130000
DTSTAMP:20230925T185357Z
CREATED:20230925T185357Z
LAST-MODIFIED:20230925T185357Z
UID:6869-1697544000-1697547600@marketingeda.com
SUMMARY:DVClub Europe - AI/ML in Verification
DESCRIPTION:This is to inform you that the next DVClub Europe meeting takes place on Tuesday 17th October with a theme of “AI/ML in Verification”.\n\nThis DVClub consider how we can save time and effort whilst improving time-to-market through the application of AI/ML to verification.\n\nAgenda (BST) \n12:00   Welcome and Introduction – Mike Bartley\, Senior Vice President – VLSI Design\, Tessolve \n12:00   Rajendra Prasad\, Infineon – Smart Adaptive Regression using Nearest Neighbour Algorithm \n12:45    Daniel Hansson\, Cadence Design System – \n13:00    Close \n  \nRegister now to become a part of this event. Free to attend online. \nEventbrite – DVClub Europe  \nBest Regards \nMike Bartley\, Senior Vice President – VLSI Design\, Tessolve
URL:https://marketingeda.com/event/dvclub-europe-ai-ml-in-verification/
CATEGORIES:EDA,Webinar
ATTACH;FMTTYPE=image/jpeg:https://marketingeda.com/wp-content/uploads/DVClub-17-October-2023.jpg
END:VEVENT
BEGIN:VEVENT
DTSTART;TZID=America/Los_Angeles:20231012T100000
DTEND;TZID=America/Los_Angeles:20231012T110000
DTSTAMP:20230918T184234Z
CREATED:20230918T184234Z
LAST-MODIFIED:20230918T184234Z
UID:6811-1697104800-1697108400@marketingeda.com
SUMMARY:The UCIe™ 1.1 Specification: Future Applications of Chiplets
DESCRIPTION:Presenter: Dr. Debendra Das Sharma\, UCIe Consortium Chairman and Intel Senior Fellow\, Chief Architect of I/O Technology and Standards at Intel  \n\n\nThe UCIe™ (Universal Chiplet Interconnect Express™) 1.1 Specification was released in August 2023\, delivering valuable improvements to the chiplet ecosystem\, extending reliability mechanisms to more protocols and supporting broader usage models. This webinar will provide an overview on enhancements made in the UCIe 1.1 specification and architectural specification attributes to define system setups and registers that will be used in test plans and compliance testing to ensure device interoperability. The presentation will also explore additional enhancements included for automotive usages – such as predictive failure analysis and health monitoring – and enabling lower-cost packaging implementations. Attendees will have a chance to participate in a live Q&A discussion immediately after the webinar to address questions from the presentation. 
URL:https://marketingeda.com/event/the-ucie-1-1-specification-future-applications-of-chiplets/
CATEGORIES:IP,Webinar
ATTACH;FMTTYPE=image/jpeg:https://marketingeda.com/wp-content/uploads/UCIe-October-12-2023.jpg
END:VEVENT
BEGIN:VEVENT
DTSTART;TZID=America/Los_Angeles:20231012T100000
DTEND;TZID=America/Los_Angeles:20231012T110000
DTSTAMP:20230908T182145Z
CREATED:20230908T182145Z
LAST-MODIFIED:20230908T182145Z
UID:6786-1697104800-1697108400@marketingeda.com
SUMMARY:Proactively Address Thermal Concerns in Advanced IC Packages
DESCRIPTION:The heterogeneous integration of chips and chiplets in IC packages is all the rage as we face “More than Moore” performance challenges. While these innovative design practices successfully address performance goals\, some design teams find that IC packages may overheat if they do not carefully plan for heat dissipation. \nThis webinar will show how design teams that implement thermal mitigation strategies early in the design cycle are facing fewer thermal concerns with their IC package prototypes.  We will walk through a reference design and discuss how Cadence Advanced Package Designer Plus combined with Celsius Thermal Solver address feasibility during the design planning stage to the full-system final signoff. \nJoin our webinar to learn how you can: \n\nEfficiently address thermal concerns throughout the design cycle\nReduce design iterations\nProactively drive predictability into your design schedules
URL:https://marketingeda.com/event/proactively-address-thermal-concerns-in-advanced-ic-packages/
CATEGORIES:EDA,IP,Webinar
ATTACH;FMTTYPE=image/jpeg:https://marketingeda.com/wp-content/uploads/Cadence-October-12-2023.jpg
END:VEVENT
BEGIN:VEVENT
DTSTART;TZID=America/Los_Angeles:20231011T090000
DTEND;TZID=America/Los_Angeles:20231011T100000
DTSTAMP:20231006T190044Z
CREATED:20231006T190044Z
LAST-MODIFIED:20231006T190044Z
UID:6919-1697014800-1697018400@marketingeda.com
SUMMARY:Mapping signal processing algorithms on AMD-Xilinx Versal to meet timing and power constraints
DESCRIPTION:In this Webinar\, we will focus on the performance-power-area trade-off in implementing signal processing algorithms on Xilinx FPGA by partitioning the tasks of the algorithms onto the processors\, logic and AI Engines resident in the AMD-Xilinx Versal FPGA.  \n\n Key Takeaways: \n\nDiscover the inner workings of FPGA components: Processor\, Logic Elements\, AIE/Tensor\, and more.\nUnderstand latency and throughput trade-offs when using NoC vs. direct interfaces.\nLearn how different data cache sizes impact AIE Tile network utilization.\nDive into various mapping decisions and their effect on application throughput and power consumption.\n\n  \nSo\, what are you waiting for? Don’t miss this opportunity
URL:https://marketingeda.com/event/mapping-signal-processing-algorithms-on-amd-xilinx-versal-to-meet-timing-and-power-constraints/
CATEGORIES:EDA,IP,Webinar
ATTACH;FMTTYPE=image/jpeg:https://marketingeda.com/wp-content/uploads/Mirabilis-October-11-2023.jpg
END:VEVENT
BEGIN:VEVENT
DTSTART;TZID=America/Los_Angeles:20231005T110000
DTEND;TZID=America/Los_Angeles:20231005T120000
DTSTAMP:20230801T173224Z
CREATED:20230801T173224Z
LAST-MODIFIED:20230801T173224Z
UID:6644-1696503600-1696507200@marketingeda.com
SUMMARY:FPGA Design Verification - Advanced Methods
DESCRIPTION:Abstract \nAs FPGA technology continues to evolve – to provide us with full-blown SoCs with CPU\, GPU\, and high-speed peripherals\, for example\, joining the traditional programmable logic area – design verification becomes increasingly challenging. Lab-based FPGA testing and bring-up alone are clearly insufficient\, especially for safety-critical designs\, and FPGA teams are adopting advanced design verification methodologies and techniques to develop homegrown verification processes. \n  \nIn this three-part webinar series\, we will discuss design verification with a focus on creating an advanced simulation-based verification process; from verification planning and team organization\, and moving on to regression setup\, functional coverage collection\, randomization and ‘verification done’ definitions. We will also show you how to develop simple yet powerful and reusable testbenches using Verilog and SystemVerilog constructs and how to functionally verify designs in the most efficient way. \n  \nIn this\, the concluding episode of the webinar series\, we will present advanced verification solutions for verifying complex design properties. We will talk about randomization\, functional coverage\, and the importance of code coverage to achieve overall design verification completeness. Also\, we will provide an overview on other important topics such as assertion and transaction-based verification and debug\, static design verification with linting tools and regressions support. Finally\, we will talk about ‘Verification Done’\, in terms of at what point can the verification be considered complete and how do we achieve it? \n  \nAgenda: \n\nCheckers and Scoreboards Development\nRandomization Methods\nFunctional Coverage and Tests Grading\nCode Coverage\nAssertion-based Verification\nTransaction-based Debugging with Riviera-PRO\nStatic Verification with Linting tools\nSetting up Regressions\nDefining “Verification Done”\nPacket-based Design Verification Example\nConclusion\nQ&A\n\n  \nWebinar Duration: \n\n45 min presentation/live demo\n15 min Q&A\n\n  \nPresenter BIO \nAlexander Gnusin\, Design Verification Technologist\, Aldec \nAlexander Gnusin accumulated 27 years of hands-on experience in various aspects of ASIC and FPGA design and verification. As a verification prime for a multi-million gates project in companies such as IBM\, Nortel\, Ericsson and Synopsys Inc\, he combined various verification methods such as static linting\, formal property checking\, dynamic simulation and hardware-assisted acceleration to efficiently achieve design verification goals. He received his M.S. in Electronics from Technion\, Israel Institute of Technology.
URL:https://marketingeda.com/event/fpga-design-verification-advanced-methods/
CATEGORIES:EDA,Webinar
ATTACH;FMTTYPE=image/jpeg:https://marketingeda.com/wp-content/uploads/Aldex-Verification.jpg
END:VEVENT
BEGIN:VEVENT
DTSTART;TZID=America/Los_Angeles:20231004T110000
DTEND;TZID=America/Los_Angeles:20231004T120000
DTSTAMP:20230921T172330Z
CREATED:20230921T172330Z
LAST-MODIFIED:20230921T172330Z
UID:6855-1696417200-1696420800@marketingeda.com
SUMMARY:Verisium Debug for UVM Testbench
DESCRIPTION:Verisium Debug offers comprehensive debugging capabilities. From RTL and UVM testbench to UPF low-power designs\, Cadence’s unified debugging platform helps users debug. In this webinar\, users will learn about the available features in Verisium Debug for UVM testbench and use these unique capabilities to visualize and debug the UVM testbench. \nWhat you will learn \n\nUnderstand the features available in Verisium Debug\n​Learn about the UVM debug capabilities in Verisium Debug\nLearn to debug UVM testbench using Verisium Debug\n\nWho should attend \n\nDesign engineers\nVerification engineers\nCAD engineers
URL:https://marketingeda.com/event/verisium-debug-for-uvm-testbench/
CATEGORIES:EDA,Webinar
ATTACH;FMTTYPE=image/jpeg:https://marketingeda.com/wp-content/uploads/Cadence-October-4-2023.jpg
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BEGIN:VEVENT
DTSTART;TZID=America/Los_Angeles:20230928T110000
DTEND;TZID=America/Los_Angeles:20230928T120000
DTSTAMP:20230801T173012Z
CREATED:20230801T172957Z
LAST-MODIFIED:20230801T173012Z
UID:6642-1695898800-1695902400@marketingeda.com
SUMMARY:FPGA Design Verification - Advanced Testbench Implementation
DESCRIPTION:Abstract \nAs FPGA technology continues to evolve – to provide us with full-blown SoCs with CPU\, GPU\, and high-speed peripherals\, for example\, joining the traditional programmable logic area – design verification becomes increasingly challenging. Lab-based FPGA testing and bring-up alone are clearly insufficient\, especially for safety-critical designs\, and FPGA teams are adopting advanced design verification methodologies and techniques to develop homegrown verification processes. \n  \nIn this three-part webinar series\, we will discuss design verification with a focus on creating an advanced simulation-based verification process; from verification planning and team organization\, and moving on to regression setup\, functional coverage collection\, randomization and ‘verification done’ definitions. We will also show you how to develop simple yet powerful and reusable testbenches using Verilog and SystemVerilog constructs and how to functionally verify designs in the most efficient way. \n  \nIn part 2 of this webinar series\, we will show you important verification patterns providing solutions to repeatable randomization\, error management and end-of-test checks. We will also provide an overview of how to define\, develop and re-use verification components such as drivers\, responders\, and monitors. Then\, we will talk about how to develop testbenches\, and how to validate their correctness with reporting and statistics collection. We will provide code examples to illustrate the topics of discussion. \n  \nAgenda: \n\nCommon Verification Patterns:\no Repeatable Randomization\no Reporting\, Error management\no End-of-Test Procedure\nVerification Components (VC) Development:\no Verification Component Types\no Defining Transactions for VC Development\no Legal and Error Operation Modes\no Controllable Randomization\no Verification in Standalone Testbenches\nTestbench Development and Verification:\no Statistical methods for Testbench Validation\no Scripting Support\nDemo with example design and testbench\nConclusion\nQ&A\n\n  \nWebinar Duration: \n\n45 min presentation/live demo\n15 min Q&A\n\n  \nPresenter BIO \nAlexander Gnusin\, Design Verification Technologist\, Aldec \nAlexander Gnusin accumulated 27 years of hands-on experience in various aspects of ASIC and FPGA design and verification. As a verification prime for a multi-million gates project in companies such as IBM\, Nortel\, Ericsson and Synopsys Inc\, he combined various verification methods such as static linting\, formal property checking\, dynamic simulation and hardware-assisted acceleration to efficiently achieve design verification goals. He received his M.S. in Electronics from Technion\, Israel Institute of Technology.
URL:https://marketingeda.com/event/fpga-design-verification-advanced-testbench-implementation/
CATEGORIES:EDA,Webinar
ATTACH;FMTTYPE=image/jpeg:https://marketingeda.com/wp-content/uploads/Aldex-Verification.jpg
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BEGIN:VEVENT
DTSTART;TZID=America/Los_Angeles:20230927T120000
DTEND;TZID=America/Los_Angeles:20230927T130000
DTSTAMP:20230818T231020Z
CREATED:20230818T231020Z
LAST-MODIFIED:20230818T231020Z
UID:6732-1695816000-1695819600@marketingeda.com
SUMMARY:Stratus HLS Automated Power Shutoff to Minimize Power and Retention Registers
DESCRIPTION:Power Shutoff is a popular technique for saving power during functionally idle periods. Implementing Power Shutoff requires a detailed understanding of which resisters must be retained to enable bring-up from the power-off state. Identifying the minimal set of retention registers is challenging and grows more difficult with design complexity. \n\nThis CadenceTECHTALK introduces a novel High-Level Synthesis-based solution for the automated implementation of Power Shutoff. This solution automatically identifies and implements Power Shutoff using the minimal set of retention registers\, yielding the lowest leakage power and saving weeks of implementation time vs. manual methods. \n\nJoin this webinar to learn how to apply this technology to your own design and interact with product experts who will demonstrate the technology in a real-world testcase. Design engineers working on low-power digital IC designs or algorithms will benefit from this TECHTALK.
URL:https://marketingeda.com/event/stratus-hls-automated-power-shutoff-to-minimize-power-and-retention-registers/
CATEGORIES:EDA,Webinar
ATTACH;FMTTYPE=image/jpeg:https://marketingeda.com/wp-content/uploads/Cadence-September-27-2023.jpg
END:VEVENT
BEGIN:VEVENT
DTSTART;TZID=America/New_York:20230927T100000
DTEND;TZID=America/New_York:20230927T110000
DTSTAMP:20230913T184118Z
CREATED:20230913T184118Z
LAST-MODIFIED:20230913T184118Z
UID:6792-1695808800-1695812400@marketingeda.com
SUMMARY:Cadence Training: Cerebrus Intelligent Chip Explorer
DESCRIPTION:Please join me\, Cadence Training and Application Engineer Krishna Atreya\, for this free technical Training Webinar. \nWhat Is the Webinar About?\nThe Cadence Cerebrus Intelligent Chip Explorer is a revolutionary\, machine learning-driven\, automated approach to chip design flow optimization. Block engineers specify the design goals\, and Cadence Cerebrus intelligently optimizes the Cadence digital full flow to meet power\, performance\, and area (PPA) goals in a completely automated way—letting engineers concurrently optimize multiple block flows\, which is particularly important for the large\, complex system-on-chip (SoC) designs needed for today’s ever more powerful electronic systems. \nWe’ll dive into: \n\nUnderstanding the Cadence Cerebrus flows\nUnderstanding flow wrapping\nFlow wrapping your design for Cadence Cerebrus readiness\n\nWhen Is the Webinar?\nWednesday\, September 27 \n07:00 PDT San Jose / 10:00 EDT New York / 15:00 BST London / 16:00 CEST Berlin / 17:00 IDT Jerusalem / 19:30 IST Bangalore / 22:00 CST Beijing \nTo register for the “Flow Wrapping: The Cadence Cerebrus Intelligent Chip Explorer Must Have” webinar\, use the REGISTER button below and sign in with your Cadence Support account (email ID and password) to log in to the Learning and Support System. Then select Enroll to register for the session. Once registered\, you’ll receive a confirmation email containing all login details. \nREGISTER \nIf you don’t have a Cadence Support account\, go to Registration Help or Cadence User Registration\, and complete the requested information. \nFor questions and inquiries or issues with registration\, reach out to eur_training@cadence.com \nKeep up with the revolution! Join Cadence’s Cerebrus Intelligent Chip Explorer Training and learn how to use Cadence Cerebrus to scale and automate your design\, improve your productivity\, and much more. \nThe online class is free for all Cadence customers with a Learning and Support account. \nWe can also organize this Cadence Cerebrus Intelligent Chip Explorer Training for you as a “Blended” or “Live” training. Please reach out to Cadence Training for further information. \nYou can also enjoy this video to get a first impression what is waiting for you! \nWant to share this and other great Cadence learning opportunities with someone else? Tell them to subscribe. \nHungry for Training?\nChoose the Cadence Training Menu that’s right for you. To view our complete training offerings\, visit the Cadence Training website.
URL:https://marketingeda.com/event/cadence-training-cerebrus-intelligent-chip-explorer/
CATEGORIES:EDA,Webinar
ATTACH;FMTTYPE=image/jpeg:https://marketingeda.com/wp-content/uploads/Cadence-September-27-2023-2.jpg
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