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BEGIN:VEVENT
DTSTART;TZID=America/Los_Angeles:20231108T100000
DTEND;TZID=America/Los_Angeles:20231108T110000
DTSTAMP:20231030T180110Z
CREATED:20231030T175759Z
LAST-MODIFIED:20231030T180110Z
UID:7009-1699437600-1699441200@marketingeda.com
SUMMARY:CMOS Circuit Techniques for Wireline Transmitters Part I
DESCRIPTION:Synopsys Webinar – Part I  \nIn this 3-part Synopsys webinar series\, we will present how hyperscale data centers are going through a paradigm shift with the advent of technologies like Artificial Intelligence (AI) and edge compute requiring hyperscale data centers to support exponential growth of data volume.  This volume of network traffic demands an increase in bandwidth to 400G\, which is now enabled by 112G Ethernet as the interconnect of choice\, with next generation architectures being designed to operate at 224Gbps supporting upcoming 800G/1.6T switches inside datacenters.  These data rates pose extreme challenges on the entire transceiver.  Attend this webinar series to find out about the challenges posed on the transmitter and a discussion on various techniques used in the different blocks to overcome the challenges of data transmission at 100s of Gbps. \nPart I: Wednesday\, November 8\, 2023 \n\nMotivation for SERDES\nTransmitter Requirements\nCurrent/Voltage Mode Drivers\n\nPart II: Wednesday\, November 29\, 2023 \n\nHigh Order Multiplexers\nFFE Equalization\nDSP-DAC Based TX Architectures\n1-UI Pulse Generation Circuits\n\nPart III: Wednesday\, December 13\, 2023 \n\nOutput Matching Network\nMeasurements and Simulation Techniques\n\n\n\n\n\n\n\n\n\n\n\nSpeaker\n\n\nListed below is the industry leader scheduled to speak. \n\n\n\n\n\n\n\n\n\n\n\n\n\n\n\n\n\n\n\n\n\n\n\n\n\n\nNoman Hai\n\n\nManager\, Analog & Mixed-Signal Circuit Design\nSynopsys\, Inc. \n\n\n\n\n\n\n\n\nNoman Hai received the B.E. degree from NED University\, Karachi\, Pakistan in 2002 and the M.Sc. degree in Electrical Engineering from Linkoping University\, Sweden in 2006 and the Ph.D. degree from University of Waterloo\, Canada\, in 2012. He has worked at Philips Semiconductors\, MACOM\, Movellus and Synopsys as an analog design engineer where he was involved in designing high speed analog circuits for wireline and A.I. applications. Currently he is an Analog Design Manager at Synopsys where he is involved in designing high speed interface IP circuits. His current interests include high speed I/O circuits\, design methodology and automation\, and mixed-signal circuits. He holds three U.S. patents
URL:https://marketingeda.com/event/cmos-circuit-techniques-for-wireline-transmitters-part-i/
CATEGORIES:IP,Webinar
ATTACH;FMTTYPE=image/jpeg:https://marketingeda.com/wp-content/uploads/Synopsys-November-8-2023.jpg
END:VEVENT
BEGIN:VEVENT
DTSTART;TZID=America/Los_Angeles:20231108T100000
DTEND;TZID=America/Los_Angeles:20231108T110000
DTSTAMP:20231018T175638Z
CREATED:20231018T175638Z
LAST-MODIFIED:20231018T175638Z
UID:6966-1699437600-1699441200@marketingeda.com
SUMMARY:Deep Dive into the UVM Register Layer: User-Defined Doors\, Predictors\, and Callbacks
DESCRIPTION:This webinar focuses on three specific aspects of the UVM register layer that will help you to model in UVM some of the less obvious ways in which registers can behave\, such as non-linear addressing\, burst access mode\, registers accessed through an embedded CPU\, and quirky registers. \nIt will cover the following topics: \n\nUsing user-defined front and back doors to extend the capabilities of the register layer beyond sending simple request and response transactions to the DUT\nUnderstanding the role played by the predictor in updating the register model and using the predictor in the presence of user-defined front doors • Using register callbacks to model quirky register behaviors\, the side-effects of register reads and writes\, and aliased registers.\nExactly what changes you can and cannot make to UVM code without disturbing the random stimulus generation\n\nTogether\, these topics provide an important set of mechanisms for extending the capabilities of the register layer in many useful ways. \nWe will show code examples that can be run in the Cadence Xcelium Parallel Simulator. \nJohn Aynsley is Doulos Co-Founder and Technical Fellow. John will present this webinar\, consisting of a one-hour broadcast with interactive Q&A available to attendees throughout. \nAttendance is free of charge.\nIf you have any queries\, please contact webinars@doulos.com
URL:https://marketingeda.com/event/deep-dive-into-the-uvm-register-layer-user-defined-doors-predictors-and-callbacks/
CATEGORIES:EDA,Webinar
ATTACH;FMTTYPE=image/jpeg:https://marketingeda.com/wp-content/uploads/Cadence-November-8-2023.jpg
END:VEVENT
BEGIN:VEVENT
DTSTART;TZID=America/Los_Angeles:20231107T100000
DTEND;TZID=America/Los_Angeles:20231107T110000
DTSTAMP:20231010T195132Z
CREATED:20231010T195132Z
LAST-MODIFIED:20231010T195132Z
UID:6937-1699351200-1699354800@marketingeda.com
SUMMARY:Proactive Data Center Management with Insight Platform
DESCRIPTION:The DataCenter Insight Platform is an enterprise software solution that simplifies data center capacity management by making it proactive\, rather than reactive. The platform is a database of data center “digital twins”—virtual models reflecting the aggregate of an organization’s toolsets and add/move/change workflows. \nBy bringing together data that is typically siloed and using predictive computational fluid dynamics (CFD) simulation to answer all the “what-ifs\,” digital twins provide actionable insights that would otherwise go unrealized. Fortune 500 companies are using Insight Platform to standardize their deployment processes and make fast and effective capacity planning decisions. \nThis webinar will describe how digital twins are deployed at scale via integration and automated workflows and provide a software demonstration of the proactive capacity planning toolset.
URL:https://marketingeda.com/event/proactive-data-center-management-with-insight-platform/
CATEGORIES:EDA,Webinar
ATTACH;FMTTYPE=image/jpeg:https://marketingeda.com/wp-content/uploads/Cadence-November-7-2023.jpg
END:VEVENT
BEGIN:VEVENT
DTSTART;TZID=America/Los_Angeles:20231101T110000
DTEND;TZID=America/Los_Angeles:20231101T120000
DTSTAMP:20231019T170231Z
CREATED:20231019T170231Z
LAST-MODIFIED:20231019T170231Z
UID:6977-1698836400-1698840000@marketingeda.com
SUMMARY:Warp Speed Gate-Level Simulations with the Xcelium Multi-Core App
DESCRIPTION:Are you ready to lead the way in gate-level digital simulations (GLS)? Dive into Cadence’s exclusive webinar and uncover the revolutionary Xcelium Multi-Core (MC) App—a game changer for GLS\, allowing you to parallelize and expedite simulations like never before. \nWhat You’ll Gain:\nInsight: Understand why the Xcelium MC App is crucial for DV engineers looking to speed up GLS.\nKnowledge: Learn how to deploy the full potential of the Xcelium MC App.\nBest Practices: Discover optimal utilization practices to maximize the efficiency of your gate-level simulations.\nExamples: See the application of the Xcelium MC App\, showcasing how you can simulate GLS at warp speed! \nBenefits: \n\nAchieve 10X faster simulations\, accelerate your aggressive project schedules\nTackle complex billion gate designs with ease\nFully leverage the capacities of modern multi-core CPUs in your server farm\n\nDon’t be left behind! Join us and catapult your GLS to warp speed\, ensuring your projects are not stalled by long pole tests but mastered with precision and efficiency.
URL:https://marketingeda.com/event/warp-speed-gate-level-simulations-with-the-xcelium-multi-core-app/
CATEGORIES:EDA,Webinar
ATTACH;FMTTYPE=image/jpeg:https://marketingeda.com/wp-content/uploads/Cadence-November-1-2023.jpg
END:VEVENT
BEGIN:VEVENT
DTSTART;TZID=America/Los_Angeles:20231101T100000
DTEND;TZID=America/Los_Angeles:20231101T103000
DTSTAMP:20231003T172423Z
CREATED:20231003T172423Z
LAST-MODIFIED:20231003T172423Z
UID:6910-1698832800-1698834600@marketingeda.com
SUMMARY:Mastering the Art of Managing IP\, Chiplets\, and Design Data
DESCRIPTION:Join us on Wednesday\, November 1st\, for an eye-opening exploration of the inadequacy of common design data and IP management capabilities in the face of today’s intricate semiconductor chip designs. Discover the keys to unlocking unparalleled success in your upcoming designs through cutting-edge capabilities and strategies that are reshaping the industry. Don’t miss this exclusive opportunity to revolutionize your approach to semiconductor chip design. \n  \nHere’s what you can learn:\n\nBest practices for efficient chip design data and IP handling.\nCutting-edge IP management strategies for reuse\, security\, and compliance.\nData integration and design flow techniques to enhance collaboration.\n\n  \nBONUS: Design Data and IP Management Best Practices eBook for All Participants! \n  \nWho should attend:\n\nSemiconductor Design and Verification Engineers\nIP Managers and Administrators\nData and tech enthusiasts\nInnovators seeking an edge\nAnyone passionate about chip design excellence\n\nDon’t miss out on this chance to gain a competitive edge in the dynamic world of semiconductor chip design. See you at the webinar!
URL:https://marketingeda.com/event/mastering-the-art-of-managing-ip-chiplets-and-design-data/
CATEGORIES:EDA,IP,Webinar
ATTACH;FMTTYPE=image/jpeg:https://marketingeda.com/wp-content/uploads/Keysight-November-1-2023.jpg
END:VEVENT
BEGIN:VEVENT
DTSTART;TZID=America/Los_Angeles:20231031T100000
DTEND;TZID=America/Los_Angeles:20231031T110000
DTSTAMP:20231013T183201Z
CREATED:20231013T183201Z
LAST-MODIFIED:20231013T183201Z
UID:6956-1698746400-1698750000@marketingeda.com
SUMMARY:Enhance Verification Quality with the Xcelium Mixed-Signal App
DESCRIPTION:The comprehensive verification of analog mixed-signal (AMS) designs has challenges in schedules and implementations due to the vast divergence in design flows of the analog and digital portions of the SoC. These discrepancies include priorities in simulation cycles (accuracy versus performance)\, design methodologies\, and verification of functionality. \nOver multiple decades\, design verification (DV) has evolved towards catching bugs earlier in the design cycles\, allowing an exponential increase in the functionality of SoCs. Extending those improvements to mixed signal is critical for continuous growth. This CadenceTECHTALK goes over many of the silicon-proven approaches enabling it\, and DV engineers will find immense value in the contents. Specifically\, it covers solutions to those challenges in mixed-signal verification (MSV) using the capabilities of the Xcelium Mixed-Signal App. \nWhat attendees will learn: \n\nDevelopment of analog modeling in SystemVerilog using real number modeling (RNM)\nMSV co-sim testbench architecture to allow swapping of models and netlists\nEnhancements of DV regression setup with a hybrid flow that allows for both RNM and co-sim
URL:https://marketingeda.com/event/enhance-verification-quality-with-the-xcelium-mixed-signal-app/
CATEGORIES:EDA,Webinar
ATTACH;FMTTYPE=image/jpeg:https://marketingeda.com/wp-content/uploads/Cadence-October-31-2023.jpg
END:VEVENT
BEGIN:VEVENT
DTSTART;TZID=America/Los_Angeles:20231019T100000
DTEND;TZID=America/Los_Angeles:20231019T110000
DTSTAMP:20231009T170426Z
CREATED:20231009T170426Z
LAST-MODIFIED:20231009T170426Z
UID:6927-1697709600-1697713200@marketingeda.com
SUMMARY:High Reliability and Functional Safety Applications for FPGA
DESCRIPTION:When designing any new system\, safety and reliability are key factors in determining if a system is safe for real-world deployment and if there are sufficient contingency plans for worst case scenarios. This is no different for the designs targeted for FPGAs based deployments. Today\, FPGA based designs are utilized in many safety critical systems in the military\, aerospace\, medical\, industrial\, robotics\, and automotive industries. These systems require meeting stringent safety regulations such as defined by ISO 26262 standard for automotive and the IEC 61508 standard for industrial applications. \nTo address this need\, Synopsys provides a comprehensive family of integrated FPGA verification products. For FPGA synthesis\, Synplify provides the state of the art and most ease-of-use automated features for functional safety and high reliability for FPGA designs. Synplify Synthesis tool can automate design logic insertion at module to register level and as well as provide full features for functional testing and debugging. This includes features such as logic duplication\, triplication\, error flag insertion and fault injection. \nIn this webinar\, we will cover and demonstrate\, how Synplify and Synopsys family of verification products enable users to meet their functional safety and high reliability needs for FPGA based designs. \n\n\n\n\n\n\n\n\n\n\nSpeakers\n\n\nListed below are the industry leaders scheduled to speak. \n\n\n\n\n\n\n\n\n\n\n\n\n\n\n\n\n\n\n\n\n\n\n\n\n\n\nKhalid Khan\n\n\nSenior Staff Applications Engineer\nSynopsys Inc \n\n\n\n\n\n\n\n\n\n\n\nKhalid Khan is a Senior Staff Application Engineer with Synopsys System Design Group based out of Synopsys HQ in Sunnyvale\, CA. He has 20+ years of experience in FPGA Synthesis\, Verification and ASIC Prototyping fields. He is currently the overall lead for the Synplify FPGA synthesis product for field application engineering team in helping define the product road map and strategy. \nHe also helps support many of the major FPGA Synthesis and Prototyping customers in the Silicon Valley region. \n\n\n\n\n\n\n\n\n\n\n\n\n\n\n\n\n\n\n\n\n\n\n\n\n\n\n\n\n\n\n\nDeAndre Hoskins\n\n\nStaff Applications Engineer\nSynopsys Inc \n\n\n\n\n\n\n\n\n\n\n\nDeAndre Hopkins is a Staff Application Engineer based in San Diego\, CA. \nHe has 15+ of experience in FPGA Synthesis and Verification flows. He has extensive background working with Military/Aerospace customers using VHDL and FPGA synthesis flows. He is based out of San Diego\, CA and supports major FPGA accounts in southern CA\, AZ\, NM\, TX regions. \n\n\n\n\n\n\n\n\n\n\n\n\n\n\n\n\n\n\n\n\n\n\n\n\n\n\n\n\n\n\n\nBobby Zuiss\n\n\nSenior Applications Engineer\nSynopsys Inc \n\n\n\n\n\n\n\n\n\n\n\nBobby Zuiss is a Senior Applications Engineer with the Synopsys System Design Group. He has 10+ years of experience with FPGA Synthesis products. He is based out of Los Angeles\, CA. He has experience working with FPGAs in both Defense and High Speed Trading industries. He supports major Military/Aerospace accounts in Southern CA\, CO\, & UT.
URL:https://marketingeda.com/event/high-reliability-and-functional-safety-applications-for-fpga/
CATEGORIES:EDA,Webinar
ATTACH;FMTTYPE=image/jpeg:https://marketingeda.com/wp-content/uploads/Synopsys-October-19-2023.jpg
END:VEVENT
BEGIN:VEVENT
DTSTART;TZID=America/New_York:20231018T100000
DTEND;TZID=America/New_York:20231018T104500
DTSTAMP:20231008T235227Z
CREATED:20231008T235227Z
LAST-MODIFIED:20231008T235227Z
UID:6922-1697623200-1697625900@marketingeda.com
SUMMARY:System-Level Thermal Signoff from Chips Through to Racks
DESCRIPTION:Today’s modern electronic designs require ever more functionality and performance to meet consumer demand. These challenges become more critical and complex when resistive losses in PCB and package structures are significant since resistive losses are temperature dependent. In this webinar\, we will look at an electrothermal co-simulation solution for the full hierarchy of electronic systems from ICs to physical enclosures using Cadence’s Celsius technologies. By combining finite-element analysis (FEA) for solid structures with computational fluid dynamics (CFD) for both liquid and gas\, as well as airflow\, designers can perform complete system analysis in a single tool. The combined workflow that ties the Celsius Thermal Solver with the Celsius EC electronic cooling solver provides even higher accuracy and faster simulation time in the modeling of electronics equipment.  \n\n\n\nSpeakers\n\n\n\n\nDr. Melika Roshandell\nProduct Marketing Director\nCadence\n\n\nDr. Melika Roshandell is product marketing director for Celsius Thermal Solver software at Cadence. Prior to Cadence she held positions as a system on chip (SoC) thermal engineer at Qualcomm for nine years and thermal engineer at Broadcom for two years. Dr. Roshandell earned her BS in mechanical engineering at the University of California\, San Diego\, and her MS and PhD in mechanical engineering at the University of California\, Irvine. \n\n\n\n\n\nKarthick Gopalakrishnan\nProduct Engineer\nCadence\n\n\nKarthick Gopalakrishnan is a product engineer at Cadence supporting the Celsius line of electrothermal analysis products. Prior to joining Cadence\, he was a thermal/CFD application engineer at Mentor Graphics. Karthick holds an MS in mechanical engineering from the North Carolina State University\, where he specialized in thermal and fluid sciences.
URL:https://marketingeda.com/event/system-level-thermal-signoff-from-chips-through-to-racks/
CATEGORIES:EDA,Webinar
ATTACH;FMTTYPE=image/jpeg:https://marketingeda.com/wp-content/uploads/Cadence-October-18-2023-1.jpg
END:VEVENT
BEGIN:VEVENT
DTSTART;TZID=America/Los_Angeles:20231018T083000
DTEND;TZID=America/Los_Angeles:20231018T091500
DTSTAMP:20230928T182610Z
CREATED:20230928T182610Z
LAST-MODIFIED:20230928T182610Z
UID:6900-1697617800-1697620500@marketingeda.com
SUMMARY:Soar to New Heights of Productivity using Cadence Managed Cloud Services
DESCRIPTION:Date: Wednesday\, October 18\, 2023 \nTime: 8:30am PT | 10:30am CT | 11:30am ET \n\n\n\n\n\n\n\n\n\n\n\n\nJoin us for this 45-minute webinar to learn how the Cadence-managed\, EDA-optimized\, ready-to-use\, and secure ISO-certified cloud platform delivers a fully integrated and proven environment to jump-start product design\, verification\, and implementation. See the platform in action as we demo the productivity features of Cadence’s digital and analog design flows. \n\n\n\n\n\n\n\n\n\n\n\n\nWhat You Will Learn \n\n\n\n\n\n\n\n\n\n\n\n\n\nHow hundreds of customers have accelerated their design\, verification\, and implementation projects\, whether for full or partial design flow in the cloud\nHow the cloud can solve your peak capacity needs\, driving faster tapeouts and time-to-market\nHow to request compute hosts and access Rapid Adoption Kits (RAKs) in the cloud for interactive and batch jobs utilizing Virtuoso and Xcelium\nHow to request a free 30-day evaluation of the environment\n\n\n\n\n\n\n\n\n\n\n\n\n\nWho Should Attend \n\n\n\n\n\n\n\n\n\n\n\n\nThis webinar will be useful for: \n\nDesign/Verification engineers\nIT/Cloud Architects\nTechnical/Business Decision Makers\n\n\n\n\n\n\n\n\n\n\n\n\n\nSpeakers: \n\n\n\n\n\n\n\nKetan Joshi\nSr. Group Director\, Cloud Team\, Cadence \n\n\n\n\n\n\n\n\n\n\n\n\nMike Stanton\nGroup Director\, IT\, Cadence
URL:https://marketingeda.com/event/soar-to-new-heights-of-productivity-using-cadence-managed-cloud-services/
CATEGORIES:EDA,Webinar
ATTACH;FMTTYPE=image/jpeg:https://marketingeda.com/wp-content/uploads/Cadence-cloud-October-18-2023.jpg
END:VEVENT
BEGIN:VEVENT
DTSTART;TZID=Europe/London:20231017T120000
DTEND;TZID=Europe/London:20231017T130000
DTSTAMP:20230925T185357Z
CREATED:20230925T185357Z
LAST-MODIFIED:20230925T185357Z
UID:6869-1697544000-1697547600@marketingeda.com
SUMMARY:DVClub Europe - AI/ML in Verification
DESCRIPTION:This is to inform you that the next DVClub Europe meeting takes place on Tuesday 17th October with a theme of “AI/ML in Verification”.\n\nThis DVClub consider how we can save time and effort whilst improving time-to-market through the application of AI/ML to verification.\n\nAgenda (BST) \n12:00   Welcome and Introduction – Mike Bartley\, Senior Vice President – VLSI Design\, Tessolve \n12:00   Rajendra Prasad\, Infineon – Smart Adaptive Regression using Nearest Neighbour Algorithm \n12:45    Daniel Hansson\, Cadence Design System – \n13:00    Close \n  \nRegister now to become a part of this event. Free to attend online. \nEventbrite – DVClub Europe  \nBest Regards \nMike Bartley\, Senior Vice President – VLSI Design\, Tessolve
URL:https://marketingeda.com/event/dvclub-europe-ai-ml-in-verification/
CATEGORIES:EDA,Webinar
ATTACH;FMTTYPE=image/jpeg:https://marketingeda.com/wp-content/uploads/DVClub-17-October-2023.jpg
END:VEVENT
BEGIN:VEVENT
DTSTART;TZID=America/Los_Angeles:20231012T100000
DTEND;TZID=America/Los_Angeles:20231012T110000
DTSTAMP:20230918T184234Z
CREATED:20230918T184234Z
LAST-MODIFIED:20230918T184234Z
UID:6811-1697104800-1697108400@marketingeda.com
SUMMARY:The UCIe™ 1.1 Specification: Future Applications of Chiplets
DESCRIPTION:Presenter: Dr. Debendra Das Sharma\, UCIe Consortium Chairman and Intel Senior Fellow\, Chief Architect of I/O Technology and Standards at Intel  \n\n\nThe UCIe™ (Universal Chiplet Interconnect Express™) 1.1 Specification was released in August 2023\, delivering valuable improvements to the chiplet ecosystem\, extending reliability mechanisms to more protocols and supporting broader usage models. This webinar will provide an overview on enhancements made in the UCIe 1.1 specification and architectural specification attributes to define system setups and registers that will be used in test plans and compliance testing to ensure device interoperability. The presentation will also explore additional enhancements included for automotive usages – such as predictive failure analysis and health monitoring – and enabling lower-cost packaging implementations. Attendees will have a chance to participate in a live Q&A discussion immediately after the webinar to address questions from the presentation. 
URL:https://marketingeda.com/event/the-ucie-1-1-specification-future-applications-of-chiplets/
CATEGORIES:IP,Webinar
ATTACH;FMTTYPE=image/jpeg:https://marketingeda.com/wp-content/uploads/UCIe-October-12-2023.jpg
END:VEVENT
BEGIN:VEVENT
DTSTART;TZID=America/Los_Angeles:20231012T100000
DTEND;TZID=America/Los_Angeles:20231012T110000
DTSTAMP:20230908T182145Z
CREATED:20230908T182145Z
LAST-MODIFIED:20230908T182145Z
UID:6786-1697104800-1697108400@marketingeda.com
SUMMARY:Proactively Address Thermal Concerns in Advanced IC Packages
DESCRIPTION:The heterogeneous integration of chips and chiplets in IC packages is all the rage as we face “More than Moore” performance challenges. While these innovative design practices successfully address performance goals\, some design teams find that IC packages may overheat if they do not carefully plan for heat dissipation. \nThis webinar will show how design teams that implement thermal mitigation strategies early in the design cycle are facing fewer thermal concerns with their IC package prototypes.  We will walk through a reference design and discuss how Cadence Advanced Package Designer Plus combined with Celsius Thermal Solver address feasibility during the design planning stage to the full-system final signoff. \nJoin our webinar to learn how you can: \n\nEfficiently address thermal concerns throughout the design cycle\nReduce design iterations\nProactively drive predictability into your design schedules
URL:https://marketingeda.com/event/proactively-address-thermal-concerns-in-advanced-ic-packages/
CATEGORIES:EDA,IP,Webinar
ATTACH;FMTTYPE=image/jpeg:https://marketingeda.com/wp-content/uploads/Cadence-October-12-2023.jpg
END:VEVENT
BEGIN:VEVENT
DTSTART;TZID=America/Los_Angeles:20231011T090000
DTEND;TZID=America/Los_Angeles:20231011T100000
DTSTAMP:20231006T190044Z
CREATED:20231006T190044Z
LAST-MODIFIED:20231006T190044Z
UID:6919-1697014800-1697018400@marketingeda.com
SUMMARY:Mapping signal processing algorithms on AMD-Xilinx Versal to meet timing and power constraints
DESCRIPTION:In this Webinar\, we will focus on the performance-power-area trade-off in implementing signal processing algorithms on Xilinx FPGA by partitioning the tasks of the algorithms onto the processors\, logic and AI Engines resident in the AMD-Xilinx Versal FPGA.  \n\n Key Takeaways: \n\nDiscover the inner workings of FPGA components: Processor\, Logic Elements\, AIE/Tensor\, and more.\nUnderstand latency and throughput trade-offs when using NoC vs. direct interfaces.\nLearn how different data cache sizes impact AIE Tile network utilization.\nDive into various mapping decisions and their effect on application throughput and power consumption.\n\n  \nSo\, what are you waiting for? Don’t miss this opportunity
URL:https://marketingeda.com/event/mapping-signal-processing-algorithms-on-amd-xilinx-versal-to-meet-timing-and-power-constraints/
CATEGORIES:EDA,IP,Webinar
ATTACH;FMTTYPE=image/jpeg:https://marketingeda.com/wp-content/uploads/Mirabilis-October-11-2023.jpg
END:VEVENT
BEGIN:VEVENT
DTSTART;TZID=America/Los_Angeles:20231005T110000
DTEND;TZID=America/Los_Angeles:20231005T120000
DTSTAMP:20230801T173224Z
CREATED:20230801T173224Z
LAST-MODIFIED:20230801T173224Z
UID:6644-1696503600-1696507200@marketingeda.com
SUMMARY:FPGA Design Verification - Advanced Methods
DESCRIPTION:Abstract \nAs FPGA technology continues to evolve – to provide us with full-blown SoCs with CPU\, GPU\, and high-speed peripherals\, for example\, joining the traditional programmable logic area – design verification becomes increasingly challenging. Lab-based FPGA testing and bring-up alone are clearly insufficient\, especially for safety-critical designs\, and FPGA teams are adopting advanced design verification methodologies and techniques to develop homegrown verification processes. \n  \nIn this three-part webinar series\, we will discuss design verification with a focus on creating an advanced simulation-based verification process; from verification planning and team organization\, and moving on to regression setup\, functional coverage collection\, randomization and ‘verification done’ definitions. We will also show you how to develop simple yet powerful and reusable testbenches using Verilog and SystemVerilog constructs and how to functionally verify designs in the most efficient way. \n  \nIn this\, the concluding episode of the webinar series\, we will present advanced verification solutions for verifying complex design properties. We will talk about randomization\, functional coverage\, and the importance of code coverage to achieve overall design verification completeness. Also\, we will provide an overview on other important topics such as assertion and transaction-based verification and debug\, static design verification with linting tools and regressions support. Finally\, we will talk about ‘Verification Done’\, in terms of at what point can the verification be considered complete and how do we achieve it? \n  \nAgenda: \n\nCheckers and Scoreboards Development\nRandomization Methods\nFunctional Coverage and Tests Grading\nCode Coverage\nAssertion-based Verification\nTransaction-based Debugging with Riviera-PRO\nStatic Verification with Linting tools\nSetting up Regressions\nDefining “Verification Done”\nPacket-based Design Verification Example\nConclusion\nQ&A\n\n  \nWebinar Duration: \n\n45 min presentation/live demo\n15 min Q&A\n\n  \nPresenter BIO \nAlexander Gnusin\, Design Verification Technologist\, Aldec \nAlexander Gnusin accumulated 27 years of hands-on experience in various aspects of ASIC and FPGA design and verification. As a verification prime for a multi-million gates project in companies such as IBM\, Nortel\, Ericsson and Synopsys Inc\, he combined various verification methods such as static linting\, formal property checking\, dynamic simulation and hardware-assisted acceleration to efficiently achieve design verification goals. He received his M.S. in Electronics from Technion\, Israel Institute of Technology.
URL:https://marketingeda.com/event/fpga-design-verification-advanced-methods/
CATEGORIES:EDA,Webinar
ATTACH;FMTTYPE=image/jpeg:https://marketingeda.com/wp-content/uploads/Aldex-Verification.jpg
END:VEVENT
BEGIN:VEVENT
DTSTART;TZID=America/Los_Angeles:20231004T110000
DTEND;TZID=America/Los_Angeles:20231004T120000
DTSTAMP:20230921T172330Z
CREATED:20230921T172330Z
LAST-MODIFIED:20230921T172330Z
UID:6855-1696417200-1696420800@marketingeda.com
SUMMARY:Verisium Debug for UVM Testbench
DESCRIPTION:Verisium Debug offers comprehensive debugging capabilities. From RTL and UVM testbench to UPF low-power designs\, Cadence’s unified debugging platform helps users debug. In this webinar\, users will learn about the available features in Verisium Debug for UVM testbench and use these unique capabilities to visualize and debug the UVM testbench. \nWhat you will learn \n\nUnderstand the features available in Verisium Debug\n​Learn about the UVM debug capabilities in Verisium Debug\nLearn to debug UVM testbench using Verisium Debug\n\nWho should attend \n\nDesign engineers\nVerification engineers\nCAD engineers
URL:https://marketingeda.com/event/verisium-debug-for-uvm-testbench/
CATEGORIES:EDA,Webinar
ATTACH;FMTTYPE=image/jpeg:https://marketingeda.com/wp-content/uploads/Cadence-October-4-2023.jpg
END:VEVENT
BEGIN:VEVENT
DTSTART;TZID=America/Los_Angeles:20230928T110000
DTEND;TZID=America/Los_Angeles:20230928T120000
DTSTAMP:20230801T173012Z
CREATED:20230801T172957Z
LAST-MODIFIED:20230801T173012Z
UID:6642-1695898800-1695902400@marketingeda.com
SUMMARY:FPGA Design Verification - Advanced Testbench Implementation
DESCRIPTION:Abstract \nAs FPGA technology continues to evolve – to provide us with full-blown SoCs with CPU\, GPU\, and high-speed peripherals\, for example\, joining the traditional programmable logic area – design verification becomes increasingly challenging. Lab-based FPGA testing and bring-up alone are clearly insufficient\, especially for safety-critical designs\, and FPGA teams are adopting advanced design verification methodologies and techniques to develop homegrown verification processes. \n  \nIn this three-part webinar series\, we will discuss design verification with a focus on creating an advanced simulation-based verification process; from verification planning and team organization\, and moving on to regression setup\, functional coverage collection\, randomization and ‘verification done’ definitions. We will also show you how to develop simple yet powerful and reusable testbenches using Verilog and SystemVerilog constructs and how to functionally verify designs in the most efficient way. \n  \nIn part 2 of this webinar series\, we will show you important verification patterns providing solutions to repeatable randomization\, error management and end-of-test checks. We will also provide an overview of how to define\, develop and re-use verification components such as drivers\, responders\, and monitors. Then\, we will talk about how to develop testbenches\, and how to validate their correctness with reporting and statistics collection. We will provide code examples to illustrate the topics of discussion. \n  \nAgenda: \n\nCommon Verification Patterns:\no Repeatable Randomization\no Reporting\, Error management\no End-of-Test Procedure\nVerification Components (VC) Development:\no Verification Component Types\no Defining Transactions for VC Development\no Legal and Error Operation Modes\no Controllable Randomization\no Verification in Standalone Testbenches\nTestbench Development and Verification:\no Statistical methods for Testbench Validation\no Scripting Support\nDemo with example design and testbench\nConclusion\nQ&A\n\n  \nWebinar Duration: \n\n45 min presentation/live demo\n15 min Q&A\n\n  \nPresenter BIO \nAlexander Gnusin\, Design Verification Technologist\, Aldec \nAlexander Gnusin accumulated 27 years of hands-on experience in various aspects of ASIC and FPGA design and verification. As a verification prime for a multi-million gates project in companies such as IBM\, Nortel\, Ericsson and Synopsys Inc\, he combined various verification methods such as static linting\, formal property checking\, dynamic simulation and hardware-assisted acceleration to efficiently achieve design verification goals. He received his M.S. in Electronics from Technion\, Israel Institute of Technology.
URL:https://marketingeda.com/event/fpga-design-verification-advanced-testbench-implementation/
CATEGORIES:EDA,Webinar
ATTACH;FMTTYPE=image/jpeg:https://marketingeda.com/wp-content/uploads/Aldex-Verification.jpg
END:VEVENT
BEGIN:VEVENT
DTSTART;TZID=America/Los_Angeles:20230927T120000
DTEND;TZID=America/Los_Angeles:20230927T130000
DTSTAMP:20230818T231020Z
CREATED:20230818T231020Z
LAST-MODIFIED:20230818T231020Z
UID:6732-1695816000-1695819600@marketingeda.com
SUMMARY:Stratus HLS Automated Power Shutoff to Minimize Power and Retention Registers
DESCRIPTION:Power Shutoff is a popular technique for saving power during functionally idle periods. Implementing Power Shutoff requires a detailed understanding of which resisters must be retained to enable bring-up from the power-off state. Identifying the minimal set of retention registers is challenging and grows more difficult with design complexity. \n\nThis CadenceTECHTALK introduces a novel High-Level Synthesis-based solution for the automated implementation of Power Shutoff. This solution automatically identifies and implements Power Shutoff using the minimal set of retention registers\, yielding the lowest leakage power and saving weeks of implementation time vs. manual methods. \n\nJoin this webinar to learn how to apply this technology to your own design and interact with product experts who will demonstrate the technology in a real-world testcase. Design engineers working on low-power digital IC designs or algorithms will benefit from this TECHTALK.
URL:https://marketingeda.com/event/stratus-hls-automated-power-shutoff-to-minimize-power-and-retention-registers/
CATEGORIES:EDA,Webinar
ATTACH;FMTTYPE=image/jpeg:https://marketingeda.com/wp-content/uploads/Cadence-September-27-2023.jpg
END:VEVENT
BEGIN:VEVENT
DTSTART;TZID=America/New_York:20230927T100000
DTEND;TZID=America/New_York:20230927T110000
DTSTAMP:20230913T184118Z
CREATED:20230913T184118Z
LAST-MODIFIED:20230913T184118Z
UID:6792-1695808800-1695812400@marketingeda.com
SUMMARY:Cadence Training: Cerebrus Intelligent Chip Explorer
DESCRIPTION:Please join me\, Cadence Training and Application Engineer Krishna Atreya\, for this free technical Training Webinar. \nWhat Is the Webinar About?\nThe Cadence Cerebrus Intelligent Chip Explorer is a revolutionary\, machine learning-driven\, automated approach to chip design flow optimization. Block engineers specify the design goals\, and Cadence Cerebrus intelligently optimizes the Cadence digital full flow to meet power\, performance\, and area (PPA) goals in a completely automated way—letting engineers concurrently optimize multiple block flows\, which is particularly important for the large\, complex system-on-chip (SoC) designs needed for today’s ever more powerful electronic systems. \nWe’ll dive into: \n\nUnderstanding the Cadence Cerebrus flows\nUnderstanding flow wrapping\nFlow wrapping your design for Cadence Cerebrus readiness\n\nWhen Is the Webinar?\nWednesday\, September 27 \n07:00 PDT San Jose / 10:00 EDT New York / 15:00 BST London / 16:00 CEST Berlin / 17:00 IDT Jerusalem / 19:30 IST Bangalore / 22:00 CST Beijing \nTo register for the “Flow Wrapping: The Cadence Cerebrus Intelligent Chip Explorer Must Have” webinar\, use the REGISTER button below and sign in with your Cadence Support account (email ID and password) to log in to the Learning and Support System. Then select Enroll to register for the session. Once registered\, you’ll receive a confirmation email containing all login details. \nREGISTER \nIf you don’t have a Cadence Support account\, go to Registration Help or Cadence User Registration\, and complete the requested information. \nFor questions and inquiries or issues with registration\, reach out to eur_training@cadence.com \nKeep up with the revolution! Join Cadence’s Cerebrus Intelligent Chip Explorer Training and learn how to use Cadence Cerebrus to scale and automate your design\, improve your productivity\, and much more. \nThe online class is free for all Cadence customers with a Learning and Support account. \nWe can also organize this Cadence Cerebrus Intelligent Chip Explorer Training for you as a “Blended” or “Live” training. Please reach out to Cadence Training for further information. \nYou can also enjoy this video to get a first impression what is waiting for you! \nWant to share this and other great Cadence learning opportunities with someone else? Tell them to subscribe. \nHungry for Training?\nChoose the Cadence Training Menu that’s right for you. To view our complete training offerings\, visit the Cadence Training website.
URL:https://marketingeda.com/event/cadence-training-cerebrus-intelligent-chip-explorer/
CATEGORIES:EDA,Webinar
ATTACH;FMTTYPE=image/jpeg:https://marketingeda.com/wp-content/uploads/Cadence-September-27-2023-2.jpg
END:VEVENT
BEGIN:VEVENT
DTSTART;TZID=America/Los_Angeles:20230927T090000
DTEND;TZID=America/Los_Angeles:20230927T130000
DTSTAMP:20230919T171317Z
CREATED:20230919T171317Z
LAST-MODIFIED:20230919T171317Z
UID:6829-1695805200-1695819600@marketingeda.com
SUMMARY:Synopsys VSO.ai Virtual Workshop
DESCRIPTION:Virtual workshop with hands-on labs \nAchieving coverage closure continues to remain a challenge for customers and there is a growing need for a system to work autonomously to reach the target as quickly and cheaply as possible with the highest quality of results. The recently released Synopsys VSO.ai address this challenge in addition to inferring coverage from RTL and finding bugs. \nIn this hands-on half day virtual workshop you will learn: \nThe different components of Synopsys VSO.ai\nThe value proposition demonstrated at customers\nUpcoming technologies \nThese technologies are natively integrated with VCS\, the industry performance leader\, and will be presented by Synopsys Verification experts.\nAttendees will gain hands-on experience in live labs and walk away with the confidence to use this technology in your current projects. Lab participation will be limited. \nWorkshop Agenda\nPacificTime \n\n\n\nTime\nSession\n\n\n9:00 – 9:15 a.m.\nOverview of coverage closure\n\n\n9:15 – 10:00 a.m.\nRegression optimization\n\n\n10:00 – 10:45 a.m.\nLab 1\n\n\n10:45 – 11:00 a.m.\nBreak\n\n\n11:00 – 11:45 a.m.\nCoverage directed solver\n\n\n11:45 a.m. – 12:30 p.m.\nLab 2\n\n\n12:30 – 12:45 p.m.\nRoadmap\n\n\n12:45 – 1:00 p.m.\nWrap-up + Q&A
URL:https://marketingeda.com/event/synopsys-vso-ai-virtual-workshop/
CATEGORIES:EDA,Webinar
ATTACH;FMTTYPE=image/jpeg:https://marketingeda.com/wp-content/uploads/Synopsys-September-27-2023.jpg
END:VEVENT
BEGIN:VEVENT
DTSTART;TZID=America/Los_Angeles:20230926T100000
DTEND;TZID=America/Los_Angeles:20230926T110000
DTSTAMP:20230921T161238Z
CREATED:20230921T161238Z
LAST-MODIFIED:20230921T161238Z
UID:6847-1695722400-1695726000@marketingeda.com
SUMMARY:Unleashing Innovation with UCIe​​​​​​​​​​​​​​
DESCRIPTION:Exploring the Next Frontier in Chip Integration\nWebinar Agenda : \n\nIntroduction to all UCIe layers\nDecrypting FLITs\, PHY Trainings\, Bring up flows FDI-RDI \, main band and side band FLIT transfers etc.\nImplementation of Stacks-Arbiter\, Retry mechanism & Retimer implementations\nShowcasing UCie FLIT transfer flow between multidies\nEnhancements done in UCIe 1.1\n\nWho Should Attend: \n\nProfessionals working on development of UCIe VIP.\nPeople keen to know how UCie VIP is shaping new era of chiplet communications\nFreshers in the field of VLSI industry.
URL:https://marketingeda.com/event/unleashing-innovation-with-ucie/
CATEGORIES:IP,Webinar
ATTACH;FMTTYPE=image/jpeg:https://marketingeda.com/wp-content/uploads/Truechip-September-26-2023.jpg
END:VEVENT
BEGIN:VEVENT
DTSTART;TZID=Asia/Kolkata:20230924T093000
DTEND;TZID=Asia/Kolkata:20230924T113000
DTSTAMP:20230921T165532Z
CREATED:20230921T165023Z
LAST-MODIFIED:20230921T165532Z
UID:6850-1695547800-1695555000@marketingeda.com
SUMMARY:Applications of Formal Verification
DESCRIPTION:It is an exciting time to explore a career in the VLSI semiconductor sector\, and we’re here to help you gain clarity on buzz and provide information on educational options towards a successful entry to this field with long-term career prospects. \nDesign Verification is one of the essential and most promising career options. In the upcoming free live webinar\, we discuss one critical verification aspect – formal verification. \nJoin us for this session on\n24th Sep Sunday from 9:30 am to 11:30 am IST.\nThe link to register is \nhttps://lnkd.in/gZiFUddW \nThe webinar is brought to you by Semiconductor Nation – Campus ConnectTM platform of FutureSkills by India Electronics and Semiconductor Association and metavlsi \nAttend this free live webinar all about the applications of Formal Verification for SoC design\, presented by VLSI Deep Dive. \nThe webinar is two hours in length and uses Google Meet. \nWe are on a mission to inspire and develop people to achieve their goals in professional life. We enable people to learn deeply through bite-sized\, interactive learning experiences. Our courses are structured and designed by leading experts in their respective fields.
URL:https://marketingeda.com/event/applications-of-formal-verification/
CATEGORIES:EDA,Webinar
ATTACH;FMTTYPE=image/jpeg:https://marketingeda.com/wp-content/uploads/VLSI-Deep-Dive-September-24th-2023.jpg
END:VEVENT
BEGIN:VEVENT
DTSTART;TZID=America/Los_Angeles:20230921T110000
DTEND;TZID=America/Los_Angeles:20230921T120000
DTSTAMP:20230908T171723Z
CREATED:20230908T171723Z
LAST-MODIFIED:20230908T171723Z
UID:6783-1695294000-1695297600@marketingeda.com
SUMMARY:UCIe-Based Chiplet Verification - from IP to SoC
DESCRIPTION:Innovative die disaggregation technologies\, enable a future where a catalog of chiplets will be available to mix and match based on the end application. The industry’s fastest emerging interconnect standard called Universal Chiplet Interconnect Express (UCIe) enables end users to combine chiplets with different functionality and technology nodes to develop highly sophisticated electronic chips. Hence\, the verification topologies of such designs have exponentially increased. \nIn this webinar\, we will explore challenges and effective solutions to optimize effort and improve productivity in the verification using “Chiplet-like” reusable verification components. This caters to all possible topologies enabling continuous verification from IP to Subsystem and finally\, at the system-level.
URL:https://marketingeda.com/event/ucie-based-chiplet-verification-from-ip-to-soc-2/
CATEGORIES:EDA,IP,Webinar
ATTACH;FMTTYPE=image/jpeg:https://marketingeda.com/wp-content/uploads/Cadence-September-21-2023.jpg
END:VEVENT
BEGIN:VEVENT
DTSTART;TZID=America/Los_Angeles:20230921T100000
DTEND;TZID=America/Los_Angeles:20230921T110000
DTSTAMP:20230920T184452Z
CREATED:20230920T184452Z
LAST-MODIFIED:20230920T184452Z
UID:6841-1695290400-1695294000@marketingeda.com
SUMMARY:Efficient Bluespec RISC-V Processor Verification for Highest Coverage Closure: A Comprehensive Case Study
DESCRIPTION:The ability to mix and match multiple ISA extensions and add user-defined ISA extensions makes RISC-V verification more challenging than conventional processor verification. This Synopsys webinar demonstrates the verification of standard RISC-V ISA extensions. A subsequent webcast will demonstrate custom ISA verification. The multiple ISA verification problem is solved by RISCV-DV with configurability for ISA specific test generation. RISCV-DV addresses the generation of ISA specific tests in one pass of simulation using Synopsys VCS® as the efficient constraint solver for instruction generation using constraint random methodology. The tests consist of valid instruction sequences (programs) for the target ISA of the processor core under verification. The generated programs are run on the Bluespec processor core simulated with Synopsys VCS and the results are compared with Spike instruction set simulation (ISS) results. \n  \nThis presentation will showcase: \n\nA reference methodology for verifying a Bluespec RV32IMC MCU-X processor core based on RISCV-DV.\nHow designers can leverage Synopsys VCS simulation and Synopsys Verdi® for debug and relevant advanced coverage methodology\, to help speed verification signoff.\nThe combination of RISCV-DV and Synopsys tools provides a powerful and flexible solution for RISC-V verification and highest coverage.\nDemo on the RISC-V verification solution on the Synopsys Cloud platform.\n\nWhether you are a chip verification architect or a verification engineer or a system designer\, this Synopsys webinar will provide valuable insights into how to set up a constraint random verification solution for a RISC-V processor to achieve the highest coverage. \n\n\n\n\n\n\n\n\n\n\nSpeakers\n\n\nListed below are the industry leaders scheduled to speak. \n\n\n\n\n\n\n\n\n\n\n\n\n\n\n\n\n\n\n\n\n\n\n\n\n\n\nBipul Talukdar\n\n\nSenior Director\, Applications Engineering\nBluespec \n\n\n\n\n\n\n\n\n\n\n\nBipul Talukdar is Senior Director of Applications Engineering for Bluespec Inc. He is an expert in hardware functional verification with a specialty in verification IP (VIP) development\, formal property verification\, and hardware emulation. He leads Application Engineering and Support for Bluespec. Bipul has a strong background in formal verification of RISC-V based cores/subsystems\, arm based cores/subsystems and coverage-based closure. His previous engineering roles at SiFive\, Cadence\, Mentor Graphics (Siemens) and SmartDV Technologies give him a broad perspective on the myriad challenges faced by design and verification teams\, allowing him to partner with customers for success throughout product evaluations and deployment. Bipul holds a Bachelor of Science in Engineering\, Electronics\, and Telecommunication from India’s National Institute of Technology\, Silchar. He is based in San Jose\, California. \n\n\n\n\n\n\n\n\n\n\n\n\n\n\n\n\n\n\n\n\n\n\n\n\n\n\n\n\n\n\n\nPrabha Krishnaswami\n\n\nApplications Engineer\, Senior Staff\nSynopsys \n\n\n\n\n\n\n\n\n\n\n\nPrabha Krishnaswami is an Application Engineer at Synopsys\, focusing on VCS and Verdi products. She also collaborates with the global RISC-V customers to showcase the Synopsys RISC-V solution. She has a background in design and verification with expertise in SoCs and subsystems. Prabha likes music\, reading and enjoys long walks.
URL:https://marketingeda.com/event/efficient-bluespec-risc-v-processor-verification-for-highest-coverage-closure-a-comprehensive-case-study/
CATEGORIES:EDA,IP,Webinar
ATTACH;FMTTYPE=image/jpeg:https://marketingeda.com/wp-content/uploads/Synopsys-September-21-2023.jpg
END:VEVENT
BEGIN:VEVENT
DTSTART;TZID=America/Los_Angeles:20230921T090000
DTEND;TZID=America/Los_Angeles:20230921T100000
DTSTAMP:20230911T162325Z
CREATED:20230911T162325Z
LAST-MODIFIED:20230911T162325Z
UID:6789-1695286800-1695290400@marketingeda.com
SUMMARY:QuantumATK V-2023.09 Release: Highlights of New and Enhanced Features
DESCRIPTION:Join our FREE online event to learn about the new and enhanced features and performance improvements in the latest QuantumATK V-2023.09 product release. \n– Enhanced ease-of-use of training Machine-Learned FFs with new predefined Workflow Builder blocks and templates \n– New interactive Interfaces Builder for building multilayer structures \n– New Accelerated molecular dynamics method for crystallization \n– New Thermochemistry pyrolysis tools to predict gas phase composition in surface processing – Integrated Charged point defect and defect diffusion simulation frameworks \n– Major speedup in bandstructure simulations with Tight Binding models for up to million atoms \n– Efficient and simplified deformation potential extraction for large nanostructures to evaluate electron-phonon coupling \n– New analysis of spectral and thermal current/conductance in Transmission Analyzer \n– More interactive IV Characteristics Analyzer and possibility to analyze inelastic current \n– New Finite Bias Spin Transfer Torque (STT) Study Object & Analyzer to evaluate the write performance of STT-MRAM \n– New Heisenberg Exchange Analyzer for exchange couplings and Curie temperature \nSynopsys Webinar Speakers: \n– Mattias Palsgaard\, Senior Applications Engineer\, Synopsys QuantumATK \n– Vaida Arcisauskaite\, Senior Applications Engineer\, Synopsys QuantumATK \n– Bo Lu\, Senior R&D Engineer\, Synopsys QuantumATK \nLearn more about the new QuantumATK V-2023.09 release here: https://www.synopsys.com/manufacturing/quantumatk/resources/release-notes.html \nYou are welcome to ask questions throughout the webinar or at the end during the Q&A session. Contact us for more information at quantumatk@synopsys.com.
URL:https://marketingeda.com/event/quantumatk-v-2023-09-release-highlights-of-new-and-enhanced-features/
CATEGORIES:EDA,Webinar
ATTACH;FMTTYPE=image/png:https://marketingeda.com/wp-content/uploads/Synopsys-September-21-2023.png
END:VEVENT
BEGIN:VEVENT
DTSTART;TZID=America/Los_Angeles:20230920T100000
DTEND;TZID=America/Los_Angeles:20230920T110000
DTSTAMP:20230919T164805Z
CREATED:20230919T164516Z
LAST-MODIFIED:20230919T164805Z
UID:6825-1695204000-1695207600@marketingeda.com
SUMMARY:Maximize Design Productivity using Vivado ML with SystemVerilog
DESCRIPTION:Although SystemVerilog is perhaps most widely used in the context of hardware verification\, it also contains many features directly relevant to FPGA hardware designers. We explore the features of SystemVerilog that are useful for RTL synthesis using Vivado™ ML Editions from AMD\, showing how the RTL SystemVerilog language constructs have been optimized for productivity and reliability. \nWe start from the basic principles of RTL coding style in SystemVerilog\, then focus on the language features that allow FPGA hardware designers to work very efficiently while at the same time avoiding synthesis pitfalls. \nContent Summary: \n\nIntroduction\nSystemVerilog in Vivado ML Editions\nModules\, ports\, parameters\, and hierarchy\nCombinational and clocked logic\nAssignments and procedures\nControl constructs and operators\nHardware-oriented data types including packages\nInterfaces and Modports\n\n\n \nMike Smith – Doulos Certified Training Instructor\, will be presenting this training webinar\, which will consist of a one-hour session and will be interactive with Q&A participation from attendees. \n\nAttendance is free of charge \nIf you have any queries\, please contact webinars@doulos.com
URL:https://marketingeda.com/event/maximize-design-productivity-using-vivado-ml-with-systemverilog/
CATEGORIES:EDA,Webinar
ATTACH;FMTTYPE=image/jpeg:https://marketingeda.com/wp-content/uploads/Doulos-September-20-2023.jpg
ORGANIZER;CN="Doulos":MAILTO:webinars@duolos.com
END:VEVENT
BEGIN:VEVENT
DTSTART;TZID=America/Los_Angeles:20230912T100000
DTEND;TZID=America/Los_Angeles:20230912T110000
DTSTAMP:20230829T220653Z
CREATED:20230829T220628Z
LAST-MODIFIED:20230829T220653Z
UID:6759-1694512800-1694516400@marketingeda.com
SUMMARY:NoC IP- Transforming Chip Communication
DESCRIPTION:Webinar Agenda : \n\nIntroduction to Mesh and Crossbar Architecture\nCache Introduction\nSupport for latest AMBA 5\nSafety and security features as ASIL Standard.\nPort configurabilities\n\nWho Should Attend: \n\nProfessionals working on development of NoC IP.\nPeople keen to know how NoC IP is shaping new era of chiplet communications\nFreshers in the field of VLSI industry.
URL:https://marketingeda.com/event/noc-ip-transforming-chip-communication/
CATEGORIES:IP,Webinar
ATTACH;FMTTYPE=image/jpeg:https://marketingeda.com/wp-content/uploads/Webinar-Series-NoC-IP-01_02.jpg
END:VEVENT
BEGIN:VEVENT
DTSTART;TZID=America/Los_Angeles:20230907T110000
DTEND;TZID=America/Los_Angeles:20230907T120000
DTSTAMP:20230801T172801Z
CREATED:20230801T172801Z
LAST-MODIFIED:20230801T172801Z
UID:6639-1694084400-1694088000@marketingeda.com
SUMMARY:FPGA Design Verification - Planning
DESCRIPTION:As FPGA technology continues to evolve – to provide us with full-blown SoCs with CPU\, GPU\, and high-speed peripherals\, for example\, joining the traditional programmable logic area – design verification becomes increasingly challenging. Lab-based FPGA testing and bring-up alone are clearly insufficient\, especially for safety-critical designs\, and FPGA teams are adopting advanced design verification methodologies and techniques to develop homegrown verification processes. \n  \nIn this three-part webinar series\, we will discuss design verification with a focus on creating an advanced simulation-based verification process; from verification planning and team organization\, and moving on to regression setup\, functional coverage collection\, randomization and ‘verification done’ definitions. We will also show you how to develop simple yet powerful and reusable testbenches using Verilog and SystemVerilog constructs and how to functionally verify designs in the most efficient way. \n  \nIn part 1 of this webinar series\, we will provide an overview of advanced simulation-based verification process and outline the differences between ASIC and FPGA-centric verification processes. Then\, we will show you how to develop a verification plan; describing WHAT to verify and HOW to verify it. Finally\, we will talk about design verification of highly configurable design and IP blocks. \n  \nAgenda: \n\nASIC Verification vs FPGA Verification\nFPGA-specific Design Verification Project Constraints\nOverview of Design Verification Stages\nOrganizing FPGA Teams\nDesign Verification Methods\nStimulus and Checker Types\nBlock\, Subsystem and System-Level\nVerification Plan Structure\nSetting Design Verification goals (WHAT)\nExtracting Design Properties\nSetting Priorities\nDefining Verification Methods\, Types and Levels (HOW)\nDefining Test Scenario\nWorking with Configurable Designs\nDemo with example design and testbench\nConclusion\nQ&A\n\n  \nWebinar Duration: \n\n45 min presentation/live demo\n15 min Q&A\n\n  \nPresenter BIO \nAlexander Gnusin\, Design Verification Technologist\, Aldec \nAlexander Gnusin accumulated 27 years of hands-on experience in various aspects of ASIC and FPGA design and verification. As a verification prime for a multi-million gates project in companies such as IBM\, Nortel\, Ericsson and Synopsys Inc\, he combined various verification methods such as static linting\, formal property checking\, dynamic simulation and hardware-assisted acceleration to efficiently achieve design verification goals. He received his M.S. in Electronics from Technion\, Israel Institute of Technology.
URL:https://marketingeda.com/event/fpga-design-verification-planning/
CATEGORIES:EDA,Webinar
ATTACH;FMTTYPE=image/jpeg:https://marketingeda.com/wp-content/uploads/Aldex-Verification.jpg
END:VEVENT
BEGIN:VEVENT
DTSTART;TZID=Asia/Jerusalem:20230906T150000
DTEND;TZID=Asia/Jerusalem:20230906T170000
DTSTAMP:20230901T163554Z
CREATED:20230901T163554Z
LAST-MODIFIED:20230901T163554Z
UID:6767-1694012400-1694019600@marketingeda.com
SUMMARY:SemIsrael Tech Webinar
DESCRIPTION:Venkata Subba Reddy Khambam\nSenior Technical ManagerSmartSoC Solutions \nThe Rise of Embedded AI: Transforming Industries and Enhancing User Experience\n\n\nEmbedded AI has become a transformative force in various industries\, revolutionizing the way we interact with technology and improving user experiences. This abstract explores the significance\, benefits\, and impact of embedded AI in sectors such as healthcare\, automotive\, manufacturing\, and consumer electronics. It also discusses the challenges and ethical considerations associated with embedded AI\, emphasizing the need for responsible development and deployment. The growing influence ofembedded AI has the potential to shape the future of technology and human interaction\, making it an essential area of study and innovation. \n\nBill Jenkins\nDirector AI Product Marketing\nAchronix \n\nHarnessing the Power of FPGAs for Ultra-Low Latency Streaming\n\n\nJoin us for a webinar on revolutionizing edge applications with real-time video and audio stream processing. Discover how FPGA technology empowers you to customize data paths\, enabling high performance with unparalleled low latency. Using conversational AI as a captivating case study\, we will delve into the transformative potential of FPGAs\, catering to the needs of engineers and industry decision-makers alike. Don’t miss this opportunity to explore cutting-edge solutions for ultra-low latency real-time streaming AI at the edge. \n\nGordon Allan\nProduct Manager\, Verification IP\nSiemens EDA \n\nSiemens + Avery – Building Better Verification IP\n\n\nSiemens EDA Verification experts describe our comprehensive Verification IP solutions for SoC and 3DIC projects in the Datacenter\, Storage\, 3DIC\, Networking\, Automotive\, Mil/Aero and other applications\, introducing our complete portfolio incorporating the recently acquired Avery Verification IP solutions. \n\nLarry Lapides\nVP Worldwide SalesImperas Software \n\nVirtual Platforms Accelerate RISC-V SoC Software Development\n\n\nThe design freedoms of RISC-V offer systems and SoC developers new flexibility to build domain specific processors\, optimized for the requirements of the target application and domain. This is driving the growing adoption of RISC-V\, however\, software is still needed on these new platforms. This could be entirely new software\, or porting legacy applications\, firmware\, libraries and operating systems to the RISC-V platform. Virtual platforms\, or software simulation\, can accelerate software tasks by providing an environment for software development\, debug and test many months before silicon is available. While virtual platforms do not replace hardware-based testing of the software\, the early availability\, ease of automation\, controllability and observability are making virtual platforms a must-have for embedded software development. This presentation will discuss the various models and tools that comprise a successful virtual platform environment\, and provide case studies in automotive\, DSP and AI/ML.
URL:https://marketingeda.com/event/semisrael-tech-webinar-6/
CATEGORIES:EDA,Webinar
ATTACH;FMTTYPE=image/jpeg:https://marketingeda.com/wp-content/uploads/SemIsrael-September-5-2023.jpg
END:VEVENT
BEGIN:VEVENT
DTSTART;TZID=America/Los_Angeles:20230906T100000
DTEND;TZID=America/Los_Angeles:20230906T110000
DTSTAMP:20230829T215426Z
CREATED:20230829T215426Z
LAST-MODIFIED:20230829T215426Z
UID:6756-1693994400-1693998000@marketingeda.com
SUMMARY:Everything You Need to Know about SystemVerilog Arrays
DESCRIPTION:This webinar gives a comprehensive guide to all aspects of SystemVerilog arrays: ordinary static arrays\, dynamic arrays\, queues and associative arrays. It also includes array methods and practical examples. \nTopics: \n\nReview of Verilog array types\nSystemVerilog packed and unpacked arrays\nSystemVerilog dynamic arrays\nSystemVerilog queues\nSystemVerilog associate arrays\nArray manipulation methods.\n\nCoding examples are shown running on Synopsys VCS and you can try out the examples yourself after the webinar on EDA Playground. \n\n\n\n\n\n\nBrian Jensen \, a Certified Training Instructor for Doulos\, will present this training webinar\, which will consist of a one-hour presentation with interactive Q&A available to attendees throughout. \n\n\n\n\n\nAttendance is free of charge \nIf you have any queries\, please contact webinars@doulos.com
URL:https://marketingeda.com/event/everything-you-need-to-know-about-systemverilog-arrays-2/
CATEGORIES:EDA,Webinar
ATTACH;FMTTYPE=image/jpeg:https://marketingeda.com/wp-content/uploads/Doulos-September-6-2023.jpg
ORGANIZER;CN="Doulos":MAILTO:webinars@duolos.com
END:VEVENT
BEGIN:VEVENT
DTSTART;TZID=Europe/London:20230905T120000
DTEND;TZID=Europe/London:20230905T130000
DTSTAMP:20230801T174617Z
CREATED:20230801T174617Z
LAST-MODIFIED:20230801T174617Z
UID:6648-1693915200-1693918800@marketingeda.com
SUMMARY:DVClub Europe - Cache Coherency Verification
DESCRIPTION:This is to inform you that the next DVClub Europe meeting takes place on Tuesday 05th September with a theme of “Cache Coherency Verification”.\n\nSoC cache coherency verification is one of the most complex challenges faced by verification engineers. And the introduction of the embedded L3 cache and the increasing number of cores in CPU clusters ais making it even more challenging. In this DVClub we will focus on how this challenge can be best approached and some automation added.\n\nAgenda (BST) \n12:00   Welcome and Introduction – Mike Bartley\, Senior Vice President – VLSI Design\, Tessolve\n12:00    David Kelf\, Breker Verification Systems\n12:20    Sponsor Speaker\n12:40    Sponsor Speaker\n13:00    Close \n  \nRegister now to become a part of this event. Free to attend online. \nEventbrite – DVClub Europe  \nBest Regards \nMike Bartley\, Senior Vice President – VLSI Design\, Tessolve
URL:https://marketingeda.com/event/dvclub-europe-cache-coherency-verification/
CATEGORIES:EDA,Webinar
ATTACH;FMTTYPE=image/png:https://marketingeda.com/wp-content/uploads/DVClub-Europe-September-5-2023.png
END:VEVENT
END:VCALENDAR