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BEGIN:VEVENT
DTSTART;TZID=America/Los_Angeles:20231011T090000
DTEND;TZID=America/Los_Angeles:20231011T100000
DTSTAMP:20231006T190044Z
CREATED:20231006T190044Z
LAST-MODIFIED:20231006T190044Z
UID:6919-1697014800-1697018400@marketingeda.com
SUMMARY:Mapping signal processing algorithms on AMD-Xilinx Versal to meet timing and power constraints
DESCRIPTION:In this Webinar\, we will focus on the performance-power-area trade-off in implementing signal processing algorithms on Xilinx FPGA by partitioning the tasks of the algorithms onto the processors\, logic and AI Engines resident in the AMD-Xilinx Versal FPGA.  \n\n Key Takeaways: \n\nDiscover the inner workings of FPGA components: Processor\, Logic Elements\, AIE/Tensor\, and more.\nUnderstand latency and throughput trade-offs when using NoC vs. direct interfaces.\nLearn how different data cache sizes impact AIE Tile network utilization.\nDive into various mapping decisions and their effect on application throughput and power consumption.\n\n  \nSo\, what are you waiting for? Don’t miss this opportunity
URL:https://marketingeda.com/event/mapping-signal-processing-algorithms-on-amd-xilinx-versal-to-meet-timing-and-power-constraints/
CATEGORIES:EDA,IP,Webinar
ATTACH;FMTTYPE=image/jpeg:https://marketingeda.com/wp-content/uploads/Mirabilis-October-11-2023.jpg
END:VEVENT
BEGIN:VEVENT
DTSTART;TZID=America/Los_Angeles:20231005T110000
DTEND;TZID=America/Los_Angeles:20231005T120000
DTSTAMP:20230801T173224Z
CREATED:20230801T173224Z
LAST-MODIFIED:20230801T173224Z
UID:6644-1696503600-1696507200@marketingeda.com
SUMMARY:FPGA Design Verification - Advanced Methods
DESCRIPTION:Abstract \nAs FPGA technology continues to evolve – to provide us with full-blown SoCs with CPU\, GPU\, and high-speed peripherals\, for example\, joining the traditional programmable logic area – design verification becomes increasingly challenging. Lab-based FPGA testing and bring-up alone are clearly insufficient\, especially for safety-critical designs\, and FPGA teams are adopting advanced design verification methodologies and techniques to develop homegrown verification processes. \n  \nIn this three-part webinar series\, we will discuss design verification with a focus on creating an advanced simulation-based verification process; from verification planning and team organization\, and moving on to regression setup\, functional coverage collection\, randomization and ‘verification done’ definitions. We will also show you how to develop simple yet powerful and reusable testbenches using Verilog and SystemVerilog constructs and how to functionally verify designs in the most efficient way. \n  \nIn this\, the concluding episode of the webinar series\, we will present advanced verification solutions for verifying complex design properties. We will talk about randomization\, functional coverage\, and the importance of code coverage to achieve overall design verification completeness. Also\, we will provide an overview on other important topics such as assertion and transaction-based verification and debug\, static design verification with linting tools and regressions support. Finally\, we will talk about ‘Verification Done’\, in terms of at what point can the verification be considered complete and how do we achieve it? \n  \nAgenda: \n\nCheckers and Scoreboards Development\nRandomization Methods\nFunctional Coverage and Tests Grading\nCode Coverage\nAssertion-based Verification\nTransaction-based Debugging with Riviera-PRO\nStatic Verification with Linting tools\nSetting up Regressions\nDefining “Verification Done”\nPacket-based Design Verification Example\nConclusion\nQ&A\n\n  \nWebinar Duration: \n\n45 min presentation/live demo\n15 min Q&A\n\n  \nPresenter BIO \nAlexander Gnusin\, Design Verification Technologist\, Aldec \nAlexander Gnusin accumulated 27 years of hands-on experience in various aspects of ASIC and FPGA design and verification. As a verification prime for a multi-million gates project in companies such as IBM\, Nortel\, Ericsson and Synopsys Inc\, he combined various verification methods such as static linting\, formal property checking\, dynamic simulation and hardware-assisted acceleration to efficiently achieve design verification goals. He received his M.S. in Electronics from Technion\, Israel Institute of Technology.
URL:https://marketingeda.com/event/fpga-design-verification-advanced-methods/
CATEGORIES:EDA,Webinar
ATTACH;FMTTYPE=image/jpeg:https://marketingeda.com/wp-content/uploads/Aldex-Verification.jpg
END:VEVENT
BEGIN:VEVENT
DTSTART;TZID=America/Los_Angeles:20231004T110000
DTEND;TZID=America/Los_Angeles:20231004T120000
DTSTAMP:20230921T172330Z
CREATED:20230921T172330Z
LAST-MODIFIED:20230921T172330Z
UID:6855-1696417200-1696420800@marketingeda.com
SUMMARY:Verisium Debug for UVM Testbench
DESCRIPTION:Verisium Debug offers comprehensive debugging capabilities. From RTL and UVM testbench to UPF low-power designs\, Cadence’s unified debugging platform helps users debug. In this webinar\, users will learn about the available features in Verisium Debug for UVM testbench and use these unique capabilities to visualize and debug the UVM testbench. \nWhat you will learn \n\nUnderstand the features available in Verisium Debug\n​Learn about the UVM debug capabilities in Verisium Debug\nLearn to debug UVM testbench using Verisium Debug\n\nWho should attend \n\nDesign engineers\nVerification engineers\nCAD engineers
URL:https://marketingeda.com/event/verisium-debug-for-uvm-testbench/
CATEGORIES:EDA,Webinar
ATTACH;FMTTYPE=image/jpeg:https://marketingeda.com/wp-content/uploads/Cadence-October-4-2023.jpg
END:VEVENT
BEGIN:VEVENT
DTSTART;TZID=America/Los_Angeles:20230928T110000
DTEND;TZID=America/Los_Angeles:20230928T120000
DTSTAMP:20230801T173012Z
CREATED:20230801T172957Z
LAST-MODIFIED:20230801T173012Z
UID:6642-1695898800-1695902400@marketingeda.com
SUMMARY:FPGA Design Verification - Advanced Testbench Implementation
DESCRIPTION:Abstract \nAs FPGA technology continues to evolve – to provide us with full-blown SoCs with CPU\, GPU\, and high-speed peripherals\, for example\, joining the traditional programmable logic area – design verification becomes increasingly challenging. Lab-based FPGA testing and bring-up alone are clearly insufficient\, especially for safety-critical designs\, and FPGA teams are adopting advanced design verification methodologies and techniques to develop homegrown verification processes. \n  \nIn this three-part webinar series\, we will discuss design verification with a focus on creating an advanced simulation-based verification process; from verification planning and team organization\, and moving on to regression setup\, functional coverage collection\, randomization and ‘verification done’ definitions. We will also show you how to develop simple yet powerful and reusable testbenches using Verilog and SystemVerilog constructs and how to functionally verify designs in the most efficient way. \n  \nIn part 2 of this webinar series\, we will show you important verification patterns providing solutions to repeatable randomization\, error management and end-of-test checks. We will also provide an overview of how to define\, develop and re-use verification components such as drivers\, responders\, and monitors. Then\, we will talk about how to develop testbenches\, and how to validate their correctness with reporting and statistics collection. We will provide code examples to illustrate the topics of discussion. \n  \nAgenda: \n\nCommon Verification Patterns:\no Repeatable Randomization\no Reporting\, Error management\no End-of-Test Procedure\nVerification Components (VC) Development:\no Verification Component Types\no Defining Transactions for VC Development\no Legal and Error Operation Modes\no Controllable Randomization\no Verification in Standalone Testbenches\nTestbench Development and Verification:\no Statistical methods for Testbench Validation\no Scripting Support\nDemo with example design and testbench\nConclusion\nQ&A\n\n  \nWebinar Duration: \n\n45 min presentation/live demo\n15 min Q&A\n\n  \nPresenter BIO \nAlexander Gnusin\, Design Verification Technologist\, Aldec \nAlexander Gnusin accumulated 27 years of hands-on experience in various aspects of ASIC and FPGA design and verification. As a verification prime for a multi-million gates project in companies such as IBM\, Nortel\, Ericsson and Synopsys Inc\, he combined various verification methods such as static linting\, formal property checking\, dynamic simulation and hardware-assisted acceleration to efficiently achieve design verification goals. He received his M.S. in Electronics from Technion\, Israel Institute of Technology.
URL:https://marketingeda.com/event/fpga-design-verification-advanced-testbench-implementation/
CATEGORIES:EDA,Webinar
ATTACH;FMTTYPE=image/jpeg:https://marketingeda.com/wp-content/uploads/Aldex-Verification.jpg
END:VEVENT
BEGIN:VEVENT
DTSTART;TZID=America/Los_Angeles:20230927T120000
DTEND;TZID=America/Los_Angeles:20230927T130000
DTSTAMP:20230818T231020Z
CREATED:20230818T231020Z
LAST-MODIFIED:20230818T231020Z
UID:6732-1695816000-1695819600@marketingeda.com
SUMMARY:Stratus HLS Automated Power Shutoff to Minimize Power and Retention Registers
DESCRIPTION:Power Shutoff is a popular technique for saving power during functionally idle periods. Implementing Power Shutoff requires a detailed understanding of which resisters must be retained to enable bring-up from the power-off state. Identifying the minimal set of retention registers is challenging and grows more difficult with design complexity. \n\nThis CadenceTECHTALK introduces a novel High-Level Synthesis-based solution for the automated implementation of Power Shutoff. This solution automatically identifies and implements Power Shutoff using the minimal set of retention registers\, yielding the lowest leakage power and saving weeks of implementation time vs. manual methods. \n\nJoin this webinar to learn how to apply this technology to your own design and interact with product experts who will demonstrate the technology in a real-world testcase. Design engineers working on low-power digital IC designs or algorithms will benefit from this TECHTALK.
URL:https://marketingeda.com/event/stratus-hls-automated-power-shutoff-to-minimize-power-and-retention-registers/
CATEGORIES:EDA,Webinar
ATTACH;FMTTYPE=image/jpeg:https://marketingeda.com/wp-content/uploads/Cadence-September-27-2023.jpg
END:VEVENT
BEGIN:VEVENT
DTSTART;TZID=America/New_York:20230927T100000
DTEND;TZID=America/New_York:20230927T110000
DTSTAMP:20230913T184118Z
CREATED:20230913T184118Z
LAST-MODIFIED:20230913T184118Z
UID:6792-1695808800-1695812400@marketingeda.com
SUMMARY:Cadence Training: Cerebrus Intelligent Chip Explorer
DESCRIPTION:Please join me\, Cadence Training and Application Engineer Krishna Atreya\, for this free technical Training Webinar. \nWhat Is the Webinar About?\nThe Cadence Cerebrus Intelligent Chip Explorer is a revolutionary\, machine learning-driven\, automated approach to chip design flow optimization. Block engineers specify the design goals\, and Cadence Cerebrus intelligently optimizes the Cadence digital full flow to meet power\, performance\, and area (PPA) goals in a completely automated way—letting engineers concurrently optimize multiple block flows\, which is particularly important for the large\, complex system-on-chip (SoC) designs needed for today’s ever more powerful electronic systems. \nWe’ll dive into: \n\nUnderstanding the Cadence Cerebrus flows\nUnderstanding flow wrapping\nFlow wrapping your design for Cadence Cerebrus readiness\n\nWhen Is the Webinar?\nWednesday\, September 27 \n07:00 PDT San Jose / 10:00 EDT New York / 15:00 BST London / 16:00 CEST Berlin / 17:00 IDT Jerusalem / 19:30 IST Bangalore / 22:00 CST Beijing \nTo register for the “Flow Wrapping: The Cadence Cerebrus Intelligent Chip Explorer Must Have” webinar\, use the REGISTER button below and sign in with your Cadence Support account (email ID and password) to log in to the Learning and Support System. Then select Enroll to register for the session. Once registered\, you’ll receive a confirmation email containing all login details. \nREGISTER \nIf you don’t have a Cadence Support account\, go to Registration Help or Cadence User Registration\, and complete the requested information. \nFor questions and inquiries or issues with registration\, reach out to eur_training@cadence.com \nKeep up with the revolution! Join Cadence’s Cerebrus Intelligent Chip Explorer Training and learn how to use Cadence Cerebrus to scale and automate your design\, improve your productivity\, and much more. \nThe online class is free for all Cadence customers with a Learning and Support account. \nWe can also organize this Cadence Cerebrus Intelligent Chip Explorer Training for you as a “Blended” or “Live” training. Please reach out to Cadence Training for further information. \nYou can also enjoy this video to get a first impression what is waiting for you! \nWant to share this and other great Cadence learning opportunities with someone else? Tell them to subscribe. \nHungry for Training?\nChoose the Cadence Training Menu that’s right for you. To view our complete training offerings\, visit the Cadence Training website.
URL:https://marketingeda.com/event/cadence-training-cerebrus-intelligent-chip-explorer/
CATEGORIES:EDA,Webinar
ATTACH;FMTTYPE=image/jpeg:https://marketingeda.com/wp-content/uploads/Cadence-September-27-2023-2.jpg
END:VEVENT
BEGIN:VEVENT
DTSTART;TZID=America/Los_Angeles:20230927T090000
DTEND;TZID=America/Los_Angeles:20230927T130000
DTSTAMP:20230919T171317Z
CREATED:20230919T171317Z
LAST-MODIFIED:20230919T171317Z
UID:6829-1695805200-1695819600@marketingeda.com
SUMMARY:Synopsys VSO.ai Virtual Workshop
DESCRIPTION:Virtual workshop with hands-on labs \nAchieving coverage closure continues to remain a challenge for customers and there is a growing need for a system to work autonomously to reach the target as quickly and cheaply as possible with the highest quality of results. The recently released Synopsys VSO.ai address this challenge in addition to inferring coverage from RTL and finding bugs. \nIn this hands-on half day virtual workshop you will learn: \nThe different components of Synopsys VSO.ai\nThe value proposition demonstrated at customers\nUpcoming technologies \nThese technologies are natively integrated with VCS\, the industry performance leader\, and will be presented by Synopsys Verification experts.\nAttendees will gain hands-on experience in live labs and walk away with the confidence to use this technology in your current projects. Lab participation will be limited. \nWorkshop Agenda\nPacificTime \n\n\n\nTime\nSession\n\n\n9:00 – 9:15 a.m.\nOverview of coverage closure\n\n\n9:15 – 10:00 a.m.\nRegression optimization\n\n\n10:00 – 10:45 a.m.\nLab 1\n\n\n10:45 – 11:00 a.m.\nBreak\n\n\n11:00 – 11:45 a.m.\nCoverage directed solver\n\n\n11:45 a.m. – 12:30 p.m.\nLab 2\n\n\n12:30 – 12:45 p.m.\nRoadmap\n\n\n12:45 – 1:00 p.m.\nWrap-up + Q&A
URL:https://marketingeda.com/event/synopsys-vso-ai-virtual-workshop/
CATEGORIES:EDA,Webinar
ATTACH;FMTTYPE=image/jpeg:https://marketingeda.com/wp-content/uploads/Synopsys-September-27-2023.jpg
END:VEVENT
BEGIN:VEVENT
DTSTART;TZID=America/Los_Angeles:20230926T100000
DTEND;TZID=America/Los_Angeles:20230926T110000
DTSTAMP:20230921T161238Z
CREATED:20230921T161238Z
LAST-MODIFIED:20230921T161238Z
UID:6847-1695722400-1695726000@marketingeda.com
SUMMARY:Unleashing Innovation with UCIe​​​​​​​​​​​​​​
DESCRIPTION:Exploring the Next Frontier in Chip Integration\nWebinar Agenda : \n\nIntroduction to all UCIe layers\nDecrypting FLITs\, PHY Trainings\, Bring up flows FDI-RDI \, main band and side band FLIT transfers etc.\nImplementation of Stacks-Arbiter\, Retry mechanism & Retimer implementations\nShowcasing UCie FLIT transfer flow between multidies\nEnhancements done in UCIe 1.1\n\nWho Should Attend: \n\nProfessionals working on development of UCIe VIP.\nPeople keen to know how UCie VIP is shaping new era of chiplet communications\nFreshers in the field of VLSI industry.
URL:https://marketingeda.com/event/unleashing-innovation-with-ucie/
CATEGORIES:IP,Webinar
ATTACH;FMTTYPE=image/jpeg:https://marketingeda.com/wp-content/uploads/Truechip-September-26-2023.jpg
END:VEVENT
BEGIN:VEVENT
DTSTART;TZID=Asia/Kolkata:20230924T093000
DTEND;TZID=Asia/Kolkata:20230924T113000
DTSTAMP:20230921T165532Z
CREATED:20230921T165023Z
LAST-MODIFIED:20230921T165532Z
UID:6850-1695547800-1695555000@marketingeda.com
SUMMARY:Applications of Formal Verification
DESCRIPTION:It is an exciting time to explore a career in the VLSI semiconductor sector\, and we’re here to help you gain clarity on buzz and provide information on educational options towards a successful entry to this field with long-term career prospects. \nDesign Verification is one of the essential and most promising career options. In the upcoming free live webinar\, we discuss one critical verification aspect – formal verification. \nJoin us for this session on\n24th Sep Sunday from 9:30 am to 11:30 am IST.\nThe link to register is \nhttps://lnkd.in/gZiFUddW \nThe webinar is brought to you by Semiconductor Nation – Campus ConnectTM platform of FutureSkills by India Electronics and Semiconductor Association and metavlsi \nAttend this free live webinar all about the applications of Formal Verification for SoC design\, presented by VLSI Deep Dive. \nThe webinar is two hours in length and uses Google Meet. \nWe are on a mission to inspire and develop people to achieve their goals in professional life. We enable people to learn deeply through bite-sized\, interactive learning experiences. Our courses are structured and designed by leading experts in their respective fields.
URL:https://marketingeda.com/event/applications-of-formal-verification/
CATEGORIES:EDA,Webinar
ATTACH;FMTTYPE=image/jpeg:https://marketingeda.com/wp-content/uploads/VLSI-Deep-Dive-September-24th-2023.jpg
END:VEVENT
BEGIN:VEVENT
DTSTART;TZID=America/Los_Angeles:20230921T110000
DTEND;TZID=America/Los_Angeles:20230921T120000
DTSTAMP:20230908T171723Z
CREATED:20230908T171723Z
LAST-MODIFIED:20230908T171723Z
UID:6783-1695294000-1695297600@marketingeda.com
SUMMARY:UCIe-Based Chiplet Verification - from IP to SoC
DESCRIPTION:Innovative die disaggregation technologies\, enable a future where a catalog of chiplets will be available to mix and match based on the end application. The industry’s fastest emerging interconnect standard called Universal Chiplet Interconnect Express (UCIe) enables end users to combine chiplets with different functionality and technology nodes to develop highly sophisticated electronic chips. Hence\, the verification topologies of such designs have exponentially increased. \nIn this webinar\, we will explore challenges and effective solutions to optimize effort and improve productivity in the verification using “Chiplet-like” reusable verification components. This caters to all possible topologies enabling continuous verification from IP to Subsystem and finally\, at the system-level.
URL:https://marketingeda.com/event/ucie-based-chiplet-verification-from-ip-to-soc-2/
CATEGORIES:EDA,IP,Webinar
ATTACH;FMTTYPE=image/jpeg:https://marketingeda.com/wp-content/uploads/Cadence-September-21-2023.jpg
END:VEVENT
BEGIN:VEVENT
DTSTART;TZID=America/Los_Angeles:20230921T100000
DTEND;TZID=America/Los_Angeles:20230921T110000
DTSTAMP:20230920T184452Z
CREATED:20230920T184452Z
LAST-MODIFIED:20230920T184452Z
UID:6841-1695290400-1695294000@marketingeda.com
SUMMARY:Efficient Bluespec RISC-V Processor Verification for Highest Coverage Closure: A Comprehensive Case Study
DESCRIPTION:The ability to mix and match multiple ISA extensions and add user-defined ISA extensions makes RISC-V verification more challenging than conventional processor verification. This Synopsys webinar demonstrates the verification of standard RISC-V ISA extensions. A subsequent webcast will demonstrate custom ISA verification. The multiple ISA verification problem is solved by RISCV-DV with configurability for ISA specific test generation. RISCV-DV addresses the generation of ISA specific tests in one pass of simulation using Synopsys VCS® as the efficient constraint solver for instruction generation using constraint random methodology. The tests consist of valid instruction sequences (programs) for the target ISA of the processor core under verification. The generated programs are run on the Bluespec processor core simulated with Synopsys VCS and the results are compared with Spike instruction set simulation (ISS) results. \n  \nThis presentation will showcase: \n\nA reference methodology for verifying a Bluespec RV32IMC MCU-X processor core based on RISCV-DV.\nHow designers can leverage Synopsys VCS simulation and Synopsys Verdi® for debug and relevant advanced coverage methodology\, to help speed verification signoff.\nThe combination of RISCV-DV and Synopsys tools provides a powerful and flexible solution for RISC-V verification and highest coverage.\nDemo on the RISC-V verification solution on the Synopsys Cloud platform.\n\nWhether you are a chip verification architect or a verification engineer or a system designer\, this Synopsys webinar will provide valuable insights into how to set up a constraint random verification solution for a RISC-V processor to achieve the highest coverage. \n\n\n\n\n\n\n\n\n\n\nSpeakers\n\n\nListed below are the industry leaders scheduled to speak. \n\n\n\n\n\n\n\n\n\n\n\n\n\n\n\n\n\n\n\n\n\n\n\n\n\n\nBipul Talukdar\n\n\nSenior Director\, Applications Engineering\nBluespec \n\n\n\n\n\n\n\n\n\n\n\nBipul Talukdar is Senior Director of Applications Engineering for Bluespec Inc. He is an expert in hardware functional verification with a specialty in verification IP (VIP) development\, formal property verification\, and hardware emulation. He leads Application Engineering and Support for Bluespec. Bipul has a strong background in formal verification of RISC-V based cores/subsystems\, arm based cores/subsystems and coverage-based closure. His previous engineering roles at SiFive\, Cadence\, Mentor Graphics (Siemens) and SmartDV Technologies give him a broad perspective on the myriad challenges faced by design and verification teams\, allowing him to partner with customers for success throughout product evaluations and deployment. Bipul holds a Bachelor of Science in Engineering\, Electronics\, and Telecommunication from India’s National Institute of Technology\, Silchar. He is based in San Jose\, California. \n\n\n\n\n\n\n\n\n\n\n\n\n\n\n\n\n\n\n\n\n\n\n\n\n\n\n\n\n\n\n\nPrabha Krishnaswami\n\n\nApplications Engineer\, Senior Staff\nSynopsys \n\n\n\n\n\n\n\n\n\n\n\nPrabha Krishnaswami is an Application Engineer at Synopsys\, focusing on VCS and Verdi products. She also collaborates with the global RISC-V customers to showcase the Synopsys RISC-V solution. She has a background in design and verification with expertise in SoCs and subsystems. Prabha likes music\, reading and enjoys long walks.
URL:https://marketingeda.com/event/efficient-bluespec-risc-v-processor-verification-for-highest-coverage-closure-a-comprehensive-case-study/
CATEGORIES:EDA,IP,Webinar
ATTACH;FMTTYPE=image/jpeg:https://marketingeda.com/wp-content/uploads/Synopsys-September-21-2023.jpg
END:VEVENT
BEGIN:VEVENT
DTSTART;TZID=America/Los_Angeles:20230921T090000
DTEND;TZID=America/Los_Angeles:20230921T100000
DTSTAMP:20230911T162325Z
CREATED:20230911T162325Z
LAST-MODIFIED:20230911T162325Z
UID:6789-1695286800-1695290400@marketingeda.com
SUMMARY:QuantumATK V-2023.09 Release: Highlights of New and Enhanced Features
DESCRIPTION:Join our FREE online event to learn about the new and enhanced features and performance improvements in the latest QuantumATK V-2023.09 product release. \n– Enhanced ease-of-use of training Machine-Learned FFs with new predefined Workflow Builder blocks and templates \n– New interactive Interfaces Builder for building multilayer structures \n– New Accelerated molecular dynamics method for crystallization \n– New Thermochemistry pyrolysis tools to predict gas phase composition in surface processing – Integrated Charged point defect and defect diffusion simulation frameworks \n– Major speedup in bandstructure simulations with Tight Binding models for up to million atoms \n– Efficient and simplified deformation potential extraction for large nanostructures to evaluate electron-phonon coupling \n– New analysis of spectral and thermal current/conductance in Transmission Analyzer \n– More interactive IV Characteristics Analyzer and possibility to analyze inelastic current \n– New Finite Bias Spin Transfer Torque (STT) Study Object & Analyzer to evaluate the write performance of STT-MRAM \n– New Heisenberg Exchange Analyzer for exchange couplings and Curie temperature \nSynopsys Webinar Speakers: \n– Mattias Palsgaard\, Senior Applications Engineer\, Synopsys QuantumATK \n– Vaida Arcisauskaite\, Senior Applications Engineer\, Synopsys QuantumATK \n– Bo Lu\, Senior R&D Engineer\, Synopsys QuantumATK \nLearn more about the new QuantumATK V-2023.09 release here: https://www.synopsys.com/manufacturing/quantumatk/resources/release-notes.html \nYou are welcome to ask questions throughout the webinar or at the end during the Q&A session. Contact us for more information at quantumatk@synopsys.com.
URL:https://marketingeda.com/event/quantumatk-v-2023-09-release-highlights-of-new-and-enhanced-features/
CATEGORIES:EDA,Webinar
ATTACH;FMTTYPE=image/png:https://marketingeda.com/wp-content/uploads/Synopsys-September-21-2023.png
END:VEVENT
BEGIN:VEVENT
DTSTART;TZID=America/Los_Angeles:20230920T100000
DTEND;TZID=America/Los_Angeles:20230920T110000
DTSTAMP:20230919T164805Z
CREATED:20230919T164516Z
LAST-MODIFIED:20230919T164805Z
UID:6825-1695204000-1695207600@marketingeda.com
SUMMARY:Maximize Design Productivity using Vivado ML with SystemVerilog
DESCRIPTION:Although SystemVerilog is perhaps most widely used in the context of hardware verification\, it also contains many features directly relevant to FPGA hardware designers. We explore the features of SystemVerilog that are useful for RTL synthesis using Vivado™ ML Editions from AMD\, showing how the RTL SystemVerilog language constructs have been optimized for productivity and reliability. \nWe start from the basic principles of RTL coding style in SystemVerilog\, then focus on the language features that allow FPGA hardware designers to work very efficiently while at the same time avoiding synthesis pitfalls. \nContent Summary: \n\nIntroduction\nSystemVerilog in Vivado ML Editions\nModules\, ports\, parameters\, and hierarchy\nCombinational and clocked logic\nAssignments and procedures\nControl constructs and operators\nHardware-oriented data types including packages\nInterfaces and Modports\n\n\n \nMike Smith – Doulos Certified Training Instructor\, will be presenting this training webinar\, which will consist of a one-hour session and will be interactive with Q&A participation from attendees. \n\nAttendance is free of charge \nIf you have any queries\, please contact webinars@doulos.com
URL:https://marketingeda.com/event/maximize-design-productivity-using-vivado-ml-with-systemverilog/
CATEGORIES:EDA,Webinar
ATTACH;FMTTYPE=image/jpeg:https://marketingeda.com/wp-content/uploads/Doulos-September-20-2023.jpg
ORGANIZER;CN="Doulos":MAILTO:webinars@duolos.com
END:VEVENT
BEGIN:VEVENT
DTSTART;TZID=America/Los_Angeles:20230912T100000
DTEND;TZID=America/Los_Angeles:20230912T110000
DTSTAMP:20230829T220653Z
CREATED:20230829T220628Z
LAST-MODIFIED:20230829T220653Z
UID:6759-1694512800-1694516400@marketingeda.com
SUMMARY:NoC IP- Transforming Chip Communication
DESCRIPTION:Webinar Agenda : \n\nIntroduction to Mesh and Crossbar Architecture\nCache Introduction\nSupport for latest AMBA 5\nSafety and security features as ASIL Standard.\nPort configurabilities\n\nWho Should Attend: \n\nProfessionals working on development of NoC IP.\nPeople keen to know how NoC IP is shaping new era of chiplet communications\nFreshers in the field of VLSI industry.
URL:https://marketingeda.com/event/noc-ip-transforming-chip-communication/
CATEGORIES:IP,Webinar
ATTACH;FMTTYPE=image/jpeg:https://marketingeda.com/wp-content/uploads/Webinar-Series-NoC-IP-01_02.jpg
END:VEVENT
BEGIN:VEVENT
DTSTART;TZID=America/Los_Angeles:20230907T110000
DTEND;TZID=America/Los_Angeles:20230907T120000
DTSTAMP:20230801T172801Z
CREATED:20230801T172801Z
LAST-MODIFIED:20230801T172801Z
UID:6639-1694084400-1694088000@marketingeda.com
SUMMARY:FPGA Design Verification - Planning
DESCRIPTION:As FPGA technology continues to evolve – to provide us with full-blown SoCs with CPU\, GPU\, and high-speed peripherals\, for example\, joining the traditional programmable logic area – design verification becomes increasingly challenging. Lab-based FPGA testing and bring-up alone are clearly insufficient\, especially for safety-critical designs\, and FPGA teams are adopting advanced design verification methodologies and techniques to develop homegrown verification processes. \n  \nIn this three-part webinar series\, we will discuss design verification with a focus on creating an advanced simulation-based verification process; from verification planning and team organization\, and moving on to regression setup\, functional coverage collection\, randomization and ‘verification done’ definitions. We will also show you how to develop simple yet powerful and reusable testbenches using Verilog and SystemVerilog constructs and how to functionally verify designs in the most efficient way. \n  \nIn part 1 of this webinar series\, we will provide an overview of advanced simulation-based verification process and outline the differences between ASIC and FPGA-centric verification processes. Then\, we will show you how to develop a verification plan; describing WHAT to verify and HOW to verify it. Finally\, we will talk about design verification of highly configurable design and IP blocks. \n  \nAgenda: \n\nASIC Verification vs FPGA Verification\nFPGA-specific Design Verification Project Constraints\nOverview of Design Verification Stages\nOrganizing FPGA Teams\nDesign Verification Methods\nStimulus and Checker Types\nBlock\, Subsystem and System-Level\nVerification Plan Structure\nSetting Design Verification goals (WHAT)\nExtracting Design Properties\nSetting Priorities\nDefining Verification Methods\, Types and Levels (HOW)\nDefining Test Scenario\nWorking with Configurable Designs\nDemo with example design and testbench\nConclusion\nQ&A\n\n  \nWebinar Duration: \n\n45 min presentation/live demo\n15 min Q&A\n\n  \nPresenter BIO \nAlexander Gnusin\, Design Verification Technologist\, Aldec \nAlexander Gnusin accumulated 27 years of hands-on experience in various aspects of ASIC and FPGA design and verification. As a verification prime for a multi-million gates project in companies such as IBM\, Nortel\, Ericsson and Synopsys Inc\, he combined various verification methods such as static linting\, formal property checking\, dynamic simulation and hardware-assisted acceleration to efficiently achieve design verification goals. He received his M.S. in Electronics from Technion\, Israel Institute of Technology.
URL:https://marketingeda.com/event/fpga-design-verification-planning/
CATEGORIES:EDA,Webinar
ATTACH;FMTTYPE=image/jpeg:https://marketingeda.com/wp-content/uploads/Aldex-Verification.jpg
END:VEVENT
BEGIN:VEVENT
DTSTART;TZID=Asia/Jerusalem:20230906T150000
DTEND;TZID=Asia/Jerusalem:20230906T170000
DTSTAMP:20230901T163554Z
CREATED:20230901T163554Z
LAST-MODIFIED:20230901T163554Z
UID:6767-1694012400-1694019600@marketingeda.com
SUMMARY:SemIsrael Tech Webinar
DESCRIPTION:Venkata Subba Reddy Khambam\nSenior Technical ManagerSmartSoC Solutions \nThe Rise of Embedded AI: Transforming Industries and Enhancing User Experience\n\n\nEmbedded AI has become a transformative force in various industries\, revolutionizing the way we interact with technology and improving user experiences. This abstract explores the significance\, benefits\, and impact of embedded AI in sectors such as healthcare\, automotive\, manufacturing\, and consumer electronics. It also discusses the challenges and ethical considerations associated with embedded AI\, emphasizing the need for responsible development and deployment. The growing influence ofembedded AI has the potential to shape the future of technology and human interaction\, making it an essential area of study and innovation. \n\nBill Jenkins\nDirector AI Product Marketing\nAchronix \n\nHarnessing the Power of FPGAs for Ultra-Low Latency Streaming\n\n\nJoin us for a webinar on revolutionizing edge applications with real-time video and audio stream processing. Discover how FPGA technology empowers you to customize data paths\, enabling high performance with unparalleled low latency. Using conversational AI as a captivating case study\, we will delve into the transformative potential of FPGAs\, catering to the needs of engineers and industry decision-makers alike. Don’t miss this opportunity to explore cutting-edge solutions for ultra-low latency real-time streaming AI at the edge. \n\nGordon Allan\nProduct Manager\, Verification IP\nSiemens EDA \n\nSiemens + Avery – Building Better Verification IP\n\n\nSiemens EDA Verification experts describe our comprehensive Verification IP solutions for SoC and 3DIC projects in the Datacenter\, Storage\, 3DIC\, Networking\, Automotive\, Mil/Aero and other applications\, introducing our complete portfolio incorporating the recently acquired Avery Verification IP solutions. \n\nLarry Lapides\nVP Worldwide SalesImperas Software \n\nVirtual Platforms Accelerate RISC-V SoC Software Development\n\n\nThe design freedoms of RISC-V offer systems and SoC developers new flexibility to build domain specific processors\, optimized for the requirements of the target application and domain. This is driving the growing adoption of RISC-V\, however\, software is still needed on these new platforms. This could be entirely new software\, or porting legacy applications\, firmware\, libraries and operating systems to the RISC-V platform. Virtual platforms\, or software simulation\, can accelerate software tasks by providing an environment for software development\, debug and test many months before silicon is available. While virtual platforms do not replace hardware-based testing of the software\, the early availability\, ease of automation\, controllability and observability are making virtual platforms a must-have for embedded software development. This presentation will discuss the various models and tools that comprise a successful virtual platform environment\, and provide case studies in automotive\, DSP and AI/ML.
URL:https://marketingeda.com/event/semisrael-tech-webinar-6/
CATEGORIES:EDA,Webinar
ATTACH;FMTTYPE=image/jpeg:https://marketingeda.com/wp-content/uploads/SemIsrael-September-5-2023.jpg
END:VEVENT
BEGIN:VEVENT
DTSTART;TZID=America/Los_Angeles:20230906T100000
DTEND;TZID=America/Los_Angeles:20230906T110000
DTSTAMP:20230829T215426Z
CREATED:20230829T215426Z
LAST-MODIFIED:20230829T215426Z
UID:6756-1693994400-1693998000@marketingeda.com
SUMMARY:Everything You Need to Know about SystemVerilog Arrays
DESCRIPTION:This webinar gives a comprehensive guide to all aspects of SystemVerilog arrays: ordinary static arrays\, dynamic arrays\, queues and associative arrays. It also includes array methods and practical examples. \nTopics: \n\nReview of Verilog array types\nSystemVerilog packed and unpacked arrays\nSystemVerilog dynamic arrays\nSystemVerilog queues\nSystemVerilog associate arrays\nArray manipulation methods.\n\nCoding examples are shown running on Synopsys VCS and you can try out the examples yourself after the webinar on EDA Playground. \n\n\n\n\n\n\nBrian Jensen \, a Certified Training Instructor for Doulos\, will present this training webinar\, which will consist of a one-hour presentation with interactive Q&A available to attendees throughout. \n\n\n\n\n\nAttendance is free of charge \nIf you have any queries\, please contact webinars@doulos.com
URL:https://marketingeda.com/event/everything-you-need-to-know-about-systemverilog-arrays-2/
CATEGORIES:EDA,Webinar
ATTACH;FMTTYPE=image/jpeg:https://marketingeda.com/wp-content/uploads/Doulos-September-6-2023.jpg
ORGANIZER;CN="Doulos":MAILTO:webinars@duolos.com
END:VEVENT
BEGIN:VEVENT
DTSTART;TZID=Europe/London:20230905T120000
DTEND;TZID=Europe/London:20230905T130000
DTSTAMP:20230801T174617Z
CREATED:20230801T174617Z
LAST-MODIFIED:20230801T174617Z
UID:6648-1693915200-1693918800@marketingeda.com
SUMMARY:DVClub Europe - Cache Coherency Verification
DESCRIPTION:This is to inform you that the next DVClub Europe meeting takes place on Tuesday 05th September with a theme of “Cache Coherency Verification”.\n\nSoC cache coherency verification is one of the most complex challenges faced by verification engineers. And the introduction of the embedded L3 cache and the increasing number of cores in CPU clusters ais making it even more challenging. In this DVClub we will focus on how this challenge can be best approached and some automation added.\n\nAgenda (BST) \n12:00   Welcome and Introduction – Mike Bartley\, Senior Vice President – VLSI Design\, Tessolve\n12:00    David Kelf\, Breker Verification Systems\n12:20    Sponsor Speaker\n12:40    Sponsor Speaker\n13:00    Close \n  \nRegister now to become a part of this event. Free to attend online. \nEventbrite – DVClub Europe  \nBest Regards \nMike Bartley\, Senior Vice President – VLSI Design\, Tessolve
URL:https://marketingeda.com/event/dvclub-europe-cache-coherency-verification/
CATEGORIES:EDA,Webinar
ATTACH;FMTTYPE=image/png:https://marketingeda.com/wp-content/uploads/DVClub-Europe-September-5-2023.png
END:VEVENT
BEGIN:VEVENT
DTSTART;TZID=America/Los_Angeles:20230831T110000
DTEND;TZID=America/Los_Angeles:20230831T120000
DTSTAMP:20230829T205052Z
CREATED:20230829T205052Z
LAST-MODIFIED:20230829T205052Z
UID:6753-1693479600-1693483200@marketingeda.com
SUMMARY:Advanced Testbench for a Complex DUT
DESCRIPTION:Functional simulation using an HDL testbench is the de facto method for proving functional correctness of FPGA designs. In this three-part webinar series\, we will present a step-by-step approach on how to architect a testbench – progressing from basic to advanced techniques. We will first use a simple DUT then go to a more complex DUT with simultaneous activities on multiple interfaces. \nIn the concluding part of this webinar series\, we are now ready to apply advanced verification to a complex DUT. From a verification point of view\, one of the most error-prone characteristics of complex DUTs is the number of simultaneous activities on multiple interfaces. Unfortunately\, there is very little awareness about the high risk this represents – not to mention all the late fixes required or\, even worse\, the escape of bugs into the customers’ products.\n\nIn this webinar\, we will explain some typical problem scenarios\, how they are handled in most projects\, and how they could be handled in a well-structured and advanced testbench – all independent of verification methodology. We will also describe how an advanced testbench can be simplified using generic testbench elements. Finally\, we will show how such a testbench could be made using UVVM\, and how this significantly improves overview\, readability\, maintainability\, extensibility\, debuggability\, and reuse.\n\nAgenda:\n\nError prone corner cases for any communication interface\nChallenges when verifying a high number of interfaces\nChallenges when verifying simultaneously active interfaces\nConnecting higher level protocols with no physical interface to the DUT\nThe structure of an advanced testbench\nComprehensive functional coverage\nScoreboards\nUVVM for advanced verification\nSolving the above using UVVM and VHDL Verification Components (VVCs)\nQ&A\n\nWebinar Duration\n\n45 min presentation/live demo\n15 min Q&A\n\nPresenter Bio: \n \nEspen Tallaksen\, CEO of EmLogic \nEspen is also the author and architect of UVVM and founder of previous Bitvis.\n\nHe has a strong interest in methodology cultivation and pragmatic efficiency and quality improvement\, and he has given many presentations at various international conferences with great feedback. He has also given courses on FPGA Design and Verification in three different continents.
URL:https://marketingeda.com/event/advanced-testbench-for-a-complex-dut-2/
CATEGORIES:EDA,Webinar
ATTACH;FMTTYPE=image/png:https://marketingeda.com/wp-content/uploads/Aldec-August-31-2023.png
END:VEVENT
BEGIN:VEVENT
DTSTART;TZID=America/Los_Angeles:20230831T110000
DTEND;TZID=America/Los_Angeles:20230831T120000
DTSTAMP:20230421T164718Z
CREATED:20230421T164718Z
LAST-MODIFIED:20230421T164718Z
UID:6311-1693479600-1693483200@marketingeda.com
SUMMARY:Advanced Testbench for a Complex DUT
DESCRIPTION:Abstract: \nFunctional simulation using an HDL testbench is the de facto method for proving functional correctness of FPGA designs. In this three-part webinar series\, we will present a step-by-step approach on how to architect a testbench – progressing from basic to advanced techniques. We will first use a simple DUT then go to a more complex DUT with simultaneous activities on multiple interfaces. \nIn the concluding part of this webinar series\, we are now ready to apply advanced verification to a complex DUT. From a verification point of view\, one of the most error-prone characteristics of complex DUTs is the number of simultaneous activities on multiple interfaces. Unfortunately\, there is very little awareness about the high risk this represents – not to mention all the late fixes required or\, even worse\, the escape of bugs into the customers’ products. \nIn this webinar\, we will explain some typical problem scenarios\, how they are handled in most projects\, and how they could be handled in a well-structured and advanced testbench – all independent of verification methodology. We will also describe how an advanced testbench can be simplified using generic testbench elements. Finally\, we will show how such a testbench could be made using UVVM\, and how this significantly improves overview\, readability\, maintainability\, extensibility\, debuggability\, and reuse. \nAgenda:\nError prone corner cases for any communication interface\nChallenges when verifying a high number of interfaces\nChallenges when verifying simultaneously active interfaces\nConnecting higher level protocols with no physical interface to the DUT\nThe structure of an advanced testbench\nComprehensive functional coverage\nScoreboards\nUVVM for advanced verification\nSolving the above using UVVM and VHDL Verification Components (VVCs)\nQ&A \nWebinar Duration\n45 min presentation/live demo\n15 min Q&A \nPresenter Bio: \nSimon Southwell has 35 years in Research and Development\, with experience in ASIC design\, FPGA\, and embedded software development. \nEspen Tallaksen\, CEO of EmLogic \nEspen is also the author and architect of UVVM and founder of previous Bitvis. \nHe has a strong interest in methodology cultivation and pragmatic efficiency and quality improvement\, and he has given many presentations at various international conferences with great feedback. He has also given courses on FPGA Design and Verification in three different continents.
URL:https://marketingeda.com/event/advanced-testbench-for-a-complex-dut/
CATEGORIES:EDA,IP,Webinar
ATTACH;FMTTYPE=image/jpeg:https://marketingeda.com/wp-content/uploads/Aldec-August-31-2023.jpg
END:VEVENT
BEGIN:VEVENT
DTSTART;TZID=America/Los_Angeles:20230831T100000
DTEND;TZID=America/Los_Angeles:20230831T110000
DTSTAMP:20230816T232407Z
CREATED:20230816T232407Z
LAST-MODIFIED:20230816T232407Z
UID:6717-1693476000-1693479600@marketingeda.com
SUMMARY:Accelerating Mainstream Adoption of Multi-Die Systems
DESCRIPTION:Synopsys recently hosted a panel discussion with Ansys\, Bosch\, Intel\, and Samsung to share their insights on the rapid adoption of multi-die systems. We invite you to the public broadcast of the panel where each company shares their view on the groundbreaking technology\, what challenges lie ahead\, and how companies can realize the promise of multi-die systems. Whether you are exploring multi-die systems or implementing the architecture in your current designs\, you’ll need the entire ecosystem across the semiconductor supply chain to help you make the adoption easier. Don’t miss the discussion. \nModerator: Marco Chiappetta\nHotTech Vision & Analysis​\nPrincipal Analyst​ \nPanelist: Murat Becer\nAnsys\nVice President\, Semiconductor R&D​ \nPanelist: Michael Schaffert\nBosch\nSenior Vice President E/E-Architecture​ \nPanelist: Lalitha Immaneni\nIntel\nVice President\, Architecture\, Design\, and Technology Solutions\, Technology Development \nPanelist: Cheolmin Park\nSamsung\nCorporate VP of AVP Business Development Team​ \nPanelist: Shekhar Kapoor\nSynopsys\nSenior Director of Product Line Management
URL:https://marketingeda.com/event/accelerating-mainstream-adoption-of-multi-die-systems/
CATEGORIES:EDA,IP,Webinar
ATTACH;FMTTYPE=image/jpeg:https://marketingeda.com/wp-content/uploads/Synopsys-August-31-203.jpg
END:VEVENT
BEGIN:VEVENT
DTSTART;TZID=America/New_York:20230830T110000
DTEND;TZID=America/New_York:20230830T120000
DTSTAMP:20230821T183724Z
CREATED:20230821T183724Z
LAST-MODIFIED:20230821T183724Z
UID:6735-1693393200-1693396800@marketingeda.com
SUMMARY:Four Important Signal Integrity Principles Demonstrated with Virtual Prototypes
DESCRIPTION:Signal integrity encompasses all the problems that arise when interconnects are not electrically transparent. One difficulty in understanding signal integrity principles is that these effects can’t be seen\, felt\, or heard. Visualizing the fields using 3D full wave simulations helps to build intuition immediately. While visualization is no substitute for understanding the electromagnetic principles at the foundation of signal integrity\, it can reinforce the understanding. \nIn this presentation\, I will offer four examples of essential principles illustrated with Ansys HFSS: signal propagation on transmission lines\, cross talk in multiple signal traces\, the impact on reflection noise and cross talk from gaps in the return path\, and the design of signal vias to reduce cross-talk and radiated emissions. \nWhat You Will Learn\n\nThe power of visualizing propagating electromagnetic fields for signal integrity applications as part of a curricula\nWhy the return path is just as important in interconnect design as the signal path\nTwo different ways of visualizing the dynamics of propagating fields as a transient simulation and the phase advance of a frequency domain simulation\nVisualizing the fields is not a substitute for understanding electromagnetics\, but it sure makes it easier\n\nWho Should Attend\nEngineering educators who are teaching courses including printed circuit design\, electromagnetics\, transmission lines\, signal integrity\, and electricity and magnetism and are looking to enhance their curricula.
URL:https://marketingeda.com/event/four-important-signal-integrity-principles-demonstrated-with-virtual-prototypes/
CATEGORIES:EDA,Webinar
ATTACH;FMTTYPE=image/jpeg:https://marketingeda.com/wp-content/uploads/Ansys-August-30-2023.jpg
END:VEVENT
BEGIN:VEVENT
DTSTART;TZID=America/Los_Angeles:20230830T110000
DTEND;TZID=America/Los_Angeles:20230830T120000
DTSTAMP:20230816T235150Z
CREATED:20230816T235150Z
LAST-MODIFIED:20230816T235150Z
UID:6724-1693393200-1693396800@marketingeda.com
SUMMARY:UCIe-Based Chiplet Verification - from IP to SoC
DESCRIPTION:Innovative die disaggregation technologies\, enable a future where a catalog of chiplets will be available to mix and match based on the end application. The industry’s fastest emerging interconnect standard called Universal Chiplet Interconnect Express (UCIe) enables end users to combine chiplets with different functionality and technology nodes to develop highly sophisticated electronic chips. Hence\, the verification topologies of such designs have exponentially increased. \nIn this webinar\, we will explore challenges and effective solutions to optimize effort and improve productivity in the verification using “Chiplet-like” reusable verification components. This caters to all possible topologies enabling continuous verification from IP to Subsystem and finally\, at the system-level.
URL:https://marketingeda.com/event/ucie-based-chiplet-verification-from-ip-to-soc/
CATEGORIES:EDA,IP,Webinar
ATTACH;FMTTYPE=image/jpeg:https://marketingeda.com/wp-content/uploads/Cadence-August-30-2023.jpg
END:VEVENT
BEGIN:VEVENT
DTSTART;TZID=America/Los_Angeles:20230829T100000
DTEND;TZID=America/Los_Angeles:20230829T110000
DTSTAMP:20230816T164837Z
CREATED:20230802T195928Z
LAST-MODIFIED:20230816T164837Z
UID:6662-1693303200-1693306800@marketingeda.com
SUMMARY:High-Speed Channel Signal Integrity Optimization
DESCRIPTION:Join our webinar as we share new optimization techniques to improve the efficiency and performance of your designs. The Optimality™ Explorer in the the Clarity™ 3D workbench allows users to navigate the design space with a panoramic view that can compensate for many years of engineering experience with an AI/ML-based optimization engine. \nDuring our webinar\, you will learn about differential pair optimization to fine-tune layout objects based on electrical or geometry parameters and control the time-domain reflects meter (TDR) impedance on your differential channel. We will also showcase a live demonstration of the Clarity 3D block in the Sigrity™ Topology Explorer (TopXp) channel and perform crosstalk optimization to get a full channel response solution faster than ever before. \nDon’t miss an excellent opportunity to gain new perspectives to help you achieve your design goals.
URL:https://marketingeda.com/event/high-speed-channel-signal-integrity-optimization/
CATEGORIES:EDA,Webinar
ATTACH;FMTTYPE=image/jpeg:https://marketingeda.com/wp-content/uploads/Cadence-August-29-2023.jpeg
END:VEVENT
BEGIN:VEVENT
DTSTART;TZID=America/Los_Angeles:20230823T100000
DTEND;TZID=America/Los_Angeles:20230823T110000
DTSTAMP:20230815T210853Z
CREATED:20230815T210838Z
LAST-MODIFIED:20230815T210853Z
UID:6706-1692784800-1692788400@marketingeda.com
SUMMARY:IP Lifecycle Management for Chiplet-Based SoCs
DESCRIPTION:Chiplet-based SoC architectures have seen increased interest over the past three years\, and recently were made a focus of the federal CHIPS and Science Act to reduce the cost of innovation for US-based semiconductor startups\, DoD projects\, and academic research. Chiplet-based architectures bring their own set of challenges however\, especially in the context of IP security. \nJoin Simon Butler\, founder of Methodics IPLM\, to learn best practices for managing IPs from inception through SoC integration\, including: \n\nEnsuring end-to-end traceability.\nManaging security concerns.\nEnforcing IP provenance.\n\nPresenters\n\n\n\n\n\n\n\n\n\n\n\nSimon Butler\n\nSimon Butler is the founder of Methodics Inc.\, acquired by Perforce in 2020. He is currently the General Manager of the Methodics IPLM business unit at Perforce. Methodics created IPLM as a new business segment in the enterprise software space to serve the needs of IP and component-based design. Simon has 30 years of IC design and EDA tool development and specializes in product strategy and design.
URL:https://marketingeda.com/event/ip-lifecycle-management-for-chiplet-based-socs/
CATEGORIES:EDA,IP,Webinar
ATTACH;FMTTYPE=image/jpeg:https://marketingeda.com/wp-content/uploads/Perforce-August-23-2023.jpg
END:VEVENT
BEGIN:VEVENT
DTSTART;TZID=America/Los_Angeles:20230823T100000
DTEND;TZID=America/Los_Angeles:20230823T110000
DTSTAMP:20230713T155945Z
CREATED:20230713T155945Z
LAST-MODIFIED:20230713T155945Z
UID:6584-1692784800-1692788400@marketingeda.com
SUMMARY:Optimize Test QoR & TTM with AI-Driven Technology
DESCRIPTION:Continuously increasing semiconductor design sizes and complexity have resulted in increased test costs. Today’s competitive environment and critical market windows are pushing companies to adopt aggressive design schedules. The traditional method of manual iterations and fine-tuning test configurations to optimize test quality-of-results (QoR) is highly unpredictable and inefficient. Engineers can no longer rely on such approaches to meet deadlines or achieve optimal results. With a global shrinking engineering workforce\, intelligent automation is needed for higher productivity and delivering first-time-right results. \n  \nThis Synopsys webinar discusses our newly introduced AI-driven test technology called Synopsys TSO.ai™– Test Space Optimization AI that dramatically minimizes test cost and time-to-market for today’s complex designs. Synopsys TSO.ai learns and converges the large ATPG search space to automatically minimize test patterns and eliminate ineffective user iterations\, enabling expert-level productivity at scale. Current engagements with leading semiconductor companies are showing an average of 20% to 25% pattern count reduction or even higher on some designs. \n\nSpeaker\n\n\nListed below is the industry leader scheduled to speak. \n\n\n\n\nRahul Singhal\n\n\nProduct Manager\nSynopsys \n\n\n\n\n\n\n\n\n\n\n\nRahul Singhal is a Product Manager for Synopsys TestMAX DFT\, Synopsys TestMAX ATPG and Test-AI products at Synopsys. His focus is on industry requirements and solutions in the areas of test compression\, test streaming solutions and ATPG. He has co-authored multiple tutorials\, papers\, posters on test in leading IEEE conferences. Rahul received his MS in Electrical Engineering from Portland State University and BS in Electrical Engineering from Purdue University.
URL:https://marketingeda.com/event/optimize-test-qor-ttm-with-ai-driven-technology/
CATEGORIES:EDA,Webinar
ATTACH;FMTTYPE=image/jpeg:https://marketingeda.com/wp-content/uploads/Synopsys-July-19-2023.jpg
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BEGIN:VEVENT
DTSTART;TZID=America/Los_Angeles:20230823T100000
DTEND;TZID=America/Los_Angeles:20230823T100000
DTSTAMP:20230811T160610Z
CREATED:20230811T160323Z
LAST-MODIFIED:20230811T160610Z
UID:6695-1692784800-1692784800@marketingeda.com
SUMMARY:Unveiling the Secrets to Proper Version Control\, Seamless Data and Tool Integration\, and Effective Collaboration
DESCRIPTION:Overview\n  \nTitle:  Unveiling the Secrets to Proper Version Control\, Seamless Data Integration\, and Effective Collaboration \nDate:  Wednesday\, August 23\, 2023 \nTime: 10:00 AM Pacific Time \nDuration:  30 minutes (+15 minutes live Q/A) \n\n\n\n\nJoin us on Wednesday\, August 23rd\, to learn how to master semiconductor design success as we unveil the secrets to proper version control\, seamless data integration\, and effective collaboration. \n  \nHere’s what you can learn: \n\nWhy maintaining proper version control and traceability will make your job easier\nHow to eliminate the data volume challenge and seamlessly integrate your tools and data\nHow to achieve effective data collaboration and communication with teams and across sites
URL:https://marketingeda.com/event/unveiling-the-secrets-to-proper/
CATEGORIES:EDA,IP,Webinar
ATTACH;FMTTYPE=image/jpeg:https://marketingeda.com/wp-content/uploads/Cliosoft-August-23-2023.jpeg
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BEGIN:VEVENT
DTSTART;TZID=America/Los_Angeles:20230822T100000
DTEND;TZID=America/Los_Angeles:20230822T110000
DTSTAMP:20230816T234252Z
CREATED:20230816T234252Z
LAST-MODIFIED:20230816T234252Z
UID:6720-1692698400-1692702000@marketingeda.com
SUMMARY:MIPI A-PHY & MASS - Revolutionizing Automotive Connectivity
DESCRIPTION:1) Intro – MASS introduction\n2) Usage – Full chip automotive systems from peripheral to processor and vice versa. E.g.Used in Radar\, LiDAR\, ADAS \, etc.\n3) APHY – PHY& Link layer for MASS\n4) PAL – Protocol adaption layer for MASS\n5) App – Application Layer For MASS like CSI2\,DSI2\, I2C\, GPIO \,Includes  FUSA  protocols like CSE\, DSE etc.\n6) VIP – Truechip MASS Verification IP Solution \n\n\n\n\nWho should attend: \n\nProfessionals working on development of  Soc/IP/VIP level of MIPI A-PHY & MASS.\nProfessionals working on verification of MIPI A-PHY & MASS at Soc/IP/VIP level or any intermediate level.\nPeople keen to know how MIPI A-PHY & MASS is shaping new era of ADAS\, ADS and other surround-sensor applications\, including cameras and in-vehicle infotainment (IVI) displays.\nFreshers in the field of VLSI industry.
URL:https://marketingeda.com/event/mipi-a-phy-mass-revolutionizing-automotive-connectivity/
CATEGORIES:IP,Webinar
ATTACH;FMTTYPE=image/jpeg:https://marketingeda.com/wp-content/uploads/Truechip-August-22-2023.jpg
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BEGIN:VEVENT
DTSTART;TZID=America/Los_Angeles:20230822T080000
DTEND;TZID=America/Los_Angeles:20230822T090000
DTSTAMP:20230728T182740Z
CREATED:20230728T182740Z
LAST-MODIFIED:20230728T182740Z
UID:6626-1692691200-1692694800@marketingeda.com
SUMMARY:Advanced Analog Design Using S-parameters
DESCRIPTION:This webinar highlights the importance of S-parameters to IC design and how Semtech Corporation\, a high-performance semiconductor\, IoT systems and Cloud connectivity service provider\, utilizes Siemens AFS XT simulation technology to accelerate Semtech’s design process without compromising on accuracy to develop differentiated analog solutions for wired and wireless applications. Two case studies of analog circuits will be discussed. \nAbstract:\nIC design is transforming at an accelerated pace along with fabrication technology. The need to incorporate more functionality has led to denser dies\, multi-die chips\, stacked 3D ICs and advanced packaging. Design technology continues to progress toward supporting higher data rates to address the increasing demand for more and enhanced connectivity. We now must deal with much more power\, ground and clock signals and their distribution on die\, between dies\, on package and on board. Signal transmission and reflection needs to be well understood to properly design for signal integrity in various signal conduits. S-parameters (scattering parameters) play a crucial part in IC design in representing passive structures and interconnects with frequency variable behavior in the RF realm. Accurate verification with these components amid large designs and sub-systems is key for first time right tapeouts\, along with a fast verification methodology that accelerates development. \nSemtech provides unique differentiation with its wired and wireless IC technology for infrastructure\, industrial\, automotive and consumer electronics applications. Semtech’s Signal Integrity Products (SIP) Group provides high performance TIAs\, CDRs\, linear equalizers and laser drivers for optical module solutions used by leading companies in hyperscale data center applications\, enterprise networking\, wireless infrastructure\, including 5G fronthaul and midhaul\, and passive optical networking/fiber-to-the-home using CMOS and BiCMOS process technologies. \nIn this webinar\, we focus on Semtech’s requirements of S-parameters for analog circuit development and how Siemens Analog FastSPICE (AFS) eXTreme technology provides differentiated performance across DC\, AC\, transient\, transient noise and RF analyses. Two case studies on 26GBd Analog Delay Line and 25Gb/s Receiver will be showcased. \nAgenda: \n\nImportance of S-parameters for IC design\nSemtech Company overview\nSemtech requirements of S-parameters\nSiemens’ Analog FastSPICE for circuit simulation\nCase Study #1 – 26GBd Analog Delay Line\nCase Study #2 – 25Gb/s Receiver\nSummary and Q&A\n\nFeatured Products: Analog FastSPICE Platform with AFS RF and AFS eXTreme Technology
URL:https://marketingeda.com/event/advanced-analog-design-using-s-parameters/
CATEGORIES:EDA,Webinar
ATTACH;FMTTYPE=image/jpeg:https://marketingeda.com/wp-content/uploads/Semtech-August-22-2023.jpg
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BEGIN:VEVENT
DTSTART;TZID=America/Los_Angeles:20230817T183000
DTEND;TZID=America/Los_Angeles:20230817T193000
DTSTAMP:20230816T225936Z
CREATED:20230816T225936Z
LAST-MODIFIED:20230816T225936Z
UID:6714-1692297000-1692300600@marketingeda.com
SUMMARY:Using Generative AI for ASIC Design
DESCRIPTION:Tools like ChatGPT can be used for a variety of purposes\, including writing Verilog. Unfortunately\, these models are not (yet) perfect\, and the quality of the output varies heavily depending on how you use them. Just as models may “hallucinate” facts they are not certain about\, they can also “hallucinate” buggy and non-functional Verilog. \nIn this presentation\, Dr. Hammond Pearce will present how he designed his team’s entry to the last Efabless AI-Generated Open-Source Silicon challenge\, with practical tips and techniques via a demo and discussion of their results: an 8-bit processor wholly designed by ChatGPT.
URL:https://marketingeda.com/event/using-generative-ai-for-asic-design/
CATEGORIES:EDA,Webinar
ATTACH;FMTTYPE=image/jpeg:https://marketingeda.com/wp-content/uploads/efabless-august-17-2023.jpg
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