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BEGIN:VEVENT
DTSTART;TZID=America/Los_Angeles:20230920T100000
DTEND;TZID=America/Los_Angeles:20230920T110000
DTSTAMP:20230919T164805Z
CREATED:20230919T164516Z
LAST-MODIFIED:20230919T164805Z
UID:6825-1695204000-1695207600@marketingeda.com
SUMMARY:Maximize Design Productivity using Vivado ML with SystemVerilog
DESCRIPTION:Although SystemVerilog is perhaps most widely used in the context of hardware verification\, it also contains many features directly relevant to FPGA hardware designers. We explore the features of SystemVerilog that are useful for RTL synthesis using Vivado™ ML Editions from AMD\, showing how the RTL SystemVerilog language constructs have been optimized for productivity and reliability. \nWe start from the basic principles of RTL coding style in SystemVerilog\, then focus on the language features that allow FPGA hardware designers to work very efficiently while at the same time avoiding synthesis pitfalls. \nContent Summary: \n\nIntroduction\nSystemVerilog in Vivado ML Editions\nModules\, ports\, parameters\, and hierarchy\nCombinational and clocked logic\nAssignments and procedures\nControl constructs and operators\nHardware-oriented data types including packages\nInterfaces and Modports\n\n\n \nMike Smith – Doulos Certified Training Instructor\, will be presenting this training webinar\, which will consist of a one-hour session and will be interactive with Q&A participation from attendees. \n\nAttendance is free of charge \nIf you have any queries\, please contact webinars@doulos.com
URL:https://marketingeda.com/event/maximize-design-productivity-using-vivado-ml-with-systemverilog/
CATEGORIES:EDA,Webinar
ATTACH;FMTTYPE=image/jpeg:https://marketingeda.com/wp-content/uploads/Doulos-September-20-2023.jpg
ORGANIZER;CN="Doulos":MAILTO:webinars@duolos.com
END:VEVENT
BEGIN:VEVENT
DTSTART;TZID=America/Los_Angeles:20230912T100000
DTEND;TZID=America/Los_Angeles:20230912T110000
DTSTAMP:20230829T220653Z
CREATED:20230829T220628Z
LAST-MODIFIED:20230829T220653Z
UID:6759-1694512800-1694516400@marketingeda.com
SUMMARY:NoC IP- Transforming Chip Communication
DESCRIPTION:Webinar Agenda : \n\nIntroduction to Mesh and Crossbar Architecture\nCache Introduction\nSupport for latest AMBA 5\nSafety and security features as ASIL Standard.\nPort configurabilities\n\nWho Should Attend: \n\nProfessionals working on development of NoC IP.\nPeople keen to know how NoC IP is shaping new era of chiplet communications\nFreshers in the field of VLSI industry.
URL:https://marketingeda.com/event/noc-ip-transforming-chip-communication/
CATEGORIES:IP,Webinar
ATTACH;FMTTYPE=image/jpeg:https://marketingeda.com/wp-content/uploads/Webinar-Series-NoC-IP-01_02.jpg
END:VEVENT
BEGIN:VEVENT
DTSTART;TZID=America/Los_Angeles:20230907T110000
DTEND;TZID=America/Los_Angeles:20230907T120000
DTSTAMP:20230801T172801Z
CREATED:20230801T172801Z
LAST-MODIFIED:20230801T172801Z
UID:6639-1694084400-1694088000@marketingeda.com
SUMMARY:FPGA Design Verification - Planning
DESCRIPTION:As FPGA technology continues to evolve – to provide us with full-blown SoCs with CPU\, GPU\, and high-speed peripherals\, for example\, joining the traditional programmable logic area – design verification becomes increasingly challenging. Lab-based FPGA testing and bring-up alone are clearly insufficient\, especially for safety-critical designs\, and FPGA teams are adopting advanced design verification methodologies and techniques to develop homegrown verification processes. \n  \nIn this three-part webinar series\, we will discuss design verification with a focus on creating an advanced simulation-based verification process; from verification planning and team organization\, and moving on to regression setup\, functional coverage collection\, randomization and ‘verification done’ definitions. We will also show you how to develop simple yet powerful and reusable testbenches using Verilog and SystemVerilog constructs and how to functionally verify designs in the most efficient way. \n  \nIn part 1 of this webinar series\, we will provide an overview of advanced simulation-based verification process and outline the differences between ASIC and FPGA-centric verification processes. Then\, we will show you how to develop a verification plan; describing WHAT to verify and HOW to verify it. Finally\, we will talk about design verification of highly configurable design and IP blocks. \n  \nAgenda: \n\nASIC Verification vs FPGA Verification\nFPGA-specific Design Verification Project Constraints\nOverview of Design Verification Stages\nOrganizing FPGA Teams\nDesign Verification Methods\nStimulus and Checker Types\nBlock\, Subsystem and System-Level\nVerification Plan Structure\nSetting Design Verification goals (WHAT)\nExtracting Design Properties\nSetting Priorities\nDefining Verification Methods\, Types and Levels (HOW)\nDefining Test Scenario\nWorking with Configurable Designs\nDemo with example design and testbench\nConclusion\nQ&A\n\n  \nWebinar Duration: \n\n45 min presentation/live demo\n15 min Q&A\n\n  \nPresenter BIO \nAlexander Gnusin\, Design Verification Technologist\, Aldec \nAlexander Gnusin accumulated 27 years of hands-on experience in various aspects of ASIC and FPGA design and verification. As a verification prime for a multi-million gates project in companies such as IBM\, Nortel\, Ericsson and Synopsys Inc\, he combined various verification methods such as static linting\, formal property checking\, dynamic simulation and hardware-assisted acceleration to efficiently achieve design verification goals. He received his M.S. in Electronics from Technion\, Israel Institute of Technology.
URL:https://marketingeda.com/event/fpga-design-verification-planning/
CATEGORIES:EDA,Webinar
ATTACH;FMTTYPE=image/jpeg:https://marketingeda.com/wp-content/uploads/Aldex-Verification.jpg
END:VEVENT
BEGIN:VEVENT
DTSTART;TZID=Asia/Jerusalem:20230906T150000
DTEND;TZID=Asia/Jerusalem:20230906T170000
DTSTAMP:20230901T163554Z
CREATED:20230901T163554Z
LAST-MODIFIED:20230901T163554Z
UID:6767-1694012400-1694019600@marketingeda.com
SUMMARY:SemIsrael Tech Webinar
DESCRIPTION:Venkata Subba Reddy Khambam\nSenior Technical ManagerSmartSoC Solutions \nThe Rise of Embedded AI: Transforming Industries and Enhancing User Experience\n\n\nEmbedded AI has become a transformative force in various industries\, revolutionizing the way we interact with technology and improving user experiences. This abstract explores the significance\, benefits\, and impact of embedded AI in sectors such as healthcare\, automotive\, manufacturing\, and consumer electronics. It also discusses the challenges and ethical considerations associated with embedded AI\, emphasizing the need for responsible development and deployment. The growing influence ofembedded AI has the potential to shape the future of technology and human interaction\, making it an essential area of study and innovation. \n\nBill Jenkins\nDirector AI Product Marketing\nAchronix \n\nHarnessing the Power of FPGAs for Ultra-Low Latency Streaming\n\n\nJoin us for a webinar on revolutionizing edge applications with real-time video and audio stream processing. Discover how FPGA technology empowers you to customize data paths\, enabling high performance with unparalleled low latency. Using conversational AI as a captivating case study\, we will delve into the transformative potential of FPGAs\, catering to the needs of engineers and industry decision-makers alike. Don’t miss this opportunity to explore cutting-edge solutions for ultra-low latency real-time streaming AI at the edge. \n\nGordon Allan\nProduct Manager\, Verification IP\nSiemens EDA \n\nSiemens + Avery – Building Better Verification IP\n\n\nSiemens EDA Verification experts describe our comprehensive Verification IP solutions for SoC and 3DIC projects in the Datacenter\, Storage\, 3DIC\, Networking\, Automotive\, Mil/Aero and other applications\, introducing our complete portfolio incorporating the recently acquired Avery Verification IP solutions. \n\nLarry Lapides\nVP Worldwide SalesImperas Software \n\nVirtual Platforms Accelerate RISC-V SoC Software Development\n\n\nThe design freedoms of RISC-V offer systems and SoC developers new flexibility to build domain specific processors\, optimized for the requirements of the target application and domain. This is driving the growing adoption of RISC-V\, however\, software is still needed on these new platforms. This could be entirely new software\, or porting legacy applications\, firmware\, libraries and operating systems to the RISC-V platform. Virtual platforms\, or software simulation\, can accelerate software tasks by providing an environment for software development\, debug and test many months before silicon is available. While virtual platforms do not replace hardware-based testing of the software\, the early availability\, ease of automation\, controllability and observability are making virtual platforms a must-have for embedded software development. This presentation will discuss the various models and tools that comprise a successful virtual platform environment\, and provide case studies in automotive\, DSP and AI/ML.
URL:https://marketingeda.com/event/semisrael-tech-webinar-6/
CATEGORIES:EDA,Webinar
ATTACH;FMTTYPE=image/jpeg:https://marketingeda.com/wp-content/uploads/SemIsrael-September-5-2023.jpg
END:VEVENT
BEGIN:VEVENT
DTSTART;TZID=America/Los_Angeles:20230906T100000
DTEND;TZID=America/Los_Angeles:20230906T110000
DTSTAMP:20230829T215426Z
CREATED:20230829T215426Z
LAST-MODIFIED:20230829T215426Z
UID:6756-1693994400-1693998000@marketingeda.com
SUMMARY:Everything You Need to Know about SystemVerilog Arrays
DESCRIPTION:This webinar gives a comprehensive guide to all aspects of SystemVerilog arrays: ordinary static arrays\, dynamic arrays\, queues and associative arrays. It also includes array methods and practical examples. \nTopics: \n\nReview of Verilog array types\nSystemVerilog packed and unpacked arrays\nSystemVerilog dynamic arrays\nSystemVerilog queues\nSystemVerilog associate arrays\nArray manipulation methods.\n\nCoding examples are shown running on Synopsys VCS and you can try out the examples yourself after the webinar on EDA Playground. \n\n\n\n\n\n\nBrian Jensen \, a Certified Training Instructor for Doulos\, will present this training webinar\, which will consist of a one-hour presentation with interactive Q&A available to attendees throughout. \n\n\n\n\n\nAttendance is free of charge \nIf you have any queries\, please contact webinars@doulos.com
URL:https://marketingeda.com/event/everything-you-need-to-know-about-systemverilog-arrays-2/
CATEGORIES:EDA,Webinar
ATTACH;FMTTYPE=image/jpeg:https://marketingeda.com/wp-content/uploads/Doulos-September-6-2023.jpg
ORGANIZER;CN="Doulos":MAILTO:webinars@duolos.com
END:VEVENT
BEGIN:VEVENT
DTSTART;TZID=Europe/London:20230905T120000
DTEND;TZID=Europe/London:20230905T130000
DTSTAMP:20230801T174617Z
CREATED:20230801T174617Z
LAST-MODIFIED:20230801T174617Z
UID:6648-1693915200-1693918800@marketingeda.com
SUMMARY:DVClub Europe - Cache Coherency Verification
DESCRIPTION:This is to inform you that the next DVClub Europe meeting takes place on Tuesday 05th September with a theme of “Cache Coherency Verification”.\n\nSoC cache coherency verification is one of the most complex challenges faced by verification engineers. And the introduction of the embedded L3 cache and the increasing number of cores in CPU clusters ais making it even more challenging. In this DVClub we will focus on how this challenge can be best approached and some automation added.\n\nAgenda (BST) \n12:00   Welcome and Introduction – Mike Bartley\, Senior Vice President – VLSI Design\, Tessolve\n12:00    David Kelf\, Breker Verification Systems\n12:20    Sponsor Speaker\n12:40    Sponsor Speaker\n13:00    Close \n  \nRegister now to become a part of this event. Free to attend online. \nEventbrite – DVClub Europe  \nBest Regards \nMike Bartley\, Senior Vice President – VLSI Design\, Tessolve
URL:https://marketingeda.com/event/dvclub-europe-cache-coherency-verification/
CATEGORIES:EDA,Webinar
ATTACH;FMTTYPE=image/png:https://marketingeda.com/wp-content/uploads/DVClub-Europe-September-5-2023.png
END:VEVENT
BEGIN:VEVENT
DTSTART;TZID=America/Los_Angeles:20230831T110000
DTEND;TZID=America/Los_Angeles:20230831T120000
DTSTAMP:20230829T205052Z
CREATED:20230829T205052Z
LAST-MODIFIED:20230829T205052Z
UID:6753-1693479600-1693483200@marketingeda.com
SUMMARY:Advanced Testbench for a Complex DUT
DESCRIPTION:Functional simulation using an HDL testbench is the de facto method for proving functional correctness of FPGA designs. In this three-part webinar series\, we will present a step-by-step approach on how to architect a testbench – progressing from basic to advanced techniques. We will first use a simple DUT then go to a more complex DUT with simultaneous activities on multiple interfaces. \nIn the concluding part of this webinar series\, we are now ready to apply advanced verification to a complex DUT. From a verification point of view\, one of the most error-prone characteristics of complex DUTs is the number of simultaneous activities on multiple interfaces. Unfortunately\, there is very little awareness about the high risk this represents – not to mention all the late fixes required or\, even worse\, the escape of bugs into the customers’ products.\n\nIn this webinar\, we will explain some typical problem scenarios\, how they are handled in most projects\, and how they could be handled in a well-structured and advanced testbench – all independent of verification methodology. We will also describe how an advanced testbench can be simplified using generic testbench elements. Finally\, we will show how such a testbench could be made using UVVM\, and how this significantly improves overview\, readability\, maintainability\, extensibility\, debuggability\, and reuse.\n\nAgenda:\n\nError prone corner cases for any communication interface\nChallenges when verifying a high number of interfaces\nChallenges when verifying simultaneously active interfaces\nConnecting higher level protocols with no physical interface to the DUT\nThe structure of an advanced testbench\nComprehensive functional coverage\nScoreboards\nUVVM for advanced verification\nSolving the above using UVVM and VHDL Verification Components (VVCs)\nQ&A\n\nWebinar Duration\n\n45 min presentation/live demo\n15 min Q&A\n\nPresenter Bio: \n \nEspen Tallaksen\, CEO of EmLogic \nEspen is also the author and architect of UVVM and founder of previous Bitvis.\n\nHe has a strong interest in methodology cultivation and pragmatic efficiency and quality improvement\, and he has given many presentations at various international conferences with great feedback. He has also given courses on FPGA Design and Verification in three different continents.
URL:https://marketingeda.com/event/advanced-testbench-for-a-complex-dut-2/
CATEGORIES:EDA,Webinar
ATTACH;FMTTYPE=image/png:https://marketingeda.com/wp-content/uploads/Aldec-August-31-2023.png
END:VEVENT
BEGIN:VEVENT
DTSTART;TZID=America/Los_Angeles:20230831T110000
DTEND;TZID=America/Los_Angeles:20230831T120000
DTSTAMP:20230421T164718Z
CREATED:20230421T164718Z
LAST-MODIFIED:20230421T164718Z
UID:6311-1693479600-1693483200@marketingeda.com
SUMMARY:Advanced Testbench for a Complex DUT
DESCRIPTION:Abstract: \nFunctional simulation using an HDL testbench is the de facto method for proving functional correctness of FPGA designs. In this three-part webinar series\, we will present a step-by-step approach on how to architect a testbench – progressing from basic to advanced techniques. We will first use a simple DUT then go to a more complex DUT with simultaneous activities on multiple interfaces. \nIn the concluding part of this webinar series\, we are now ready to apply advanced verification to a complex DUT. From a verification point of view\, one of the most error-prone characteristics of complex DUTs is the number of simultaneous activities on multiple interfaces. Unfortunately\, there is very little awareness about the high risk this represents – not to mention all the late fixes required or\, even worse\, the escape of bugs into the customers’ products. \nIn this webinar\, we will explain some typical problem scenarios\, how they are handled in most projects\, and how they could be handled in a well-structured and advanced testbench – all independent of verification methodology. We will also describe how an advanced testbench can be simplified using generic testbench elements. Finally\, we will show how such a testbench could be made using UVVM\, and how this significantly improves overview\, readability\, maintainability\, extensibility\, debuggability\, and reuse. \nAgenda:\nError prone corner cases for any communication interface\nChallenges when verifying a high number of interfaces\nChallenges when verifying simultaneously active interfaces\nConnecting higher level protocols with no physical interface to the DUT\nThe structure of an advanced testbench\nComprehensive functional coverage\nScoreboards\nUVVM for advanced verification\nSolving the above using UVVM and VHDL Verification Components (VVCs)\nQ&A \nWebinar Duration\n45 min presentation/live demo\n15 min Q&A \nPresenter Bio: \nSimon Southwell has 35 years in Research and Development\, with experience in ASIC design\, FPGA\, and embedded software development. \nEspen Tallaksen\, CEO of EmLogic \nEspen is also the author and architect of UVVM and founder of previous Bitvis. \nHe has a strong interest in methodology cultivation and pragmatic efficiency and quality improvement\, and he has given many presentations at various international conferences with great feedback. He has also given courses on FPGA Design and Verification in three different continents.
URL:https://marketingeda.com/event/advanced-testbench-for-a-complex-dut/
CATEGORIES:EDA,IP,Webinar
ATTACH;FMTTYPE=image/jpeg:https://marketingeda.com/wp-content/uploads/Aldec-August-31-2023.jpg
END:VEVENT
BEGIN:VEVENT
DTSTART;TZID=America/Los_Angeles:20230831T100000
DTEND;TZID=America/Los_Angeles:20230831T110000
DTSTAMP:20230816T232407Z
CREATED:20230816T232407Z
LAST-MODIFIED:20230816T232407Z
UID:6717-1693476000-1693479600@marketingeda.com
SUMMARY:Accelerating Mainstream Adoption of Multi-Die Systems
DESCRIPTION:Synopsys recently hosted a panel discussion with Ansys\, Bosch\, Intel\, and Samsung to share their insights on the rapid adoption of multi-die systems. We invite you to the public broadcast of the panel where each company shares their view on the groundbreaking technology\, what challenges lie ahead\, and how companies can realize the promise of multi-die systems. Whether you are exploring multi-die systems or implementing the architecture in your current designs\, you’ll need the entire ecosystem across the semiconductor supply chain to help you make the adoption easier. Don’t miss the discussion. \nModerator: Marco Chiappetta\nHotTech Vision & Analysis​\nPrincipal Analyst​ \nPanelist: Murat Becer\nAnsys\nVice President\, Semiconductor R&D​ \nPanelist: Michael Schaffert\nBosch\nSenior Vice President E/E-Architecture​ \nPanelist: Lalitha Immaneni\nIntel\nVice President\, Architecture\, Design\, and Technology Solutions\, Technology Development \nPanelist: Cheolmin Park\nSamsung\nCorporate VP of AVP Business Development Team​ \nPanelist: Shekhar Kapoor\nSynopsys\nSenior Director of Product Line Management
URL:https://marketingeda.com/event/accelerating-mainstream-adoption-of-multi-die-systems/
CATEGORIES:EDA,IP,Webinar
ATTACH;FMTTYPE=image/jpeg:https://marketingeda.com/wp-content/uploads/Synopsys-August-31-203.jpg
END:VEVENT
BEGIN:VEVENT
DTSTART;TZID=America/New_York:20230830T110000
DTEND;TZID=America/New_York:20230830T120000
DTSTAMP:20230821T183724Z
CREATED:20230821T183724Z
LAST-MODIFIED:20230821T183724Z
UID:6735-1693393200-1693396800@marketingeda.com
SUMMARY:Four Important Signal Integrity Principles Demonstrated with Virtual Prototypes
DESCRIPTION:Signal integrity encompasses all the problems that arise when interconnects are not electrically transparent. One difficulty in understanding signal integrity principles is that these effects can’t be seen\, felt\, or heard. Visualizing the fields using 3D full wave simulations helps to build intuition immediately. While visualization is no substitute for understanding the electromagnetic principles at the foundation of signal integrity\, it can reinforce the understanding. \nIn this presentation\, I will offer four examples of essential principles illustrated with Ansys HFSS: signal propagation on transmission lines\, cross talk in multiple signal traces\, the impact on reflection noise and cross talk from gaps in the return path\, and the design of signal vias to reduce cross-talk and radiated emissions. \nWhat You Will Learn\n\nThe power of visualizing propagating electromagnetic fields for signal integrity applications as part of a curricula\nWhy the return path is just as important in interconnect design as the signal path\nTwo different ways of visualizing the dynamics of propagating fields as a transient simulation and the phase advance of a frequency domain simulation\nVisualizing the fields is not a substitute for understanding electromagnetics\, but it sure makes it easier\n\nWho Should Attend\nEngineering educators who are teaching courses including printed circuit design\, electromagnetics\, transmission lines\, signal integrity\, and electricity and magnetism and are looking to enhance their curricula.
URL:https://marketingeda.com/event/four-important-signal-integrity-principles-demonstrated-with-virtual-prototypes/
CATEGORIES:EDA,Webinar
ATTACH;FMTTYPE=image/jpeg:https://marketingeda.com/wp-content/uploads/Ansys-August-30-2023.jpg
END:VEVENT
BEGIN:VEVENT
DTSTART;TZID=America/Los_Angeles:20230830T110000
DTEND;TZID=America/Los_Angeles:20230830T120000
DTSTAMP:20230816T235150Z
CREATED:20230816T235150Z
LAST-MODIFIED:20230816T235150Z
UID:6724-1693393200-1693396800@marketingeda.com
SUMMARY:UCIe-Based Chiplet Verification - from IP to SoC
DESCRIPTION:Innovative die disaggregation technologies\, enable a future where a catalog of chiplets will be available to mix and match based on the end application. The industry’s fastest emerging interconnect standard called Universal Chiplet Interconnect Express (UCIe) enables end users to combine chiplets with different functionality and technology nodes to develop highly sophisticated electronic chips. Hence\, the verification topologies of such designs have exponentially increased. \nIn this webinar\, we will explore challenges and effective solutions to optimize effort and improve productivity in the verification using “Chiplet-like” reusable verification components. This caters to all possible topologies enabling continuous verification from IP to Subsystem and finally\, at the system-level.
URL:https://marketingeda.com/event/ucie-based-chiplet-verification-from-ip-to-soc/
CATEGORIES:EDA,IP,Webinar
ATTACH;FMTTYPE=image/jpeg:https://marketingeda.com/wp-content/uploads/Cadence-August-30-2023.jpg
END:VEVENT
BEGIN:VEVENT
DTSTART;TZID=America/Los_Angeles:20230829T100000
DTEND;TZID=America/Los_Angeles:20230829T110000
DTSTAMP:20230816T164837Z
CREATED:20230802T195928Z
LAST-MODIFIED:20230816T164837Z
UID:6662-1693303200-1693306800@marketingeda.com
SUMMARY:High-Speed Channel Signal Integrity Optimization
DESCRIPTION:Join our webinar as we share new optimization techniques to improve the efficiency and performance of your designs. The Optimality™ Explorer in the the Clarity™ 3D workbench allows users to navigate the design space with a panoramic view that can compensate for many years of engineering experience with an AI/ML-based optimization engine. \nDuring our webinar\, you will learn about differential pair optimization to fine-tune layout objects based on electrical or geometry parameters and control the time-domain reflects meter (TDR) impedance on your differential channel. We will also showcase a live demonstration of the Clarity 3D block in the Sigrity™ Topology Explorer (TopXp) channel and perform crosstalk optimization to get a full channel response solution faster than ever before. \nDon’t miss an excellent opportunity to gain new perspectives to help you achieve your design goals.
URL:https://marketingeda.com/event/high-speed-channel-signal-integrity-optimization/
CATEGORIES:EDA,Webinar
ATTACH;FMTTYPE=image/jpeg:https://marketingeda.com/wp-content/uploads/Cadence-August-29-2023.jpeg
END:VEVENT
BEGIN:VEVENT
DTSTART;TZID=America/Los_Angeles:20230823T100000
DTEND;TZID=America/Los_Angeles:20230823T110000
DTSTAMP:20230815T210853Z
CREATED:20230815T210838Z
LAST-MODIFIED:20230815T210853Z
UID:6706-1692784800-1692788400@marketingeda.com
SUMMARY:IP Lifecycle Management for Chiplet-Based SoCs
DESCRIPTION:Chiplet-based SoC architectures have seen increased interest over the past three years\, and recently were made a focus of the federal CHIPS and Science Act to reduce the cost of innovation for US-based semiconductor startups\, DoD projects\, and academic research. Chiplet-based architectures bring their own set of challenges however\, especially in the context of IP security. \nJoin Simon Butler\, founder of Methodics IPLM\, to learn best practices for managing IPs from inception through SoC integration\, including: \n\nEnsuring end-to-end traceability.\nManaging security concerns.\nEnforcing IP provenance.\n\nPresenters\n\n\n\n\n\n\n\n\n\n\n\nSimon Butler\n\nSimon Butler is the founder of Methodics Inc.\, acquired by Perforce in 2020. He is currently the General Manager of the Methodics IPLM business unit at Perforce. Methodics created IPLM as a new business segment in the enterprise software space to serve the needs of IP and component-based design. Simon has 30 years of IC design and EDA tool development and specializes in product strategy and design.
URL:https://marketingeda.com/event/ip-lifecycle-management-for-chiplet-based-socs/
CATEGORIES:EDA,IP,Webinar
ATTACH;FMTTYPE=image/jpeg:https://marketingeda.com/wp-content/uploads/Perforce-August-23-2023.jpg
END:VEVENT
BEGIN:VEVENT
DTSTART;TZID=America/Los_Angeles:20230823T100000
DTEND;TZID=America/Los_Angeles:20230823T110000
DTSTAMP:20230713T155945Z
CREATED:20230713T155945Z
LAST-MODIFIED:20230713T155945Z
UID:6584-1692784800-1692788400@marketingeda.com
SUMMARY:Optimize Test QoR & TTM with AI-Driven Technology
DESCRIPTION:Continuously increasing semiconductor design sizes and complexity have resulted in increased test costs. Today’s competitive environment and critical market windows are pushing companies to adopt aggressive design schedules. The traditional method of manual iterations and fine-tuning test configurations to optimize test quality-of-results (QoR) is highly unpredictable and inefficient. Engineers can no longer rely on such approaches to meet deadlines or achieve optimal results. With a global shrinking engineering workforce\, intelligent automation is needed for higher productivity and delivering first-time-right results. \n  \nThis Synopsys webinar discusses our newly introduced AI-driven test technology called Synopsys TSO.ai™– Test Space Optimization AI that dramatically minimizes test cost and time-to-market for today’s complex designs. Synopsys TSO.ai learns and converges the large ATPG search space to automatically minimize test patterns and eliminate ineffective user iterations\, enabling expert-level productivity at scale. Current engagements with leading semiconductor companies are showing an average of 20% to 25% pattern count reduction or even higher on some designs. \n\nSpeaker\n\n\nListed below is the industry leader scheduled to speak. \n\n\n\n\nRahul Singhal\n\n\nProduct Manager\nSynopsys \n\n\n\n\n\n\n\n\n\n\n\nRahul Singhal is a Product Manager for Synopsys TestMAX DFT\, Synopsys TestMAX ATPG and Test-AI products at Synopsys. His focus is on industry requirements and solutions in the areas of test compression\, test streaming solutions and ATPG. He has co-authored multiple tutorials\, papers\, posters on test in leading IEEE conferences. Rahul received his MS in Electrical Engineering from Portland State University and BS in Electrical Engineering from Purdue University.
URL:https://marketingeda.com/event/optimize-test-qor-ttm-with-ai-driven-technology/
CATEGORIES:EDA,Webinar
ATTACH;FMTTYPE=image/jpeg:https://marketingeda.com/wp-content/uploads/Synopsys-July-19-2023.jpg
END:VEVENT
BEGIN:VEVENT
DTSTART;TZID=America/Los_Angeles:20230823T100000
DTEND;TZID=America/Los_Angeles:20230823T100000
DTSTAMP:20230811T160610Z
CREATED:20230811T160323Z
LAST-MODIFIED:20230811T160610Z
UID:6695-1692784800-1692784800@marketingeda.com
SUMMARY:Unveiling the Secrets to Proper Version Control\, Seamless Data and Tool Integration\, and Effective Collaboration
DESCRIPTION:Overview\n  \nTitle:  Unveiling the Secrets to Proper Version Control\, Seamless Data Integration\, and Effective Collaboration \nDate:  Wednesday\, August 23\, 2023 \nTime: 10:00 AM Pacific Time \nDuration:  30 minutes (+15 minutes live Q/A) \n\n\n\n\nJoin us on Wednesday\, August 23rd\, to learn how to master semiconductor design success as we unveil the secrets to proper version control\, seamless data integration\, and effective collaboration. \n  \nHere’s what you can learn: \n\nWhy maintaining proper version control and traceability will make your job easier\nHow to eliminate the data volume challenge and seamlessly integrate your tools and data\nHow to achieve effective data collaboration and communication with teams and across sites
URL:https://marketingeda.com/event/unveiling-the-secrets-to-proper/
CATEGORIES:EDA,IP,Webinar
ATTACH;FMTTYPE=image/jpeg:https://marketingeda.com/wp-content/uploads/Cliosoft-August-23-2023.jpeg
END:VEVENT
BEGIN:VEVENT
DTSTART;TZID=America/Los_Angeles:20230822T100000
DTEND;TZID=America/Los_Angeles:20230822T110000
DTSTAMP:20230816T234252Z
CREATED:20230816T234252Z
LAST-MODIFIED:20230816T234252Z
UID:6720-1692698400-1692702000@marketingeda.com
SUMMARY:MIPI A-PHY & MASS - Revolutionizing Automotive Connectivity
DESCRIPTION:1) Intro – MASS introduction\n2) Usage – Full chip automotive systems from peripheral to processor and vice versa. E.g.Used in Radar\, LiDAR\, ADAS \, etc.\n3) APHY – PHY& Link layer for MASS\n4) PAL – Protocol adaption layer for MASS\n5) App – Application Layer For MASS like CSI2\,DSI2\, I2C\, GPIO \,Includes  FUSA  protocols like CSE\, DSE etc.\n6) VIP – Truechip MASS Verification IP Solution \n\n\n\n\nWho should attend: \n\nProfessionals working on development of  Soc/IP/VIP level of MIPI A-PHY & MASS.\nProfessionals working on verification of MIPI A-PHY & MASS at Soc/IP/VIP level or any intermediate level.\nPeople keen to know how MIPI A-PHY & MASS is shaping new era of ADAS\, ADS and other surround-sensor applications\, including cameras and in-vehicle infotainment (IVI) displays.\nFreshers in the field of VLSI industry.
URL:https://marketingeda.com/event/mipi-a-phy-mass-revolutionizing-automotive-connectivity/
CATEGORIES:IP,Webinar
ATTACH;FMTTYPE=image/jpeg:https://marketingeda.com/wp-content/uploads/Truechip-August-22-2023.jpg
END:VEVENT
BEGIN:VEVENT
DTSTART;TZID=America/Los_Angeles:20230822T080000
DTEND;TZID=America/Los_Angeles:20230822T090000
DTSTAMP:20230728T182740Z
CREATED:20230728T182740Z
LAST-MODIFIED:20230728T182740Z
UID:6626-1692691200-1692694800@marketingeda.com
SUMMARY:Advanced Analog Design Using S-parameters
DESCRIPTION:This webinar highlights the importance of S-parameters to IC design and how Semtech Corporation\, a high-performance semiconductor\, IoT systems and Cloud connectivity service provider\, utilizes Siemens AFS XT simulation technology to accelerate Semtech’s design process without compromising on accuracy to develop differentiated analog solutions for wired and wireless applications. Two case studies of analog circuits will be discussed. \nAbstract:\nIC design is transforming at an accelerated pace along with fabrication technology. The need to incorporate more functionality has led to denser dies\, multi-die chips\, stacked 3D ICs and advanced packaging. Design technology continues to progress toward supporting higher data rates to address the increasing demand for more and enhanced connectivity. We now must deal with much more power\, ground and clock signals and their distribution on die\, between dies\, on package and on board. Signal transmission and reflection needs to be well understood to properly design for signal integrity in various signal conduits. S-parameters (scattering parameters) play a crucial part in IC design in representing passive structures and interconnects with frequency variable behavior in the RF realm. Accurate verification with these components amid large designs and sub-systems is key for first time right tapeouts\, along with a fast verification methodology that accelerates development. \nSemtech provides unique differentiation with its wired and wireless IC technology for infrastructure\, industrial\, automotive and consumer electronics applications. Semtech’s Signal Integrity Products (SIP) Group provides high performance TIAs\, CDRs\, linear equalizers and laser drivers for optical module solutions used by leading companies in hyperscale data center applications\, enterprise networking\, wireless infrastructure\, including 5G fronthaul and midhaul\, and passive optical networking/fiber-to-the-home using CMOS and BiCMOS process technologies. \nIn this webinar\, we focus on Semtech’s requirements of S-parameters for analog circuit development and how Siemens Analog FastSPICE (AFS) eXTreme technology provides differentiated performance across DC\, AC\, transient\, transient noise and RF analyses. Two case studies on 26GBd Analog Delay Line and 25Gb/s Receiver will be showcased. \nAgenda: \n\nImportance of S-parameters for IC design\nSemtech Company overview\nSemtech requirements of S-parameters\nSiemens’ Analog FastSPICE for circuit simulation\nCase Study #1 – 26GBd Analog Delay Line\nCase Study #2 – 25Gb/s Receiver\nSummary and Q&A\n\nFeatured Products: Analog FastSPICE Platform with AFS RF and AFS eXTreme Technology
URL:https://marketingeda.com/event/advanced-analog-design-using-s-parameters/
CATEGORIES:EDA,Webinar
ATTACH;FMTTYPE=image/jpeg:https://marketingeda.com/wp-content/uploads/Semtech-August-22-2023.jpg
END:VEVENT
BEGIN:VEVENT
DTSTART;TZID=America/Los_Angeles:20230817T183000
DTEND;TZID=America/Los_Angeles:20230817T193000
DTSTAMP:20230816T225936Z
CREATED:20230816T225936Z
LAST-MODIFIED:20230816T225936Z
UID:6714-1692297000-1692300600@marketingeda.com
SUMMARY:Using Generative AI for ASIC Design
DESCRIPTION:Tools like ChatGPT can be used for a variety of purposes\, including writing Verilog. Unfortunately\, these models are not (yet) perfect\, and the quality of the output varies heavily depending on how you use them. Just as models may “hallucinate” facts they are not certain about\, they can also “hallucinate” buggy and non-functional Verilog. \nIn this presentation\, Dr. Hammond Pearce will present how he designed his team’s entry to the last Efabless AI-Generated Open-Source Silicon challenge\, with practical tips and techniques via a demo and discussion of their results: an 8-bit processor wholly designed by ChatGPT.
URL:https://marketingeda.com/event/using-generative-ai-for-asic-design/
CATEGORIES:EDA,Webinar
ATTACH;FMTTYPE=image/jpeg:https://marketingeda.com/wp-content/uploads/efabless-august-17-2023.jpg
END:VEVENT
BEGIN:VEVENT
DTSTART;TZID=America/Los_Angeles:20230815T100000
DTEND;TZID=America/Los_Angeles:20230815T110000
DTSTAMP:20230804T163719Z
CREATED:20230804T163719Z
LAST-MODIFIED:20230804T163719Z
UID:6680-1692093600-1692097200@marketingeda.com
SUMMARY:UCIe: On-Package Chiplet Innovation Opportunities
DESCRIPTION:High-performance workloads demand on-package integration of heterogeneous processing units\, on-package memory\, and communication infrastructure to meet the demands of today’s data centers\, autonomous vehicles\, etc. On-package interconnects are a critical component to deliver the power-efficient performance for this evolving landscape. \nUniversal Chiplet Interconnect Express (UCIe)\, is an open industry standard with a fully specified stack that comprehends plug-and-play interoperability of chiplets on a package; In this webinar\, we will discuss the usages\, key metrics and the silicon health associated with different technology choices in UCIe and how it will evolve going forward. We will also delve into the challenges and opportunities for chiplets connected through UCIe\, including production test\, repair and in-field silicon lifecycle management. \n\n\n\n\n\n\n\n\n\n\nSpeakers\n\n\nListed below are the industry leaders scheduled to speak. \n\n\n\n\n\n\n\n\n\n\n\n\n\n\n\n\n\n\n\n\n\n\n\n\n\n\nDr. Debendra Das Sharma\n\n\nSenior Fellow\, co-GM Memory and I/O Technologies\nIntel \n\n\n\n\n\n\n\n\n\n\n\nDr. Das Sharma is an Intel Senior Fellow and co-GM of Memory and I/O Technologies at the Data Platforms and AI Group\, Intel Corporation. He is a co-inventor and founding member of the CXL and UCIe consortia\, Chair of UCIe Consortium\, Co-lead of the CXL Board Technical Task Force and member of the Board of Directors of PCI-SIG. He holds 160+ US patents. A Senior Member of IEEE\, Dr. Das Sharma has been awarded the 2019 Distinguished Alumnus Award by IIT\, the 2021 IEEE Region Engineer of the Year Award\, the 2022 PCI-SIG Lifetime Contribution Award\, and the 2022 IEEE CAS Industrial Pioneer Award. \n\n\n\n\n\n\n\n\n\n\n\n\n\n\n\n\n\n\n\n\n\n\n\n\n\n\n\n\n\n\n\nDr. Yervant Zorian\n\n\nChief Architect & Fellow\, Silicon Lifecycle Management\nSynopsys\, Inc. \n\n\n\n\n\n\n\n\n\n\n\nDr. Zorian is a Chief Architect and Fellow at Synopsys\, as well as President of Synopsys Armenia. He is President of IEEE Test Technology Technical Council (TTTC)\, the Founder of IEEE 1500 Standardization Working Group\, and General Chair of the 50th Design Automation Conference (DAC) and 50th International Test Conference (ITC). He authored 5 books\, 400 referred papers\, and holds 45 US patents. A Fellow of IEEE\, Dr. Zorian has been the recipient of 2005 IEEE CAS Industrial Pioneer Award\, 2006 IEEE Hans Karlsson Award\, 2014 Republic of Armenia’s National Medal of Science\, and 2022 IEEE TTTC Lifetime Contribution Medal.
URL:https://marketingeda.com/event/ucie-on-package-chiplet-innovation-opportunities/
CATEGORIES:EDA,Webinar
ATTACH;FMTTYPE=image/jpeg:https://marketingeda.com/wp-content/uploads/Synopsys-August-15-2023.jpg
END:VEVENT
BEGIN:VEVENT
DTSTART;TZID=America/Los_Angeles:20230810T100000
DTEND;TZID=America/Los_Angeles:20230810T110000
DTSTAMP:20230808T220630Z
CREATED:20230808T220630Z
LAST-MODIFIED:20230808T220630Z
UID:6690-1691661600-1691665200@marketingeda.com
SUMMARY:Dealing with Inconclusive Formal Proofs
DESCRIPTION:Webinar Overview:\nFormal proofs of end-to-end properties can be a very valuable contribution to RTL sign-off and yet are often the most difficult to achieve. \nIn this webinar Doulos Senior Member Technical Staff\, Doug Smith will explore some practical ways of dealing with inconclusive formal proofs when using Jasper by Cadence . This includes the use of complexity analysis and bounded reachability analysis\, over-constraining the design\, setting cut points\, and creating abstractions. \nThis webinar will be useful to anyone who wants to learn to make more effective use of formal. \nWebinar topics include: \n– Formal Verification Overview\n– Formal Apps\n– Formal Coverage\n– Assertion Coverage\n– Inconclusive Formal Proofs\n– Cut Points and Abstraction \nAttendance is FREE and live Q&A will be provided throughout the broadcast.
URL:https://marketingeda.com/event/dealing-with-inconclusive-formal-proofs-2/
CATEGORIES:EDA,Webinar
ATTACH;FMTTYPE=image/jpeg:https://marketingeda.com/wp-content/uploads/Doulos-August-10-2023.jpg
ORGANIZER;CN="Doulos":MAILTO:webinars@duolos.com
END:VEVENT
BEGIN:VEVENT
DTSTART;TZID=America/Los_Angeles:20230810T090000
DTEND;TZID=America/Los_Angeles:20230810T100000
DTSTAMP:20230727T200404Z
CREATED:20230727T200404Z
LAST-MODIFIED:20230727T200404Z
UID:6623-1691658000-1691661600@marketingeda.com
SUMMARY:Step-by-Step Guide for Your  UCIe Design Verification
DESCRIPTION:As traditional Moore’s law scaling approaches its physical limits\, the industry is moving towards multi-die solutions for higher electronics system densities. Multi-die designs present one way for engineers to pack more functionality into silicon chips and improve yield without affecting fabrication feasibility or project budgets. \nThe Universal Chiplet Interconnect Express (UCIe) standard was introduced in March of 2022 to help standardize die-to-die connectivity in multi-die systems. UCIe can streamline interoperability between dies on different process technologies from various suppliers. However\, multi-die system’s complexity drives the need for a high quality verification process by utilizing Protocol verification IPs and hardware-based verification solutions to achieve great levels of quality in SoCs. \nThis Synopsys webinar explains various multi-die design types\, UCIe multi-die design verification challenges\, and how Synopsys verification solutions helps in overcoming these challenges. \n\n\n\n\n\n\n\n\n\n\nSpeakers\n\n\nListed below are the industry leaders scheduled to speak. \n\n\n\n\nVarun Agrawal\n\n\nSenior Staff\, Product Manager \nSynopsys \n\n\n\n\n\n\n\n\nVarun Agrawal is a Product Manager for VIP\, Virtual System Adaptors and Protocol Solutions for Hardware Assisted Platforms\, System Design Group\, at Synopsys. \nVarun has 15 years of experience in IP to system level functional verification with expertise in simulation\, emulation and virtualization domain. Prior to Product Management\, Varun led R&D projects in virtualization and emulation\, and worked in various development and customer facing roles at multiple design and EDA companies. He holds Bachelors in Electronics and Communication from NIT Hamirpur\, India\, and MBA in International Marketing from India Institute of Foreign Trade (IIFT)\, New Delhi\, India. \n\n\n\n\nNarasimha Babu GVL\n\n\nScientist  \nSynopsys \n\n\n\n\n\n\n\n\nNarasimha Babu GVL is a Synopsys Scientist with 18+ years of experience providing protocol verification solutions for a variety of standard protocols including Ethernet\, AMBA\, MIPI\, UFS\, PCIe\, CXL and UCIe. \nBabu is a primary Synopsys representative for the Compute Express Link (CXL) Compliance Work Group and part of the DVCon India steering committee. He is also actively involved in writing and editing technical blog publications on Protocol verification.
URL:https://marketingeda.com/event/step-by-step-guide-for-your-ucie-design-verification/
CATEGORIES:EDA,Webinar
ATTACH;FMTTYPE=image/jpeg:https://marketingeda.com/wp-content/uploads/Synopsys-August-10-2023.jpg
END:VEVENT
BEGIN:VEVENT
DTSTART;TZID=America/Los_Angeles:20230808T083000
DTEND;TZID=America/Los_Angeles:20230808T091500
DTSTAMP:20230801T170422Z
CREATED:20230801T170422Z
LAST-MODIFIED:20230801T170422Z
UID:6631-1691483400-1691486100@marketingeda.com
SUMMARY:Deliver Next-gen Smartphones
DESCRIPTION:Stefan Rosinger\, Senior Director\, Product Management – Arm \n\n\nAbout this talk\nJoin us for a look at how the latest Arm Cortex compute cluster launched as part of Arm’s Total Compute Solution 2023 can help OEMs deliver next-level immersion\, AI intelligence and security while promoting greater efficiency in their mobiles\, laptops\, home\, and wearable devices. We will cover:\n\n-How Cortex-X4 achieves double-digit performance gains\, as well as great efficiency\n-Cortex-A720 & Cortex-A520 processor efficiency gains\, and how they are benefitting not just flagship but also mid-range and entry-level devices\n-The performance\, scalability and efficiency provided by the DynamIQ Shared Unit 120 (DSU-120)\n-How the cluster is being utilized for AI and other new demanding workloads\n-How the industry-leading Armv9.2 architecture and the move to 64-bit clusters has changed developer access to more security and performance
URL:https://marketingeda.com/event/deliver-next-gen-smartphones/
CATEGORIES:IP,Webinar
ATTACH;FMTTYPE=image/jpeg:https://marketingeda.com/wp-content/uploads/Arm-August-8-2023.jpg
END:VEVENT
BEGIN:VEVENT
DTSTART;TZID=America/Los_Angeles:20230803T090000
DTEND;TZID=America/Los_Angeles:20230803T100000
DTSTAMP:20230727T175737Z
CREATED:20230727T175737Z
LAST-MODIFIED:20230727T175737Z
UID:6620-1691053200-1691056800@marketingeda.com
SUMMARY:An Introduction to Correct-by-Construction Golden Specification-based IP/SoC Development
DESCRIPTION:This webinar explores front-end automation advances that encompass an innovative register information management system to capture hardware functionality and addressable register map in a single “executable” specification. \nAppropriate Audience: \n● Architects/RTL Designers\n● Verification Engineers\n● Pre-Silicon Validation Teams\n● Post-Silicon Lab Bring-up Team Members\n● Technical Writers\n● Firmware Engineers\n● Embedded Programmers \nLearn How To: \n● Quickly and efficiently create correct-by-construction reusable designs\n● Quickly and comprehensively verify registers and memories\n● Swiftly generate device drivers\n● Automatically generate derived documentation for Tech-Pubs\, Lab\, internal and external customers\n● Eliminate inefficiencies in the design process\n● Prevent errors from entering the system by giving appropriate error messages in the specification itself\n● Carefully manage register information – and any inevitable changes – throughout the design process\n● Increase entire development team productivity with auto generation of Register database information in the formats desired by the various teams.\n● Reduce design cost by reducing iterations that result due to lack of accurate communication between various teams Specification Automation Benefits & Capabilities:\n● Deliver the ease of a document editor to the system architect or designer for the creation of an executable specification\n● Executable specification contains everything needed to fully describe the design including documentation and register descriptions\n● All downstream views are generated from this single specification\n● Dramatically increase productivity while reducing risk \nPresenter Bio: \nNikita Gulliya\, RnD Engineer\, joined Agnisys in 2017 and serves on the product engineering team. A SystemRDL expert\, she has led various SystemRDL trainings for Agnisys customers around the globe. \n*This webinar is in partnership with SemiWiki and Agnisys
URL:https://marketingeda.com/event/an-introduction-to-correct-by-construction-golden-specification-based-ip-soc-development/
CATEGORIES:EDA,Webinar
ATTACH;FMTTYPE=image/webp:https://marketingeda.com/wp-content/uploads/Agnisys-August-3-2023.webp
END:VEVENT
BEGIN:VEVENT
DTSTART;TZID=America/Los_Angeles:20230802T100000
DTEND;TZID=America/Los_Angeles:20230802T110000
DTSTAMP:20230713T155542Z
CREATED:20230713T155542Z
LAST-MODIFIED:20230713T155542Z
UID:6582-1690970400-1690974000@marketingeda.com
SUMMARY:Accelerate Coverage Closure with Synopsys VSO.ai
DESCRIPTION:70% of engineering time is spent verifying a design but it is largely a manual effort. As the industry faces ongoing engineering shortages companies are forced to make their engineering teams 10 times more productive at finding and isolating bugs per day. Increasing design complexities are also driving up the compute resources needed to verify todays designs. \n  \nTo address these resource challenges\, teams need to shift from an entirely manual verification process to utilizing autonomous verification – where human interaction is reduced\, enabling the ability to achieve coverage closure faster. The goal is that once a coverage target is set\, the system works autonomously to reach the target as quickly and cheaply as possible with the highest quality of results. \n  \nThis Synopsys webinar will introduce and explore the Synopsys VSO.ai™ solution\, Verification Space Optimization\, using machine learning technologies to identify and eliminate redundancies in regressions\, automate coverage root cause analysis\, and infer coverage from RTL and stimulus to identify coverage gaps and provide coverage guidance. \n\nSpeakers\n\n\nListed below are the industry leaders scheduled to speak. \n\n\n\n\nWill Chen\n\n\nPrincipal Applications Engineer\nSynopsys \n\n\n\n\n\n\n\n\n\n\n\nWill Chen is a Principal Applications engineer in Synopsys’ Customer Success EDA Group. Will has over 20 years of experience with account and project management for functional verification. He has recently been focusing on using AI/ML to improve verification efficiency and productivity. \n\n\n\n\nTaruna Reddy\n\n\nStaff Product Manager\nSynopsys \n\n\n\n\n\n\n\n\n\n\n\nTaruna Reddy is a Staff Product Manager in the EDA Group at Synopsys. Taruna has 18 years of experience in EDA and functional verification. Prior to joining Synopsys\, Taruna held field applications and verification engineering positions at Mentor Graphics\, Verilab and Xtreme-EDA.
URL:https://marketingeda.com/event/accelerate-coverage-closure-with-synopsys-vso-ai/
CATEGORIES:EDA,Webinar
ATTACH;FMTTYPE=image/jpeg:https://marketingeda.com/wp-content/uploads/Synopsys-July-19-2023.jpg
END:VEVENT
BEGIN:VEVENT
DTSTART;TZID=America/Los_Angeles:20230726T100000
DTEND;TZID=America/Los_Angeles:20230726T110000
DTSTAMP:20230724T212740Z
CREATED:20230724T212740Z
LAST-MODIFIED:20230724T212740Z
UID:6609-1690365600-1690369200@marketingeda.com
SUMMARY:A Novel Approach to Implementing Logical ECOs with Synopsys Formality ECO on High Performance RISC-V Cores
DESCRIPTION:RTL engineering change order (ECO) is vital to ensuring proper functionality of integrated circuits (ICs). Retiming and auto ungrouping optimize RTL implementation and enhance PPA. However\, aggressive optimizations in CPU RTL designs present challenges due to increased design complexity and potential mapping issues. \n  \nSynopsys Formality ECO offers an efficient and accurate solution for RTL ECO by automating the comprehensive ECO flow\, analyzing differences between original RTL and ECO RTL\, generating patches\, and validating changes. Formality ECO also supports aggressive RTL optimization techniques\, including retiming and auto ungrouping\, while providing advanced analysis and debug features to streamline the ECO process. \n  \nIn this Synopsys webinar\, presenters from SiFive will share the advantages of Synopsys Formality ECO on their overall ECO cycle which has enhanced patching capabilities and resulted in faster verification runtime leading to improved TAT. With the retimed and flattened design\, it is difficult to generate the sizable patch for fast CPUs designs targeted by SiFive. SiFive designs have strict requirements on the patch size\, patch affecting hierarchies\, changes applicable to RTL and ease of implementation at route_opt stage. By using Synopsys Formality ECO suite\, SiFive has been able to generate a hassle-free patch and verify it 3-5x faster than traditional formal verification ensuring performance of the CPU. \n\nSpeakers\n\n\nListed below are the industry leaders scheduled to speak. \n\n\n\n\nVivek Upadhyaya\n\n\nTechnical Director\nSiFive \n\n\n\n\n\n\n\n\nVivek Upadhyaya brings over 20 years of extensive experience in VLSI industry\, specializing in High-Speed CPU Implementation. Currently he is holding esteemed position as a Technical Director at SiFive in Physical Implementation Group. His previous roles encompassed notable companies such as Broadcom\, Cadence\, Intel\, and STMicroelectronics\, focusing on RTL-to-GDSII implementation. He is graduate from CCS University Meerut\, UP. \n\n\n\n\nRupali Kale Gaikwad\n\n\nStaff Engineer\nSynopsys \n\n\n\n\n\n\n\n\nRupali Kale Gaikwad is a Staff Engineer at Synopsys\, holds Master’s degree in Microelectronics from BITS\, Pilani. Over a span of 12 years\, she has worked on various advanced node ASIC designs of different sectors including automotive\, networking\, modem\, healthcare\, high speed CPU implementation. In Synopsys she is responsible for Ecosystem customer success for complete RTL2GDS solution.
URL:https://marketingeda.com/event/a-novel-approach-to-implementing-logical-ecos-with-synopsys-formality-eco-on-high-performance-risc-v-cores/
CATEGORIES:EDA,Webinar
ATTACH;FMTTYPE=image/jpeg:https://marketingeda.com/wp-content/uploads/Synopsys-July-26-2023.jpg
END:VEVENT
BEGIN:VEVENT
DTSTART;TZID=America/Los_Angeles:20230726T100000
DTEND;TZID=America/Los_Angeles:20230726T110000
DTSTAMP:20230713T160341Z
CREATED:20230713T160341Z
LAST-MODIFIED:20230713T160341Z
UID:6586-1690365600-1690369200@marketingeda.com
SUMMARY:Solution for 3D-IC Interposer Signal Integrity
DESCRIPTION:3D-IC design requires early analysis of thermal properties\, power delivery\, and signal integrity. This webinar will work through the process of simulating heterogeneously integrated chiplets. Learn about the integrated workflow that begins with silicon design data being accurately modeled with 3D FEM extraction. The Cadence Clarity 3D Solver has the unique ability to efficiently import and solve for complex structures\, including degassing holes. Accurate interconnect models can then be cascaded with IBIS I/O models for end-to-end signal integrity analysis and confirm that high-speed signals meet compliance testing. \nIncluded will be a step-by-step approach to importing GDS into the simulation environment. The interposer multiblock analysis workflow in Clarity 3D Solver will show how to edit the layout\, simulate\, and then view all simulation results. \nIf you think performing channel extractions on a large interposer is a complex and time-consuming process\, this is the perfect webinar for you.
URL:https://marketingeda.com/event/solution-for-3d-ic-interposer-signal-integrity-2/
CATEGORIES:EDA,Webinar
ATTACH;FMTTYPE=image/jpeg:https://marketingeda.com/wp-content/uploads/Cadence-July-26-2023-1.jpg
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BEGIN:VEVENT
DTSTART;TZID=America/Los_Angeles:20230726T100000
DTEND;TZID=America/Los_Angeles:20230726T110000
DTSTAMP:20230629T182125Z
CREATED:20230629T182125Z
LAST-MODIFIED:20230629T182125Z
UID:6562-1690365600-1690369200@marketingeda.com
SUMMARY:Solution for 3D-IC Interposer Signal Integrity
DESCRIPTION:Our upcoming CadenceTECHTALK: Solution for 3D-IC Interposer Signal Integrity is designed to teach engineers to translate a GDSII stream format (GDSII) file and partition it into simulation blocks for the Clarity 3D field solver. \nFirst\, you will learn to use GDS-supporting files to simplify GDS to SPD translation and reuse those files to make the translation effortlessly repeatable. You will then learn to use the interposer multiblock analysis workflow in Clarity\, edit the layout\, if necessary\, using scripts\, create ports concurrently\, set up computer resources\, and then view all simulation results. \nIf you think performing channel extractions on a large interposer is a complex and time-consuming process\, this is the perfect webinar for you. \nFor questions\, inquiries\, or issues with registration\, send an email to events@cadence.com 
URL:https://marketingeda.com/event/solution-for-3d-ic-interposer-signal-integrity/
CATEGORIES:EDA,Webinar
ATTACH;FMTTYPE=image/jpeg:https://marketingeda.com/wp-content/uploads/Cadence-July-26-2023.jpg
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BEGIN:VEVENT
DTSTART;TZID=America/Los_Angeles:20230720T100000
DTEND;TZID=America/Los_Angeles:20230720T110000
DTSTAMP:20230713T201325Z
CREATED:20230713T201325Z
LAST-MODIFIED:20230713T201325Z
UID:6595-1689847200-1689850800@marketingeda.com
SUMMARY:Achieve First-pass Silicon Leveraging SDC Verification Early with No Noise
DESCRIPTION:As today’s designs are getting more complex\, design constraints complexity also increases multifold. While ensuring design correctness typically gets a lot of attention including code review\, functional verification\, implementation\, etc.\, correctness of constraints requires the same level of attention. Quality of implementation and timing analysis is highly dependent on quality of constraints. For achieving first-past silicon efficiently\, it is imperative to ensure that the constraints are correct and complete early at RTL before progressing to late design stages of implementation and timing analysis. \n  \nIn this presentation\, we will focus on the conceptual foundations of constraints verification at RTL using Synopsys Timing Constraints Manager. Further\, we will cover the types of constraints issues flagged and noise reduction techniques using built in formal verification. Lastly\, we will discuss the need for timing exception verification (MCP/FP) and the use of formal and simulation techniques to deliver complete verification results to pinpoint incorrect timing exceptions. \n\nSpeaker\n\n\nListed below is the industry leader scheduled to speak. \n\n\n\n\nRimpy Chugh\n\n\nSenior Product Marketing Manager\nSynopsys \n\n\n\n\n\n\n\n\nRimpy Chugh is a Senior Product Marketing Manager in the Verification Group at Synopsys\, with 10 years of varied experience in EDA and functional verification. Prior to joining Synopsys\, Rimpy held field applications and verification engineering positions at Mentor Graphics\, Cadence and HCL Technologies. She holds an MBA from Indian Institute of Management\, Bangalore and a Bachelor of Technology from YMCA Institute of Technology\, India.
URL:https://marketingeda.com/event/achieve-first-pass-silicon-leveraging-sdc-verification-early-with-no-noise/
CATEGORIES:EDA,Webinar
ATTACH;FMTTYPE=image/jpeg:https://marketingeda.com/wp-content/uploads/Synopsys-July-20-2023.jpg
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BEGIN:VEVENT
DTSTART;TZID=America/Los_Angeles:20230720T080000
DTEND;TZID=America/Los_Angeles:20230720T090000
DTSTAMP:20230629T192722Z
CREATED:20230629T192722Z
LAST-MODIFIED:20230629T192722Z
UID:6565-1689840000-1689843600@marketingeda.com
SUMMARY:3D-IC Foundry Frameworks
DESCRIPTION:Join us on July 20th; Ansys R&D members will discuss an overview of the 3D-IC technology development frameworks offered by TSMC\, Samsung\, and Intel and how Ansys simulation tools and workflows fit into those frameworks. \n\n\nAbout this Webinar\nSemiconductor applications such as Mobile (5G)\, Automotive\, and Datacenter (HPC\, AI) demand better scaling\, performance\, and lower power usage. Advanced packaging is moving towards 3DIC systems to address these needs\, as evidenced by the technology directions from TSMC\, Samsung\, and Intel. We’ll present a comprehensive overview of these technologies\, and the Ansys flows to address EMIR\, Thermal integrity\, and mechanical stress challenges posed by these 3DIC systems. \nWhat You Will Learn\n\nAdvanced 3DIC packaging trends and challenges faced by engineers\n3DIC system data flows from P&R to analysis tools\nEMIR and Thermal Integrity flows using RedHawk SCTM and RedHawk SC ElectroThermalTM\n\n\n\n\n\nSpeakers\nMallik Vusirikala\n\nMallik Vusirikala is a Director Product Specialist at Ansys\, responsible for strategic directions and deployment of the RedHawk product line for Power integrity and related solutions. He has been with Ansys for over 12 years. Prior to that he was with Texas instruments in the CAD flow/ methodology group developing multiple flows for standard cell library creation. He obtained his bachelor’s degree with Honors in Computer Science and Engineering from the National Institute of Technology\, Hamirpur (India). \nDr. Lang Lin\n\nDr. Lang Lin is a principal product manager of Ansys Inc. based in San Jose\, California. He is dedicated into developing 3D-IC multiphysics simulation and security verification methodologies to worldwide semiconductor customers. Before joining Ansys\, he worked for Intel Corp. as a design engineer. He has published 50+ technical papers and patents\, served as reviewer\, program committee or tutorial speaker of several IEEE conferences such as HOST\, ICCAD\, DAC and ASPDAC.
URL:https://marketingeda.com/event/3d-ic-foundry-frameworks/
CATEGORIES:EDA,Foundry,Webinar
ATTACH;FMTTYPE=image/jpeg:https://marketingeda.com/wp-content/uploads/Ansys-July-20-2023.jpg
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BEGIN:VEVENT
DTSTART;TZID=America/Los_Angeles:20230719T100000
DTEND;TZID=America/Los_Angeles:20230719T110000
DTSTAMP:20230713T154956Z
CREATED:20230713T154956Z
LAST-MODIFIED:20230713T154956Z
UID:6579-1689760800-1689764400@marketingeda.com
SUMMARY:Achieve Optimal PPA Targets Using AI-Driven Technology
DESCRIPTION:Complexity brought on by advanced process nodes have opened the door to challenges in achieving optimal power\, performance\, and area (PPA). Manual methods are no longer viable given shrinking market windows. The need to drive for better results faster is increasing\, and traditional methods cannot keep pace often taking months of tuning using 100s of trials. Even then\, results are not optimal. AI-driven technology can help. \n  \nThis Synopsys webinar discusses the challenges facing engineers creating complex designs and introduces Synopsys Design Space Optimization solution\, DSO.ai™. The industry’s first autonomous artificial intelligence (AI) application for chip design\, Synopsys DSO.ai searches for optimization targets in very large solution spaces of chip design\, utilizing reinforcement learning to enhance power\, performance\, and area. RTL-to-GDSII full flow optimization unlocks PPA potential across both logical and physical domains with reported productivity enhancements of more than 3x\, power reductions of up to 15%\, and substantial die size reductions. We’ll explore case studies from AMD\, Intel\, and STMicro on how they are applying this technology to surpass the most challenging goals in chip design and reach new levels of productivity.
URL:https://marketingeda.com/event/achieve-optimal-ppa-targets-using-ai-driven-technology/
CATEGORIES:EDA,Webinar
ATTACH;FMTTYPE=image/jpeg:https://marketingeda.com/wp-content/uploads/Synopsys-July-19-2023.jpg
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