BEGIN:VCALENDAR
VERSION:2.0
PRODID:-//Marketing EDA - ECPv6.17.5//NONSGML v1.0//EN
CALSCALE:GREGORIAN
METHOD:PUBLISH
X-WR-CALNAME:Marketing EDA
X-ORIGINAL-URL:https://marketingeda.com
X-WR-CALDESC:Events for Marketing EDA
REFRESH-INTERVAL;VALUE=DURATION:PT1H
X-Robots-Tag:noindex
X-PUBLISHED-TTL:PT1H
BEGIN:VTIMEZONE
TZID:America/Los_Angeles
BEGIN:DAYLIGHT
TZOFFSETFROM:-0800
TZOFFSETTO:-0700
TZNAME:PDT
DTSTART:20220313T100000
END:DAYLIGHT
BEGIN:STANDARD
TZOFFSETFROM:-0700
TZOFFSETTO:-0800
TZNAME:PST
DTSTART:20221106T090000
END:STANDARD
BEGIN:DAYLIGHT
TZOFFSETFROM:-0800
TZOFFSETTO:-0700
TZNAME:PDT
DTSTART:20230312T100000
END:DAYLIGHT
BEGIN:STANDARD
TZOFFSETFROM:-0700
TZOFFSETTO:-0800
TZNAME:PST
DTSTART:20231105T090000
END:STANDARD
BEGIN:DAYLIGHT
TZOFFSETFROM:-0800
TZOFFSETTO:-0700
TZNAME:PDT
DTSTART:20240310T100000
END:DAYLIGHT
BEGIN:STANDARD
TZOFFSETFROM:-0700
TZOFFSETTO:-0800
TZNAME:PST
DTSTART:20241103T090000
END:STANDARD
END:VTIMEZONE
BEGIN:VTIMEZONE
TZID:Europe/London
BEGIN:DAYLIGHT
TZOFFSETFROM:+0000
TZOFFSETTO:+0100
TZNAME:BST
DTSTART:20220327T010000
END:DAYLIGHT
BEGIN:STANDARD
TZOFFSETFROM:+0100
TZOFFSETTO:+0000
TZNAME:GMT
DTSTART:20221030T010000
END:STANDARD
BEGIN:DAYLIGHT
TZOFFSETFROM:+0000
TZOFFSETTO:+0100
TZNAME:BST
DTSTART:20230326T010000
END:DAYLIGHT
BEGIN:STANDARD
TZOFFSETFROM:+0100
TZOFFSETTO:+0000
TZNAME:GMT
DTSTART:20231029T010000
END:STANDARD
BEGIN:DAYLIGHT
TZOFFSETFROM:+0000
TZOFFSETTO:+0100
TZNAME:BST
DTSTART:20240331T010000
END:DAYLIGHT
BEGIN:STANDARD
TZOFFSETFROM:+0100
TZOFFSETTO:+0000
TZNAME:GMT
DTSTART:20241027T010000
END:STANDARD
END:VTIMEZONE
BEGIN:VEVENT
DTSTART;TZID=America/Los_Angeles:20230823T100000
DTEND;TZID=America/Los_Angeles:20230823T110000
DTSTAMP:20230815T210853Z
CREATED:20230815T210838Z
LAST-MODIFIED:20230815T210853Z
UID:6706-1692784800-1692788400@marketingeda.com
SUMMARY:IP Lifecycle Management for Chiplet-Based SoCs
DESCRIPTION:Chiplet-based SoC architectures have seen increased interest over the past three years\, and recently were made a focus of the federal CHIPS and Science Act to reduce the cost of innovation for US-based semiconductor startups\, DoD projects\, and academic research. Chiplet-based architectures bring their own set of challenges however\, especially in the context of IP security. \nJoin Simon Butler\, founder of Methodics IPLM\, to learn best practices for managing IPs from inception through SoC integration\, including: \n\nEnsuring end-to-end traceability.\nManaging security concerns.\nEnforcing IP provenance.\n\nPresenters\n\n\n\n\n\n\n\n\n\n\n\nSimon Butler\n\nSimon Butler is the founder of Methodics Inc.\, acquired by Perforce in 2020. He is currently the General Manager of the Methodics IPLM business unit at Perforce. Methodics created IPLM as a new business segment in the enterprise software space to serve the needs of IP and component-based design. Simon has 30 years of IC design and EDA tool development and specializes in product strategy and design.
URL:https://marketingeda.com/event/ip-lifecycle-management-for-chiplet-based-socs/
CATEGORIES:EDA,IP,Webinar
ATTACH;FMTTYPE=image/jpeg:https://marketingeda.com/wp-content/uploads/Perforce-August-23-2023.jpg
END:VEVENT
BEGIN:VEVENT
DTSTART;TZID=America/Los_Angeles:20230823T100000
DTEND;TZID=America/Los_Angeles:20230823T110000
DTSTAMP:20230713T155945Z
CREATED:20230713T155945Z
LAST-MODIFIED:20230713T155945Z
UID:6584-1692784800-1692788400@marketingeda.com
SUMMARY:Optimize Test QoR & TTM with AI-Driven Technology
DESCRIPTION:Continuously increasing semiconductor design sizes and complexity have resulted in increased test costs. Today’s competitive environment and critical market windows are pushing companies to adopt aggressive design schedules. The traditional method of manual iterations and fine-tuning test configurations to optimize test quality-of-results (QoR) is highly unpredictable and inefficient. Engineers can no longer rely on such approaches to meet deadlines or achieve optimal results. With a global shrinking engineering workforce\, intelligent automation is needed for higher productivity and delivering first-time-right results. \n  \nThis Synopsys webinar discusses our newly introduced AI-driven test technology called Synopsys TSO.ai™– Test Space Optimization AI that dramatically minimizes test cost and time-to-market for today’s complex designs. Synopsys TSO.ai learns and converges the large ATPG search space to automatically minimize test patterns and eliminate ineffective user iterations\, enabling expert-level productivity at scale. Current engagements with leading semiconductor companies are showing an average of 20% to 25% pattern count reduction or even higher on some designs. \n\nSpeaker\n\n\nListed below is the industry leader scheduled to speak. \n\n\n\n\nRahul Singhal\n\n\nProduct Manager\nSynopsys \n\n\n\n\n\n\n\n\n\n\n\nRahul Singhal is a Product Manager for Synopsys TestMAX DFT\, Synopsys TestMAX ATPG and Test-AI products at Synopsys. His focus is on industry requirements and solutions in the areas of test compression\, test streaming solutions and ATPG. He has co-authored multiple tutorials\, papers\, posters on test in leading IEEE conferences. Rahul received his MS in Electrical Engineering from Portland State University and BS in Electrical Engineering from Purdue University.
URL:https://marketingeda.com/event/optimize-test-qor-ttm-with-ai-driven-technology/
CATEGORIES:EDA,Webinar
ATTACH;FMTTYPE=image/jpeg:https://marketingeda.com/wp-content/uploads/Synopsys-July-19-2023.jpg
END:VEVENT
BEGIN:VEVENT
DTSTART;TZID=America/Los_Angeles:20230823T100000
DTEND;TZID=America/Los_Angeles:20230823T100000
DTSTAMP:20230811T160610Z
CREATED:20230811T160323Z
LAST-MODIFIED:20230811T160610Z
UID:6695-1692784800-1692784800@marketingeda.com
SUMMARY:Unveiling the Secrets to Proper Version Control\, Seamless Data and Tool Integration\, and Effective Collaboration
DESCRIPTION:Overview\n  \nTitle:  Unveiling the Secrets to Proper Version Control\, Seamless Data Integration\, and Effective Collaboration \nDate:  Wednesday\, August 23\, 2023 \nTime: 10:00 AM Pacific Time \nDuration:  30 minutes (+15 minutes live Q/A) \n\n\n\n\nJoin us on Wednesday\, August 23rd\, to learn how to master semiconductor design success as we unveil the secrets to proper version control\, seamless data integration\, and effective collaboration. \n  \nHere’s what you can learn: \n\nWhy maintaining proper version control and traceability will make your job easier\nHow to eliminate the data volume challenge and seamlessly integrate your tools and data\nHow to achieve effective data collaboration and communication with teams and across sites
URL:https://marketingeda.com/event/unveiling-the-secrets-to-proper/
CATEGORIES:EDA,IP,Webinar
ATTACH;FMTTYPE=image/jpeg:https://marketingeda.com/wp-content/uploads/Cliosoft-August-23-2023.jpeg
END:VEVENT
BEGIN:VEVENT
DTSTART;TZID=America/Los_Angeles:20230822T100000
DTEND;TZID=America/Los_Angeles:20230822T110000
DTSTAMP:20230816T234252Z
CREATED:20230816T234252Z
LAST-MODIFIED:20230816T234252Z
UID:6720-1692698400-1692702000@marketingeda.com
SUMMARY:MIPI A-PHY & MASS - Revolutionizing Automotive Connectivity
DESCRIPTION:1) Intro – MASS introduction\n2) Usage – Full chip automotive systems from peripheral to processor and vice versa. E.g.Used in Radar\, LiDAR\, ADAS \, etc.\n3) APHY – PHY& Link layer for MASS\n4) PAL – Protocol adaption layer for MASS\n5) App – Application Layer For MASS like CSI2\,DSI2\, I2C\, GPIO \,Includes  FUSA  protocols like CSE\, DSE etc.\n6) VIP – Truechip MASS Verification IP Solution \n\n\n\n\nWho should attend: \n\nProfessionals working on development of  Soc/IP/VIP level of MIPI A-PHY & MASS.\nProfessionals working on verification of MIPI A-PHY & MASS at Soc/IP/VIP level or any intermediate level.\nPeople keen to know how MIPI A-PHY & MASS is shaping new era of ADAS\, ADS and other surround-sensor applications\, including cameras and in-vehicle infotainment (IVI) displays.\nFreshers in the field of VLSI industry.
URL:https://marketingeda.com/event/mipi-a-phy-mass-revolutionizing-automotive-connectivity/
CATEGORIES:IP,Webinar
ATTACH;FMTTYPE=image/jpeg:https://marketingeda.com/wp-content/uploads/Truechip-August-22-2023.jpg
END:VEVENT
BEGIN:VEVENT
DTSTART;TZID=America/Los_Angeles:20230822T080000
DTEND;TZID=America/Los_Angeles:20230822T090000
DTSTAMP:20230728T182740Z
CREATED:20230728T182740Z
LAST-MODIFIED:20230728T182740Z
UID:6626-1692691200-1692694800@marketingeda.com
SUMMARY:Advanced Analog Design Using S-parameters
DESCRIPTION:This webinar highlights the importance of S-parameters to IC design and how Semtech Corporation\, a high-performance semiconductor\, IoT systems and Cloud connectivity service provider\, utilizes Siemens AFS XT simulation technology to accelerate Semtech’s design process without compromising on accuracy to develop differentiated analog solutions for wired and wireless applications. Two case studies of analog circuits will be discussed. \nAbstract:\nIC design is transforming at an accelerated pace along with fabrication technology. The need to incorporate more functionality has led to denser dies\, multi-die chips\, stacked 3D ICs and advanced packaging. Design technology continues to progress toward supporting higher data rates to address the increasing demand for more and enhanced connectivity. We now must deal with much more power\, ground and clock signals and their distribution on die\, between dies\, on package and on board. Signal transmission and reflection needs to be well understood to properly design for signal integrity in various signal conduits. S-parameters (scattering parameters) play a crucial part in IC design in representing passive structures and interconnects with frequency variable behavior in the RF realm. Accurate verification with these components amid large designs and sub-systems is key for first time right tapeouts\, along with a fast verification methodology that accelerates development. \nSemtech provides unique differentiation with its wired and wireless IC technology for infrastructure\, industrial\, automotive and consumer electronics applications. Semtech’s Signal Integrity Products (SIP) Group provides high performance TIAs\, CDRs\, linear equalizers and laser drivers for optical module solutions used by leading companies in hyperscale data center applications\, enterprise networking\, wireless infrastructure\, including 5G fronthaul and midhaul\, and passive optical networking/fiber-to-the-home using CMOS and BiCMOS process technologies. \nIn this webinar\, we focus on Semtech’s requirements of S-parameters for analog circuit development and how Siemens Analog FastSPICE (AFS) eXTreme technology provides differentiated performance across DC\, AC\, transient\, transient noise and RF analyses. Two case studies on 26GBd Analog Delay Line and 25Gb/s Receiver will be showcased. \nAgenda: \n\nImportance of S-parameters for IC design\nSemtech Company overview\nSemtech requirements of S-parameters\nSiemens’ Analog FastSPICE for circuit simulation\nCase Study #1 – 26GBd Analog Delay Line\nCase Study #2 – 25Gb/s Receiver\nSummary and Q&A\n\nFeatured Products: Analog FastSPICE Platform with AFS RF and AFS eXTreme Technology
URL:https://marketingeda.com/event/advanced-analog-design-using-s-parameters/
CATEGORIES:EDA,Webinar
ATTACH;FMTTYPE=image/jpeg:https://marketingeda.com/wp-content/uploads/Semtech-August-22-2023.jpg
END:VEVENT
BEGIN:VEVENT
DTSTART;TZID=America/Los_Angeles:20230817T183000
DTEND;TZID=America/Los_Angeles:20230817T193000
DTSTAMP:20230816T225936Z
CREATED:20230816T225936Z
LAST-MODIFIED:20230816T225936Z
UID:6714-1692297000-1692300600@marketingeda.com
SUMMARY:Using Generative AI for ASIC Design
DESCRIPTION:Tools like ChatGPT can be used for a variety of purposes\, including writing Verilog. Unfortunately\, these models are not (yet) perfect\, and the quality of the output varies heavily depending on how you use them. Just as models may “hallucinate” facts they are not certain about\, they can also “hallucinate” buggy and non-functional Verilog. \nIn this presentation\, Dr. Hammond Pearce will present how he designed his team’s entry to the last Efabless AI-Generated Open-Source Silicon challenge\, with practical tips and techniques via a demo and discussion of their results: an 8-bit processor wholly designed by ChatGPT.
URL:https://marketingeda.com/event/using-generative-ai-for-asic-design/
CATEGORIES:EDA,Webinar
ATTACH;FMTTYPE=image/jpeg:https://marketingeda.com/wp-content/uploads/efabless-august-17-2023.jpg
END:VEVENT
BEGIN:VEVENT
DTSTART;TZID=America/Los_Angeles:20230815T100000
DTEND;TZID=America/Los_Angeles:20230815T110000
DTSTAMP:20230804T163719Z
CREATED:20230804T163719Z
LAST-MODIFIED:20230804T163719Z
UID:6680-1692093600-1692097200@marketingeda.com
SUMMARY:UCIe: On-Package Chiplet Innovation Opportunities
DESCRIPTION:High-performance workloads demand on-package integration of heterogeneous processing units\, on-package memory\, and communication infrastructure to meet the demands of today’s data centers\, autonomous vehicles\, etc. On-package interconnects are a critical component to deliver the power-efficient performance for this evolving landscape. \nUniversal Chiplet Interconnect Express (UCIe)\, is an open industry standard with a fully specified stack that comprehends plug-and-play interoperability of chiplets on a package; In this webinar\, we will discuss the usages\, key metrics and the silicon health associated with different technology choices in UCIe and how it will evolve going forward. We will also delve into the challenges and opportunities for chiplets connected through UCIe\, including production test\, repair and in-field silicon lifecycle management. \n\n\n\n\n\n\n\n\n\n\nSpeakers\n\n\nListed below are the industry leaders scheduled to speak. \n\n\n\n\n\n\n\n\n\n\n\n\n\n\n\n\n\n\n\n\n\n\n\n\n\n\nDr. Debendra Das Sharma\n\n\nSenior Fellow\, co-GM Memory and I/O Technologies\nIntel \n\n\n\n\n\n\n\n\n\n\n\nDr. Das Sharma is an Intel Senior Fellow and co-GM of Memory and I/O Technologies at the Data Platforms and AI Group\, Intel Corporation. He is a co-inventor and founding member of the CXL and UCIe consortia\, Chair of UCIe Consortium\, Co-lead of the CXL Board Technical Task Force and member of the Board of Directors of PCI-SIG. He holds 160+ US patents. A Senior Member of IEEE\, Dr. Das Sharma has been awarded the 2019 Distinguished Alumnus Award by IIT\, the 2021 IEEE Region Engineer of the Year Award\, the 2022 PCI-SIG Lifetime Contribution Award\, and the 2022 IEEE CAS Industrial Pioneer Award. \n\n\n\n\n\n\n\n\n\n\n\n\n\n\n\n\n\n\n\n\n\n\n\n\n\n\n\n\n\n\n\nDr. Yervant Zorian\n\n\nChief Architect & Fellow\, Silicon Lifecycle Management\nSynopsys\, Inc. \n\n\n\n\n\n\n\n\n\n\n\nDr. Zorian is a Chief Architect and Fellow at Synopsys\, as well as President of Synopsys Armenia. He is President of IEEE Test Technology Technical Council (TTTC)\, the Founder of IEEE 1500 Standardization Working Group\, and General Chair of the 50th Design Automation Conference (DAC) and 50th International Test Conference (ITC). He authored 5 books\, 400 referred papers\, and holds 45 US patents. A Fellow of IEEE\, Dr. Zorian has been the recipient of 2005 IEEE CAS Industrial Pioneer Award\, 2006 IEEE Hans Karlsson Award\, 2014 Republic of Armenia’s National Medal of Science\, and 2022 IEEE TTTC Lifetime Contribution Medal.
URL:https://marketingeda.com/event/ucie-on-package-chiplet-innovation-opportunities/
CATEGORIES:EDA,Webinar
ATTACH;FMTTYPE=image/jpeg:https://marketingeda.com/wp-content/uploads/Synopsys-August-15-2023.jpg
END:VEVENT
BEGIN:VEVENT
DTSTART;TZID=America/Los_Angeles:20230810T100000
DTEND;TZID=America/Los_Angeles:20230810T110000
DTSTAMP:20230808T220630Z
CREATED:20230808T220630Z
LAST-MODIFIED:20230808T220630Z
UID:6690-1691661600-1691665200@marketingeda.com
SUMMARY:Dealing with Inconclusive Formal Proofs
DESCRIPTION:Webinar Overview:\nFormal proofs of end-to-end properties can be a very valuable contribution to RTL sign-off and yet are often the most difficult to achieve. \nIn this webinar Doulos Senior Member Technical Staff\, Doug Smith will explore some practical ways of dealing with inconclusive formal proofs when using Jasper by Cadence . This includes the use of complexity analysis and bounded reachability analysis\, over-constraining the design\, setting cut points\, and creating abstractions. \nThis webinar will be useful to anyone who wants to learn to make more effective use of formal. \nWebinar topics include: \n– Formal Verification Overview\n– Formal Apps\n– Formal Coverage\n– Assertion Coverage\n– Inconclusive Formal Proofs\n– Cut Points and Abstraction \nAttendance is FREE and live Q&A will be provided throughout the broadcast.
URL:https://marketingeda.com/event/dealing-with-inconclusive-formal-proofs-2/
CATEGORIES:EDA,Webinar
ATTACH;FMTTYPE=image/jpeg:https://marketingeda.com/wp-content/uploads/Doulos-August-10-2023.jpg
ORGANIZER;CN="Doulos":MAILTO:webinars@duolos.com
END:VEVENT
BEGIN:VEVENT
DTSTART;TZID=America/Los_Angeles:20230810T090000
DTEND;TZID=America/Los_Angeles:20230810T100000
DTSTAMP:20230727T200404Z
CREATED:20230727T200404Z
LAST-MODIFIED:20230727T200404Z
UID:6623-1691658000-1691661600@marketingeda.com
SUMMARY:Step-by-Step Guide for Your  UCIe Design Verification
DESCRIPTION:As traditional Moore’s law scaling approaches its physical limits\, the industry is moving towards multi-die solutions for higher electronics system densities. Multi-die designs present one way for engineers to pack more functionality into silicon chips and improve yield without affecting fabrication feasibility or project budgets. \nThe Universal Chiplet Interconnect Express (UCIe) standard was introduced in March of 2022 to help standardize die-to-die connectivity in multi-die systems. UCIe can streamline interoperability between dies on different process technologies from various suppliers. However\, multi-die system’s complexity drives the need for a high quality verification process by utilizing Protocol verification IPs and hardware-based verification solutions to achieve great levels of quality in SoCs. \nThis Synopsys webinar explains various multi-die design types\, UCIe multi-die design verification challenges\, and how Synopsys verification solutions helps in overcoming these challenges. \n\n\n\n\n\n\n\n\n\n\nSpeakers\n\n\nListed below are the industry leaders scheduled to speak. \n\n\n\n\nVarun Agrawal\n\n\nSenior Staff\, Product Manager \nSynopsys \n\n\n\n\n\n\n\n\nVarun Agrawal is a Product Manager for VIP\, Virtual System Adaptors and Protocol Solutions for Hardware Assisted Platforms\, System Design Group\, at Synopsys. \nVarun has 15 years of experience in IP to system level functional verification with expertise in simulation\, emulation and virtualization domain. Prior to Product Management\, Varun led R&D projects in virtualization and emulation\, and worked in various development and customer facing roles at multiple design and EDA companies. He holds Bachelors in Electronics and Communication from NIT Hamirpur\, India\, and MBA in International Marketing from India Institute of Foreign Trade (IIFT)\, New Delhi\, India. \n\n\n\n\nNarasimha Babu GVL\n\n\nScientist  \nSynopsys \n\n\n\n\n\n\n\n\nNarasimha Babu GVL is a Synopsys Scientist with 18+ years of experience providing protocol verification solutions for a variety of standard protocols including Ethernet\, AMBA\, MIPI\, UFS\, PCIe\, CXL and UCIe. \nBabu is a primary Synopsys representative for the Compute Express Link (CXL) Compliance Work Group and part of the DVCon India steering committee. He is also actively involved in writing and editing technical blog publications on Protocol verification.
URL:https://marketingeda.com/event/step-by-step-guide-for-your-ucie-design-verification/
CATEGORIES:EDA,Webinar
ATTACH;FMTTYPE=image/jpeg:https://marketingeda.com/wp-content/uploads/Synopsys-August-10-2023.jpg
END:VEVENT
BEGIN:VEVENT
DTSTART;TZID=America/Los_Angeles:20230808T083000
DTEND;TZID=America/Los_Angeles:20230808T091500
DTSTAMP:20230801T170422Z
CREATED:20230801T170422Z
LAST-MODIFIED:20230801T170422Z
UID:6631-1691483400-1691486100@marketingeda.com
SUMMARY:Deliver Next-gen Smartphones
DESCRIPTION:Stefan Rosinger\, Senior Director\, Product Management – Arm \n\n\nAbout this talk\nJoin us for a look at how the latest Arm Cortex compute cluster launched as part of Arm’s Total Compute Solution 2023 can help OEMs deliver next-level immersion\, AI intelligence and security while promoting greater efficiency in their mobiles\, laptops\, home\, and wearable devices. We will cover:\n\n-How Cortex-X4 achieves double-digit performance gains\, as well as great efficiency\n-Cortex-A720 & Cortex-A520 processor efficiency gains\, and how they are benefitting not just flagship but also mid-range and entry-level devices\n-The performance\, scalability and efficiency provided by the DynamIQ Shared Unit 120 (DSU-120)\n-How the cluster is being utilized for AI and other new demanding workloads\n-How the industry-leading Armv9.2 architecture and the move to 64-bit clusters has changed developer access to more security and performance
URL:https://marketingeda.com/event/deliver-next-gen-smartphones/
CATEGORIES:IP,Webinar
ATTACH;FMTTYPE=image/jpeg:https://marketingeda.com/wp-content/uploads/Arm-August-8-2023.jpg
END:VEVENT
BEGIN:VEVENT
DTSTART;TZID=America/Los_Angeles:20230803T090000
DTEND;TZID=America/Los_Angeles:20230803T100000
DTSTAMP:20230727T175737Z
CREATED:20230727T175737Z
LAST-MODIFIED:20230727T175737Z
UID:6620-1691053200-1691056800@marketingeda.com
SUMMARY:An Introduction to Correct-by-Construction Golden Specification-based IP/SoC Development
DESCRIPTION:This webinar explores front-end automation advances that encompass an innovative register information management system to capture hardware functionality and addressable register map in a single “executable” specification. \nAppropriate Audience: \n● Architects/RTL Designers\n● Verification Engineers\n● Pre-Silicon Validation Teams\n● Post-Silicon Lab Bring-up Team Members\n● Technical Writers\n● Firmware Engineers\n● Embedded Programmers \nLearn How To: \n● Quickly and efficiently create correct-by-construction reusable designs\n● Quickly and comprehensively verify registers and memories\n● Swiftly generate device drivers\n● Automatically generate derived documentation for Tech-Pubs\, Lab\, internal and external customers\n● Eliminate inefficiencies in the design process\n● Prevent errors from entering the system by giving appropriate error messages in the specification itself\n● Carefully manage register information – and any inevitable changes – throughout the design process\n● Increase entire development team productivity with auto generation of Register database information in the formats desired by the various teams.\n● Reduce design cost by reducing iterations that result due to lack of accurate communication between various teams Specification Automation Benefits & Capabilities:\n● Deliver the ease of a document editor to the system architect or designer for the creation of an executable specification\n● Executable specification contains everything needed to fully describe the design including documentation and register descriptions\n● All downstream views are generated from this single specification\n● Dramatically increase productivity while reducing risk \nPresenter Bio: \nNikita Gulliya\, RnD Engineer\, joined Agnisys in 2017 and serves on the product engineering team. A SystemRDL expert\, she has led various SystemRDL trainings for Agnisys customers around the globe. \n*This webinar is in partnership with SemiWiki and Agnisys
URL:https://marketingeda.com/event/an-introduction-to-correct-by-construction-golden-specification-based-ip-soc-development/
CATEGORIES:EDA,Webinar
ATTACH;FMTTYPE=image/webp:https://marketingeda.com/wp-content/uploads/Agnisys-August-3-2023.webp
END:VEVENT
BEGIN:VEVENT
DTSTART;TZID=America/Los_Angeles:20230802T100000
DTEND;TZID=America/Los_Angeles:20230802T110000
DTSTAMP:20230713T155542Z
CREATED:20230713T155542Z
LAST-MODIFIED:20230713T155542Z
UID:6582-1690970400-1690974000@marketingeda.com
SUMMARY:Accelerate Coverage Closure with Synopsys VSO.ai
DESCRIPTION:70% of engineering time is spent verifying a design but it is largely a manual effort. As the industry faces ongoing engineering shortages companies are forced to make their engineering teams 10 times more productive at finding and isolating bugs per day. Increasing design complexities are also driving up the compute resources needed to verify todays designs. \n  \nTo address these resource challenges\, teams need to shift from an entirely manual verification process to utilizing autonomous verification – where human interaction is reduced\, enabling the ability to achieve coverage closure faster. The goal is that once a coverage target is set\, the system works autonomously to reach the target as quickly and cheaply as possible with the highest quality of results. \n  \nThis Synopsys webinar will introduce and explore the Synopsys VSO.ai™ solution\, Verification Space Optimization\, using machine learning technologies to identify and eliminate redundancies in regressions\, automate coverage root cause analysis\, and infer coverage from RTL and stimulus to identify coverage gaps and provide coverage guidance. \n\nSpeakers\n\n\nListed below are the industry leaders scheduled to speak. \n\n\n\n\nWill Chen\n\n\nPrincipal Applications Engineer\nSynopsys \n\n\n\n\n\n\n\n\n\n\n\nWill Chen is a Principal Applications engineer in Synopsys’ Customer Success EDA Group. Will has over 20 years of experience with account and project management for functional verification. He has recently been focusing on using AI/ML to improve verification efficiency and productivity. \n\n\n\n\nTaruna Reddy\n\n\nStaff Product Manager\nSynopsys \n\n\n\n\n\n\n\n\n\n\n\nTaruna Reddy is a Staff Product Manager in the EDA Group at Synopsys. Taruna has 18 years of experience in EDA and functional verification. Prior to joining Synopsys\, Taruna held field applications and verification engineering positions at Mentor Graphics\, Verilab and Xtreme-EDA.
URL:https://marketingeda.com/event/accelerate-coverage-closure-with-synopsys-vso-ai/
CATEGORIES:EDA,Webinar
ATTACH;FMTTYPE=image/jpeg:https://marketingeda.com/wp-content/uploads/Synopsys-July-19-2023.jpg
END:VEVENT
BEGIN:VEVENT
DTSTART;TZID=America/Los_Angeles:20230726T100000
DTEND;TZID=America/Los_Angeles:20230726T110000
DTSTAMP:20230724T212740Z
CREATED:20230724T212740Z
LAST-MODIFIED:20230724T212740Z
UID:6609-1690365600-1690369200@marketingeda.com
SUMMARY:A Novel Approach to Implementing Logical ECOs with Synopsys Formality ECO on High Performance RISC-V Cores
DESCRIPTION:RTL engineering change order (ECO) is vital to ensuring proper functionality of integrated circuits (ICs). Retiming and auto ungrouping optimize RTL implementation and enhance PPA. However\, aggressive optimizations in CPU RTL designs present challenges due to increased design complexity and potential mapping issues. \n  \nSynopsys Formality ECO offers an efficient and accurate solution for RTL ECO by automating the comprehensive ECO flow\, analyzing differences between original RTL and ECO RTL\, generating patches\, and validating changes. Formality ECO also supports aggressive RTL optimization techniques\, including retiming and auto ungrouping\, while providing advanced analysis and debug features to streamline the ECO process. \n  \nIn this Synopsys webinar\, presenters from SiFive will share the advantages of Synopsys Formality ECO on their overall ECO cycle which has enhanced patching capabilities and resulted in faster verification runtime leading to improved TAT. With the retimed and flattened design\, it is difficult to generate the sizable patch for fast CPUs designs targeted by SiFive. SiFive designs have strict requirements on the patch size\, patch affecting hierarchies\, changes applicable to RTL and ease of implementation at route_opt stage. By using Synopsys Formality ECO suite\, SiFive has been able to generate a hassle-free patch and verify it 3-5x faster than traditional formal verification ensuring performance of the CPU. \n\nSpeakers\n\n\nListed below are the industry leaders scheduled to speak. \n\n\n\n\nVivek Upadhyaya\n\n\nTechnical Director\nSiFive \n\n\n\n\n\n\n\n\nVivek Upadhyaya brings over 20 years of extensive experience in VLSI industry\, specializing in High-Speed CPU Implementation. Currently he is holding esteemed position as a Technical Director at SiFive in Physical Implementation Group. His previous roles encompassed notable companies such as Broadcom\, Cadence\, Intel\, and STMicroelectronics\, focusing on RTL-to-GDSII implementation. He is graduate from CCS University Meerut\, UP. \n\n\n\n\nRupali Kale Gaikwad\n\n\nStaff Engineer\nSynopsys \n\n\n\n\n\n\n\n\nRupali Kale Gaikwad is a Staff Engineer at Synopsys\, holds Master’s degree in Microelectronics from BITS\, Pilani. Over a span of 12 years\, she has worked on various advanced node ASIC designs of different sectors including automotive\, networking\, modem\, healthcare\, high speed CPU implementation. In Synopsys she is responsible for Ecosystem customer success for complete RTL2GDS solution.
URL:https://marketingeda.com/event/a-novel-approach-to-implementing-logical-ecos-with-synopsys-formality-eco-on-high-performance-risc-v-cores/
CATEGORIES:EDA,Webinar
ATTACH;FMTTYPE=image/jpeg:https://marketingeda.com/wp-content/uploads/Synopsys-July-26-2023.jpg
END:VEVENT
BEGIN:VEVENT
DTSTART;TZID=America/Los_Angeles:20230726T100000
DTEND;TZID=America/Los_Angeles:20230726T110000
DTSTAMP:20230713T160341Z
CREATED:20230713T160341Z
LAST-MODIFIED:20230713T160341Z
UID:6586-1690365600-1690369200@marketingeda.com
SUMMARY:Solution for 3D-IC Interposer Signal Integrity
DESCRIPTION:3D-IC design requires early analysis of thermal properties\, power delivery\, and signal integrity. This webinar will work through the process of simulating heterogeneously integrated chiplets. Learn about the integrated workflow that begins with silicon design data being accurately modeled with 3D FEM extraction. The Cadence Clarity 3D Solver has the unique ability to efficiently import and solve for complex structures\, including degassing holes. Accurate interconnect models can then be cascaded with IBIS I/O models for end-to-end signal integrity analysis and confirm that high-speed signals meet compliance testing. \nIncluded will be a step-by-step approach to importing GDS into the simulation environment. The interposer multiblock analysis workflow in Clarity 3D Solver will show how to edit the layout\, simulate\, and then view all simulation results. \nIf you think performing channel extractions on a large interposer is a complex and time-consuming process\, this is the perfect webinar for you.
URL:https://marketingeda.com/event/solution-for-3d-ic-interposer-signal-integrity-2/
CATEGORIES:EDA,Webinar
ATTACH;FMTTYPE=image/jpeg:https://marketingeda.com/wp-content/uploads/Cadence-July-26-2023-1.jpg
END:VEVENT
BEGIN:VEVENT
DTSTART;TZID=America/Los_Angeles:20230726T100000
DTEND;TZID=America/Los_Angeles:20230726T110000
DTSTAMP:20230629T182125Z
CREATED:20230629T182125Z
LAST-MODIFIED:20230629T182125Z
UID:6562-1690365600-1690369200@marketingeda.com
SUMMARY:Solution for 3D-IC Interposer Signal Integrity
DESCRIPTION:Our upcoming CadenceTECHTALK: Solution for 3D-IC Interposer Signal Integrity is designed to teach engineers to translate a GDSII stream format (GDSII) file and partition it into simulation blocks for the Clarity 3D field solver. \nFirst\, you will learn to use GDS-supporting files to simplify GDS to SPD translation and reuse those files to make the translation effortlessly repeatable. You will then learn to use the interposer multiblock analysis workflow in Clarity\, edit the layout\, if necessary\, using scripts\, create ports concurrently\, set up computer resources\, and then view all simulation results. \nIf you think performing channel extractions on a large interposer is a complex and time-consuming process\, this is the perfect webinar for you. \nFor questions\, inquiries\, or issues with registration\, send an email to events@cadence.com 
URL:https://marketingeda.com/event/solution-for-3d-ic-interposer-signal-integrity/
CATEGORIES:EDA,Webinar
ATTACH;FMTTYPE=image/jpeg:https://marketingeda.com/wp-content/uploads/Cadence-July-26-2023.jpg
END:VEVENT
BEGIN:VEVENT
DTSTART;TZID=America/Los_Angeles:20230720T100000
DTEND;TZID=America/Los_Angeles:20230720T110000
DTSTAMP:20230713T201325Z
CREATED:20230713T201325Z
LAST-MODIFIED:20230713T201325Z
UID:6595-1689847200-1689850800@marketingeda.com
SUMMARY:Achieve First-pass Silicon Leveraging SDC Verification Early with No Noise
DESCRIPTION:As today’s designs are getting more complex\, design constraints complexity also increases multifold. While ensuring design correctness typically gets a lot of attention including code review\, functional verification\, implementation\, etc.\, correctness of constraints requires the same level of attention. Quality of implementation and timing analysis is highly dependent on quality of constraints. For achieving first-past silicon efficiently\, it is imperative to ensure that the constraints are correct and complete early at RTL before progressing to late design stages of implementation and timing analysis. \n  \nIn this presentation\, we will focus on the conceptual foundations of constraints verification at RTL using Synopsys Timing Constraints Manager. Further\, we will cover the types of constraints issues flagged and noise reduction techniques using built in formal verification. Lastly\, we will discuss the need for timing exception verification (MCP/FP) and the use of formal and simulation techniques to deliver complete verification results to pinpoint incorrect timing exceptions. \n\nSpeaker\n\n\nListed below is the industry leader scheduled to speak. \n\n\n\n\nRimpy Chugh\n\n\nSenior Product Marketing Manager\nSynopsys \n\n\n\n\n\n\n\n\nRimpy Chugh is a Senior Product Marketing Manager in the Verification Group at Synopsys\, with 10 years of varied experience in EDA and functional verification. Prior to joining Synopsys\, Rimpy held field applications and verification engineering positions at Mentor Graphics\, Cadence and HCL Technologies. She holds an MBA from Indian Institute of Management\, Bangalore and a Bachelor of Technology from YMCA Institute of Technology\, India.
URL:https://marketingeda.com/event/achieve-first-pass-silicon-leveraging-sdc-verification-early-with-no-noise/
CATEGORIES:EDA,Webinar
ATTACH;FMTTYPE=image/jpeg:https://marketingeda.com/wp-content/uploads/Synopsys-July-20-2023.jpg
END:VEVENT
BEGIN:VEVENT
DTSTART;TZID=America/Los_Angeles:20230720T080000
DTEND;TZID=America/Los_Angeles:20230720T090000
DTSTAMP:20230629T192722Z
CREATED:20230629T192722Z
LAST-MODIFIED:20230629T192722Z
UID:6565-1689840000-1689843600@marketingeda.com
SUMMARY:3D-IC Foundry Frameworks
DESCRIPTION:Join us on July 20th; Ansys R&D members will discuss an overview of the 3D-IC technology development frameworks offered by TSMC\, Samsung\, and Intel and how Ansys simulation tools and workflows fit into those frameworks. \n\n\nAbout this Webinar\nSemiconductor applications such as Mobile (5G)\, Automotive\, and Datacenter (HPC\, AI) demand better scaling\, performance\, and lower power usage. Advanced packaging is moving towards 3DIC systems to address these needs\, as evidenced by the technology directions from TSMC\, Samsung\, and Intel. We’ll present a comprehensive overview of these technologies\, and the Ansys flows to address EMIR\, Thermal integrity\, and mechanical stress challenges posed by these 3DIC systems. \nWhat You Will Learn\n\nAdvanced 3DIC packaging trends and challenges faced by engineers\n3DIC system data flows from P&R to analysis tools\nEMIR and Thermal Integrity flows using RedHawk SCTM and RedHawk SC ElectroThermalTM\n\n\n\n\n\nSpeakers\nMallik Vusirikala\n\nMallik Vusirikala is a Director Product Specialist at Ansys\, responsible for strategic directions and deployment of the RedHawk product line for Power integrity and related solutions. He has been with Ansys for over 12 years. Prior to that he was with Texas instruments in the CAD flow/ methodology group developing multiple flows for standard cell library creation. He obtained his bachelor’s degree with Honors in Computer Science and Engineering from the National Institute of Technology\, Hamirpur (India). \nDr. Lang Lin\n\nDr. Lang Lin is a principal product manager of Ansys Inc. based in San Jose\, California. He is dedicated into developing 3D-IC multiphysics simulation and security verification methodologies to worldwide semiconductor customers. Before joining Ansys\, he worked for Intel Corp. as a design engineer. He has published 50+ technical papers and patents\, served as reviewer\, program committee or tutorial speaker of several IEEE conferences such as HOST\, ICCAD\, DAC and ASPDAC.
URL:https://marketingeda.com/event/3d-ic-foundry-frameworks/
CATEGORIES:EDA,Foundry,Webinar
ATTACH;FMTTYPE=image/jpeg:https://marketingeda.com/wp-content/uploads/Ansys-July-20-2023.jpg
END:VEVENT
BEGIN:VEVENT
DTSTART;TZID=America/Los_Angeles:20230719T100000
DTEND;TZID=America/Los_Angeles:20230719T110000
DTSTAMP:20230713T154956Z
CREATED:20230713T154956Z
LAST-MODIFIED:20230713T154956Z
UID:6579-1689760800-1689764400@marketingeda.com
SUMMARY:Achieve Optimal PPA Targets Using AI-Driven Technology
DESCRIPTION:Complexity brought on by advanced process nodes have opened the door to challenges in achieving optimal power\, performance\, and area (PPA). Manual methods are no longer viable given shrinking market windows. The need to drive for better results faster is increasing\, and traditional methods cannot keep pace often taking months of tuning using 100s of trials. Even then\, results are not optimal. AI-driven technology can help. \n  \nThis Synopsys webinar discusses the challenges facing engineers creating complex designs and introduces Synopsys Design Space Optimization solution\, DSO.ai™. The industry’s first autonomous artificial intelligence (AI) application for chip design\, Synopsys DSO.ai searches for optimization targets in very large solution spaces of chip design\, utilizing reinforcement learning to enhance power\, performance\, and area. RTL-to-GDSII full flow optimization unlocks PPA potential across both logical and physical domains with reported productivity enhancements of more than 3x\, power reductions of up to 15%\, and substantial die size reductions. We’ll explore case studies from AMD\, Intel\, and STMicro on how they are applying this technology to surpass the most challenging goals in chip design and reach new levels of productivity.
URL:https://marketingeda.com/event/achieve-optimal-ppa-targets-using-ai-driven-technology/
CATEGORIES:EDA,Webinar
ATTACH;FMTTYPE=image/jpeg:https://marketingeda.com/wp-content/uploads/Synopsys-July-19-2023.jpg
END:VEVENT
BEGIN:VEVENT
DTSTART;TZID=America/Los_Angeles:20230718T110000
DTEND;TZID=America/Los_Angeles:20230718T120000
DTSTAMP:20230713T190809Z
CREATED:20230713T190809Z
LAST-MODIFIED:20230713T190809Z
UID:6589-1689678000-1689681600@marketingeda.com
SUMMARY:Automated Verification for Cache Coherent RISC-V SoCs
DESCRIPTION:RISC-V SoC design complexity continues to increase and create new verification challenges. Private caches\, shared caches\, and shared main memory create potential caches/memory coherency problems that require modern\, automated verification approaches. \nIn this webinar\, we’ll demonstrate how Perspec System Verifier\, with the pre-defined System Traffic Library (STL)\, provides an out-of-the-box verification plan and test suite for heterogeneous\, multi-core\, and cache-coherent processors. STL has built-in atomic actions and coherency scenarios to allow verification engineers to quickly generate test scenarios\, such as targeting false sharing\, true sharing\, cache state transitions\, snoop traffic\, coherency irritators\, extreme stress scenarios\, IO coherency\, and many more areas. Perspec System Verifier also helps visualize scenarios and analyze coverage before test execution.
URL:https://marketingeda.com/event/automated-verification-for-cache-coherent-risc-v-socs/
CATEGORIES:EDA,Webinar
ATTACH;FMTTYPE=image/jpeg:https://marketingeda.com/wp-content/uploads/Cadence-July-18-2023.jpg
END:VEVENT
BEGIN:VEVENT
DTSTART;TZID=America/Los_Angeles:20230718T100000
DTEND;TZID=America/Los_Angeles:20230718T110000
DTSTAMP:20230713T200623Z
CREATED:20230713T200623Z
LAST-MODIFIED:20230713T200623Z
UID:6592-1689674400-1689678000@marketingeda.com
SUMMARY:Key MAC Considerations for the Road to 1.6T Ethernet Success
DESCRIPTION:224G SerDes designs are a reality and the path to 1.6T is clearer than ever. This webinar delves into the considerations\, challenges and solutions designers need to know for the MAC required for these 224G Ethernet PHY IP designs. Dive deep into the nuances of PHY/MAC layer interactions\, timing considerations\, and forward error correction.  We will shed light on key challenges for bandwidth hungry applications including latency optimization\, and SI techniques. Discover how Synopsys MAC IP solutions can help ensure your product is first to market. \n\nSpeakers\n\n\nListed below are the industry leaders scheduled to speak. \n\n\n\n\nJohn Swanson\n\n\nHPC Controller & Datapath Product Line Manager\nSynopsys \n\n\n\n\n\n\n\n\n\n\n\nJohn Swanson is the HPC Controller & Datapath Product Line Manager in Synopsys’ Solutions Group. John has worked in the development and deployment of verification\, integration\, and implementation tools\, IP\, standards\, and methodologies used in IP based design for over 25 years. His assignments have encompassed engineering\, methodology\, business development\, and marketing. John has also been involved in various standards activities including Chair of the Verification Technical Working Group in the SPIRIT Consortium; Synopsys representative on the Power.org technical subcommittee and is active in many IEEE and consortium groups today. \nPrior to joining Synopsys\, he worked for Amoco Oil working on wellhead automation and control systems. He is an Honor graduate from DeVry Institute of Technology where he completed his Engineering degree with Presidents List Honors. \n\n\n\n\nJon Ames\n\n\nSr. Staff Product Marketing Manager\nSynopsys \n\n\n\n\n\n\n\n\n\n\n\nJon Ames is a Sr. Staff Product Marketing Manager for the Synopsys Ethernet Controller IP portfolio.  Jon has been working in the communications industry since 1988 and has led engineering and market activities from the early days of 10/100 Switched Ethernet through Metro and Transport variants to the latest Data Center and High-Performance Computing Ethernet technologies.  Since graduating in Computer Science and Electronic Engineering the in UK\, Jon has worked at the leading companies in the networking and silicon solution industries.
URL:https://marketingeda.com/event/key-mac-considerations-for-the-road-to-1-6t-ethernet-success/
CATEGORIES:IP,Webinar
ATTACH;FMTTYPE=image/jpeg:https://marketingeda.com/wp-content/uploads/Synopsys-July-18-2023.jpg
END:VEVENT
BEGIN:VEVENT
DTSTART;TZID=America/Los_Angeles:20230713T100000
DTEND;TZID=America/Los_Angeles:20230713T110000
DTSTAMP:20230620T160839Z
CREATED:20230620T160839Z
LAST-MODIFIED:20230620T160839Z
UID:6529-1689242400-1689246000@marketingeda.com
SUMMARY:Comprehensive Static Verification for FPGA and ASIC RTL Designers
DESCRIPTION:As designs get increasingly complex\, design teams are looking to find bugs earlier\, to reduce rework and shorten time-to-market. The ultimate “shift left” is to put easy-to-use static verification in the hands of RTL designers to eliminate bugs at their source. \nThis webinar covers comprehensive static verification capabilities in the Cadence® Jasper™ Superlint and CDC apps for lint\, design-for-test (DFT)\, clock domain crossing (CDC)\, and reset domain crossing (RDC). \n\nWhat You Will Learn \n\nAll the static checks that should be performed to hand off better-quality RTL\nHow Jasper apps provide easy-to-use debug capabilities\, leveraging Jasper’s industry-leading formal verification technology to reduce noise and automate violation handling and waivers\nAutomatic formal checks\, which do not require any formal verification experience\, add significant value beyond the structural-only checks that most designers are used to\n\n\nFPGA designs have grown immensely in complexity and are just as prone to CDC bug escapes as ASIC designs\, so we encourage all RTL designers to attend.
URL:https://marketingeda.com/event/comprehensive-static-verification-for-fpga-and-asic-rtl-designers/
CATEGORIES:EDA,Webinar
ATTACH;FMTTYPE=image/jpeg:https://marketingeda.com/wp-content/uploads/Cadence-July-13-2023.jpg
END:VEVENT
BEGIN:VEVENT
DTSTART;TZID=America/Los_Angeles:20230712T120000
DTEND;TZID=America/Los_Angeles:20230712T130000
DTSTAMP:20230621T180336Z
CREATED:20230621T180336Z
LAST-MODIFIED:20230621T180336Z
UID:6550-1689163200-1689166800@marketingeda.com
SUMMARY:An AI/ML Driven High-Level Synthesis Solution
DESCRIPTION:High-Level Synthesis (HLS) tools yield better PPA when the “right set” of optimization constraints and tool settings are applied. Determining the right set of constraints and settings requires design and tool experience and exploration. AI/ML technology has proven highly effective at exploring the solution space and lowering the required tool expertise. This CadenceTECHTALK™ presents details on the integration of Stratus HLS with the Cadence Cerebrus™ Intelligent Chip Explorer. Join us and learn how the Cadence Cerebrus/Stratus integration efficiently explores the solution space and lowers the learning curve for producing expert-quality HLS results.
URL:https://marketingeda.com/event/an-ai-ml-driven-high-level-synthesis-solution/
CATEGORIES:EDA,Webinar
ATTACH;FMTTYPE=image/jpeg:https://marketingeda.com/wp-content/uploads/Cadence-July-12-2023.jpg
END:VEVENT
BEGIN:VEVENT
DTSTART;TZID=Europe/London:20230711T120000
DTEND;TZID=Europe/London:20230711T130000
DTSTAMP:20230608T155840Z
CREATED:20230608T155840Z
LAST-MODIFIED:20230608T155840Z
UID:6467-1689076800-1689080400@marketingeda.com
SUMMARY:Embedded UVM (eUVM)
DESCRIPTION:This is to inform you that the next DVClub Europe meeting takes place on Tuesday 11th July with a theme of “Embedded UVM(eUVM)”.\n\nIntroduction to Embedded UVM to enable HPC-Powered UVM Testbenches with MultiCore Performance.\n\nAgenda (BST) \n12:00   Welcome and Introduction – Mike Bartley\, Senior Vice President – VLSI Design\, Tessolve \n12:00   Puneet Goel\, Coverify Systems Technology LLP – HPC-Powered UVM Testbenching \n13:00   TBD \nRegister now to become a part of this event. Free to attend online. \nEventbrite – DVClub Europe 
URL:https://marketingeda.com/event/embedded-uvm-euvm/
CATEGORIES:EDA,Webinar
ATTACH;FMTTYPE=image/jpeg:https://marketingeda.com/wp-content/uploads/DVClub-Europe-2023.jpg
END:VEVENT
BEGIN:VEVENT
DTSTART;TZID=America/Los_Angeles:20230629T140000
DTEND;TZID=America/Los_Angeles:20230629T153000
DTSTAMP:20230602T184706Z
CREATED:20230602T184706Z
LAST-MODIFIED:20230602T184706Z
UID:6447-1688047200-1688052600@marketingeda.com
SUMMARY:UCIe PHY Modeling and Simulation with XMODEL
DESCRIPTION:Chiplets are emerging as a new way of building IC systems via heterogeneous integration\, and Universal Chip Interconnect Express (UCIe) is one of the standards defining the interconnects among chiplets. This webinar presents the SystemVerilog models of a Universal Chiplet Interconnect Express (UCIe) interface\, including both the analog circuits in the electrical layer and digital FSMs in the logical layer. The whole physical layer (PHY) model can be efficiently simulated in SystemVerilog\, using Scientific Analog’s XMODEL. \nThis webinar is organized in two parts. The first part gives a brief overview of the UCIe standard and explains why XMODEL is the best way to model and verify UCIe PHY\, especially considering the close interactions between its electrical layer and logical layer. It will show how to model various analog circuits in the electrical layer\, including the phase-locked loop (PLL)\, delay-locked loop (DLL)\, duty-cycle corrector\, phase interpolator\, and transmitter/receiver circuits. Each circuit block is modeled using XMODEL primitives\, which enable fast and accurate simulation of their analog behaviors in SystemVerilog. \nThe second part shows how you can design the finite-state machines (FSMs) in the logical layer\, performing digital training and calibrations on the reference voltage levels\, clock-to-data timing\, lane-to-lane skews\, and link data rate via a series of data transmission tests with pseudo-random bit sequences. All the FSMs are described in SystemVerilog\, and with XMODEL\, you can simulate this logical layer model interacting with the electrical layer model entirely in SystemVerilog. It implies that you can also use various features of SystemVerilog to check the thoroughness of your simulation\, such as checking the FSM state coverage. \nThis webinar will be beneficial to everyone who is interested in the design and verification of UCIe PHY. For analog circuit designers\, the presented models will help understand the requirements posed on each circuit block\, such as the scaling of bandwidth to support a wide range of data rates from 4GT/s to 32GT/s. For digital verification engineers\, the presented testbenches will show how to perform SystemVerilog-based verification on the systems containing analog circuits. And most importantly\, by running the simulations with the provided models\, you can gain a hands-on understanding on how the various components of a UCIe PHY work to realize a high-bandwidth interconnect between chiplets.
URL:https://marketingeda.com/event/ucie-phy-modeling-and-simulation-with-xmodel/
CATEGORIES:EDA,Webinar
ATTACH;FMTTYPE=image/jpeg:https://marketingeda.com/wp-content/uploads/Scientific-Analog-June-29-2023.jpg
END:VEVENT
BEGIN:VEVENT
DTSTART;TZID=America/Los_Angeles:20230627T110000
DTEND;TZID=America/Los_Angeles:20230627T120000
DTSTAMP:20230616T173450Z
CREATED:20230616T173450Z
LAST-MODIFIED:20230616T173450Z
UID:6502-1687863600-1687867200@marketingeda.com
SUMMARY:Verisium Debug for UPF Low Power Design
DESCRIPTION:Verisium Debug offers comprehensive debugging capabilities. From RTL\, UVM testbench to UPF low-power designs\, users can use the Cadence unified debugging platform for debugging. In this webinar\, users will learn about the available features in Verisium Debug for UPF power-aware designs and using the unique capabilities to visualize and debug UPF low-power designs. \nWhat you will learn \n\nUnderstand features available in Verisium Debug\n​Learn about the low-power debug capabilities available in Verisium Debug\nLearn how to debug UPF low-power designs with Verisium Debug\n\nWho should attend \n\nDesign engineers\nVerification engineers\nCAD engineers
URL:https://marketingeda.com/event/verisium-debug-for-upf-low-power-design/
CATEGORIES:EDA,Webinar
ATTACH;FMTTYPE=image/jpeg:https://marketingeda.com/wp-content/uploads/Cadence-June-27-2023.jpg
END:VEVENT
BEGIN:VEVENT
DTSTART;TZID=America/Los_Angeles:20230623T100000
DTEND;TZID=America/Los_Angeles:20230623T110000
DTSTAMP:20230612T212746Z
CREATED:20230612T212528Z
LAST-MODIFIED:20230612T212746Z
UID:6485-1687514400-1687518000@marketingeda.com
SUMMARY:Dealing with Complexity in Formal through Abstraction and Reduction
DESCRIPTION:In the world of formal verification\, abstractions along with design reductions\, help reduce the state space and make it easier for formal to converge on its proofs. \nIn this webinar Doulos Senior Member Technical Staff\, Doug Smith will explore the process of abstraction\, safe design reductions\, and when to use them. Doug will show practical examples of both (using VC Formal from Synopsys) and discuss formal results obtained by using abstractions and reductions. \nThe content will be useful to anyone who wants to learn to make more effective use of formal. \nAttendance is FREE and live Q&A will be provided throughout the broadcast. \n\n \nDoug Smith – Doulos Senior Member Technical Staff will present this training webinar\, which will consist of a one-hour presentation with interactive Q&A available to attendees throughout. \n\nAttendance is free of charge \nIf you have any queries\, please contact webinars@doulos.com
URL:https://marketingeda.com/event/dealing-with-complexity-in-formal-through-abstraction-and-reduction/
CATEGORIES:EDA,Webinar
ATTACH;FMTTYPE=image/jpeg:https://marketingeda.com/wp-content/uploads/Doulos-June-23-2023.jpg
ORGANIZER;CN="Doulos":MAILTO:webinars@duolos.com
END:VEVENT
BEGIN:VEVENT
DTSTART;TZID=America/Los_Angeles:20230622T110000
DTEND;TZID=America/Los_Angeles:20230622T120000
DTSTAMP:20230620T182517Z
CREATED:20230620T182517Z
LAST-MODIFIED:20230620T182517Z
UID:6546-1687431600-1687435200@marketingeda.com
SUMMARY:How AI and Semiconductors Will Drive Innovation and Productivity
DESCRIPTION:Semiconductors are critical to the functioning of the modern world driving economic competitiveness\, national security\, and technologies ranging from modern defense capabilities to autonomous vehicles. Artificial Intelligence and the hardware used in this platform are impacting how the world will use information to increase productivity. The semiconductors used in these platforms are instrumental to its functionality and are the backbone behind advancements in these technologies. \nPlease join a panel of industry experts for a conversation on how semiconductors are enabling the revolution in AI and what it means for the U.S. economy. Panelists include Jerry Chen\, Director of Global Business Development for Manufacturing & Industrial at NVIDIA; Ramine Roane Corporate Vice President of AI at AMD; and Stelios Diamantidis\, head of Synopsys’ Artificial Intelligence Strategy in the Office of the President. The session will be moderated by Robert Casanova\, Director of Industry Statistics and Economy Policy at SIA.
URL:https://marketingeda.com/event/how-ai-and-semiconductors-will-drive-innovation-and-productivity/
CATEGORIES:EDA,IP,Webinar
ATTACH;FMTTYPE=image/jpeg:https://marketingeda.com/wp-content/uploads/SIA-June-22-2023.jpg
END:VEVENT
BEGIN:VEVENT
DTSTART;TZID=America/Los_Angeles:20230622T080000
DTEND;TZID=America/Los_Angeles:20230622T090000
DTSTAMP:20230612T175957Z
CREATED:20230612T175957Z
LAST-MODIFIED:20230612T175957Z
UID:6475-1687420800-1687424400@marketingeda.com
SUMMARY:Design and Analysis of Multi-Die & 3D-IC Systems
DESCRIPTION:The architecture and heterogeneous integration capability of 3D-IC (three-dimensional integrated circuits) offer many benefits. The latest configuration methods\, CoWoS (Chip On Wafer on Substrate) and WoW (Wafer on Wafer) from TSMC\, provide advantages by significantly reducing the interconnect length and signal power loss. These new technologies have introduced the need for innovative ways to solve novel physics challenges. Solving the complex issues related to the structural\, thermal\, power\, and signal integrity of the entire 2.5D/3D-IC system cannot be accomplished using only traditional tools. Advanced simulation methods and highly accurate solvers are required to accurately predict the entire multiphysics coupling in 3D-IC systems including interposers and heterogeneous components. \nIn this webinar\, Jerome discusses the latest developments in 3D-IC design\, challenges\, and how simulation is the key to successful 3D-IC design. He also presents a comprehensive environment to simulate these physics and achieve the Structural\, Thermal\, Power\, and Signal integrity of the entire 3D-IC system. Chiplet designers\, Interposer designers\, 3D-IC designers\, and 3D-IC architects will find this webinar helpful. \nPresenter: \nJerome Toublanc has over 20 years of Semiconductor industry experience\, working for various EDA companies such as Avanti\, Synopsys\, and Apache. He has contributed to the successes of worldwide customers in roles ranging from Application Engineer to Product Management and has covered the chip development flow from RTL to GDSII. He is now a business development executive for Ansys. His mission is to identify emerging Multiphysics Integrity challenges within the semiconductor industry and develop product solutions for the complete Chip-Package-PCB ecosystem. \n*This webinar is in partnership with SemiWiki and Ansys*
URL:https://marketingeda.com/event/design-and-analysis-of-multi-die-3d-ic-systems/
CATEGORIES:EDA,Webinar
ATTACH;FMTTYPE=image/webp:https://marketingeda.com/wp-content/uploads/Ansys-June-22-2023.webp
END:VEVENT
BEGIN:VEVENT
DTSTART;TZID=America/Los_Angeles:20230621T100000
DTEND;TZID=America/Los_Angeles:20230621T110000
DTSTAMP:20230612T212024Z
CREATED:20230612T211941Z
LAST-MODIFIED:20230612T212024Z
UID:6481-1687341600-1687345200@marketingeda.com
SUMMARY:Achieve Out-of-the-Box Equivalence Checking with Synopsys Formality ML-driven Distributed Processing
DESCRIPTION:When designers synthesize chip designs with aggressive PPA targets\, the expectation and goal is to be able to complete verification with minimal effort and a fast turn-around-time. Synopsys Design Compiler and Fusion Compiler offer a broad spectrum of optimization techniques such as retiming\, multibit banking and advanced data-path optimizations\, though these techniques can end up being inconsequential if they cannot be verified through equivalence checking. Therefore\, the ideal setup is completed quickly using equivalence checking to provide out-of-the-box results so lengthy iterations and engineer hours aren’t spent converging on verification pass.\nThis presentation will detail how Synopsys Formality ML-driven Distributed Processing (DPX) delivered out-of-the-box verification for STMicroelectronics Design team without the need to scale back optimizations or sacrifice PPA goals. Attendees will walk away with an understanding of how Synopsys Formality equivalence checking captures the design transformation/optimizations in Formality Guide Files (SVF) for rapid setup of the verification environment to avoid multiple iterative runs. In addition\, ML-driven adaptive distributed verification techniques will be highlighted\, which help to partition the design and run solvers in parallel to further accelerate verification runtime and out-of-the-box results. \nSpeakers\n\n\n\n\nNathalie Méloux\n\n\nPrincipal Engineer\nSTMicroelectronics \n\n\n\n\n\n\n\n\nNathalie Méloux\, Principal Engineer at STMicroelectronics\, has been working in the microcontroller division for over 20 years. She has greatly contributed to the development of the STM32 microcontrollers families since its inception. Nathalie has extensive experience in the areas of digital design methodology and low-power implementation flow. She is in charge of the digital flow\, the support of the design implementation from RTL through Synthesis to P&R including signoff timing analysis\, equivalence checking\, power analysis and optimizations all along the flow. \nNathalie Meloux holds a master’s degree in Microelectronics and Robotics from Polytech Montpellier\, France and a D.E.A. (post-Master’s degree) in Microelectronics from the University of Montpellier (Faculty of Science)\, France. \n\n\n\n\nStephane Maulet\n\n\nApplications Engineer\, Sr Staff\nSynopsys \n\n\n\n\n\n\n\n\nStephane Maulet is a Senior Staff Applications Engineer at Synopsys. He has almost 20 years of experience in Synopsys front-end tools spanning Synopsys Design Compiler\, Synopsys Fusion Compiler\, Synopsys Formality and Synopsys Formality ECO. \nStephane holds a master’s degree in Microelectronics Engineering from Grenoble INP\, France.
URL:https://marketingeda.com/event/out-of-the-box-equivalence-checking-synopsys-formality/
CATEGORIES:EDA,Webinar
ATTACH;FMTTYPE=image/jpeg:https://marketingeda.com/wp-content/uploads/Synopsys-June-21-2023.jpg
END:VEVENT
BEGIN:VEVENT
DTSTART;TZID=America/Los_Angeles:20230621T100000
DTEND;TZID=America/Los_Angeles:20230621T110000
DTSTAMP:20230606T180716Z
CREATED:20230606T180716Z
LAST-MODIFIED:20230606T180716Z
UID:6460-1687341600-1687345200@marketingeda.com
SUMMARY:Applying AI/ML Technology for Rapid Design Optimization
DESCRIPTION:The problem of optimization is a long-standing one in the field of design. For years\, the most conventional approach was the brute-force method of running parametric sweeps on the design space. However\, as systems become more complex and the number of parameters increases\, the computational resource and time cost becomes unsustainable. With the Cadence Optimality Explorer\, users can explore the same design space more efficiently and intelligently. By leveraging artificial intelligence/machine learning technology\, Optimality Explorer removes the need for exhaustive sweeps and dramatically reduces the number of iterations required to converge to the optimized solution.
URL:https://marketingeda.com/event/applying-ai-ml-technology-for-rapid-design-optimization/
CATEGORIES:EDA,Webinar
ATTACH;FMTTYPE=image/jpeg:https://marketingeda.com/wp-content/uploads/Cadence-June-21-2023-1.jpg
END:VEVENT
END:VCALENDAR