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BEGIN:VEVENT
DTSTART;TZID=America/Los_Angeles:20230726T100000
DTEND;TZID=America/Los_Angeles:20230726T110000
DTSTAMP:20230724T212740Z
CREATED:20230724T212740Z
LAST-MODIFIED:20230724T212740Z
UID:6609-1690365600-1690369200@marketingeda.com
SUMMARY:A Novel Approach to Implementing Logical ECOs with Synopsys Formality ECO on High Performance RISC-V Cores
DESCRIPTION:RTL engineering change order (ECO) is vital to ensuring proper functionality of integrated circuits (ICs). Retiming and auto ungrouping optimize RTL implementation and enhance PPA. However\, aggressive optimizations in CPU RTL designs present challenges due to increased design complexity and potential mapping issues. \n  \nSynopsys Formality ECO offers an efficient and accurate solution for RTL ECO by automating the comprehensive ECO flow\, analyzing differences between original RTL and ECO RTL\, generating patches\, and validating changes. Formality ECO also supports aggressive RTL optimization techniques\, including retiming and auto ungrouping\, while providing advanced analysis and debug features to streamline the ECO process. \n  \nIn this Synopsys webinar\, presenters from SiFive will share the advantages of Synopsys Formality ECO on their overall ECO cycle which has enhanced patching capabilities and resulted in faster verification runtime leading to improved TAT. With the retimed and flattened design\, it is difficult to generate the sizable patch for fast CPUs designs targeted by SiFive. SiFive designs have strict requirements on the patch size\, patch affecting hierarchies\, changes applicable to RTL and ease of implementation at route_opt stage. By using Synopsys Formality ECO suite\, SiFive has been able to generate a hassle-free patch and verify it 3-5x faster than traditional formal verification ensuring performance of the CPU. \n\nSpeakers\n\n\nListed below are the industry leaders scheduled to speak. \n\n\n\n\nVivek Upadhyaya\n\n\nTechnical Director\nSiFive \n\n\n\n\n\n\n\n\nVivek Upadhyaya brings over 20 years of extensive experience in VLSI industry\, specializing in High-Speed CPU Implementation. Currently he is holding esteemed position as a Technical Director at SiFive in Physical Implementation Group. His previous roles encompassed notable companies such as Broadcom\, Cadence\, Intel\, and STMicroelectronics\, focusing on RTL-to-GDSII implementation. He is graduate from CCS University Meerut\, UP. \n\n\n\n\nRupali Kale Gaikwad\n\n\nStaff Engineer\nSynopsys \n\n\n\n\n\n\n\n\nRupali Kale Gaikwad is a Staff Engineer at Synopsys\, holds Master’s degree in Microelectronics from BITS\, Pilani. Over a span of 12 years\, she has worked on various advanced node ASIC designs of different sectors including automotive\, networking\, modem\, healthcare\, high speed CPU implementation. In Synopsys she is responsible for Ecosystem customer success for complete RTL2GDS solution.
URL:https://marketingeda.com/event/a-novel-approach-to-implementing-logical-ecos-with-synopsys-formality-eco-on-high-performance-risc-v-cores/
CATEGORIES:EDA,Webinar
ATTACH;FMTTYPE=image/jpeg:https://marketingeda.com/wp-content/uploads/Synopsys-July-26-2023.jpg
END:VEVENT
BEGIN:VEVENT
DTSTART;TZID=America/Los_Angeles:20230726T100000
DTEND;TZID=America/Los_Angeles:20230726T110000
DTSTAMP:20230713T160341Z
CREATED:20230713T160341Z
LAST-MODIFIED:20230713T160341Z
UID:6586-1690365600-1690369200@marketingeda.com
SUMMARY:Solution for 3D-IC Interposer Signal Integrity
DESCRIPTION:3D-IC design requires early analysis of thermal properties\, power delivery\, and signal integrity. This webinar will work through the process of simulating heterogeneously integrated chiplets. Learn about the integrated workflow that begins with silicon design data being accurately modeled with 3D FEM extraction. The Cadence Clarity 3D Solver has the unique ability to efficiently import and solve for complex structures\, including degassing holes. Accurate interconnect models can then be cascaded with IBIS I/O models for end-to-end signal integrity analysis and confirm that high-speed signals meet compliance testing. \nIncluded will be a step-by-step approach to importing GDS into the simulation environment. The interposer multiblock analysis workflow in Clarity 3D Solver will show how to edit the layout\, simulate\, and then view all simulation results. \nIf you think performing channel extractions on a large interposer is a complex and time-consuming process\, this is the perfect webinar for you.
URL:https://marketingeda.com/event/solution-for-3d-ic-interposer-signal-integrity-2/
CATEGORIES:EDA,Webinar
ATTACH;FMTTYPE=image/jpeg:https://marketingeda.com/wp-content/uploads/Cadence-July-26-2023-1.jpg
END:VEVENT
BEGIN:VEVENT
DTSTART;TZID=America/Los_Angeles:20230726T100000
DTEND;TZID=America/Los_Angeles:20230726T110000
DTSTAMP:20230629T182125Z
CREATED:20230629T182125Z
LAST-MODIFIED:20230629T182125Z
UID:6562-1690365600-1690369200@marketingeda.com
SUMMARY:Solution for 3D-IC Interposer Signal Integrity
DESCRIPTION:Our upcoming CadenceTECHTALK: Solution for 3D-IC Interposer Signal Integrity is designed to teach engineers to translate a GDSII stream format (GDSII) file and partition it into simulation blocks for the Clarity 3D field solver. \nFirst\, you will learn to use GDS-supporting files to simplify GDS to SPD translation and reuse those files to make the translation effortlessly repeatable. You will then learn to use the interposer multiblock analysis workflow in Clarity\, edit the layout\, if necessary\, using scripts\, create ports concurrently\, set up computer resources\, and then view all simulation results. \nIf you think performing channel extractions on a large interposer is a complex and time-consuming process\, this is the perfect webinar for you. \nFor questions\, inquiries\, or issues with registration\, send an email to events@cadence.com 
URL:https://marketingeda.com/event/solution-for-3d-ic-interposer-signal-integrity/
CATEGORIES:EDA,Webinar
ATTACH;FMTTYPE=image/jpeg:https://marketingeda.com/wp-content/uploads/Cadence-July-26-2023.jpg
END:VEVENT
BEGIN:VEVENT
DTSTART;TZID=America/Los_Angeles:20230720T100000
DTEND;TZID=America/Los_Angeles:20230720T110000
DTSTAMP:20230713T201325Z
CREATED:20230713T201325Z
LAST-MODIFIED:20230713T201325Z
UID:6595-1689847200-1689850800@marketingeda.com
SUMMARY:Achieve First-pass Silicon Leveraging SDC Verification Early with No Noise
DESCRIPTION:As today’s designs are getting more complex\, design constraints complexity also increases multifold. While ensuring design correctness typically gets a lot of attention including code review\, functional verification\, implementation\, etc.\, correctness of constraints requires the same level of attention. Quality of implementation and timing analysis is highly dependent on quality of constraints. For achieving first-past silicon efficiently\, it is imperative to ensure that the constraints are correct and complete early at RTL before progressing to late design stages of implementation and timing analysis. \n  \nIn this presentation\, we will focus on the conceptual foundations of constraints verification at RTL using Synopsys Timing Constraints Manager. Further\, we will cover the types of constraints issues flagged and noise reduction techniques using built in formal verification. Lastly\, we will discuss the need for timing exception verification (MCP/FP) and the use of formal and simulation techniques to deliver complete verification results to pinpoint incorrect timing exceptions. \n\nSpeaker\n\n\nListed below is the industry leader scheduled to speak. \n\n\n\n\nRimpy Chugh\n\n\nSenior Product Marketing Manager\nSynopsys \n\n\n\n\n\n\n\n\nRimpy Chugh is a Senior Product Marketing Manager in the Verification Group at Synopsys\, with 10 years of varied experience in EDA and functional verification. Prior to joining Synopsys\, Rimpy held field applications and verification engineering positions at Mentor Graphics\, Cadence and HCL Technologies. She holds an MBA from Indian Institute of Management\, Bangalore and a Bachelor of Technology from YMCA Institute of Technology\, India.
URL:https://marketingeda.com/event/achieve-first-pass-silicon-leveraging-sdc-verification-early-with-no-noise/
CATEGORIES:EDA,Webinar
ATTACH;FMTTYPE=image/jpeg:https://marketingeda.com/wp-content/uploads/Synopsys-July-20-2023.jpg
END:VEVENT
BEGIN:VEVENT
DTSTART;TZID=America/Los_Angeles:20230720T080000
DTEND;TZID=America/Los_Angeles:20230720T090000
DTSTAMP:20230629T192722Z
CREATED:20230629T192722Z
LAST-MODIFIED:20230629T192722Z
UID:6565-1689840000-1689843600@marketingeda.com
SUMMARY:3D-IC Foundry Frameworks
DESCRIPTION:Join us on July 20th; Ansys R&D members will discuss an overview of the 3D-IC technology development frameworks offered by TSMC\, Samsung\, and Intel and how Ansys simulation tools and workflows fit into those frameworks. \n\n\nAbout this Webinar\nSemiconductor applications such as Mobile (5G)\, Automotive\, and Datacenter (HPC\, AI) demand better scaling\, performance\, and lower power usage. Advanced packaging is moving towards 3DIC systems to address these needs\, as evidenced by the technology directions from TSMC\, Samsung\, and Intel. We’ll present a comprehensive overview of these technologies\, and the Ansys flows to address EMIR\, Thermal integrity\, and mechanical stress challenges posed by these 3DIC systems. \nWhat You Will Learn\n\nAdvanced 3DIC packaging trends and challenges faced by engineers\n3DIC system data flows from P&R to analysis tools\nEMIR and Thermal Integrity flows using RedHawk SCTM and RedHawk SC ElectroThermalTM\n\n\n\n\n\nSpeakers\nMallik Vusirikala\n\nMallik Vusirikala is a Director Product Specialist at Ansys\, responsible for strategic directions and deployment of the RedHawk product line for Power integrity and related solutions. He has been with Ansys for over 12 years. Prior to that he was with Texas instruments in the CAD flow/ methodology group developing multiple flows for standard cell library creation. He obtained his bachelor’s degree with Honors in Computer Science and Engineering from the National Institute of Technology\, Hamirpur (India). \nDr. Lang Lin\n\nDr. Lang Lin is a principal product manager of Ansys Inc. based in San Jose\, California. He is dedicated into developing 3D-IC multiphysics simulation and security verification methodologies to worldwide semiconductor customers. Before joining Ansys\, he worked for Intel Corp. as a design engineer. He has published 50+ technical papers and patents\, served as reviewer\, program committee or tutorial speaker of several IEEE conferences such as HOST\, ICCAD\, DAC and ASPDAC.
URL:https://marketingeda.com/event/3d-ic-foundry-frameworks/
CATEGORIES:EDA,Foundry,Webinar
ATTACH;FMTTYPE=image/jpeg:https://marketingeda.com/wp-content/uploads/Ansys-July-20-2023.jpg
END:VEVENT
BEGIN:VEVENT
DTSTART;TZID=America/Los_Angeles:20230719T100000
DTEND;TZID=America/Los_Angeles:20230719T110000
DTSTAMP:20230713T154956Z
CREATED:20230713T154956Z
LAST-MODIFIED:20230713T154956Z
UID:6579-1689760800-1689764400@marketingeda.com
SUMMARY:Achieve Optimal PPA Targets Using AI-Driven Technology
DESCRIPTION:Complexity brought on by advanced process nodes have opened the door to challenges in achieving optimal power\, performance\, and area (PPA). Manual methods are no longer viable given shrinking market windows. The need to drive for better results faster is increasing\, and traditional methods cannot keep pace often taking months of tuning using 100s of trials. Even then\, results are not optimal. AI-driven technology can help. \n  \nThis Synopsys webinar discusses the challenges facing engineers creating complex designs and introduces Synopsys Design Space Optimization solution\, DSO.ai™. The industry’s first autonomous artificial intelligence (AI) application for chip design\, Synopsys DSO.ai searches for optimization targets in very large solution spaces of chip design\, utilizing reinforcement learning to enhance power\, performance\, and area. RTL-to-GDSII full flow optimization unlocks PPA potential across both logical and physical domains with reported productivity enhancements of more than 3x\, power reductions of up to 15%\, and substantial die size reductions. We’ll explore case studies from AMD\, Intel\, and STMicro on how they are applying this technology to surpass the most challenging goals in chip design and reach new levels of productivity.
URL:https://marketingeda.com/event/achieve-optimal-ppa-targets-using-ai-driven-technology/
CATEGORIES:EDA,Webinar
ATTACH;FMTTYPE=image/jpeg:https://marketingeda.com/wp-content/uploads/Synopsys-July-19-2023.jpg
END:VEVENT
BEGIN:VEVENT
DTSTART;TZID=America/Los_Angeles:20230718T110000
DTEND;TZID=America/Los_Angeles:20230718T120000
DTSTAMP:20230713T190809Z
CREATED:20230713T190809Z
LAST-MODIFIED:20230713T190809Z
UID:6589-1689678000-1689681600@marketingeda.com
SUMMARY:Automated Verification for Cache Coherent RISC-V SoCs
DESCRIPTION:RISC-V SoC design complexity continues to increase and create new verification challenges. Private caches\, shared caches\, and shared main memory create potential caches/memory coherency problems that require modern\, automated verification approaches. \nIn this webinar\, we’ll demonstrate how Perspec System Verifier\, with the pre-defined System Traffic Library (STL)\, provides an out-of-the-box verification plan and test suite for heterogeneous\, multi-core\, and cache-coherent processors. STL has built-in atomic actions and coherency scenarios to allow verification engineers to quickly generate test scenarios\, such as targeting false sharing\, true sharing\, cache state transitions\, snoop traffic\, coherency irritators\, extreme stress scenarios\, IO coherency\, and many more areas. Perspec System Verifier also helps visualize scenarios and analyze coverage before test execution.
URL:https://marketingeda.com/event/automated-verification-for-cache-coherent-risc-v-socs/
CATEGORIES:EDA,Webinar
ATTACH;FMTTYPE=image/jpeg:https://marketingeda.com/wp-content/uploads/Cadence-July-18-2023.jpg
END:VEVENT
BEGIN:VEVENT
DTSTART;TZID=America/Los_Angeles:20230718T100000
DTEND;TZID=America/Los_Angeles:20230718T110000
DTSTAMP:20230713T200623Z
CREATED:20230713T200623Z
LAST-MODIFIED:20230713T200623Z
UID:6592-1689674400-1689678000@marketingeda.com
SUMMARY:Key MAC Considerations for the Road to 1.6T Ethernet Success
DESCRIPTION:224G SerDes designs are a reality and the path to 1.6T is clearer than ever. This webinar delves into the considerations\, challenges and solutions designers need to know for the MAC required for these 224G Ethernet PHY IP designs. Dive deep into the nuances of PHY/MAC layer interactions\, timing considerations\, and forward error correction.  We will shed light on key challenges for bandwidth hungry applications including latency optimization\, and SI techniques. Discover how Synopsys MAC IP solutions can help ensure your product is first to market. \n\nSpeakers\n\n\nListed below are the industry leaders scheduled to speak. \n\n\n\n\nJohn Swanson\n\n\nHPC Controller & Datapath Product Line Manager\nSynopsys \n\n\n\n\n\n\n\n\n\n\n\nJohn Swanson is the HPC Controller & Datapath Product Line Manager in Synopsys’ Solutions Group. John has worked in the development and deployment of verification\, integration\, and implementation tools\, IP\, standards\, and methodologies used in IP based design for over 25 years. His assignments have encompassed engineering\, methodology\, business development\, and marketing. John has also been involved in various standards activities including Chair of the Verification Technical Working Group in the SPIRIT Consortium; Synopsys representative on the Power.org technical subcommittee and is active in many IEEE and consortium groups today. \nPrior to joining Synopsys\, he worked for Amoco Oil working on wellhead automation and control systems. He is an Honor graduate from DeVry Institute of Technology where he completed his Engineering degree with Presidents List Honors. \n\n\n\n\nJon Ames\n\n\nSr. Staff Product Marketing Manager\nSynopsys \n\n\n\n\n\n\n\n\n\n\n\nJon Ames is a Sr. Staff Product Marketing Manager for the Synopsys Ethernet Controller IP portfolio.  Jon has been working in the communications industry since 1988 and has led engineering and market activities from the early days of 10/100 Switched Ethernet through Metro and Transport variants to the latest Data Center and High-Performance Computing Ethernet technologies.  Since graduating in Computer Science and Electronic Engineering the in UK\, Jon has worked at the leading companies in the networking and silicon solution industries.
URL:https://marketingeda.com/event/key-mac-considerations-for-the-road-to-1-6t-ethernet-success/
CATEGORIES:IP,Webinar
ATTACH;FMTTYPE=image/jpeg:https://marketingeda.com/wp-content/uploads/Synopsys-July-18-2023.jpg
END:VEVENT
BEGIN:VEVENT
DTSTART;TZID=America/Los_Angeles:20230713T100000
DTEND;TZID=America/Los_Angeles:20230713T110000
DTSTAMP:20230620T160839Z
CREATED:20230620T160839Z
LAST-MODIFIED:20230620T160839Z
UID:6529-1689242400-1689246000@marketingeda.com
SUMMARY:Comprehensive Static Verification for FPGA and ASIC RTL Designers
DESCRIPTION:As designs get increasingly complex\, design teams are looking to find bugs earlier\, to reduce rework and shorten time-to-market. The ultimate “shift left” is to put easy-to-use static verification in the hands of RTL designers to eliminate bugs at their source. \nThis webinar covers comprehensive static verification capabilities in the Cadence® Jasper™ Superlint and CDC apps for lint\, design-for-test (DFT)\, clock domain crossing (CDC)\, and reset domain crossing (RDC). \n\nWhat You Will Learn \n\nAll the static checks that should be performed to hand off better-quality RTL\nHow Jasper apps provide easy-to-use debug capabilities\, leveraging Jasper’s industry-leading formal verification technology to reduce noise and automate violation handling and waivers\nAutomatic formal checks\, which do not require any formal verification experience\, add significant value beyond the structural-only checks that most designers are used to\n\n\nFPGA designs have grown immensely in complexity and are just as prone to CDC bug escapes as ASIC designs\, so we encourage all RTL designers to attend.
URL:https://marketingeda.com/event/comprehensive-static-verification-for-fpga-and-asic-rtl-designers/
CATEGORIES:EDA,Webinar
ATTACH;FMTTYPE=image/jpeg:https://marketingeda.com/wp-content/uploads/Cadence-July-13-2023.jpg
END:VEVENT
BEGIN:VEVENT
DTSTART;TZID=America/Los_Angeles:20230712T120000
DTEND;TZID=America/Los_Angeles:20230712T130000
DTSTAMP:20230621T180336Z
CREATED:20230621T180336Z
LAST-MODIFIED:20230621T180336Z
UID:6550-1689163200-1689166800@marketingeda.com
SUMMARY:An AI/ML Driven High-Level Synthesis Solution
DESCRIPTION:High-Level Synthesis (HLS) tools yield better PPA when the “right set” of optimization constraints and tool settings are applied. Determining the right set of constraints and settings requires design and tool experience and exploration. AI/ML technology has proven highly effective at exploring the solution space and lowering the required tool expertise. This CadenceTECHTALK™ presents details on the integration of Stratus HLS with the Cadence Cerebrus™ Intelligent Chip Explorer. Join us and learn how the Cadence Cerebrus/Stratus integration efficiently explores the solution space and lowers the learning curve for producing expert-quality HLS results.
URL:https://marketingeda.com/event/an-ai-ml-driven-high-level-synthesis-solution/
CATEGORIES:EDA,Webinar
ATTACH;FMTTYPE=image/jpeg:https://marketingeda.com/wp-content/uploads/Cadence-July-12-2023.jpg
END:VEVENT
BEGIN:VEVENT
DTSTART;TZID=Europe/London:20230711T120000
DTEND;TZID=Europe/London:20230711T130000
DTSTAMP:20230608T155840Z
CREATED:20230608T155840Z
LAST-MODIFIED:20230608T155840Z
UID:6467-1689076800-1689080400@marketingeda.com
SUMMARY:Embedded UVM (eUVM)
DESCRIPTION:This is to inform you that the next DVClub Europe meeting takes place on Tuesday 11th July with a theme of “Embedded UVM(eUVM)”.\n\nIntroduction to Embedded UVM to enable HPC-Powered UVM Testbenches with MultiCore Performance.\n\nAgenda (BST) \n12:00   Welcome and Introduction – Mike Bartley\, Senior Vice President – VLSI Design\, Tessolve \n12:00   Puneet Goel\, Coverify Systems Technology LLP – HPC-Powered UVM Testbenching \n13:00   TBD \nRegister now to become a part of this event. Free to attend online. \nEventbrite – DVClub Europe 
URL:https://marketingeda.com/event/embedded-uvm-euvm/
CATEGORIES:EDA,Webinar
ATTACH;FMTTYPE=image/jpeg:https://marketingeda.com/wp-content/uploads/DVClub-Europe-2023.jpg
END:VEVENT
BEGIN:VEVENT
DTSTART;TZID=America/Los_Angeles:20230629T140000
DTEND;TZID=America/Los_Angeles:20230629T153000
DTSTAMP:20230602T184706Z
CREATED:20230602T184706Z
LAST-MODIFIED:20230602T184706Z
UID:6447-1688047200-1688052600@marketingeda.com
SUMMARY:UCIe PHY Modeling and Simulation with XMODEL
DESCRIPTION:Chiplets are emerging as a new way of building IC systems via heterogeneous integration\, and Universal Chip Interconnect Express (UCIe) is one of the standards defining the interconnects among chiplets. This webinar presents the SystemVerilog models of a Universal Chiplet Interconnect Express (UCIe) interface\, including both the analog circuits in the electrical layer and digital FSMs in the logical layer. The whole physical layer (PHY) model can be efficiently simulated in SystemVerilog\, using Scientific Analog’s XMODEL. \nThis webinar is organized in two parts. The first part gives a brief overview of the UCIe standard and explains why XMODEL is the best way to model and verify UCIe PHY\, especially considering the close interactions between its electrical layer and logical layer. It will show how to model various analog circuits in the electrical layer\, including the phase-locked loop (PLL)\, delay-locked loop (DLL)\, duty-cycle corrector\, phase interpolator\, and transmitter/receiver circuits. Each circuit block is modeled using XMODEL primitives\, which enable fast and accurate simulation of their analog behaviors in SystemVerilog. \nThe second part shows how you can design the finite-state machines (FSMs) in the logical layer\, performing digital training and calibrations on the reference voltage levels\, clock-to-data timing\, lane-to-lane skews\, and link data rate via a series of data transmission tests with pseudo-random bit sequences. All the FSMs are described in SystemVerilog\, and with XMODEL\, you can simulate this logical layer model interacting with the electrical layer model entirely in SystemVerilog. It implies that you can also use various features of SystemVerilog to check the thoroughness of your simulation\, such as checking the FSM state coverage. \nThis webinar will be beneficial to everyone who is interested in the design and verification of UCIe PHY. For analog circuit designers\, the presented models will help understand the requirements posed on each circuit block\, such as the scaling of bandwidth to support a wide range of data rates from 4GT/s to 32GT/s. For digital verification engineers\, the presented testbenches will show how to perform SystemVerilog-based verification on the systems containing analog circuits. And most importantly\, by running the simulations with the provided models\, you can gain a hands-on understanding on how the various components of a UCIe PHY work to realize a high-bandwidth interconnect between chiplets.
URL:https://marketingeda.com/event/ucie-phy-modeling-and-simulation-with-xmodel/
CATEGORIES:EDA,Webinar
ATTACH;FMTTYPE=image/jpeg:https://marketingeda.com/wp-content/uploads/Scientific-Analog-June-29-2023.jpg
END:VEVENT
BEGIN:VEVENT
DTSTART;TZID=America/Los_Angeles:20230627T110000
DTEND;TZID=America/Los_Angeles:20230627T120000
DTSTAMP:20230616T173450Z
CREATED:20230616T173450Z
LAST-MODIFIED:20230616T173450Z
UID:6502-1687863600-1687867200@marketingeda.com
SUMMARY:Verisium Debug for UPF Low Power Design
DESCRIPTION:Verisium Debug offers comprehensive debugging capabilities. From RTL\, UVM testbench to UPF low-power designs\, users can use the Cadence unified debugging platform for debugging. In this webinar\, users will learn about the available features in Verisium Debug for UPF power-aware designs and using the unique capabilities to visualize and debug UPF low-power designs. \nWhat you will learn \n\nUnderstand features available in Verisium Debug\n​Learn about the low-power debug capabilities available in Verisium Debug\nLearn how to debug UPF low-power designs with Verisium Debug\n\nWho should attend \n\nDesign engineers\nVerification engineers\nCAD engineers
URL:https://marketingeda.com/event/verisium-debug-for-upf-low-power-design/
CATEGORIES:EDA,Webinar
ATTACH;FMTTYPE=image/jpeg:https://marketingeda.com/wp-content/uploads/Cadence-June-27-2023.jpg
END:VEVENT
BEGIN:VEVENT
DTSTART;TZID=America/Los_Angeles:20230623T100000
DTEND;TZID=America/Los_Angeles:20230623T110000
DTSTAMP:20230612T212746Z
CREATED:20230612T212528Z
LAST-MODIFIED:20230612T212746Z
UID:6485-1687514400-1687518000@marketingeda.com
SUMMARY:Dealing with Complexity in Formal through Abstraction and Reduction
DESCRIPTION:In the world of formal verification\, abstractions along with design reductions\, help reduce the state space and make it easier for formal to converge on its proofs. \nIn this webinar Doulos Senior Member Technical Staff\, Doug Smith will explore the process of abstraction\, safe design reductions\, and when to use them. Doug will show practical examples of both (using VC Formal from Synopsys) and discuss formal results obtained by using abstractions and reductions. \nThe content will be useful to anyone who wants to learn to make more effective use of formal. \nAttendance is FREE and live Q&A will be provided throughout the broadcast. \n\n \nDoug Smith – Doulos Senior Member Technical Staff will present this training webinar\, which will consist of a one-hour presentation with interactive Q&A available to attendees throughout. \n\nAttendance is free of charge \nIf you have any queries\, please contact webinars@doulos.com
URL:https://marketingeda.com/event/dealing-with-complexity-in-formal-through-abstraction-and-reduction/
CATEGORIES:EDA,Webinar
ATTACH;FMTTYPE=image/jpeg:https://marketingeda.com/wp-content/uploads/Doulos-June-23-2023.jpg
ORGANIZER;CN="Doulos":MAILTO:webinars@duolos.com
END:VEVENT
BEGIN:VEVENT
DTSTART;TZID=America/Los_Angeles:20230622T110000
DTEND;TZID=America/Los_Angeles:20230622T120000
DTSTAMP:20230620T182517Z
CREATED:20230620T182517Z
LAST-MODIFIED:20230620T182517Z
UID:6546-1687431600-1687435200@marketingeda.com
SUMMARY:How AI and Semiconductors Will Drive Innovation and Productivity
DESCRIPTION:Semiconductors are critical to the functioning of the modern world driving economic competitiveness\, national security\, and technologies ranging from modern defense capabilities to autonomous vehicles. Artificial Intelligence and the hardware used in this platform are impacting how the world will use information to increase productivity. The semiconductors used in these platforms are instrumental to its functionality and are the backbone behind advancements in these technologies. \nPlease join a panel of industry experts for a conversation on how semiconductors are enabling the revolution in AI and what it means for the U.S. economy. Panelists include Jerry Chen\, Director of Global Business Development for Manufacturing & Industrial at NVIDIA; Ramine Roane Corporate Vice President of AI at AMD; and Stelios Diamantidis\, head of Synopsys’ Artificial Intelligence Strategy in the Office of the President. The session will be moderated by Robert Casanova\, Director of Industry Statistics and Economy Policy at SIA.
URL:https://marketingeda.com/event/how-ai-and-semiconductors-will-drive-innovation-and-productivity/
CATEGORIES:EDA,IP,Webinar
ATTACH;FMTTYPE=image/jpeg:https://marketingeda.com/wp-content/uploads/SIA-June-22-2023.jpg
END:VEVENT
BEGIN:VEVENT
DTSTART;TZID=America/Los_Angeles:20230622T080000
DTEND;TZID=America/Los_Angeles:20230622T090000
DTSTAMP:20230612T175957Z
CREATED:20230612T175957Z
LAST-MODIFIED:20230612T175957Z
UID:6475-1687420800-1687424400@marketingeda.com
SUMMARY:Design and Analysis of Multi-Die & 3D-IC Systems
DESCRIPTION:The architecture and heterogeneous integration capability of 3D-IC (three-dimensional integrated circuits) offer many benefits. The latest configuration methods\, CoWoS (Chip On Wafer on Substrate) and WoW (Wafer on Wafer) from TSMC\, provide advantages by significantly reducing the interconnect length and signal power loss. These new technologies have introduced the need for innovative ways to solve novel physics challenges. Solving the complex issues related to the structural\, thermal\, power\, and signal integrity of the entire 2.5D/3D-IC system cannot be accomplished using only traditional tools. Advanced simulation methods and highly accurate solvers are required to accurately predict the entire multiphysics coupling in 3D-IC systems including interposers and heterogeneous components. \nIn this webinar\, Jerome discusses the latest developments in 3D-IC design\, challenges\, and how simulation is the key to successful 3D-IC design. He also presents a comprehensive environment to simulate these physics and achieve the Structural\, Thermal\, Power\, and Signal integrity of the entire 3D-IC system. Chiplet designers\, Interposer designers\, 3D-IC designers\, and 3D-IC architects will find this webinar helpful. \nPresenter: \nJerome Toublanc has over 20 years of Semiconductor industry experience\, working for various EDA companies such as Avanti\, Synopsys\, and Apache. He has contributed to the successes of worldwide customers in roles ranging from Application Engineer to Product Management and has covered the chip development flow from RTL to GDSII. He is now a business development executive for Ansys. His mission is to identify emerging Multiphysics Integrity challenges within the semiconductor industry and develop product solutions for the complete Chip-Package-PCB ecosystem. \n*This webinar is in partnership with SemiWiki and Ansys*
URL:https://marketingeda.com/event/design-and-analysis-of-multi-die-3d-ic-systems/
CATEGORIES:EDA,Webinar
ATTACH;FMTTYPE=image/webp:https://marketingeda.com/wp-content/uploads/Ansys-June-22-2023.webp
END:VEVENT
BEGIN:VEVENT
DTSTART;TZID=America/Los_Angeles:20230621T100000
DTEND;TZID=America/Los_Angeles:20230621T110000
DTSTAMP:20230612T212024Z
CREATED:20230612T211941Z
LAST-MODIFIED:20230612T212024Z
UID:6481-1687341600-1687345200@marketingeda.com
SUMMARY:Achieve Out-of-the-Box Equivalence Checking with Synopsys Formality ML-driven Distributed Processing
DESCRIPTION:When designers synthesize chip designs with aggressive PPA targets\, the expectation and goal is to be able to complete verification with minimal effort and a fast turn-around-time. Synopsys Design Compiler and Fusion Compiler offer a broad spectrum of optimization techniques such as retiming\, multibit banking and advanced data-path optimizations\, though these techniques can end up being inconsequential if they cannot be verified through equivalence checking. Therefore\, the ideal setup is completed quickly using equivalence checking to provide out-of-the-box results so lengthy iterations and engineer hours aren’t spent converging on verification pass.\nThis presentation will detail how Synopsys Formality ML-driven Distributed Processing (DPX) delivered out-of-the-box verification for STMicroelectronics Design team without the need to scale back optimizations or sacrifice PPA goals. Attendees will walk away with an understanding of how Synopsys Formality equivalence checking captures the design transformation/optimizations in Formality Guide Files (SVF) for rapid setup of the verification environment to avoid multiple iterative runs. In addition\, ML-driven adaptive distributed verification techniques will be highlighted\, which help to partition the design and run solvers in parallel to further accelerate verification runtime and out-of-the-box results. \nSpeakers\n\n\n\n\nNathalie Méloux\n\n\nPrincipal Engineer\nSTMicroelectronics \n\n\n\n\n\n\n\n\nNathalie Méloux\, Principal Engineer at STMicroelectronics\, has been working in the microcontroller division for over 20 years. She has greatly contributed to the development of the STM32 microcontrollers families since its inception. Nathalie has extensive experience in the areas of digital design methodology and low-power implementation flow. She is in charge of the digital flow\, the support of the design implementation from RTL through Synthesis to P&R including signoff timing analysis\, equivalence checking\, power analysis and optimizations all along the flow. \nNathalie Meloux holds a master’s degree in Microelectronics and Robotics from Polytech Montpellier\, France and a D.E.A. (post-Master’s degree) in Microelectronics from the University of Montpellier (Faculty of Science)\, France. \n\n\n\n\nStephane Maulet\n\n\nApplications Engineer\, Sr Staff\nSynopsys \n\n\n\n\n\n\n\n\nStephane Maulet is a Senior Staff Applications Engineer at Synopsys. He has almost 20 years of experience in Synopsys front-end tools spanning Synopsys Design Compiler\, Synopsys Fusion Compiler\, Synopsys Formality and Synopsys Formality ECO. \nStephane holds a master’s degree in Microelectronics Engineering from Grenoble INP\, France.
URL:https://marketingeda.com/event/out-of-the-box-equivalence-checking-synopsys-formality/
CATEGORIES:EDA,Webinar
ATTACH;FMTTYPE=image/jpeg:https://marketingeda.com/wp-content/uploads/Synopsys-June-21-2023.jpg
END:VEVENT
BEGIN:VEVENT
DTSTART;TZID=America/Los_Angeles:20230621T100000
DTEND;TZID=America/Los_Angeles:20230621T110000
DTSTAMP:20230606T180716Z
CREATED:20230606T180716Z
LAST-MODIFIED:20230606T180716Z
UID:6460-1687341600-1687345200@marketingeda.com
SUMMARY:Applying AI/ML Technology for Rapid Design Optimization
DESCRIPTION:The problem of optimization is a long-standing one in the field of design. For years\, the most conventional approach was the brute-force method of running parametric sweeps on the design space. However\, as systems become more complex and the number of parameters increases\, the computational resource and time cost becomes unsustainable. With the Cadence Optimality Explorer\, users can explore the same design space more efficiently and intelligently. By leveraging artificial intelligence/machine learning technology\, Optimality Explorer removes the need for exhaustive sweeps and dramatically reduces the number of iterations required to converge to the optimized solution.
URL:https://marketingeda.com/event/applying-ai-ml-technology-for-rapid-design-optimization/
CATEGORIES:EDA,Webinar
ATTACH;FMTTYPE=image/jpeg:https://marketingeda.com/wp-content/uploads/Cadence-June-21-2023-1.jpg
END:VEVENT
BEGIN:VEVENT
DTSTART;TZID=America/Los_Angeles:20230620T100000
DTEND;TZID=America/Los_Angeles:20230620T110000
DTSTAMP:20230612T211032Z
CREATED:20230612T211032Z
LAST-MODIFIED:20230612T211032Z
UID:6478-1687255200-1687258800@marketingeda.com
SUMMARY:Leveraging Silicon Lifecycle Management (SLM) for Automotive Applications
DESCRIPTION:Automobiles are today’s supercomputers and with that statement comes great challenges. A vehicle is a highly demanding environment for electronics. Temperature and humidity extremes\, noise and vibration\, electrical interference\, exposure to alpha particles\, and other factors all make it hard to design and manufacture chips that will operate correctly under all conditions. In addition\, the growing importance of Transportation as a Service (TaaS) is pushing availability requirements to 24/7/365. As specified by the ISO 26262 safety standard\, chips must be able to detect defects and take corrective action on their own. \nFor all these reasons\, developing chips for automotive applications is challenging. Proper pre-silicon design\, verification\, and validation are essential\, but further attention to detail is needed during system bring-up\, manufacturing\, production test\, and field operation. \nIn this webinar you will learn how Silicon Lifecycle Management (SLM) has emerged as a leading paradigm to make product development and deployment more deterministic for automotive applications \n  \nSpeakers\n\n\n\n\nSashi Obilisetty\n\n\nGroup Dir\, R&D in the EDA Group\nSynopsys\, Inc. \n\n\n\n\n\n\n\n\nSashi Obilisetty is Group Dir\, R&D in the EDA Group at Synopsys. In her 12+ year tenure at Synopsys\, Sashi has been instrumental in enabling several Synopsys technologies in the design\, verification and post-silicon space. She is one of the key leaders involved in ushering AI usage in Synopsys products. She was the Chief Architect for Silicon Solutions at Google Cloud. Sashi founded 2 startups in the verification domain. Sashi has a Bachelors in Electronics and Communication Engineering from Birla Institute of Technology\, Mesra and a Master’s in Computer Engineering from UMASS\, Amherst. \n\n\n\n\n\nPawini Mahajan\n\n\nStaff Product Manager\nSynopsys\, Inc. \n\n\n\n\n\n\n\n\nPawini Mahajan is a Staff Product Manager within the Hardware Analytics and Test group at Synopsys\, specializing in silicon life cycle management solutions for Automotive. In this role she is responsible for Automotive Go-to-Market activities\, understanding and communicating SLM-based solutions for automotive applications to the broad automotive ecosystem. Before joining Synopsys\, she managed an engineering team at Intel focused on reducing defective parts per million (DPPM) for Intel’s flagship products. In addition\, she has actively participated in several notable fundraisers\, including cancer awareness\, women in technology and academic fund gifting. She holds a master’s degree in electrical engineering from Arizona State University.
URL:https://marketingeda.com/event/leveraging-silicon-lifecycle-management-slm-for-automotive-applications/
CATEGORIES:EDA,Webinar
ATTACH;FMTTYPE=image/jpeg:https://marketingeda.com/wp-content/uploads/Synopsys-June-20-2023.jpg
END:VEVENT
BEGIN:VEVENT
DTSTART;TZID=America/Los_Angeles:20230620T080000
DTEND;TZID=America/Los_Angeles:20230620T090000
DTSTAMP:20230613T175913Z
CREATED:20230613T175913Z
LAST-MODIFIED:20230613T175913Z
UID:6496-1687248000-1687251600@marketingeda.com
SUMMARY:Designing for Six Sigma: Electronics Simulation Powered by Parametric Variation
DESCRIPTION:The webinar focuses on the simulation-driven optimization of electronics\, Integrated Circuits applications to achieve a six-sigma level of quality. Electronics are part of our daily life\, with innovative and connected transportation\, buildings\, and communications. However\, the design of electronic devices is a complex process\, and achieving a six-sigma level of quality is a significant challenge. The six-sigma level of quality requires a method capable of producing products with no more than 3.4 defects per million opportunities. Achieving this level of quality is critical for ensuring reliability\, performance\, and longevity. \nThe webinar will cover the use of Ansys electronic and semiconductor simulation capabilities combined with parametric studies and optimization methodologies to improve the design and manufacturability through two use cases: \n\nAnsys HFSS + Parametric Variation in Ansys optiSLang for Electronics 3D Design & Analysis\nAnsys RaptorX + Parametric Variation in Ansys optiSLang for Integrated Circuits Physical Design & Analysis\n\nWhat You Will Learn\n\nLearn how to evaluate and optimize Integrated-Circuits performance through simulation-driven approach which involves the use of models to predict the behavior of the Integrated Circuits (IC) under various conditions.\nLearn how the Robust Design Optimization process takes the simulation to the next level. It involves identifying critical parameters that affect most the quality of the design\, creating robust parametric models to predict the simulation outputs and using AI/ML algorithms to find optimal values with automated and systematic simulation process.\nThe key benefits are to obtain better robustness against manufacturing tolerances\, eliminate manufacturing uncertainties and avoid costly product recalls due to defects discovered after the product is in the market.\nThe webinar will showcase 2 product integrations for electronics applications that aim to achieve six-sigma level of quality through process integration and design optimization.\nThe audience will gain insights into the key challenges and strategies involved in optimizing IC electronics designs through Robust Design Optimization methodology for high-quality and reliable performance.\n\nWho Should Attend\nDesign & Simulation Engineers/ Managers in Electronics & Semiconductor industries \nSpeaker\nJuliano Mologni\nKelly Damalou\nDavid Schneider
URL:https://marketingeda.com/event/designing-for-six-sigma-electronics-simulation-powered-by-parametric-variation/
CATEGORIES:EDA,Webinar
ATTACH;FMTTYPE=image/jpeg:https://marketingeda.com/wp-content/uploads/Amsys-June-20-2023.jpg
END:VEVENT
BEGIN:VEVENT
DTSTART;TZID=America/New_York:20230614T130000
DTEND;TZID=America/New_York:20230614T140000
DTSTAMP:20230606T003848Z
CREATED:20230606T003848Z
LAST-MODIFIED:20230606T003848Z
UID:6453-1686747600-1686751200@marketingeda.com
SUMMARY:Microelectronics Design Security: Better with Formal Methods
DESCRIPTION:Whether you are developing Systems-on-Chip (SoCs) for mobile and wearables\, automotive\, aerospace\, defense\, data centers\, or entertainment\, securing your proprietary data and customers’ information is critical to your company’s long-term success. Hackers can exploit vulnerabilities in these systems — at the network\, system\, device\, or chip levels. As SoC designs get more complex\, this 30-minute Webinar aims to show chip designers how they can best ensure secure data is handled correctly inside the chip while reducing deployment time. \nThis Webinar will help attendees understand: \n\nThe role of formal methods for security verification\nThe key challenges of formal verification and why addressing them is critical\nHow to ensure information flow tracking verifies data integrity and leakage issues\nHow a next-generation formal verification solution is helping users analyze and debug the root cause of security violations\n\nAn audience Q&A session will follow the technical presentation. \n\n\nSpeakers:\nJin Zhang is a Director of Product Management at Synopsys\, who is responsible for VC Formal. Jin has more than 25 years of experience working in the EDA industry\, driving new products and technologies to the market in the formal verification space. She worked at Cadence\, Real Intent\, EVE\, and Oski Technology prior to joining Synopsys. Jin holds a Ph.D. in electrical and computer engineering and an MBA in international management.\n\n\n\n\nIan Land serves as Synopsys’s Senior Director of Security\, Government\, and Aerospace Solutions. Ian has more than 20 years of semiconductor experience and has spent more than 15 years in disciplines that require security. Before joining Synopsys\, he worked for Intel\, Altera\, and Xilinx. Ian holds a bachelor’s degree in mechanical engineering from UCLA and a master’s degree in mechanical engineering and management from MIT.
URL:https://marketingeda.com/event/microelectronics-design-security-better-with-formal-methods/
CATEGORIES:EDA,Webinar
ATTACH;FMTTYPE=image/jpeg:https://marketingeda.com/wp-content/uploads/SynopsysSAE-June-14-2023.jpg
END:VEVENT
BEGIN:VEVENT
DTSTART;TZID=Europe/Paris:20230614T100000
DTEND;TZID=Europe/Paris:20230614T110000
DTSTAMP:20230606T003107Z
CREATED:20230606T003107Z
LAST-MODIFIED:20230606T003107Z
UID:6450-1686736800-1686740400@marketingeda.com
SUMMARY:Verify Your SoC Design Efficiently from Planning to Coverage Closure using Synopsys Verification Family
DESCRIPTION:Verifying an SoC is an extremely complex process that requires agile turnaround\, constant control feedback\, and flexibility to adapt to evolving project needs. Coverage is an efficient metric for the number of potential bugs found and needs to be tracked at each stage of the project. The verification process starts from defining the verification goals\, automating test execution\, collecting and analyzing coverage metrics\, and then tracking and providing guidance until coverage closure is reached. In this webcast\, we will describe how to easily achieve this process using the Synopsys Verification Family of tools including VCS\, Verdi\, and VC Execution Manager. \n\n\n\n\n\n\n\n\n\n\nSpeaker\n\n\nListed below is the industry leader scheduled to speak. \n\n\n\n\n\n\n\n\n\n\n\n\n\n\n\n\n\n\n\n\n\n\n\n\n\n\nXavier Mathes\n\n\nSenior Staff Application Engineer\nSynopsys \n\n\n\n\n\n\n\n\n\n\n\nXavier Mathes is a Senior Staff Application Engineer at Synopsys. He is responsible for multiple verification products including Synopsys VCS\, Verdi\, Verification IP\, VC Execution Manager\, HAPS\, and Synplify. Xavier previously worked at IBM\, Philips Semiconductor\, Synplicity\, and other semiconductor companies. His combined 26 years working in the industry has brought a wealth of knowledge and experience in the areas of semiconductor design and verification. Xavier has a Masters of Science in Electrical Engineer from CentraleSupelec.
URL:https://marketingeda.com/event/verify-your-soc-design-efficiently-from-planning-to-coverage-closure-using-synopsys-verification-family/
CATEGORIES:EDA,Webinar
ATTACH;FMTTYPE=image/jpeg:https://marketingeda.com/wp-content/uploads/Synopsys-June-14-2023.jpg
END:VEVENT
BEGIN:VEVENT
DTSTART;TZID=America/Los_Angeles:20230613T080000
DTEND;TZID=America/Los_Angeles:20230613T090000
DTSTAMP:20230524T191605Z
CREATED:20230524T191605Z
LAST-MODIFIED:20230524T191605Z
UID:6434-1686643200-1686646800@marketingeda.com
SUMMARY:Driving Forward with UWB Radar: Enhancing Child Safety in Automotive
DESCRIPTION:Fueled by the recent adoption by leading smartphone brands\, the UWB wireless technology is enjoying an explosive growth in market interest and applications. In automotive\, UWB is already the de-facto choice for Digital Keys in the premium segment. The deployment of UWB anchor points in modern car creates a cost-effective platform for offering advanced in-cabin radar\, enabling features such as Child Presence Detection (CPD). \nIn this webinar\, you will learn about: \n• UWB technology and ecosystem (UWB alliance\, CCC\, FiRa)\n• How does UWB Radar work\n• CEVA’s UWB and Radar solutions\n\n\nTarget Audience\nSystem engineers\, SoC designers\, and product managers targeting UWB devices\, that are looking to add radar capabilities to products for automotive\, industrial\, consumer\, and others\n\n\nSpeakers\n\n\n\n\n\n\n\nNavot Goren\nUWB Product Director\, CEVA Inc.
URL:https://marketingeda.com/event/driving-forward-with-uwb-radar-enhancing-child-safety-in-automotive/
CATEGORIES:IP,Webinar
ATTACH;FMTTYPE=image/jpeg:https://marketingeda.com/wp-content/uploads/CEVA-June-13-2023.jpg
END:VEVENT
BEGIN:VEVENT
DTSTART;TZID=America/Los_Angeles:20230613T080000
DTEND;TZID=America/Los_Angeles:20230613T090000
DTSTAMP:20230326T033357Z
CREATED:20230326T033357Z
LAST-MODIFIED:20230326T033357Z
UID:6206-1686643200-1686646800@marketingeda.com
SUMMARY:Run Ansys HFSS in the Cloud with AWS to Boost Simulation
DESCRIPTION:About This Webinar\nEngineers worldwide use Ansys HFSS software to design high-frequency\, high-speed electronics found in communications systems\, advanced driver assistance systems (ADAS)\, satellites\, and internet-of-things (IoT) products. Ansys HFSS is a 3D electromagnetic (EM) simulation software for designing and simulating high-frequency electronic products such as antennas\, antenna arrays\, RF or microwave components\, high-speed interconnects\, filters\, connectors\, IC packages\, and printed circuit boards. These different use cases often require large complex models to solve on a traditional workstation\, and leveraging an HPC cluster is often tedious\, time-consuming\, and expensive. Ansys recently partnered with AWS (Amazon Web Services) to develop a new product that optimizes using  Ansys applications on the cloud. \nAnsys Gateway powered by AWS is the solution for developers\, designers\, and engineers who want to manage their complete Ansys Simulation & CAD/CAE developments in the cloud. Access cloud computing resources from anywhere on virtually any device via your web browser. You can create\, customize\, and connect cloud applications with minimal technical skills.  Install your 3rd party applications alongside Ansys applications. \nWhat You Will Learn\n\nWhy the cloud can solve your challenges\nDiscover use cases where the cloud can help\nLearn the benefits you can leverage from using the cloud from AWS\nWatch a quick demo of Ansys HFSS running directly in-browser on Ansys Gateway powered by AWS\n\nSpeaker\nJJ Jones
URL:https://marketingeda.com/event/run-ansys-hfss-in-the-cloud-with-aws-to-boost-simulation/
CATEGORIES:EDA,Webinar
ATTACH;FMTTYPE=image/jpeg:https://marketingeda.com/wp-content/uploads/Ansys-June-13-2023.jpg
END:VEVENT
BEGIN:VEVENT
DTSTART;TZID=America/Los_Angeles:20230607T110000
DTEND;TZID=America/Los_Angeles:20230607T120000
DTSTAMP:20230523T172645Z
CREATED:20230523T172645Z
LAST-MODIFIED:20230523T172645Z
UID:6430-1686135600-1686139200@marketingeda.com
SUMMARY:Xcelium: The Key to Unlocking Unmatched Mixed-Signal Performance
DESCRIPTION:Xcelium mixed-signal simulation enables teams to achieve digital simulation speeds of analog models and opens mixed-signal designs to advanced verification techniques typically applied within standard verification flows.  Built on a SystemVerilog Real Number Modeling (RNM) foundation\, Xcelium automates the signal integration of digital and RNM code to achieve digital simulation speeds for mixed-signal designs. This capability is further enhanced using the EEnet package\, which defines a specialized net type useful for passing voltage values across the design. Cadence adds randomization\, coverage\, incremental elaboration\, advanced debugging\, and other techniques to bring advanced verification to mixed-signal system designs. You can attend our webinar to learn more about how you can accelerate your mixed-signal simulations with RNM and EEnet in Xcelium. \n\nLearn about accelerating mixed-signal simulations with RNM and EEnet in Xcelium\nLearn about utilizing a full verification flow of randomization\, coverage\, incremental elaboration\, and advanced debug with mixed-signal designs\nLearn about achieving digital simulation speeds of analog models
URL:https://marketingeda.com/event/xcelium-the-key-to-unlocking-unmatched-mixed-signal-performance/
CATEGORIES:EDA,Webinar
ATTACH;FMTTYPE=image/jpeg:https://marketingeda.com/wp-content/uploads/Cadence-June-7-2023.jpg
END:VEVENT
BEGIN:VEVENT
DTSTART;TZID=America/New_York:20230601T120000
DTEND;TZID=America/New_York:20230601T130000
DTSTAMP:20230522T170521Z
CREATED:20230522T170521Z
LAST-MODIFIED:20230522T170521Z
UID:6419-1685620800-1685624400@marketingeda.com
SUMMARY:Accelerate Software Innovation Through Target-Optimized Code Generation and Virtual Prototypes
DESCRIPTION:Increasingly complex automotive systems are driving the need for new and powerful E/E architectures\, and new technology is emerging that offers a significant computational increase compared to previous generation SoCs. To deliver next-generation\, differentiated software solutions\, model-based design (MBD) workflows must be deployed to handle this new level of complexity. Code generation solutions that optimize microcontroller performance to meet the development and deployment challenges of e-mobility\, advanced control\, and signal processing are a key part of this workflow. This 30-minute Webinar will explore this workflow in which virtual prototypes can substitute the physical target for much of that traditional MBD workflow. \nThis Webinar will include: \n\n  \n\n\nAn overview of the benefits of using advanced virtual prototypes in the MBD workflow\, such as faster turn-around time\, better debug capabilities\, and maximized deployment to developers\n\n\nHighlights of the features and capabilities of support packages for specialized microcontrollers\n\n\n\nLive demonstrations for a hands-on understanding of how fully virtual workflow with virtual prototypes is applied \n\n\n\n\nA Q&A session will follow the technical presentation. \nSpeakers:\n\nKevin Brand\, Principal Engineer\, Synopsys\nKevin Brand\, a Principal R&D Engineer for Synopsys\, has worked in the virtual prototyping field for 18 years. With a strong focus on automotive\, he has concentrated on R&D in recent years\, directly enabling and deploying virtual prototyping solutions at semiconductor\, Tier 1\, and OEM companies. He holds a master’s degree in electronic engineering from Napier University\, Edinburgh\, and previously worked in the aerospace and defense domain. \n  \nDineshkumar Selvaraj\, Lead Principal Engineer\, Infineon Technologies \nDinesh Selvaraj leads virtual prototype development for the AURIX family of microcontrollers at Infineon Technologies. He has more than 18 years of ESL domain experience with a focus on development of virtual prototypes for classical pre-silicon software validation\, RTL co-simulation\, and early performance analysis and optimization using models. Prior to joining Infineon\, Dinesh worked for Intel and Tata Elxsi. He holds an electrical engineering degree from the National Institute of Technology\, Trichy. \nKelly Zhang\, Application Engineer\, MathWorks \nAs an Application Engineer at MathWorks\, Kelly Zhang focuses on model-based design workflows\, Simulink use\, control system design\, code generation\, and verification and validation tools. She holds a bachelor’s and master’s degree in aerospace engineering from the University of Toronto as well as a master’s degree in mechanical engineering with a focus on control and robotic systems from Carnegie Mellon University.
URL:https://marketingeda.com/event/accelerate-software-innovation-through-target-optimized-code-generation-and-virtual-prototypes/
CATEGORIES:EDA,Webinar
ATTACH;FMTTYPE=image/jpeg:https://marketingeda.com/wp-content/uploads/Synopsys-June-1-2023.jpg
END:VEVENT
BEGIN:VEVENT
DTSTART;TZID=America/Los_Angeles:20230601T110000
DTEND;TZID=America/Los_Angeles:20230601T120000
DTSTAMP:20230421T164256Z
CREATED:20230421T164256Z
LAST-MODIFIED:20230421T164256Z
UID:6308-1685617200-1685620800@marketingeda.com
SUMMARY:Advanced Testbench for a Simple DUT
DESCRIPTION:Abstract: \nFunctional simulation using an HDL testbench is the de facto method for proving functional correctness of FPGA designs. In this three-part webinar series\, we will present a step-by-step approach on how to architect a testbench – progressing from basic to advanced techniques. We will first use a simple DUT then go to a more complex DUT with simultaneous activities on multiple interfaces. \nIn part 2 of this webinar series\, we will show you how to verify a relatively simple DUT with high quality requirements using an advanced testbench without using any verification framework. We will also discuss the elements of an advanced testbench infrastructure to verify our simple DUT more efficiently\, check and prove that we have indeed verified our simple DUT more thoroughly\, start to use advanced Bus Functional Models (BFMs) that allow simpler and more advanced interface control\, and introduce functional coverage. \nHaving shown you these more advanced testbench techniques\, we will continue to show how UVVM can be used to implement them in the simplest ways possible and with a focus on readability\, maintainability\, and extensibility. \nAgenda:\nWhat is required when verifying for higher quality?\nThe elements of an advanced testbench infrastructure\nAdvanced BFMs\nBFM vs Protocol Checkers\nBFM limitations\nAdvanced randomization\nSpecification Coverage\, aka Requirements Coverage\nIntroducing functional coverage\nUVVM advanced BFMs\nUVVM for high quality verification\nQ&A \nWebinar Duration\n45 min presentation/live demo\n15 min Q&A \nPresenter Bio: \nSimon Southwell has 35 years in Research and Development\, with experience in ASIC design\, FPGA\, and embedded software development. \nEspen Tallaksen\, CEO of EmLogic \nEspen is also the author and architect of UVVM and founder of previous Bitvis. \nHe has a strong interest in methodology cultivation and pragmatic efficiency and quality improvement\, and he has given many presentations at various international conferences with great feedback. He has also given courses on FPGA Design and Verification in three different continents.
URL:https://marketingeda.com/event/advanced-testbench-for-a-simple-dut/
CATEGORIES:EDA,IP,Webinar
ATTACH;FMTTYPE=image/jpeg:https://marketingeda.com/wp-content/uploads/Aldec-June-1-2023.jpg
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BEGIN:VEVENT
DTSTART;TZID=America/Los_Angeles:20230525T090000
DTEND;TZID=America/Los_Angeles:20230525T100000
DTSTAMP:20230522T165126Z
CREATED:20230516T000921Z
LAST-MODIFIED:20230522T165126Z
UID:6400-1685005200-1685008800@marketingeda.com
SUMMARY:Don’t Take the Risk\, Formally Verify Your RISC-V Cores
DESCRIPTION:Synopsys Webinar | Thursday\, May 25\, 2023 | 9:00 a.m. PT \n\n\n\n\n\n\n\n\n\n\n\n\n\nAccording to a recent Semico Research report\, the RISC-V Core IP market is expected to grow at a 34.9% CAGR through year 2027. With increasing popularity\, it is of utmost importance that the RISC-V Core IPs are secure and bug free. ​ \nIn this joint Synopsys webinar with SyoSil\, will discuss how to use formal verification to ensure functional correctness and security of RISC-V Cores. We will cover the high-level formal verification goals and example tasks so attendees can obtain a comprehensive view of the many facets of RISC-V Core verification using formal technologies. We will explore a specific case study that uses the so-called ‘S2QED’ methodology to verify a scalar five-stage RISC-V Core. We will also show a demo for this case study using Synopsys VC Formal. ​ \nThe attendees will walk away with a comprehensive understanding of the formal verification requirements for RISC-V Cores to ensure functionality and security\, as well as specific examples of using formal property verification to find intra- and inter-instruction design bugs. ​ \n\n\n\n\n\n\n\n\n\n\nSpeakers\n\n\nListed below are the industry leaders scheduled to speak. \n\n\n\n\n\n\n\n\n\n\n\n\n\n\n\n\n\n\n\n\n\n\n\n\n\n\nSiddartha Papineni\n\n\nSr Staff Application Engineer\nSynopsys \n\n\n\n\n\n\n\n\n\n\n\nSid Papineni is a Sr. Staff Applications Engineer at Synopsys and works on formal verification consulting services and Synopsys VC Formal SEQ\, DPV\, and product engineering activities. Sid has 11+ years of experience in the formal verification domain\, focused mainly on formal property verification and datapath validation methodologies. \n\n\n\n\n\n\n\n\n\n\n\n\n\n\n\n\n\n\n\n\n\n\n\n\n\n\n\n\n\n\n\nFrederik Möllerström Lauridsen\n\n\nVerification Engineer\nSyoSil \n\n\n\n\n\n\n\n\n\n\n\nFrederik Möllerström Lauridsen is a verification engineer at SyoSil. His technical competences and interests lie within both formal verification and SV/UVM based constrained random verification. Frederik holds a PhD degree in mathematics and computer science and a MSc degree in logic from the University of Amsterdam\, and a BSc in Mathematics from the University of Copenhagen.
URL:https://marketingeda.com/event/dont-take-the-risk-formally-verify-your-risc-v-cores/
CATEGORIES:EDA,Webinar
ATTACH;FMTTYPE=image/jpeg:https://marketingeda.com/wp-content/uploads/Synopsys-May-25-2023.jpg
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BEGIN:VEVENT
DTSTART;TZID=Asia/Kolkata:20230524T100000
DTEND;TZID=Asia/Kolkata:20230524T104500
DTSTAMP:20230516T025644Z
CREATED:20230515T235833Z
LAST-MODIFIED:20230516T025644Z
UID:6397-1684922400-1684925100@marketingeda.com
SUMMARY:Accelerate Coverage Closure and Debug with Synopsys AI-Driven Verification Solutions
DESCRIPTION:Synopsys Webinar | Wednesday\, May 24\, 2023 | 10:00 – 10:45 a.m. IST \n\n\n\n\n\n\n\n\n\n\n\n\nEngineering resources are getting stretched thinner and thinner as design complexity increases. Automation is a significant driver to help engineers overcome resource constraints and meet critical time-to-market windows. Two of the top three challenges cited by the engineering community in a recent survey are in the areas of coverage closure and system-level debug. How do we efficiently and accurately understand and reach coverage closure and how do we accelerate and maximize the debug process? These challenges can be addressed with the latest Synopsys AI-Driven debug automation and coverage closure technologies. \nIn this webinar\, we’ll discuss Synopsys Verdi Regression Debug Automation (RDA)\, the ground-breaking AI-driven debug technology that includes the necessary predictive analysis to automate the manual and error-prone process of finding the root cause(s) of failures in the design-under-test (DUT) and testbench. \nWe’ll also explore the latest Synopsys simulation technologies – Verification Space Optimization (VSO.ai) and VCS Intelligent Coverage Optimization (ICO). These AI-driven technologies help accelerate and improve coverage\, expose more bugs\, and reduce regression turnaround time. \n\n\n\n\n\n\n\n\n\nSpeaker\n\n\nListed below is the industry leader scheduled to speak. \n\n\n\n\n\n\n\n\n\n\n\n\n\n\n\n\n\n\n\n\n\n\n\n\n\n\nTaruna Reddy\n\n\nProduct Marketing Manager\, Staff \nSynopsys \n\n\n\n\n\n\n\n\n\n\n\n\nTaruna Reddy is a Staff Product Manager in the EDA Group at Synopsys. Taruna has 18 years of experience in EDA and functional verification. Prior to joining Synopsys\, Taruna held field applications and verification engineering positions at Mentor Graphics\, Verilab and Xtreme-EDA. She holds a MSEE from Clemson University and Bachelor of Technology from India.
URL:https://marketingeda.com/event/accelerate-coverage-closure-and-debug-with-synopsys-ai-driven-verification-solutions/
CATEGORIES:EDA,Webinar
ATTACH;FMTTYPE=image/jpeg:https://marketingeda.com/wp-content/uploads/Synopsys-May-24-2023-2.jpg
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BEGIN:VEVENT
DTSTART;TZID=America/Los_Angeles:20230524T090000
DTEND;TZID=America/Los_Angeles:20230525T120000
DTSTAMP:20230515T234754Z
CREATED:20230515T234719Z
LAST-MODIFIED:20230515T234754Z
UID:6394-1684918800-1685016000@marketingeda.com
SUMMARY:Requirements for Multi-Die System Success
DESCRIPTION:Wednesday\, May 24\, 2023 and Thursday\, May 25\, 2023  \n\n\n\n\n\n\n\n\n\n\nThe industry is moving to multi-die systems to benefit from the greater compute performance\, increased functionality\, and new levels of flexibility. Challenges for multi-die systems are exacerbated and require greater focus on a number of requirements such as early partitioning and thermal planning\, die/package co-design\, secure and robust die-to-die connectivity\, reliability and health\, as well as verification and system validation. Attend this webinar series to find out about some of the essential requirements that can help you overcome multi-die system challenges and make your move to multi-die systems successful. \n\n\nMay 24th presentation topics will include: \n\n9:00 a.m. PDT: Multi-Die System Trends\, Challenges and Requirements\n10:00 a.m. PDT: Benefits of Early Architecture Design for Multi-Die Systems\n11:00 a.m. PDT: Innovations in Multi-Die System Co-Design and System Analysis\n\nMay 25th presentation topics will include: \n\n9:00 a.m. PDT: Successful Connectivity of Heterogeneous Dies with UCIe IP\n10:00 a.m. PDT: Identifying and Overcoming Multi-Die System Verification Challenges\n11:00 a.m. PDT: Optimizing Multi-Die System Health from Die to Package to In-Field\n\n  \nRegister once for access to all the webinars.
URL:https://marketingeda.com/event/requirements-for-multi-die-system-success/
CATEGORIES:EDA,IP,Webinar
ATTACH;FMTTYPE=image/jpeg:https://marketingeda.com/wp-content/uploads/Synopsys-May-24-25-2023.jpg
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