BEGIN:VCALENDAR VERSION:2.0 PRODID:-//Marketing EDA - ECPv6.15.20//NONSGML v1.0//EN CALSCALE:GREGORIAN METHOD:PUBLISH X-ORIGINAL-URL:https://marketingeda.com X-WR-CALDESC:Events for Marketing EDA REFRESH-INTERVAL;VALUE=DURATION:PT1H X-Robots-Tag:noindex X-PUBLISHED-TTL:PT1H BEGIN:VTIMEZONE TZID:Europe/London BEGIN:DAYLIGHT TZOFFSETFROM:+0000 TZOFFSETTO:+0100 TZNAME:BST DTSTART:20230326T010000 END:DAYLIGHT BEGIN:STANDARD TZOFFSETFROM:+0100 TZOFFSETTO:+0000 TZNAME:GMT DTSTART:20231029T010000 END:STANDARD BEGIN:DAYLIGHT TZOFFSETFROM:+0000 TZOFFSETTO:+0100 TZNAME:BST DTSTART:20240331T010000 END:DAYLIGHT BEGIN:STANDARD TZOFFSETFROM:+0100 TZOFFSETTO:+0000 TZNAME:GMT DTSTART:20241027T010000 END:STANDARD BEGIN:DAYLIGHT TZOFFSETFROM:+0000 TZOFFSETTO:+0100 TZNAME:BST DTSTART:20250330T010000 END:DAYLIGHT BEGIN:STANDARD TZOFFSETFROM:+0100 TZOFFSETTO:+0000 TZNAME:GMT DTSTART:20251026T010000 END:STANDARD END:VTIMEZONE BEGIN:VTIMEZONE TZID:America/Los_Angeles BEGIN:DAYLIGHT TZOFFSETFROM:-0800 TZOFFSETTO:-0700 TZNAME:PDT DTSTART:20230312T100000 END:DAYLIGHT BEGIN:STANDARD TZOFFSETFROM:-0700 TZOFFSETTO:-0800 TZNAME:PST DTSTART:20231105T090000 END:STANDARD BEGIN:DAYLIGHT TZOFFSETFROM:-0800 TZOFFSETTO:-0700 TZNAME:PDT DTSTART:20240310T100000 END:DAYLIGHT BEGIN:STANDARD TZOFFSETFROM:-0700 TZOFFSETTO:-0800 TZNAME:PST DTSTART:20241103T090000 END:STANDARD BEGIN:DAYLIGHT TZOFFSETFROM:-0800 TZOFFSETTO:-0700 TZNAME:PDT DTSTART:20250309T100000 END:DAYLIGHT BEGIN:STANDARD TZOFFSETFROM:-0700 TZOFFSETTO:-0800 TZNAME:PST DTSTART:20251102T090000 END:STANDARD END:VTIMEZONE BEGIN:VTIMEZONE TZID:America/New_York BEGIN:DAYLIGHT TZOFFSETFROM:-0500 TZOFFSETTO:-0400 TZNAME:EDT DTSTART:20230312T070000 END:DAYLIGHT BEGIN:STANDARD TZOFFSETFROM:-0400 TZOFFSETTO:-0500 TZNAME:EST DTSTART:20231105T060000 END:STANDARD BEGIN:DAYLIGHT TZOFFSETFROM:-0500 TZOFFSETTO:-0400 TZNAME:EDT DTSTART:20240310T070000 END:DAYLIGHT BEGIN:STANDARD TZOFFSETFROM:-0400 TZOFFSETTO:-0500 TZNAME:EST DTSTART:20241103T060000 END:STANDARD BEGIN:DAYLIGHT TZOFFSETFROM:-0500 TZOFFSETTO:-0400 TZNAME:EDT DTSTART:20250309T070000 END:DAYLIGHT BEGIN:STANDARD TZOFFSETFROM:-0400 TZOFFSETTO:-0500 TZNAME:EST DTSTART:20251102T060000 END:STANDARD END:VTIMEZONE BEGIN:VEVENT DTSTART;TZID=Europe/London:20241127T150000 DTEND;TZID=Europe/London:20241127T153000 DTSTAMP:20260418T054334 CREATED:20241105T181903Z LAST-MODIFIED:20241105T181903Z UID:8475-1732719600-1732721400@marketingeda.com SUMMARY:Webinar 3: Tessolve AI assisted advanced DV Flow and Use cases DESCRIPTION:Webinar 3: Tessolve AI assisted advanced DV Flow and Use cases \nWith the increasing importance of AI in engineering and the exciting potential for it’s use in Design Verification\, Tessolve has been working on improving internal DV processes\, with impressive reductions in both effort and costs\, and with many clients to improve both efficiency and quality in DV through AI. In this series of 3 short webinars\, Tessolve will outline the work done to demonstrate the potential for improving both productivity and quality\, and how you could get involved in this (zero cost) collaboration to capture similar benefits. \nAgenda (GMT) \n15:00 Welcome and Introduction – Mike Bartley\, Tessolve \n15:00 Marmik Soni & Mike Bartley\, Tessolve Semiconductor \n15:20 Close \nAdditional Information on Tessolve AI assisted advanced DV Flow and Use cases\n\nAI Training Bots\nAI Assistance\, CoPilot\nAI Code CoPilot\nRAG\nRAG Assessment\nAI Agents\n\nTessolve reserves the right to cancel registration at its discretion. \nShare this:\n Share on LinkedIn (Opens in new window)\n LinkedIn\n \n Share on X (Opens in new window)\n X\n \n Share on Facebook (Opens in new window)\n Facebook\n Like this:Like Loading... URL:https://marketingeda.com/event/webinar-3-tessolve-ai-assisted-advanced-dv-flow-and-use-cases/ CATEGORIES:EDA,Webinar ATTACH;FMTTYPE=image/jpeg:https://marketingeda.com/wp-content/uploads/Tessolve-November-27-2024.jpg END:VEVENT BEGIN:VEVENT DTSTART;TZID=Europe/London:20241121T093000 DTEND;TZID=Europe/London:20241121T140000 DTSTAMP:20260418T054334 CREATED:20241113T173601Z LAST-MODIFIED:20241113T173601Z UID:8506-1732181400-1732197600@marketingeda.com SUMMARY:FPGA Front Runner: FPGA Safety and Security DESCRIPTION:This event covers the challenges in ensuring an FPGA is secure and demonstrably safe as per the relevant industry safety standards. This includes supply chains\, FPGA hardware and the IP used on the FPGA\n \nAgenda (GMT) \n\n\n\nTime\nSpeaker\nDetails\n\n\n09.30\nArrival and registration\n\n\n10.00\nTobias Adryan\, Synopsys\nSecuring FPGAs Beyond the Bitstream\n\n\n10.30\nEspen Tallaksen\, EmLogic\nFPGA Requirements Tracking and the Requirements Traceability Matrix\n\n\n11.00\nAndrew Swirski\, Beetlebox\nSecuring FPGA Development Pipelines with DevSecOps\n\n\n11.30\nRefreshment break\n\n\n12.00\nIan Pearson\, Microchip Technology Inc.\nEU Cyber Resilience Act – Impacts on Business and Product Design\n\n\n12.30\nFlemming Christensen\, Sundance Multiprocessor Technology Ltd\nHow to secure supply of ‘COTS’ FPGA Modules\n\n\n13.00\nPeter Davies\, Thales\n\n\n\n13.30\nLunch and networking\n\n\n14.00\nEnd\n\n\n\n\n\n\n\n FPGA Front Runner event Partner: TechWorks & Tessolve \nNOTE \nPlease be aware that if you register for both the in-person and virtual events\, your physical ticket will be cancelled\, preventing access on the event day. \nWe also maintain a blacklist; individuals who register for the in-person event but fail to attend will be restricted from participating in future events. If you book a physical ticket but cannot attend then please cancel it in advance. \nShare this:\n Share on LinkedIn (Opens in new window)\n LinkedIn\n \n Share on X (Opens in new window)\n X\n \n Share on Facebook (Opens in new window)\n Facebook\n Like this:Like Loading... URL:https://marketingeda.com/event/fpga-front-runner-fpga-safety-and-security/ LOCATION:The Cass Centre\, Shaftesbury Road\, Cambridge\, CB2 8BS\, United Kingdom CATEGORIES:EDA,Webinar ATTACH;FMTTYPE=image/jpeg:https://marketingeda.com/wp-content/uploads/Tessolve-21-November-2024.jpg END:VEVENT BEGIN:VEVENT DTSTART;TZID=America/Los_Angeles:20241121T080000 DTEND;TZID=America/Los_Angeles:20241121T090000 DTSTAMP:20260418T054334 CREATED:20241107T182710Z LAST-MODIFIED:20241107T182710Z UID:8486-1732176000-1732179600@marketingeda.com SUMMARY:Accelerating Electric Vehicle Development: Integrated design flow for power modules with functional safety and reliability focus DESCRIPTION:This webinar to delve into the integrated design flow for power modules for electric vehicles (EVs) for enhanced functional safety and reliability. The power modules are distinguished by their high voltage and current requirements\, substantial power dissipation\, and the resulting temperature rise. Ensuring their safety and reliability is paramount. We will explore how Cadence’s cutting-edge solutions – Allegro X\, PSpice\, Clarity 3D Solver\, and Celsius Thermal Solver—designed to support a thermally aware design process\, come together in an end-to-end integrated design solution \nShare this:\n Share on LinkedIn (Opens in new window)\n LinkedIn\n \n Share on X (Opens in new window)\n X\n \n Share on Facebook (Opens in new window)\n Facebook\n Like this:Like Loading... URL:https://marketingeda.com/event/accelerating-electric-vehicle-development-integrated-design-flow-for-power-modules-with-functional-safety-and-reliability-focus/ CATEGORIES:EDA,Webinar ATTACH;FMTTYPE=image/jpeg:https://marketingeda.com/wp-content/uploads/Cadence-November-21-2024.jpg END:VEVENT BEGIN:VEVENT DTSTART;TZID=America/Los_Angeles:20241121T080000 DTEND;TZID=America/Los_Angeles:20241121T090000 DTSTAMP:20260418T054334 CREATED:20241031T164508Z LAST-MODIFIED:20241031T164508Z UID:8466-1732176000-1732179600@marketingeda.com SUMMARY:Boost your verification productivity with Questa Verification IQ DESCRIPTION:This session will explore Questa Verification IQ (VIQ)\, Siemens EDA’s next-generation collaborative and data-driven verification solution. VIQ revolutionizes the verification process by providing advanced analytics\, enhanced collaboration\, and comprehensive traceability. By leveraging machine learning\, VIQ significantly enhances verification efficiency to boost your productivity. \nWhat you will learn: \n\n‌How to implement a collaborative\, plan-driven verification process\, complemented by a requirement-driven process for complete traceability from requirements to implementation and verification results\nSetting up a collaborative regression environment with live visibility and control to drive debug and optimize verification flows\nEnabling team-based collaborative analysis to accelerate coverage closure by applying analytics\nConfiguring dashboards with visualizations and insights into what happened and why\, utilizing trending data\, gauges\, and cross-analytics\n‌\n\nWho should attend: \nVerification Engineers & Managers \n\n\nProducts Covered:   \n\nQuesta Verification IQ:\n\nTestplan Author\nRegression Navigator\nCoverage Analyzer\nVerification Insight\n\n\n\n\n\nSpeaker:\n\n\n\n\n\n\nMark Carey\nProduct Engineer\, Siemens EDA\n\n\n\n\nMark Carey is a Product Engineer in the Digital Verification Technologies division at Siemens EDA. With over two decades of experience in EDA\, he started his career as a software developer before moving into technical marketing and product management roles across design\, virtual prototyping\, requirement traceability\, and now works as part of the verification management team. \n\n\n\nShare this:\n Share on LinkedIn (Opens in new window)\n LinkedIn\n \n Share on X (Opens in new window)\n X\n \n Share on Facebook (Opens in new window)\n Facebook\n Like this:Like Loading... URL:https://marketingeda.com/event/boost-your-verification-productivity-with-questa-verification-iq/ CATEGORIES:EDA,Webinar ATTACH;FMTTYPE=image/jpeg:https://marketingeda.com/wp-content/uploads/Siemens-November-21-2024.jpg END:VEVENT BEGIN:VEVENT DTSTART;TZID=Europe/London:20241120T150000 DTEND;TZID=Europe/London:20241120T153000 DTSTAMP:20260418T054334 CREATED:20241105T181405Z LAST-MODIFIED:20241105T181405Z UID:8472-1732114800-1732116600@marketingeda.com SUMMARY:Webinar 2: Tessolve AI assisted DV Flow DESCRIPTION:With the increasing importance of AI in engineering and the exciting potential for it’s use in Design Verification\, Tessolve has been working on improving internal DV processes\, with impressive reductions in both effort and costs\, and with many clients to improve both efficiency and quality in DV through AI. In this series of 3 short webinars\, Tessolve will outline the work done to demonstrate the potential for improving both productivity and quality\, and how you could get involved in this (zero cost) collaboration to capture similar benefits. \nAgenda (GMT) \n15:00 Welcome and Introduction – Mike Bartley\, Tessolve \n15:00 Marmik Soni & Mike Bartley\, Tessolve Semiconductor \n15:20 Close \nAdditional Information Tessolve AI assisted DV Flow\n  \n\nSpec Analysis\nRegister Extraction\nTest Flow\nAssertion Generation\nCoverpoints\nTestcases\nScripts for UVM etc.\n\nTessolve reserves the right to cancel registration at its discretion. \nShare this:\n Share on LinkedIn (Opens in new window)\n LinkedIn\n \n Share on X (Opens in new window)\n X\n \n Share on Facebook (Opens in new window)\n Facebook\n Like this:Like Loading... URL:https://marketingeda.com/event/webinar-2-tessolve-ai-assisted-dv-flow/ CATEGORIES:EDA,Webinar ATTACH;FMTTYPE=image/jpeg:https://marketingeda.com/wp-content/uploads/Tessolve-November-20-2024.jpg END:VEVENT BEGIN:VEVENT DTSTART;TZID=America/Los_Angeles:20241120T070000 DTEND;TZID=America/Los_Angeles:20241120T090000 DTSTAMP:20260418T054334 CREATED:20241025T162958Z LAST-MODIFIED:20241025T162958Z UID:8453-1732086000-1732093200@marketingeda.com SUMMARY:Fast Track RTL Debug with the Verisium Debug Python App Store DESCRIPTION:Working with debugging scripts locally and manually can be challenging\, as can reusing and organizing them. What if there was a way to create your own app with the required functionality and to register it with the tool? \nThe answer lies in the Verisium Debug Python App Store. Instantly add additional features and capabilities to your Verisium Debug Application using Python Apps that interact with Verisium Debug via the Python API. \nJoin us for this Training Webinar and discover the Verisium Debug Python App Store. The app store allows you to search for existing apps\, learn about them\, install\, or uninstall them\, and even customize existing apps. \nDate and Time\nWednesday\, November 20\, 2024\n07:00 PST San Jose / 10:00 EST New York / 15:00 GMT London / 16:00 CET Munich / 17:00 IST Jerusalem / 20:30 IST Bangalore / 23:00 CST Beijing \n  \nTo register for this webinar\, sign in with your Cadence Support account (email ID and password) to log in to the Learning and Support System*. Then select Enroll to register. Once registered\, you’ll receive a confirmation email containing all login details. \nA quick reminder: \n\nIf you haven’t received a registration confirmation within one hour of registering\, please check your spam folder and ensure your pop-up blockers are off and cookies are enabled.\nFor issues with registration or other inquiries\, reach out to eur_training_webinars@cadence.com\n\nShare this:\n Share on LinkedIn (Opens in new window)\n LinkedIn\n \n Share on X (Opens in new window)\n X\n \n Share on Facebook (Opens in new window)\n Facebook\n Like this:Like Loading... URL:https://marketingeda.com/event/fast-track-rtl-debug-with-the-verisium-debug-python-app-store/ CATEGORIES:EDA,Webinar ATTACH;FMTTYPE=image/jpeg:https://marketingeda.com/wp-content/uploads/Cadence-November-20-2024.jpg END:VEVENT BEGIN:VEVENT DTSTART;TZID=America/Los_Angeles:20241119T090000 DTEND;TZID=America/Los_Angeles:20241119T100000 DTSTAMP:20260418T054334 CREATED:20241019T030235Z LAST-MODIFIED:20241019T030235Z UID:8436-1732006800-1732010400@marketingeda.com SUMMARY:Ansys-Synopsys Technology Update: The Latest Advances in Multi-Die Design DESCRIPTION:The semiconductor industry is rapidly adopting 2.5D and 3D multi-die designs as the significant benefits have become clear for applications like HPC\, GPU\, mobile\, and AI/ML. Multi-die design technology has been quickly evolving with early experiences leading to the development of more advanced implementation and analysis techniques. \nFor the past years\, Synopsys and Ansys have been creating design flows that carry designers through early exploration\, implementation\, and final signoff. They are deeply engaged with semiconductor designers on advanced multi-die projects and have helped customers bring successful designs to market. \nRegister now to learn about:\n– Multi-die design best practices for thermal\, signal\, and power integrity\n– Insights from practical multi-die design case studies\n– More advanced packaging technologies for thermal management\, backside power\, and co-packaged optics \nSPEAKERS \nMarc Swinnen is Product Marketing Director for semiconductor products at Ansys in San Jose\, CA. Before joining Ansys\, Marc was Director of Product Marketing at Cadence Design Systems and has worked in Marketing and Technical Support positions at Synopsys\, Azuro\, and Sequence Design\, where he gained experience with a wide array of digital and analog design tools. \nKeith Lanier is a Product Management Director at Synopsys focusing on multi-die and 3D heterogeneous integration (3DHI) solutions involving the latest advanced packaging technology. He brings over 30 years of experience in custom design\, analog/mixed signal (AMS) and RF/mmWave product experience\, including 8 years designing high speed data converters and amplifiers at Analog Devices. \nShare this:\n Share on LinkedIn (Opens in new window)\n LinkedIn\n \n Share on X (Opens in new window)\n X\n \n Share on Facebook (Opens in new window)\n Facebook\n Like this:Like Loading... URL:https://marketingeda.com/event/ansys-synopsys-technology-update-the-latest-advances-in-multi-die-design/ CATEGORIES:EDA,IP,Webinar ATTACH;FMTTYPE=image/jpeg:https://marketingeda.com/wp-content/uploads/Ansys-Synopsys-November-19-2024.jpg END:VEVENT BEGIN:VEVENT DTSTART;TZID=America/Los_Angeles:20241114T100000 DTEND;TZID=America/Los_Angeles:20241114T110000 DTSTAMP:20260418T054334 CREATED:20241030T170948Z LAST-MODIFIED:20241030T170948Z UID:8460-1731578400-1731582000@marketingeda.com SUMMARY:Optimize Systems and Semiconductor Architecture for Deep Learning Algorithms Using System-Level Modeling DESCRIPTION:In a world where artificial intelligence and machine learning are embedded in critical applications—from real-time tracking and object detection to autonomous systems—the architecture behind these innovations must be both powerful and efficient. To help engineers and architects address these challenges\, our upcoming webinar will demonstrate how System-Level Modeling can be a game-changer in optimizing the performance and power efficiency of deep learning algorithms\, including Deep and Convolutional Neural Networks (DNNs and CNNs). \nThrough system-level modeling\, design teams can analyze and optimize critical factors such as response time\, power consumption\, component selection\, and cost-effectiveness before finalizing their designs. This session is particularly beneficial for SoC architects\, embedded systems designers\, and other professionals working to balance performance\, power\, and cost for AI deployments in demanding environments. \nWhat You’ll Learn \nWith AI systems like CNNs now integral to technologies in real-time tracking\, object detection\, and autonomous navigation\, the need for architecture trade-offs has intensified. Our approach to system-level modeling allows teams to: \n\nEvaluate Hardware Combinations: Assess combinations of CPUs\, GPUs\, AI-specific processing units\, and standalone FPGAs to select the best configuration for your needs.\nOptimize Task Partitioning: Partition tasks across chips to achieve targeted performance without compromising power efficiency or exceeding budget constraints.\nRealistic Workload Simulation: Use cycle-accurate models to depict AI/ML algorithm performance under real-world conditions\, creating accurate simulations of hardware components in action.\n\nThrough detailed case studies across industries like automotive\, avionics\, data centers\, and radar systems\, you’ll see how this methodology applies to diverse scenarios\, helping to trade off key performance indicators (e.g.\, vehicle mileage vs. processing power). \n\n\n\n\nKey Takeaways\n\n\n\n\n\nTrade-Off Latency\, Power\, and Cost Using Early Simulation\n\nBy modeling early\, teams can visualize trade-offs and make informed decisions on processor and component selection to hit project goals effectively.\n\n\nIntegrate Shift-Left and Shift-Right Strategies in System-Level Modeling\n\nBring software testing and design validation forward to avoid issues in later stages\, enhancing the quality of final designs.\n\n\nMap Applications to Diverse Processing Units\n\nLearn to deploy applications seamlessly across CPUs\, GPUs\, TPUs\, and AI engines to maximize AI’s impact while optimizing for cost and power.\n\n\nFoster Collaboration Between OEMs\, Tier 1 Suppliers\, and Semiconductor Manufacturers\n\nUse our methodology to facilitate better communication and integration across all stakeholders involved in the AI hardware design process.\n\n\n\nWhether you’re involved in automotive\, avionics\, or advanced SoC architectures\, this session offers an invaluable opportunity to master the nuances of system-level modeling for AI architecture and streamline your deep learning deployment. \nDon’t Miss Out on Transforming Your AI Deployment Strategy!\nJoin us for this exclusive session and gain the insights you need to optimize your systems and semiconductor architecture for cutting-edge deep learning applications. \n\n\n\n\nDate: November 14th\, 2024\nSession 1: 11:30 AM India / 3:00 PM Japan or Korea / 2:00 PM China \nSign up: https://bit.ly/4eZqnjP \nSession 2: 10:00 AM USA PDT / 1:00 PM USA EDT \nRegister: https://bit.ly/3YFM82o \n\n\nShare this:\n Share on LinkedIn (Opens in new window)\n LinkedIn\n \n Share on X (Opens in new window)\n X\n \n Share on Facebook (Opens in new window)\n Facebook\n Like this:Like Loading... URL:https://marketingeda.com/event/optimize-systems-and-semiconductor-architecture-for-deep-learning-algorithms-using-system-level-modeling/ CATEGORIES:EDA,Webinar ATTACH;FMTTYPE=image/jpeg:https://marketingeda.com/wp-content/uploads/Mirabilis-November-14-2024.jpg END:VEVENT BEGIN:VEVENT DTSTART;TZID=America/Los_Angeles:20241114T100000 DTEND;TZID=America/Los_Angeles:20241114T110000 DTSTAMP:20260418T054334 CREATED:20241025T163841Z LAST-MODIFIED:20241025T163841Z UID:8456-1731578400-1731582000@marketingeda.com SUMMARY:AI-Driven Constraint Generation for PCB and IC Package Design DESCRIPTION:Join our webinar to discover how AI-driven optimization and automation in constraint generation can boost productivity and shorten design cycles for PCB and IC package design. Learn how integrating Allegro X and Sigrity X can streamline your workflow. \nKey Takeaways:\n \n\nLearn how the Sigrity Topology Workbench\, a robust system-level SI/PI environment for what-if and pre-route analysis\, is linked to the Allegro X PCB and IC package implementation tools.\nExperience the power of AI optimization in simulating parameterized structures to quickly reach target objectives\, and see how the physical attributes that meet these target objectives are automatically fed into the implementation tool as constraints.\nEnvision the efficiency of reusing or updating AI-generated constraints in future designs to consistently reduce design cycle time\n\nShare this:\n Share on LinkedIn (Opens in new window)\n LinkedIn\n \n Share on X (Opens in new window)\n X\n \n Share on Facebook (Opens in new window)\n Facebook\n Like this:Like Loading... URL:https://marketingeda.com/event/ai-driven-constraint-generation-for-pcb-and-ic-package-design/ CATEGORIES:EDA,Webinar ATTACH;FMTTYPE=image/jpeg:https://marketingeda.com/wp-content/uploads/Cadence-November-14-2024.jpg END:VEVENT BEGIN:VEVENT DTSTART;TZID=Europe/London:20241113T150000 DTEND;TZID=Europe/London:20241113T153000 DTSTAMP:20260418T054334 CREATED:20241105T180842Z LAST-MODIFIED:20241105T180842Z UID:8469-1731510000-1731511800@marketingeda.com SUMMARY:Tessolve AI Strategy & Eco System for DV DESCRIPTION:With the increasing importance of AI in engineering and the exciting potential for it’s use in Design Verification\, Tessolve has been working on improving internal DV processes\, with impressive reductions in both effort and costs\, and with many clients to improve both efficiency and quality in DV through AI. In this series of 3 short webinars\, Tessolve will outline the work done to demonstrate the potential for improving both productivity and quality\, and how you could get involved in this (zero cost) collaboration to capture similar benefits. \nAgenda (GMT) \n15:00 Welcome and Introduction – Mike Bartley\, Tessolve \n15:00 Marmik Soni & Mike Bartley\, Tessolve Semiconductor \n15:20 Close \nAdditional Information on Tessolve AI Strategy & Eco System for DV\n\nAI Strategies at Tessolve\nAI Tool range for DV-\n\nDV RAG Tool\,\nAssertify\,\nUnit TB Generation\,\nUVM AI\,\nISO26262 AI etc.\n\n\n\n  \nTessolve reserves the right to cancel registration at its discretion. \nShare this:\n Share on LinkedIn (Opens in new window)\n LinkedIn\n \n Share on X (Opens in new window)\n X\n \n Share on Facebook (Opens in new window)\n Facebook\n Like this:Like Loading... URL:https://marketingeda.com/event/tessolve-ai-strategy-eco-system-for-dv/ CATEGORIES:EDA,Webinar ATTACH;FMTTYPE=image/jpeg:https://marketingeda.com/wp-content/uploads/Tesolve-November-13-2024.jpg END:VEVENT BEGIN:VEVENT DTSTART;TZID=America/New_York:20241113T090000 DTEND;TZID=America/New_York:20241113T100000 DTSTAMP:20260418T054334 CREATED:20241016T181319Z LAST-MODIFIED:20241016T181319Z UID:8422-1731488400-1731492000@marketingeda.com SUMMARY:ASIP University Day 2024: Domain-Specific Processor Design using ASIP Designer DESCRIPTION:The AI revolution and other application domains\, like data centers\, advanced wireless communications\, image and video processing\, automated driving assistance\, and post-quantum cryptography need more powerful architectures with higher performance. This is driving demand for heterogeneous multicore systems including application specific instruction set processors (ASIPs). \nASIPs have become a mainstream implementation option for modern SoCs\, i.e. when standard processor IP cannot meet challenging application-specific requirements\, and fixed hardware is not flexible enough. This growth has driven many university projects and increased interest in initiatives like RISC-V\, which has significantly expanded beyond UC Berkeley. \n\nWhy Attend? \nYou will hear from leading university teams about their ASIP design project results across various application domains. Additionally\, Synopsys will provide a technical update on ASIP Designer with reference examples. \nThis event offers a great opportunity to exchange ideas\, build networks\, and gain valuable insights from university partners. \nDon’t miss out – register now to secure your spot! \nShare this:\n Share on LinkedIn (Opens in new window)\n LinkedIn\n \n Share on X (Opens in new window)\n X\n \n Share on Facebook (Opens in new window)\n Facebook\n Like this:Like Loading... URL:https://marketingeda.com/event/asip-university-day-2024-domain-specific-processor-design-using-asip-designer/ CATEGORIES:IP,Webinar ATTACH;FMTTYPE=image/jpeg:https://marketingeda.com/wp-content/uploads/Synopsys-November-13-2024.jpg END:VEVENT BEGIN:VEVENT DTSTART;TZID=America/Los_Angeles:20241112T110000 DTEND;TZID=America/Los_Angeles:20241112T120000 DTSTAMP:20260418T054334 CREATED:20241021T181622Z LAST-MODIFIED:20241021T181734Z UID:8440-1731409200-1731412800@marketingeda.com SUMMARY:Rise Together Beyond RTL : Practical Techniques for Improving ASIC Design Efficiency and Early Verification DESCRIPTION:High-level design techniques and automation tools to address the limitations of traditional RTL\, reduce verification times\, improve performance\, and manage growing design complexity—integrating seamlessly.\n\n\nWhat You’ll Learn:\n\n\n\n\nThis Lunch & Learn offers an in-depth look at Rise Design Automation tools and illustrates how high-level design and early verification techniques can bring value to your projects. No prior experience with high-level design is necessary\, but familiarity with hardware design and RTL synthesis is recommended. \nSome key takeaways you can expect: \n** Rise Design Automation Overview – Introduction to the tools\, use cases\, methodologies\, and project value of raising the abstraction beyond RTL with Rise. \n** SystemVerilog – Technical details of how to use SystemVerilog for high-level design – highlighting both “loosely-timed” and “untimed” SystemVerilog. \n** Handling Control and Data Flow – Learn practical approaches to optimizing control and data paths to meet timing and performance requirements without adding unnecessary complexity. \n** Applying Design Space Exploration – Explore design configurations by adjusting loop unrolling\, pipelining\, and scheduling to optimize power\, performance\, and area—while gaining early insights into trade-offs. \n** Improving Early Verification – How to integrate verification earlier in the design process to detect bugs faster and reduce the risk of late-stage rework. \n** Real-World Use Cases – See how high-level design techniques are used to efficiently build a high-performance compute accelerator for applications like machine learning\, DSP\, and video/image processing. \n** Learn how collaboration between system architects\, RTL designers\, and verification engineers speeds up development and delivers more reliable hardware. \n\n\n\n\nWho should attend:\n\n\n\n\n** Design Engineers looking to improve control paths\, data flow\, and performance\, while adopting new methods gradually and with minimal risk. \n** Verification Engineers looking to implement earlier\, more efficient verification processes to minimize risk and accelerate timelines\, without overhauling their current flows. \n** Project Leads managing trade-offs in timelines\, power\, performance\, and area\, while ensuring smooth integration of new techniques into existing processes. \n** System Architects looking to model\, explore\, and validate architectural decisions early\, focusing on performance\, power\, and area trade-offs without late-stage surprises. \n\n\n\n\nSpeakers\n\n\n\nMike Fingeroff\, Chief of High-Level Synthesis (HLS) With over 20 years of experience in hardware design automation\, Mike has specialized in High-Level Synthesis (HLS)\, focusing on machine learning and early performance modeling using SystemVerilog\, SystemC\, and MatchLib. He is the author of The High-Level Synthesis Blue Book\, and his expertise includes C++\, SystemC\, and video and wireless algorithms.\n\n\nAllan Klinck\, Co-Founder Allan is a co-founder of RDA and a technology leader with expertise in high-level design and AI/ML frameworks for verification. He has driven innovation in verification and low-power technologies\, helping teams enhance efficiency and performance in modern\, complex designs.\n\n\nEllie Burns currently serves as the Head of Marketing at Rise Design Automation (RDA). With over 30 years of experience in the semiconductor and EDA industries\, she has held diverse roles in engineering\, applications engineering\, technical marketing\, product management\, and senior leadership\, specializing in driving business growth through strategic marketing.\n\nShare this:\n Share on LinkedIn (Opens in new window)\n LinkedIn\n \n Share on X (Opens in new window)\n X\n \n Share on Facebook (Opens in new window)\n Facebook\n Like this:Like Loading... URL:https://marketingeda.com/event/rise-together-beyond-rtl-practical-techniques-for-improving-asic-design-efficiency-and-early-verification/ CATEGORIES:EDA,Webinar ATTACH;FMTTYPE=image/jpeg:https://marketingeda.com/wp-content/uploads/Rise-DA-November-12-2024.jpg END:VEVENT BEGIN:VEVENT DTSTART;TZID=America/Los_Angeles:20241107T070000 DTEND;TZID=America/Los_Angeles:20241107T080000 DTSTAMP:20260418T054334 CREATED:20241023T171101Z LAST-MODIFIED:20241023T171101Z UID:8449-1730962800-1730966400@marketingeda.com SUMMARY:Navigating COTS-IP in DO-254: Strategies for Safe and Efficient FPGA Design DESCRIPTION:The integration of COTS-IP (Commercial Off-The-Shelf Intellectual Property) components in FPGA-based Avionics systems can significantly speed up development and enhance performance. However\, it also introduces unique challenges\, as these components may not align with the strict aviation development assurance standards required for DO-254 compliance. This webinar will guide you through the process of balancing the benefits and risks associated with COTS-IP in Avionics designs. \nIn this joint webinar with friends and partners\, Aldec\, we’ll explore different types of IPs available on the market\, their roles in the design assurance process\, and practical strategies for integrating them safely. You’ll discover key factors for choosing the right vendor and IP\, best practices for verification\, and effective planning and execution techniques to ensure your systems meet safety requirements. \nWhat you’ll learn:\n1. COTS-IP usage:\na. What are COTS-IPs and what are the different IP types\nb. Applicable guidance for COTS-IP\nc. Verification strategies and methods\nd. Methods for achieving coverage\ne. Putting it all together and showing compliance \nSpeakers: \nMartin Beeby\, Head of Advanced Avionics Systems and Managing Director of ConsuNova EU\, ConsuNova With over 35 years of experience in the development of avionics Systems\, Hardware and Software\, Martin has a wealth of certification experience with systems ranging from DAL-A to DAL-D. Martin is an active contributor to many industry standard working groups developing new guidance for Avionics development and is an active CVE on multiple European programs. \nJanusz Kitel\, DO-254 Program Manager\, Aldec Janusz brings over 18 years of experience in software and hardware design and verification\, with more than a decade dedicated to mastering DO-254 compliance. His work ensures that Aldec products meet the strict standards of the aerospace industry\, while also providing customers with valuable support in overcoming tooling challenges in airborne electronic hardware (AEH) projects. \nShare this:\n Share on LinkedIn (Opens in new window)\n LinkedIn\n \n Share on X (Opens in new window)\n X\n \n Share on Facebook (Opens in new window)\n Facebook\n Like this:Like Loading... URL:https://marketingeda.com/event/navigating-cots-ip-in-do-254-strategies-for-safe-and-efficient-fpga-design/ CATEGORIES:EDA,IP,Webinar ATTACH;FMTTYPE=image/jpeg:https://marketingeda.com/wp-content/uploads/Aldec-November-7-2024.jpg END:VEVENT BEGIN:VEVENT DTSTART;TZID=America/Los_Angeles:20241106T100000 DTEND;TZID=America/Los_Angeles:20241106T110000 DTSTAMP:20260418T054334 CREATED:20241018T165537Z LAST-MODIFIED:20241018T165537Z UID:8433-1730887200-1730890800@marketingeda.com SUMMARY:Navigating Trends and Tools in Automotive Design with Cadence DESCRIPTION:Join us for our first webinar in this insightful series\, where we explore the rapidly evolving automotive landscape. We will focus on the rise of autonomous and electric vehicles\, highlighting key trends such as ADAS\, software-defined vehicles\, and zonal architectures. \nLearn how Cadence’s advanced automotive solutions are addressing the increasing compute demands and in-vehicle networking requirements while prioritizing power efficiency and safety. \nEquip yourself with the knowledge to thrive in this dynamic environment. We look forward to traveling this road together! \nWhat will be covered: \n\nEmerging trends in ADAS\, software-defined vehicles\, zonal architectures\, connectivity\, and electrification\nHow high-performance centralized computing\, cloud-native software development\, power management\, safety design support\, and system design and analysis are creating new opportunities for industry players and reshaping automotive design.\n\nWho Should Attend: \n\nThis free event is a terrific opportunity for design/CAD engineers\, CAD managers\, IT managers\, and business leaders seeking to optimize their design flow and technology infrastructure within the automotive industry.\n\nShare this:\n Share on LinkedIn (Opens in new window)\n LinkedIn\n \n Share on X (Opens in new window)\n X\n \n Share on Facebook (Opens in new window)\n Facebook\n Like this:Like Loading... URL:https://marketingeda.com/event/navigating-trends-and-tools-in-automotive-design-with-cadence/ CATEGORIES:EDA,Webinar ATTACH;FMTTYPE=image/jpeg:https://marketingeda.com/wp-content/uploads/Cadence-Nnovember-6-2024.jpg END:VEVENT BEGIN:VEVENT DTSTART;TZID=America/Los_Angeles:20241030T090000 DTEND;TZID=America/Los_Angeles:20241030T100000 DTSTAMP:20260418T054334 CREATED:20241016T180601Z LAST-MODIFIED:20241016T180601Z UID:8419-1730278800-1730282400@marketingeda.com SUMMARY:Verifying the next generation High Bandwidth Memory controllers for AI and HPC applications DESCRIPTION:High Bandwidth Memory (HBM) has revolutionized AI\, machine learning\, and High-Performance Computing by significantly increasing data transfer speeds and alleviating performance bottlenecks. The introduction of next-generation HBM4 is especially transformative\, enabling faster training and execution of complex AI models. JEDEC has announced that the HBM4 specification is nearing finalization. In this webinar\, you will learn how Siemens’s scalable and customizable Avery HBM Verification IP helps companies like Rambus verify their industry-leading HBM4 Controller IP through rigorous testing to ensure reliability and performance. \n\n  \nWhat You Will Learn:  \n\nWhat’s new in HBM4\nChallenges involved in verifying advanced HBM generations\nUnique features in Siemens’s HBM4 memory models\nRambus’s newly-announced HBM4 memory controller IP\n\nWho Should Attend:  \n\nDesign & Verification Engineers\, Architects\nManagers and Directors for memory controllers\n\nWhat/Which Products are Covered:   \n\nSiemens Avery HBM4 Verification IP\nRambus HBM4 Memory Controller\n\nSpeakers:\n\n\n\n\n\n\nKamlesh Mulchandani\nApplication Engineering Consultant\, Siemens EDA\n\n\n\n\nKamlesh Mulchandani is an Application Engineering Consultant at Siemens EDA. In his role as a Verification IP AE\, Kamlesh bridges the gap between Verification IP technology and customer needs through collaboration\, technical support and by tailoring Siemens solutions for specific user applications. Prior to Siemens\, Kamlesh worked at Cadence as a Memory Subsystem Design & Verification Engineer where he worked on verifying LPDDRx/DDRx & GDDRx IPs. \n\n\n\n\n\n\n\nNidish Kamath\nDirector of Product Management for Memory Interface IP\, Rambus\n\n\n\n\nNidish Kamath is the Director of Product Management for Memory Interface IP at Rambus.  He previously held marketing and product management roles at AMD\, Kioxia (formerly Toshiba Memory)\, Avalanche Technologies\, Brocade and Qualcomm\, where he worked on computational storage\, SmartNICs and GPU cluster networking solutions. He has served in various standards and industry associations such as SNIA\, Center for Open Source Software (CROSS)\, CXL Consortium\, UEC and JEDEC. \n\n\n\nShare this:\n Share on LinkedIn (Opens in new window)\n LinkedIn\n \n Share on X (Opens in new window)\n X\n \n Share on Facebook (Opens in new window)\n Facebook\n Like this:Like Loading... URL:https://marketingeda.com/event/verifying-the-next-generation-high-bandwidth-memory-controllers-for-ai-and-hpc-applications/ CATEGORIES:EDA,Webinar ATTACH;FMTTYPE=image/jpeg:https://marketingeda.com/wp-content/uploads/Siemens-October-30-2024.jpg END:VEVENT BEGIN:VEVENT DTSTART;TZID=America/Los_Angeles:20241023T090000 DTEND;TZID=America/Los_Angeles:20241023T100000 DTSTAMP:20260418T054334 CREATED:20241009T193236Z LAST-MODIFIED:20241009T193236Z UID:8402-1729674000-1729677600@marketingeda.com SUMMARY:Hardware Verification using VirtuaLAB DESCRIPTION:VirtuaLAB protocol solutions offer a full-stack testing environment with seamless connectivity and stimulus traffic generation for designs under test. It operates autonomously\, adapting to scenarios without requiring protocol knowledge from the user. VirtuaLAB significantly reduces test and compliance suite regression times\, running at high emulation speeds\, integrated with Protocol Analyzer for complete protocol visibility and performance metrics. Supporting any scenario\, it enables users to focus on their design’s unique value while ensuring reliable standard protocol interactions. \nWho Should Attend: \n\nEngineers and Managers responsible for System Design Verification of complex SoCs\nEngineers and Managers responsible for design performance verification\n\nWhat you will learn: \n\nAttendees will learn how VirtuaLAB protocol solutions provide a full stack from the physical to the application layer to connect to your design under test and create stimulus traffic as a host\, or respond to commands in the form of a compliant device.\nAttendees will learn the ease of bring-up of a VirtuaLAB environment with no testbench required\, but how to use real-world software to create workloads exactly matching the end-user of your silicon.\nAttendees will see a demonstration of VirtuaLAB running a back-to-back UFS4 host model and RTL SSD model DUT\, running the LLAMA 3.1 LLM\, and providing query responses in real-time.\n\nSpeaker:\n\n\n\n\n\n\nBen Whitehead\nDirector of Product Management\, Siemens EDA\n\n\n\n\n\nShare this:\n Share on LinkedIn (Opens in new window)\n LinkedIn\n \n Share on X (Opens in new window)\n X\n \n Share on Facebook (Opens in new window)\n Facebook\n Like this:Like Loading... URL:https://marketingeda.com/event/hardware-verification-using-virtualab/ CATEGORIES:EDA,Webinar ATTACH;FMTTYPE=image/jpeg:https://marketingeda.com/wp-content/uploads/Siemens-October-23-2024.jpg END:VEVENT BEGIN:VEVENT DTSTART;TZID=America/Los_Angeles:20241017T110000 DTEND;TZID=America/Los_Angeles:20241017T120000 DTSTAMP:20260418T054334 CREATED:20241014T214312Z LAST-MODIFIED:20241014T214312Z UID:8416-1729162800-1729166400@marketingeda.com SUMMARY:Static and Dynamic CDC Verification of AXI4 Stream-based IPs DESCRIPTION:The AXI4 Stream protocol is used as a standard interface to exchange data between connected IPs within FPGA designs. For crossing clock domains\, the AXI4 Stream interconnect is based on switches capable of transferring data to another asynchronous clock domain. The alternative solution is a dual-port AXI4 Stream IP\, capable of changing clock domains when packet routing is not required. \nStatic and dynamic clock domain crossing (CDC) verification methods complement each other to ensure flawless operation of multi-clock designs. ALDEC_CDC rules plugin contains 58 rules for checking design quality\, design constraints\, and clock and reset trees. It is also used for validating design synchronization circuits. However\, static CDC verification methods alone may not guarantee the completeness of the CDC verification task. Dynamic CDC verification is crucial. The two main methods for dynamic CDC verification are checking with CDC assertions and modeling of random delay insertion on clock domain crossings.\n\nIn this webinar\, we will introduce both static and dynamic verification methods for CDC verification of AXI4 Stream-based IPs. We will discuss the CDC assertions that are auto-generated from ALINT-PRO\, and we will also demonstrate the design and usage of the synchronizer models with random delay insertion.\n\nAgenda:\n\nCDC verification process overview\n\nStatic CDC verification checks\nAssertions usage in CDC verification\nThe concept of delay randomization at CDC crossing in functional simulation\n\n\nAXI Stream protocol overview\nAXI CDC Port Verification\n\nRunning CDC static checks with ALINT-PRO\nGeneration SV Assertion with ALINT-PRO\nDeveloping the testbench for AXI CDC Port dynamic verification\nSimulating design with generated CDC assertions\nSimulating design with random delay insertion in synchronizer models\n\n\nConclusion\nQ&A\n\n\nWebinar Duration\n\n45 min presentation/live demo\n\nBio: \nAlex Gnusin\, Aldec’s ALINT-PRO Product Manager \nAlex accumulated 27 years of hands-on experience in various aspects of ASIC and FPGA design and verification. As a verification prime for a multi-million gates project in companies such as IBM\, Nortel\, Ericsson and Synopsys Inc\, he combined various verification methods such as static linting\, formal property checking\, dynamic simulation and hardware-assisted acceleration to efficiently achieve design verification goals. He received his M.S. in Electronics from Technion\, Israel Institute of Technology. \nShare this:\n Share on LinkedIn (Opens in new window)\n LinkedIn\n \n Share on X (Opens in new window)\n X\n \n Share on Facebook (Opens in new window)\n Facebook\n Like this:Like Loading... URL:https://marketingeda.com/event/static-and-dynamic-cdc-verification-of-axi4-stream-based-ips/ CATEGORIES:EDA,IP,Webinar ATTACH;FMTTYPE=image/jpeg:https://marketingeda.com/wp-content/uploads/Aldec-October-17-2024.jpg END:VEVENT BEGIN:VEVENT DTSTART;TZID=America/Los_Angeles:20241015T100000 DTEND;TZID=America/Los_Angeles:20241015T110000 DTSTAMP:20260418T054334 CREATED:20241008T164139Z LAST-MODIFIED:20241008T164139Z UID:8399-1728986400-1728990000@marketingeda.com SUMMARY:ARM corelink\, Arteris NoC\, UCIe\, Bunch-of-wires\, CXL and PCIe- Designing the interconnect is not for the weak-hearted DESCRIPTION:There are so many options for Network-on-Chip: ARM-Corelink CMN700\, Arteris FlexNoC\, open-source NoC interconnect\, and of course developing home-grown fully customized solutions. Where does each solution fit? Where do we use it- backplane vs inside domains? How does AMBA AXI or PCIe or CXL fit in the mix? With the advent of chiplet\, do we go with UCIe or bunch-of-wires. Where do we locate the DRAM and the task scheduler? Lots of questions need to be answered before the SoC or chiplets can be implemented. \nIn this Webinar\, we will take the mystery out of these architecture decisions by demonstrating how system modeling can provide quantitative metrics to validate and optimize these requirements. For this purpose we will use the mapping of a CNN- Resnet 50 on an AI processor\, Open Architecture Management (OAM) system\, heterogeneous compute SoC-FPGA and development of a custom NoC. \nTo measure the quality of the design\, we will show the running of standard and synthetic workloads. Quantitative metrics generated will include latency\, throughput\, buffer occupancy\, peak power consumed\, heat generated\, cache hit-miss and memory bandwidth. We will also show how the source of bottlenecks can be identified. The design can be experimented with different routing schemes\, schedulers\, buffer size\, clock speeds\, flits\, clock domains\, flow control credit and quality-of-service. \nShare this:\n Share on LinkedIn (Opens in new window)\n LinkedIn\n \n Share on X (Opens in new window)\n X\n \n Share on Facebook (Opens in new window)\n Facebook\n Like this:Like Loading... URL:https://marketingeda.com/event/arm-corelink-arteris-noc-ucie-bunch-of-wires-cxl-and-pcie-designing-the-interconnect-is-not-for-the-weak-hearted/ CATEGORIES:EDA,IP,Webinar ATTACH;FMTTYPE=image/jpeg:https://marketingeda.com/wp-content/uploads/Mirabilis-October-15-2024.jpg END:VEVENT BEGIN:VEVENT DTSTART;TZID=America/Los_Angeles:20241010T110000 DTEND;TZID=America/Los_Angeles:20241010T120000 DTSTAMP:20260418T054334 CREATED:20241007T181311Z LAST-MODIFIED:20241007T181311Z UID:8383-1728558000-1728561600@marketingeda.com SUMMARY:The Development and Evolution of Verilog & SystemVerilog DESCRIPTION:Abstract: \nSystemVerilog is a super next-generation Verilog with a fancy marketing name. SystemVerilog leveraged many of its features from other languages and methodologies. Class-based capabilities\, constrained random testing (CRT)\, and functional coverage were all features that were added to SystemVerilog and incorporated into the Universal Verification Methodology (UVM). UVM has become the most dominant and powerful verification methodology used to verify designs by engineers today. \nCliff Cummings has been a member of the Verilog & SystemVerilog Standards Groups since 1994 and will offer his unique and historical perspective on how features were added to SystemVerilog\, why the features were added\, and the origins of many of those features.\n\nAgenda:\n\nVerilog HDL and Its Ancestors and Descendants (reference paper)\nBrief History of Verilog & SystemVerilog\nHILO\, Verilog\, C\, PLI\nSDF\, Synthesis\, VHDL\, VPI\nSuperlog\, IHDL (Intel)\, SystemC\, Vera\nOOP\, e-Specman\, SystemVerilog\, C++\nOVL\, PSL\, SVA\nOVM / UVM history\nSimulation & Functional Coverage\nQ&A\n\n\nWebinar Duration\n\n45 min presentation/live demo\n15 min Q&A\n\nBio: \nClifford E. Cummings\, \nVice President of Training at Paradigm Works and Founder of Sunburst Design \nCliff Cummings is Vice President of Training at Paradigm Works and Founder of Sunburst Design. Cliff teaches world-class SystemVerilog\, UVM\, CDC and synthesis training classes. Cliff has 42 years of ASIC\, FPGA and system design experience and 32 years of combined Verilog\, SystemVerilog\, UVM verification\, synthesis\, and methodology training experience.  Cliff has taught expert Verilog\, SystemVerilog\, Design Synthesis\, CDC and UVM Verification to thousands of engineers world-wide and has presented more than 50 papers on these topics.  Cliff holds a BSEE from Brigham Young University and an MSEE from Oregon State University. \nShare this:\n Share on LinkedIn (Opens in new window)\n LinkedIn\n \n Share on X (Opens in new window)\n X\n \n Share on Facebook (Opens in new window)\n Facebook\n Like this:Like Loading... URL:https://marketingeda.com/event/the-development-and-evolution-of-verilog-systemverilog/ CATEGORIES:EDA,Webinar ATTACH;FMTTYPE=image/jpeg:https://marketingeda.com/wp-content/uploads/Aldec-October-10-2024.jpg END:VEVENT BEGIN:VEVENT DTSTART;TZID=Europe/London:20241008T120000 DTEND;TZID=Europe/London:20241008T130000 DTSTAMP:20260418T054334 CREATED:20240911T161307Z LAST-MODIFIED:20240911T161307Z UID:8325-1728388800-1728392400@marketingeda.com SUMMARY:Cocotb 2.0: Modernize your testbenches for even more productivity DESCRIPTION:Cocotb 2.0 is the latest major version of cocotb\, ironing out many quirks that have accumulated over the years. With only small changes to your testbenches\, you can benefit from improved typing and less surprising corner cases. In this talk\, we’ll show what’s new in cocotb 2.0\, and how you can modernize your code bases to make best use of it.  We also have a presentation from a cocotb user performing HDL simulation with python cocotb\, with a Transaction Level Modelling (TLM) approach with a completely free and open source chain (GHDL simulator and WSL Linux). \n\n\n\n\n\n\n\n\n\n\n\n\n\n\n\n\n\n\n\n\n\n\n\n\n\n\n\n\n\n\n\n\n\n\n\n\n\n\n\n\nAgenda (BST):\n\n\n\n\n\n\n\nTime\nSession Description\nSlides\nVideos\n\n\n12.00 BST\nWelcome and Introduction \nMike Bartley\,Tessolve\n\n\n\n\n12.00 BST\nSimple yet powerful: Open-source HDL simulation with Cocotb \nHayder Al-Hakeem ( Wärtsilä Finland)\n\n\n\n\n12.30 BST\nCocotb 2.0: Modernize your testbenches for even more productivity \nPhilipp Wagner ( FOSSi Foundation)\n\n\n\n\n13.00 BST\n  \nClose\n\n\n\n\n\n\n\n\n\n\n\n\n\n\n\n\n\n\n\n\n\n\n\n\n\n\n\n\n\nAbout DVClub\n\n\n\n\nThe principal goal of each DVCLUB meeting is to have fun while helping build the European verification community through regular educational and networking events. Attendance at DVClub Europe meetings is free and is open to all non-service provider semiconductor professionals. Each meeting addresses a specific issue faced by the design and verification community and whatever your speciality provides an excellent opportunity for updating knowledge as well as share experiences\, insights and issues with other members of the verification community. \n\n\n\n\n\n\n\nShare this:\n Share on LinkedIn (Opens in new window)\n LinkedIn\n \n Share on X (Opens in new window)\n X\n \n Share on Facebook (Opens in new window)\n Facebook\n Like this:Like Loading... URL:https://marketingeda.com/event/cocotb-2-0-modernize-your-testbenches-for-even-more-productivity/ CATEGORIES:EDA,Webinar ATTACH;FMTTYPE=image/jpeg:https://marketingeda.com/wp-content/uploads/DVCon-Europe-October-2024.jpg END:VEVENT BEGIN:VEVENT DTSTART;TZID=America/Los_Angeles:20241002T090000 DTEND;TZID=America/Los_Angeles:20241002T100000 DTSTAMP:20260418T054334 CREATED:20240906T215750Z LAST-MODIFIED:20240906T215750Z UID:8307-1727859600-1727863200@marketingeda.com SUMMARY:Redefining Mobile Experiences with AI - Session 2 DESCRIPTION:The Arm platform is providing the foundation for the next wave of AI smartphones and laptops. As AI models rapidly evolve\, we’re seeing that software begins to outpace hardware\, requiring additional innovation at all levels of the compute stack. \nTo meet these growing demands\, the Arm platform offers a new compute solution for maximum performance and efficiency\, on leading process nodes. Join this webinar series to learn more about this solution\, including the latest Arm Armv9 CPUs and GPUs\, the benefits and opportunities of running AI on device\, and how to innovate and speed time to market. \nThe CPU Cluster on Wednesday\, Oct 2\, 2024\n\n9:00 a.m. BST / 4:00 p.m. Beijing\n5:00 p.m. BST / 9:00 a.m. PT\n\nThis webinar covers: \n\nAn overview of Arm’s most performant\, efficient\, and versatile CPU cluster based on the Armv9 architecture for maximum performance and power efficiency.\nFeatures\, benefits\, and performance enhancements of Arm Cortex-X925\, Cortex-A725 CPU\, Cortex-A520 CPU and Arm DSU-120.\nHow this CPU cluster can improve consumer experiences on mobile devices.\n\nSpeaker: Manish Pandey\, Senior Product Manager\, Arm \nFirst Session – September 18th \nShare this:\n Share on LinkedIn (Opens in new window)\n LinkedIn\n \n Share on X (Opens in new window)\n X\n \n Share on Facebook (Opens in new window)\n Facebook\n Like this:Like Loading... URL:https://marketingeda.com/event/redefining-mobile-experiences-with-ai-session-2/ CATEGORIES:IP,Webinar ATTACH;FMTTYPE=image/jpeg:https://marketingeda.com/wp-content/uploads/Arm-September-18-2024.jpg END:VEVENT BEGIN:VEVENT DTSTART;TZID=America/Los_Angeles:20241001T110000 DTEND;TZID=America/Los_Angeles:20241001T113000 DTSTAMP:20260418T054334 CREATED:20240930T220024Z LAST-MODIFIED:20240930T220024Z UID:8361-1727780400-1727782200@marketingeda.com SUMMARY:Interactive SPICE Model Verification Platform ME-Pro DESCRIPTION:ME-Pro™ is a unified tool for designers\, process developers\, modeling engineers\, and PDK engineer providing robust simulation and analysis capabilities for semiconductor device model verification and evaluation. \nThis comprehensive platform supports evaluation across device\, circuit\, and process domains enabling interactive development and offering critical feedback for process improvements. With decades of Primarius’ expertise\, ME-Pro™ features pre-configured templates\, hundreds of verification data entries\, and the built-in NanoSpice parallel simulator that is all designed to streamline setup and reduce learning curves. \nPresenter\nErik Supnet is a Senior Application Engineer at Primarius for two years supporting pre-sales and post-sales activities for modeling and simulation products. He earned his B.S. in Computer Engineering and M.A in Education at the University of the Pacific. Prior to his current role\, he held design engineering positions as D.E.C\, SiByte\, Broadcom\, and Intel\, and has a background in custom circuit design\, automation\, methodologies\, and education. \nShare this:\n Share on LinkedIn (Opens in new window)\n LinkedIn\n \n Share on X (Opens in new window)\n X\n \n Share on Facebook (Opens in new window)\n Facebook\n Like this:Like Loading... URL:https://marketingeda.com/event/interactive-spice-model-verification-platform-me-pro/ CATEGORIES:EDA,Webinar ATTACH;FMTTYPE=image/jpeg:https://marketingeda.com/wp-content/uploads/primarius-October-1-2024.jpg END:VEVENT BEGIN:VEVENT DTSTART;TZID=America/Los_Angeles:20240926T100000 DTEND;TZID=America/Los_Angeles:20240926T110000 DTSTAMP:20260418T054334 CREATED:20240911T233717Z LAST-MODIFIED:20240911T233717Z UID:8333-1727344800-1727348400@marketingeda.com SUMMARY:Learn How to Simulate 2D-TMD-Channel FETs with Atomistic Precision DESCRIPTION:Are 2D-TMD-channel transistors suitable candidates for the replacement of silicon ? Considering the extreme scaling down to a few atomic layers of the FET channel\, only an atomistic solution looks viable. In this context\, we show how the Victory Atomistic tool can answer this essential question thanks to quantum mechanics\, offering valuable support for the prototyping effort of a 2D transistor in a professional TCAD environment. \nWhat You Will Learn\n\nAn understanding of the physics and engineering of 2D TMD NR architectures at the atomic scale\nWhy to use Atomistic TCAD\nHow to simulate and prototype at the atomic level\nExample of a 2D-TMD TFET\n\n\n\n\n\n\nPresenter\n\n\n\n\nDr. Philippe Blaise\, Senior Application Engineer\, Silvaco\, Inc. \nDr. Philippe Blaise has been a senior application engineer in atomistic simulation at Silvaco’s TCAD Division for three years. Prior to joining Silvaco\, Dr. Blaise was a senior engineer specialized in atomistic simulation of new memory devices and transistors at CEA/LETI for 15 years. He is a former member of the IEEE IEDM Modelling and Simulation Committee. He is co-author of more than 50 papers in peer-review journals in the field and 30 contributions to conferences and workshops\, plus 5 patents and one book chapter.\nDr. Blaise holds a Master’s degree in applied mathematics from ENSIMAG engineering school and a Ph.D. in solid states physics from the Université Grenoble Alpes\, France. \n\n\n\n\n\nWHO SHOULD ATTEND:\n\n\n\n\nTCAD engineers\, device engineers\, process engineers\, product managers\, and engineering management. \n\n\nShare this:\n Share on LinkedIn (Opens in new window)\n LinkedIn\n \n Share on X (Opens in new window)\n X\n \n Share on Facebook (Opens in new window)\n Facebook\n Like this:Like Loading... URL:https://marketingeda.com/event/learn-how-to-simulate-2d-tmd-channel-fets-with-atomistic-precision/ CATEGORIES:EDA,Webinar ATTACH;FMTTYPE=image/jpeg:https://marketingeda.com/wp-content/uploads/Silvaco-September-26-2024.jpg END:VEVENT BEGIN:VEVENT DTSTART;TZID=America/New_York:20240918T100000 DTEND;TZID=America/New_York:20240918T110000 DTSTAMP:20260418T054334 CREATED:20240820T165149Z LAST-MODIFIED:20240820T165235Z UID:8255-1726653600-1726657200@marketingeda.com SUMMARY:A Beginner's Guide to RTL-to-GDSII Front-End Flow DESCRIPTION:In this Training Webinar\, explore the concepts of RTL design\, design verification\, and coverage analysis while unveiling the exciting world of front-end design flow. Walk through the essential steps in creating integrated circuits\, the building blocks of modern electronics. \nThis webinar provides practical knowledge\, making it your gateway to understanding the magic behind RTL-to-GDSII front-end design flow. \nWe’ll break down the process into manageable stages\, from defining the chip’s functionality to its physical realization. We’ll investigate the front-end part of the RTL-to-GDSII flow—from specification to functional verification and design coverage—and explore: \n\nKey concepts of specifying chip behavior and performance\nHow to translate ideas into a digital blueprint and transform that into a design\nHow to ensure your design is free of errors\n\nWebinar: A Beginner’s Guide to RTL-to-GDSII Front-End Flow\nDate: Wednesday\, September 18\, 2024\nTime: 07:00 PDT San Jose / 10:00 EDT New York / 15:00 BST London / 16:00 CEST Munich / 17:00 IDT Jerusalem / 19:30 IST Bangalore / 22:00 CST Beijing \nShare this:\n Share on LinkedIn (Opens in new window)\n LinkedIn\n \n Share on X (Opens in new window)\n X\n \n Share on Facebook (Opens in new window)\n Facebook\n Like this:Like Loading... URL:https://marketingeda.com/event/beginners-guide-rtl-gdsii-front-end-flow/ CATEGORIES:EDA,Webinar ATTACH;FMTTYPE=image/jpeg:https://marketingeda.com/wp-content/uploads/Cadence-September-18-2024-1.jpg END:VEVENT BEGIN:VEVENT DTSTART;TZID=America/Los_Angeles:20240918T090000 DTEND;TZID=America/Los_Angeles:20240918T100000 DTSTAMP:20260418T054334 CREATED:20240906T215234Z LAST-MODIFIED:20240906T215837Z UID:8304-1726650000-1726653600@marketingeda.com SUMMARY:Redefining Mobile Experiences with AI DESCRIPTION:The Arm platform is providing the foundation for the next wave of AI smartphones and laptops. As AI models rapidly evolve\, we’re seeing that software begins to outpace hardware\, requiring additional innovation at all levels of the compute stack. \nTo meet these growing demands\, the Arm platform offers a new compute solution for maximum performance and efficiency\, on leading process nodes. Join this webinar series to learn more about this solution\, including the latest Arm Armv9 CPUs and GPUs\, the benefits and opportunities of running AI on device\, and how to innovate and speed time to market. \nSession 1: The Arm Platform on Wednesday\, Sept 18\, 2024\n\n9:00 a.m. BST / 4:00 p.m. Beijing\n5:00 p.m. BST / 9:00 a.m. PT\n\nThis webinar covers: \n\nThe latest Arm technology\, Arm Compute Subsystems (CSS) for Client\, which helps push the boundaries of premium mobile experiences.\nFeatures\, benefits\, and performance enhancements of Armv9 based Arm Cortex CPUs and Immortalis and Mali GPUs.\nHow Arm partners can rapidly innovate and speed time to market.\nPerformance and efficiency enhancements that increase the responsiveness of GenAI.\nHow to unlock 3 nm PPA benefits with physical implementations.\n\nSpeaker: Kinjal Dave\, Senior Director Product Management\, Arm \nSecond Session – October 2nd \nShare this:\n Share on LinkedIn (Opens in new window)\n LinkedIn\n \n Share on X (Opens in new window)\n X\n \n Share on Facebook (Opens in new window)\n Facebook\n Like this:Like Loading... URL:https://marketingeda.com/event/redefining-mobile-experiences-with-ai/ CATEGORIES:IP,Webinar ATTACH;FMTTYPE=image/jpeg:https://marketingeda.com/wp-content/uploads/Arm-September-18-2024.jpg END:VEVENT BEGIN:VEVENT DTSTART;TZID=America/Los_Angeles:20240918T080000 DTEND;TZID=America/Los_Angeles:20240918T090000 DTSTAMP:20260418T054334 CREATED:20240813T192856Z LAST-MODIFIED:20240813T192856Z UID:8231-1726646400-1726650000@marketingeda.com SUMMARY:Managing Constraints Like a Pro in OrCAD X DESCRIPTION:Join us in this constraint-focused webinar to learn all the best practices for managing constraints in your design with OrCAD X Presto PCB Editor. \nWe’ll cover everything from the basics of setting up spacing and physical constraints to advanced electrical constraints\, which are critical for HDI designs. \nThe webinar will feature a brief presentation\, a live demonstration using the NVIDIA Jetson Xavier Developer Kit Carrier Board\, and a Q&A session. \nTopics Covered:\n\nNavigating the constraint manager and reusing constraints\nCreating constraint sets\nSetting up physical and spacing constraints\nSetting up advanced constraints for HDI\nElectrical constraints (Propagation Delay\, Net Scheduling\, Differential Pairs)\nSetting up blind\, buried\, and microvias\nAnalysis setup\nPreview of the new constraints panel in OrCAD X Presto PCB Editor\n\n\nWe welcome PCB designers of all experience levels to join us. Enhance your expertise in managing basic and advanced constraints in your OrCAD X Presto designs! \n\nSPEAKERS: \nAdam Fuchs\, Principal Product Engineer\, Cadence \nHOST: \nSupreeth Mannava\, Senior Principal Product Manager\, Cadence \nShare this:\n Share on LinkedIn (Opens in new window)\n LinkedIn\n \n Share on X (Opens in new window)\n X\n \n Share on Facebook (Opens in new window)\n Facebook\n Like this:Like Loading... URL:https://marketingeda.com/event/managing-constraints-like-a-pro-in-orcad-x/ CATEGORIES:EDA,Webinar ATTACH;FMTTYPE=image/jpeg:https://marketingeda.com/wp-content/uploads/Cadence-September-18-2024.jpg END:VEVENT BEGIN:VEVENT DTSTART;TZID=America/Los_Angeles:20240912T120000 DTEND;TZID=America/Los_Angeles:20240912T130000 DTSTAMP:20260418T054334 CREATED:20240823T181114Z LAST-MODIFIED:20240823T181126Z UID:8265-1726142400-1726146000@marketingeda.com SUMMARY:Unleash Performance\, Save Power: Mastering Processor Customization with the Tensilica Instruction Extension (TIE) Language DESCRIPTION:Join us for an engaging webinar where we show you how to turbocharge performance and minimize power consumption by harnessing the power of custom instructions using the TIE language. Don’t miss this opportunity to optimize your processors like never before! \nTIE enables you to compute and move data many times faster than conventional processors\, resulting in faster yet more power-efficient cores while maintaining full programmability and debugability. \nThis webinar will introduce users to the easy-to-use TIE language and techniques for accelerating computation that can be used to optimize processors for specific target applications. \nLearn how Tensilica TIE language can be implemented to: \n\nSignificantly save SOC Power\nTurbocharge SOC Performance\nMaster processor customization with custom instructions\n\nShare this:\n Share on LinkedIn (Opens in new window)\n LinkedIn\n \n Share on X (Opens in new window)\n X\n \n Share on Facebook (Opens in new window)\n Facebook\n Like this:Like Loading... URL:https://marketingeda.com/event/unleash-performance-save-power-mastering-processor-customization-with-the-tensilica-instruction-extension-tie-language/ CATEGORIES:EDA,IP,Webinar ATTACH;FMTTYPE=image/jpeg:https://marketingeda.com/wp-content/uploads/Cadence-September-12-2024-1.jpg END:VEVENT BEGIN:VEVENT DTSTART;TZID=America/Los_Angeles:20240912T100000 DTEND;TZID=America/Los_Angeles:20240912T110000 DTSTAMP:20260418T054334 CREATED:20240814T174526Z LAST-MODIFIED:20240814T174526Z UID:8237-1726135200-1726138800@marketingeda.com SUMMARY:Leveraging Verisium Debug to Debug Digital-Mixed Signal Designs DESCRIPTION:Many of today’s designs that are primarily digital also contain analog components. We refer to such designs as “Digital-Mixed-Signal” or DMS designs. In this webinar\, we will demonstrate using the Verisium Debug App to debug such DMS designs. \n\n\n\n\n\n\n\n\n\n\n\n\nWhat You Will Learn \n\n\n\n\n\n\n\n\n\n\n\n\n\nHow Verisium Debug supports debugging Xcelium (Real Number Modeling) RNM and mixed Xcelium and Spectre simulations\nHow Verisium Debug can be used to debug User-Defined Nets (UDNs)\nThe analog waveform debug features of Verisium Debug\n\n\n\n\n\n\n\n\n\n\n\n\n\nWho Should Attend \n\n\n\n\n\n\n\n\n\n\n\n\nThis webinar is designed for design and verification engineers of all levels who need to debug Digital-Mixed-Signal designs when simulating using Xcelium Real Number Modeling (RNM) or mixed Xcelium/Spectre Digital-Mixed-Signal simulations. \n\n\n\n\n\n\n\n\n\n\n\n\nSpeakers \n\n\n\n\n\n\n\n\n\n\n\n\n\nDoug Koslow\, Product Engineering Architect\, Cadence\nRich Chang\, Product Marketing Director\, Cadence\n\n\n\n\n\n\n\nShare this:\n Share on LinkedIn (Opens in new window)\n LinkedIn\n \n Share on X (Opens in new window)\n X\n \n Share on Facebook (Opens in new window)\n Facebook\n Like this:Like Loading... URL:https://marketingeda.com/event/leveraging-verisium-debug-to-debug-digital-mixed-signal-designs/ CATEGORIES:EDA,Webinar ATTACH;FMTTYPE=image/jpeg:https://marketingeda.com/wp-content/uploads/Cadence-September-12-2024.jpeg END:VEVENT BEGIN:VEVENT DTSTART;TZID=America/Los_Angeles:20240912T100000 DTEND;TZID=America/Los_Angeles:20240912T110000 DTSTAMP:20260418T054334 CREATED:20240813T193538Z LAST-MODIFIED:20240813T193558Z UID:8234-1726135200-1726138800@marketingeda.com SUMMARY:Addressing 3D-IC Power Integrity Design Challenges DESCRIPTION:Power network design and analysis of 3D-ICs is a major challenge because of the complex nature and large size of the power network. In addition\, designers must deal with the complexity of routing power through the interposer\, multiple dies\, through-silicon vias (TSVs)\, and through-dielectric vias (TDVs). In this webinar\, you will learn how the Cadence Integrity 3D-IC Platform and Voltus IC Power Integrity Solution provides: \n\nFully integrated solution for early planning and analysis of 3D-IC power networks\n3D-IC chip-centric power integrity signoff\nHierarchical methods that significantly improve the capacity and performance of power integrity signoff while maintaining a very high level of accuracy at signoff\n\nShare this:\n Share on LinkedIn (Opens in new window)\n LinkedIn\n \n Share on X (Opens in new window)\n X\n \n Share on Facebook (Opens in new window)\n Facebook\n Like this:Like Loading... URL:https://marketingeda.com/event/addressing-3d-ic-power-integrity-design-challenges/ CATEGORIES:EDA,IP,Webinar ATTACH;FMTTYPE=image/jpeg:https://marketingeda.com/wp-content/uploads/Cadence-September-12-2024.jpg END:VEVENT BEGIN:VEVENT DTSTART;TZID=America/Los_Angeles:20240911T080000 DTEND;TZID=America/Los_Angeles:20240911T090000 DTSTAMP:20260418T054334 CREATED:20240821T163437Z LAST-MODIFIED:20240821T163437Z UID:8259-1726041600-1726045200@marketingeda.com SUMMARY:Questa Formal Verification IP AMBA: Achieve Protocol Compliance in Designs DESCRIPTION:Delve into how Questa Formal Verification IP (VIP) for the AMBA protocol ensures that designs incorporating AMBA adhere strictly to the protocol; all without the need for simulation. The solution integrates comprehensive protocol knowledge and provides user-friendly interfaces\, significantly reducing the setup time for verification environments. Optimized for top-tier performance and scalability\, Questa Formal VIP AMBA is the ideal tool for achieving high-efficiency and accurate protocol compliance. Don’t miss this opportunity to learn how to streamline your verification process and enhance your design workflows. \n  \nWhat You Will Learn:  \n\nChallenges in IP Integration\nUnderstand the common obstacles faced by designers and verification teams during IP integration and how to overcome them.\nBenefits of Formal Verification Ips\nDiscover the advantages of using formal verification IPs\, including enhanced accuracy and reduced need for simulation.\nCapabilities and Supported Protocols\nExplore the extensive capabilities of Questa Formal VIP AMBA and the range of protocols it supports.\nFrom Specification to Formal Properties\nLearn how protocol specifications are transformed into formal properties for effective verification.\nDebugging Protocol Violations\nGain insights into debugging techniques for protocol violations to ensure compliance and reliability.\n\n            \nWho Should Attend:  \n\nRTL Design Engineers\nDesign Integrators\nDesign Verification Engineers\n\nWhat/Which Products are Covered:   \n\nQuesta Formal VIP AMBA\nQuesta Formal VIP OnChip\nQuesta Check Register\n\n\n\nSpeaker:\n\n\n\n\n\n\nNicolae Tusinschi\nFormal Verification Solutions Product Manager\, Siemens EDA\n\n\n\n\nNicolae Tusinschi is a product manager for formal verification solutions at Siemens EDA. He holds a master’s degree combined between the University of Southampton and the University of Kaiserslautern. After a master’s thesis at Continental\, Nicolae joined OneSpin\, where he worked in QA\, then as a product specialist and later served as product owner for design verification tools at OneSpin. His key projects include integrating simulation coverage with formal metrics\, leveraging coverage results in the verification process\, formal verification of RISC-V cores. \n\n\n\nShare this:\n Share on LinkedIn (Opens in new window)\n LinkedIn\n \n Share on X (Opens in new window)\n X\n \n Share on Facebook (Opens in new window)\n Facebook\n Like this:Like Loading... URL:https://marketingeda.com/event/questa-formal-verification-ip-amba-achieve-protocol-compliance-in-designs/ CATEGORIES:EDA,IP,Webinar ATTACH;FMTTYPE=image/jpeg:https://marketingeda.com/wp-content/uploads/Siemens-Setember-11-2024.jpg END:VEVENT END:VCALENDAR