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BEGIN:VEVENT
DTSTART;TZID=America/Los_Angeles:20230627T110000
DTEND;TZID=America/Los_Angeles:20230627T120000
DTSTAMP:20230616T173450Z
CREATED:20230616T173450Z
LAST-MODIFIED:20230616T173450Z
UID:6502-1687863600-1687867200@marketingeda.com
SUMMARY:Verisium Debug for UPF Low Power Design
DESCRIPTION:Verisium Debug offers comprehensive debugging capabilities. From RTL\, UVM testbench to UPF low-power designs\, users can use the Cadence unified debugging platform for debugging. In this webinar\, users will learn about the available features in Verisium Debug for UPF power-aware designs and using the unique capabilities to visualize and debug UPF low-power designs. \nWhat you will learn \n\nUnderstand features available in Verisium Debug\n​Learn about the low-power debug capabilities available in Verisium Debug\nLearn how to debug UPF low-power designs with Verisium Debug\n\nWho should attend \n\nDesign engineers\nVerification engineers\nCAD engineers
URL:https://marketingeda.com/event/verisium-debug-for-upf-low-power-design/
CATEGORIES:EDA,Webinar
ATTACH;FMTTYPE=image/jpeg:https://marketingeda.com/wp-content/uploads/Cadence-June-27-2023.jpg
END:VEVENT
BEGIN:VEVENT
DTSTART;TZID=America/Los_Angeles:20230623T100000
DTEND;TZID=America/Los_Angeles:20230623T110000
DTSTAMP:20230612T212746Z
CREATED:20230612T212528Z
LAST-MODIFIED:20230612T212746Z
UID:6485-1687514400-1687518000@marketingeda.com
SUMMARY:Dealing with Complexity in Formal through Abstraction and Reduction
DESCRIPTION:In the world of formal verification\, abstractions along with design reductions\, help reduce the state space and make it easier for formal to converge on its proofs. \nIn this webinar Doulos Senior Member Technical Staff\, Doug Smith will explore the process of abstraction\, safe design reductions\, and when to use them. Doug will show practical examples of both (using VC Formal from Synopsys) and discuss formal results obtained by using abstractions and reductions. \nThe content will be useful to anyone who wants to learn to make more effective use of formal. \nAttendance is FREE and live Q&A will be provided throughout the broadcast. \n\n \nDoug Smith – Doulos Senior Member Technical Staff will present this training webinar\, which will consist of a one-hour presentation with interactive Q&A available to attendees throughout. \n\nAttendance is free of charge \nIf you have any queries\, please contact webinars@doulos.com
URL:https://marketingeda.com/event/dealing-with-complexity-in-formal-through-abstraction-and-reduction/
CATEGORIES:EDA,Webinar
ATTACH;FMTTYPE=image/jpeg:https://marketingeda.com/wp-content/uploads/Doulos-June-23-2023.jpg
ORGANIZER;CN="Doulos":MAILTO:webinars@duolos.com
END:VEVENT
BEGIN:VEVENT
DTSTART;TZID=America/Los_Angeles:20230622T110000
DTEND;TZID=America/Los_Angeles:20230622T120000
DTSTAMP:20230620T182517Z
CREATED:20230620T182517Z
LAST-MODIFIED:20230620T182517Z
UID:6546-1687431600-1687435200@marketingeda.com
SUMMARY:How AI and Semiconductors Will Drive Innovation and Productivity
DESCRIPTION:Semiconductors are critical to the functioning of the modern world driving economic competitiveness\, national security\, and technologies ranging from modern defense capabilities to autonomous vehicles. Artificial Intelligence and the hardware used in this platform are impacting how the world will use information to increase productivity. The semiconductors used in these platforms are instrumental to its functionality and are the backbone behind advancements in these technologies. \nPlease join a panel of industry experts for a conversation on how semiconductors are enabling the revolution in AI and what it means for the U.S. economy. Panelists include Jerry Chen\, Director of Global Business Development for Manufacturing & Industrial at NVIDIA; Ramine Roane Corporate Vice President of AI at AMD; and Stelios Diamantidis\, head of Synopsys’ Artificial Intelligence Strategy in the Office of the President. The session will be moderated by Robert Casanova\, Director of Industry Statistics and Economy Policy at SIA.
URL:https://marketingeda.com/event/how-ai-and-semiconductors-will-drive-innovation-and-productivity/
CATEGORIES:EDA,IP,Webinar
ATTACH;FMTTYPE=image/jpeg:https://marketingeda.com/wp-content/uploads/SIA-June-22-2023.jpg
END:VEVENT
BEGIN:VEVENT
DTSTART;TZID=America/Los_Angeles:20230622T080000
DTEND;TZID=America/Los_Angeles:20230622T090000
DTSTAMP:20230612T175957Z
CREATED:20230612T175957Z
LAST-MODIFIED:20230612T175957Z
UID:6475-1687420800-1687424400@marketingeda.com
SUMMARY:Design and Analysis of Multi-Die & 3D-IC Systems
DESCRIPTION:The architecture and heterogeneous integration capability of 3D-IC (three-dimensional integrated circuits) offer many benefits. The latest configuration methods\, CoWoS (Chip On Wafer on Substrate) and WoW (Wafer on Wafer) from TSMC\, provide advantages by significantly reducing the interconnect length and signal power loss. These new technologies have introduced the need for innovative ways to solve novel physics challenges. Solving the complex issues related to the structural\, thermal\, power\, and signal integrity of the entire 2.5D/3D-IC system cannot be accomplished using only traditional tools. Advanced simulation methods and highly accurate solvers are required to accurately predict the entire multiphysics coupling in 3D-IC systems including interposers and heterogeneous components. \nIn this webinar\, Jerome discusses the latest developments in 3D-IC design\, challenges\, and how simulation is the key to successful 3D-IC design. He also presents a comprehensive environment to simulate these physics and achieve the Structural\, Thermal\, Power\, and Signal integrity of the entire 3D-IC system. Chiplet designers\, Interposer designers\, 3D-IC designers\, and 3D-IC architects will find this webinar helpful. \nPresenter: \nJerome Toublanc has over 20 years of Semiconductor industry experience\, working for various EDA companies such as Avanti\, Synopsys\, and Apache. He has contributed to the successes of worldwide customers in roles ranging from Application Engineer to Product Management and has covered the chip development flow from RTL to GDSII. He is now a business development executive for Ansys. His mission is to identify emerging Multiphysics Integrity challenges within the semiconductor industry and develop product solutions for the complete Chip-Package-PCB ecosystem. \n*This webinar is in partnership with SemiWiki and Ansys*
URL:https://marketingeda.com/event/design-and-analysis-of-multi-die-3d-ic-systems/
CATEGORIES:EDA,Webinar
ATTACH;FMTTYPE=image/webp:https://marketingeda.com/wp-content/uploads/Ansys-June-22-2023.webp
END:VEVENT
BEGIN:VEVENT
DTSTART;TZID=America/Los_Angeles:20230621T100000
DTEND;TZID=America/Los_Angeles:20230621T110000
DTSTAMP:20230612T212024Z
CREATED:20230612T211941Z
LAST-MODIFIED:20230612T212024Z
UID:6481-1687341600-1687345200@marketingeda.com
SUMMARY:Achieve Out-of-the-Box Equivalence Checking with Synopsys Formality ML-driven Distributed Processing
DESCRIPTION:When designers synthesize chip designs with aggressive PPA targets\, the expectation and goal is to be able to complete verification with minimal effort and a fast turn-around-time. Synopsys Design Compiler and Fusion Compiler offer a broad spectrum of optimization techniques such as retiming\, multibit banking and advanced data-path optimizations\, though these techniques can end up being inconsequential if they cannot be verified through equivalence checking. Therefore\, the ideal setup is completed quickly using equivalence checking to provide out-of-the-box results so lengthy iterations and engineer hours aren’t spent converging on verification pass.\nThis presentation will detail how Synopsys Formality ML-driven Distributed Processing (DPX) delivered out-of-the-box verification for STMicroelectronics Design team without the need to scale back optimizations or sacrifice PPA goals. Attendees will walk away with an understanding of how Synopsys Formality equivalence checking captures the design transformation/optimizations in Formality Guide Files (SVF) for rapid setup of the verification environment to avoid multiple iterative runs. In addition\, ML-driven adaptive distributed verification techniques will be highlighted\, which help to partition the design and run solvers in parallel to further accelerate verification runtime and out-of-the-box results. \nSpeakers\n\n\n\n\nNathalie Méloux\n\n\nPrincipal Engineer\nSTMicroelectronics \n\n\n\n\n\n\n\n\nNathalie Méloux\, Principal Engineer at STMicroelectronics\, has been working in the microcontroller division for over 20 years. She has greatly contributed to the development of the STM32 microcontrollers families since its inception. Nathalie has extensive experience in the areas of digital design methodology and low-power implementation flow. She is in charge of the digital flow\, the support of the design implementation from RTL through Synthesis to P&R including signoff timing analysis\, equivalence checking\, power analysis and optimizations all along the flow. \nNathalie Meloux holds a master’s degree in Microelectronics and Robotics from Polytech Montpellier\, France and a D.E.A. (post-Master’s degree) in Microelectronics from the University of Montpellier (Faculty of Science)\, France. \n\n\n\n\nStephane Maulet\n\n\nApplications Engineer\, Sr Staff\nSynopsys \n\n\n\n\n\n\n\n\nStephane Maulet is a Senior Staff Applications Engineer at Synopsys. He has almost 20 years of experience in Synopsys front-end tools spanning Synopsys Design Compiler\, Synopsys Fusion Compiler\, Synopsys Formality and Synopsys Formality ECO. \nStephane holds a master’s degree in Microelectronics Engineering from Grenoble INP\, France.
URL:https://marketingeda.com/event/out-of-the-box-equivalence-checking-synopsys-formality/
CATEGORIES:EDA,Webinar
ATTACH;FMTTYPE=image/jpeg:https://marketingeda.com/wp-content/uploads/Synopsys-June-21-2023.jpg
END:VEVENT
BEGIN:VEVENT
DTSTART;TZID=America/Los_Angeles:20230621T100000
DTEND;TZID=America/Los_Angeles:20230621T110000
DTSTAMP:20230606T180716Z
CREATED:20230606T180716Z
LAST-MODIFIED:20230606T180716Z
UID:6460-1687341600-1687345200@marketingeda.com
SUMMARY:Applying AI/ML Technology for Rapid Design Optimization
DESCRIPTION:The problem of optimization is a long-standing one in the field of design. For years\, the most conventional approach was the brute-force method of running parametric sweeps on the design space. However\, as systems become more complex and the number of parameters increases\, the computational resource and time cost becomes unsustainable. With the Cadence Optimality Explorer\, users can explore the same design space more efficiently and intelligently. By leveraging artificial intelligence/machine learning technology\, Optimality Explorer removes the need for exhaustive sweeps and dramatically reduces the number of iterations required to converge to the optimized solution.
URL:https://marketingeda.com/event/applying-ai-ml-technology-for-rapid-design-optimization/
CATEGORIES:EDA,Webinar
ATTACH;FMTTYPE=image/jpeg:https://marketingeda.com/wp-content/uploads/Cadence-June-21-2023-1.jpg
END:VEVENT
BEGIN:VEVENT
DTSTART;TZID=America/Los_Angeles:20230620T100000
DTEND;TZID=America/Los_Angeles:20230620T110000
DTSTAMP:20230612T211032Z
CREATED:20230612T211032Z
LAST-MODIFIED:20230612T211032Z
UID:6478-1687255200-1687258800@marketingeda.com
SUMMARY:Leveraging Silicon Lifecycle Management (SLM) for Automotive Applications
DESCRIPTION:Automobiles are today’s supercomputers and with that statement comes great challenges. A vehicle is a highly demanding environment for electronics. Temperature and humidity extremes\, noise and vibration\, electrical interference\, exposure to alpha particles\, and other factors all make it hard to design and manufacture chips that will operate correctly under all conditions. In addition\, the growing importance of Transportation as a Service (TaaS) is pushing availability requirements to 24/7/365. As specified by the ISO 26262 safety standard\, chips must be able to detect defects and take corrective action on their own. \nFor all these reasons\, developing chips for automotive applications is challenging. Proper pre-silicon design\, verification\, and validation are essential\, but further attention to detail is needed during system bring-up\, manufacturing\, production test\, and field operation. \nIn this webinar you will learn how Silicon Lifecycle Management (SLM) has emerged as a leading paradigm to make product development and deployment more deterministic for automotive applications \n  \nSpeakers\n\n\n\n\nSashi Obilisetty\n\n\nGroup Dir\, R&D in the EDA Group\nSynopsys\, Inc. \n\n\n\n\n\n\n\n\nSashi Obilisetty is Group Dir\, R&D in the EDA Group at Synopsys. In her 12+ year tenure at Synopsys\, Sashi has been instrumental in enabling several Synopsys technologies in the design\, verification and post-silicon space. She is one of the key leaders involved in ushering AI usage in Synopsys products. She was the Chief Architect for Silicon Solutions at Google Cloud. Sashi founded 2 startups in the verification domain. Sashi has a Bachelors in Electronics and Communication Engineering from Birla Institute of Technology\, Mesra and a Master’s in Computer Engineering from UMASS\, Amherst. \n\n\n\n\n\nPawini Mahajan\n\n\nStaff Product Manager\nSynopsys\, Inc. \n\n\n\n\n\n\n\n\nPawini Mahajan is a Staff Product Manager within the Hardware Analytics and Test group at Synopsys\, specializing in silicon life cycle management solutions for Automotive. In this role she is responsible for Automotive Go-to-Market activities\, understanding and communicating SLM-based solutions for automotive applications to the broad automotive ecosystem. Before joining Synopsys\, she managed an engineering team at Intel focused on reducing defective parts per million (DPPM) for Intel’s flagship products. In addition\, she has actively participated in several notable fundraisers\, including cancer awareness\, women in technology and academic fund gifting. She holds a master’s degree in electrical engineering from Arizona State University.
URL:https://marketingeda.com/event/leveraging-silicon-lifecycle-management-slm-for-automotive-applications/
CATEGORIES:EDA,Webinar
ATTACH;FMTTYPE=image/jpeg:https://marketingeda.com/wp-content/uploads/Synopsys-June-20-2023.jpg
END:VEVENT
BEGIN:VEVENT
DTSTART;TZID=America/Los_Angeles:20230620T080000
DTEND;TZID=America/Los_Angeles:20230620T090000
DTSTAMP:20230613T175913Z
CREATED:20230613T175913Z
LAST-MODIFIED:20230613T175913Z
UID:6496-1687248000-1687251600@marketingeda.com
SUMMARY:Designing for Six Sigma: Electronics Simulation Powered by Parametric Variation
DESCRIPTION:The webinar focuses on the simulation-driven optimization of electronics\, Integrated Circuits applications to achieve a six-sigma level of quality. Electronics are part of our daily life\, with innovative and connected transportation\, buildings\, and communications. However\, the design of electronic devices is a complex process\, and achieving a six-sigma level of quality is a significant challenge. The six-sigma level of quality requires a method capable of producing products with no more than 3.4 defects per million opportunities. Achieving this level of quality is critical for ensuring reliability\, performance\, and longevity. \nThe webinar will cover the use of Ansys electronic and semiconductor simulation capabilities combined with parametric studies and optimization methodologies to improve the design and manufacturability through two use cases: \n\nAnsys HFSS + Parametric Variation in Ansys optiSLang for Electronics 3D Design & Analysis\nAnsys RaptorX + Parametric Variation in Ansys optiSLang for Integrated Circuits Physical Design & Analysis\n\nWhat You Will Learn\n\nLearn how to evaluate and optimize Integrated-Circuits performance through simulation-driven approach which involves the use of models to predict the behavior of the Integrated Circuits (IC) under various conditions.\nLearn how the Robust Design Optimization process takes the simulation to the next level. It involves identifying critical parameters that affect most the quality of the design\, creating robust parametric models to predict the simulation outputs and using AI/ML algorithms to find optimal values with automated and systematic simulation process.\nThe key benefits are to obtain better robustness against manufacturing tolerances\, eliminate manufacturing uncertainties and avoid costly product recalls due to defects discovered after the product is in the market.\nThe webinar will showcase 2 product integrations for electronics applications that aim to achieve six-sigma level of quality through process integration and design optimization.\nThe audience will gain insights into the key challenges and strategies involved in optimizing IC electronics designs through Robust Design Optimization methodology for high-quality and reliable performance.\n\nWho Should Attend\nDesign & Simulation Engineers/ Managers in Electronics & Semiconductor industries \nSpeaker\nJuliano Mologni\nKelly Damalou\nDavid Schneider
URL:https://marketingeda.com/event/designing-for-six-sigma-electronics-simulation-powered-by-parametric-variation/
CATEGORIES:EDA,Webinar
ATTACH;FMTTYPE=image/jpeg:https://marketingeda.com/wp-content/uploads/Amsys-June-20-2023.jpg
END:VEVENT
BEGIN:VEVENT
DTSTART;TZID=America/New_York:20230614T130000
DTEND;TZID=America/New_York:20230614T140000
DTSTAMP:20230606T003848Z
CREATED:20230606T003848Z
LAST-MODIFIED:20230606T003848Z
UID:6453-1686747600-1686751200@marketingeda.com
SUMMARY:Microelectronics Design Security: Better with Formal Methods
DESCRIPTION:Whether you are developing Systems-on-Chip (SoCs) for mobile and wearables\, automotive\, aerospace\, defense\, data centers\, or entertainment\, securing your proprietary data and customers’ information is critical to your company’s long-term success. Hackers can exploit vulnerabilities in these systems — at the network\, system\, device\, or chip levels. As SoC designs get more complex\, this 30-minute Webinar aims to show chip designers how they can best ensure secure data is handled correctly inside the chip while reducing deployment time. \nThis Webinar will help attendees understand: \n\nThe role of formal methods for security verification\nThe key challenges of formal verification and why addressing them is critical\nHow to ensure information flow tracking verifies data integrity and leakage issues\nHow a next-generation formal verification solution is helping users analyze and debug the root cause of security violations\n\nAn audience Q&A session will follow the technical presentation. \n\n\nSpeakers:\nJin Zhang is a Director of Product Management at Synopsys\, who is responsible for VC Formal. Jin has more than 25 years of experience working in the EDA industry\, driving new products and technologies to the market in the formal verification space. She worked at Cadence\, Real Intent\, EVE\, and Oski Technology prior to joining Synopsys. Jin holds a Ph.D. in electrical and computer engineering and an MBA in international management.\n\n\n\n\nIan Land serves as Synopsys’s Senior Director of Security\, Government\, and Aerospace Solutions. Ian has more than 20 years of semiconductor experience and has spent more than 15 years in disciplines that require security. Before joining Synopsys\, he worked for Intel\, Altera\, and Xilinx. Ian holds a bachelor’s degree in mechanical engineering from UCLA and a master’s degree in mechanical engineering and management from MIT.
URL:https://marketingeda.com/event/microelectronics-design-security-better-with-formal-methods/
CATEGORIES:EDA,Webinar
ATTACH;FMTTYPE=image/jpeg:https://marketingeda.com/wp-content/uploads/SynopsysSAE-June-14-2023.jpg
END:VEVENT
BEGIN:VEVENT
DTSTART;TZID=Europe/Paris:20230614T100000
DTEND;TZID=Europe/Paris:20230614T110000
DTSTAMP:20230606T003107Z
CREATED:20230606T003107Z
LAST-MODIFIED:20230606T003107Z
UID:6450-1686736800-1686740400@marketingeda.com
SUMMARY:Verify Your SoC Design Efficiently from Planning to Coverage Closure using Synopsys Verification Family
DESCRIPTION:Verifying an SoC is an extremely complex process that requires agile turnaround\, constant control feedback\, and flexibility to adapt to evolving project needs. Coverage is an efficient metric for the number of potential bugs found and needs to be tracked at each stage of the project. The verification process starts from defining the verification goals\, automating test execution\, collecting and analyzing coverage metrics\, and then tracking and providing guidance until coverage closure is reached. In this webcast\, we will describe how to easily achieve this process using the Synopsys Verification Family of tools including VCS\, Verdi\, and VC Execution Manager. \n\n\n\n\n\n\n\n\n\n\nSpeaker\n\n\nListed below is the industry leader scheduled to speak. \n\n\n\n\n\n\n\n\n\n\n\n\n\n\n\n\n\n\n\n\n\n\n\n\n\n\nXavier Mathes\n\n\nSenior Staff Application Engineer\nSynopsys \n\n\n\n\n\n\n\n\n\n\n\nXavier Mathes is a Senior Staff Application Engineer at Synopsys. He is responsible for multiple verification products including Synopsys VCS\, Verdi\, Verification IP\, VC Execution Manager\, HAPS\, and Synplify. Xavier previously worked at IBM\, Philips Semiconductor\, Synplicity\, and other semiconductor companies. His combined 26 years working in the industry has brought a wealth of knowledge and experience in the areas of semiconductor design and verification. Xavier has a Masters of Science in Electrical Engineer from CentraleSupelec.
URL:https://marketingeda.com/event/verify-your-soc-design-efficiently-from-planning-to-coverage-closure-using-synopsys-verification-family/
CATEGORIES:EDA,Webinar
ATTACH;FMTTYPE=image/jpeg:https://marketingeda.com/wp-content/uploads/Synopsys-June-14-2023.jpg
END:VEVENT
BEGIN:VEVENT
DTSTART;TZID=America/Los_Angeles:20230613T080000
DTEND;TZID=America/Los_Angeles:20230613T090000
DTSTAMP:20230524T191605Z
CREATED:20230524T191605Z
LAST-MODIFIED:20230524T191605Z
UID:6434-1686643200-1686646800@marketingeda.com
SUMMARY:Driving Forward with UWB Radar: Enhancing Child Safety in Automotive
DESCRIPTION:Fueled by the recent adoption by leading smartphone brands\, the UWB wireless technology is enjoying an explosive growth in market interest and applications. In automotive\, UWB is already the de-facto choice for Digital Keys in the premium segment. The deployment of UWB anchor points in modern car creates a cost-effective platform for offering advanced in-cabin radar\, enabling features such as Child Presence Detection (CPD). \nIn this webinar\, you will learn about: \n• UWB technology and ecosystem (UWB alliance\, CCC\, FiRa)\n• How does UWB Radar work\n• CEVA’s UWB and Radar solutions\n\n\nTarget Audience\nSystem engineers\, SoC designers\, and product managers targeting UWB devices\, that are looking to add radar capabilities to products for automotive\, industrial\, consumer\, and others\n\n\nSpeakers\n\n\n\n\n\n\n\nNavot Goren\nUWB Product Director\, CEVA Inc.
URL:https://marketingeda.com/event/driving-forward-with-uwb-radar-enhancing-child-safety-in-automotive/
CATEGORIES:IP,Webinar
ATTACH;FMTTYPE=image/jpeg:https://marketingeda.com/wp-content/uploads/CEVA-June-13-2023.jpg
END:VEVENT
BEGIN:VEVENT
DTSTART;TZID=America/Los_Angeles:20230613T080000
DTEND;TZID=America/Los_Angeles:20230613T090000
DTSTAMP:20230326T033357Z
CREATED:20230326T033357Z
LAST-MODIFIED:20230326T033357Z
UID:6206-1686643200-1686646800@marketingeda.com
SUMMARY:Run Ansys HFSS in the Cloud with AWS to Boost Simulation
DESCRIPTION:About This Webinar\nEngineers worldwide use Ansys HFSS software to design high-frequency\, high-speed electronics found in communications systems\, advanced driver assistance systems (ADAS)\, satellites\, and internet-of-things (IoT) products. Ansys HFSS is a 3D electromagnetic (EM) simulation software for designing and simulating high-frequency electronic products such as antennas\, antenna arrays\, RF or microwave components\, high-speed interconnects\, filters\, connectors\, IC packages\, and printed circuit boards. These different use cases often require large complex models to solve on a traditional workstation\, and leveraging an HPC cluster is often tedious\, time-consuming\, and expensive. Ansys recently partnered with AWS (Amazon Web Services) to develop a new product that optimizes using  Ansys applications on the cloud. \nAnsys Gateway powered by AWS is the solution for developers\, designers\, and engineers who want to manage their complete Ansys Simulation & CAD/CAE developments in the cloud. Access cloud computing resources from anywhere on virtually any device via your web browser. You can create\, customize\, and connect cloud applications with minimal technical skills.  Install your 3rd party applications alongside Ansys applications. \nWhat You Will Learn\n\nWhy the cloud can solve your challenges\nDiscover use cases where the cloud can help\nLearn the benefits you can leverage from using the cloud from AWS\nWatch a quick demo of Ansys HFSS running directly in-browser on Ansys Gateway powered by AWS\n\nSpeaker\nJJ Jones
URL:https://marketingeda.com/event/run-ansys-hfss-in-the-cloud-with-aws-to-boost-simulation/
CATEGORIES:EDA,Webinar
ATTACH;FMTTYPE=image/jpeg:https://marketingeda.com/wp-content/uploads/Ansys-June-13-2023.jpg
END:VEVENT
BEGIN:VEVENT
DTSTART;TZID=America/Los_Angeles:20230607T110000
DTEND;TZID=America/Los_Angeles:20230607T120000
DTSTAMP:20230523T172645Z
CREATED:20230523T172645Z
LAST-MODIFIED:20230523T172645Z
UID:6430-1686135600-1686139200@marketingeda.com
SUMMARY:Xcelium: The Key to Unlocking Unmatched Mixed-Signal Performance
DESCRIPTION:Xcelium mixed-signal simulation enables teams to achieve digital simulation speeds of analog models and opens mixed-signal designs to advanced verification techniques typically applied within standard verification flows.  Built on a SystemVerilog Real Number Modeling (RNM) foundation\, Xcelium automates the signal integration of digital and RNM code to achieve digital simulation speeds for mixed-signal designs. This capability is further enhanced using the EEnet package\, which defines a specialized net type useful for passing voltage values across the design. Cadence adds randomization\, coverage\, incremental elaboration\, advanced debugging\, and other techniques to bring advanced verification to mixed-signal system designs. You can attend our webinar to learn more about how you can accelerate your mixed-signal simulations with RNM and EEnet in Xcelium. \n\nLearn about accelerating mixed-signal simulations with RNM and EEnet in Xcelium\nLearn about utilizing a full verification flow of randomization\, coverage\, incremental elaboration\, and advanced debug with mixed-signal designs\nLearn about achieving digital simulation speeds of analog models
URL:https://marketingeda.com/event/xcelium-the-key-to-unlocking-unmatched-mixed-signal-performance/
CATEGORIES:EDA,Webinar
ATTACH;FMTTYPE=image/jpeg:https://marketingeda.com/wp-content/uploads/Cadence-June-7-2023.jpg
END:VEVENT
BEGIN:VEVENT
DTSTART;TZID=America/New_York:20230601T120000
DTEND;TZID=America/New_York:20230601T130000
DTSTAMP:20230522T170521Z
CREATED:20230522T170521Z
LAST-MODIFIED:20230522T170521Z
UID:6419-1685620800-1685624400@marketingeda.com
SUMMARY:Accelerate Software Innovation Through Target-Optimized Code Generation and Virtual Prototypes
DESCRIPTION:Increasingly complex automotive systems are driving the need for new and powerful E/E architectures\, and new technology is emerging that offers a significant computational increase compared to previous generation SoCs. To deliver next-generation\, differentiated software solutions\, model-based design (MBD) workflows must be deployed to handle this new level of complexity. Code generation solutions that optimize microcontroller performance to meet the development and deployment challenges of e-mobility\, advanced control\, and signal processing are a key part of this workflow. This 30-minute Webinar will explore this workflow in which virtual prototypes can substitute the physical target for much of that traditional MBD workflow. \nThis Webinar will include: \n\n  \n\n\nAn overview of the benefits of using advanced virtual prototypes in the MBD workflow\, such as faster turn-around time\, better debug capabilities\, and maximized deployment to developers\n\n\nHighlights of the features and capabilities of support packages for specialized microcontrollers\n\n\n\nLive demonstrations for a hands-on understanding of how fully virtual workflow with virtual prototypes is applied \n\n\n\n\nA Q&A session will follow the technical presentation. \nSpeakers:\n\nKevin Brand\, Principal Engineer\, Synopsys\nKevin Brand\, a Principal R&D Engineer for Synopsys\, has worked in the virtual prototyping field for 18 years. With a strong focus on automotive\, he has concentrated on R&D in recent years\, directly enabling and deploying virtual prototyping solutions at semiconductor\, Tier 1\, and OEM companies. He holds a master’s degree in electronic engineering from Napier University\, Edinburgh\, and previously worked in the aerospace and defense domain. \n  \nDineshkumar Selvaraj\, Lead Principal Engineer\, Infineon Technologies \nDinesh Selvaraj leads virtual prototype development for the AURIX family of microcontrollers at Infineon Technologies. He has more than 18 years of ESL domain experience with a focus on development of virtual prototypes for classical pre-silicon software validation\, RTL co-simulation\, and early performance analysis and optimization using models. Prior to joining Infineon\, Dinesh worked for Intel and Tata Elxsi. He holds an electrical engineering degree from the National Institute of Technology\, Trichy. \nKelly Zhang\, Application Engineer\, MathWorks \nAs an Application Engineer at MathWorks\, Kelly Zhang focuses on model-based design workflows\, Simulink use\, control system design\, code generation\, and verification and validation tools. She holds a bachelor’s and master’s degree in aerospace engineering from the University of Toronto as well as a master’s degree in mechanical engineering with a focus on control and robotic systems from Carnegie Mellon University.
URL:https://marketingeda.com/event/accelerate-software-innovation-through-target-optimized-code-generation-and-virtual-prototypes/
CATEGORIES:EDA,Webinar
ATTACH;FMTTYPE=image/jpeg:https://marketingeda.com/wp-content/uploads/Synopsys-June-1-2023.jpg
END:VEVENT
BEGIN:VEVENT
DTSTART;TZID=America/Los_Angeles:20230601T110000
DTEND;TZID=America/Los_Angeles:20230601T120000
DTSTAMP:20230421T164256Z
CREATED:20230421T164256Z
LAST-MODIFIED:20230421T164256Z
UID:6308-1685617200-1685620800@marketingeda.com
SUMMARY:Advanced Testbench for a Simple DUT
DESCRIPTION:Abstract: \nFunctional simulation using an HDL testbench is the de facto method for proving functional correctness of FPGA designs. In this three-part webinar series\, we will present a step-by-step approach on how to architect a testbench – progressing from basic to advanced techniques. We will first use a simple DUT then go to a more complex DUT with simultaneous activities on multiple interfaces. \nIn part 2 of this webinar series\, we will show you how to verify a relatively simple DUT with high quality requirements using an advanced testbench without using any verification framework. We will also discuss the elements of an advanced testbench infrastructure to verify our simple DUT more efficiently\, check and prove that we have indeed verified our simple DUT more thoroughly\, start to use advanced Bus Functional Models (BFMs) that allow simpler and more advanced interface control\, and introduce functional coverage. \nHaving shown you these more advanced testbench techniques\, we will continue to show how UVVM can be used to implement them in the simplest ways possible and with a focus on readability\, maintainability\, and extensibility. \nAgenda:\nWhat is required when verifying for higher quality?\nThe elements of an advanced testbench infrastructure\nAdvanced BFMs\nBFM vs Protocol Checkers\nBFM limitations\nAdvanced randomization\nSpecification Coverage\, aka Requirements Coverage\nIntroducing functional coverage\nUVVM advanced BFMs\nUVVM for high quality verification\nQ&A \nWebinar Duration\n45 min presentation/live demo\n15 min Q&A \nPresenter Bio: \nSimon Southwell has 35 years in Research and Development\, with experience in ASIC design\, FPGA\, and embedded software development. \nEspen Tallaksen\, CEO of EmLogic \nEspen is also the author and architect of UVVM and founder of previous Bitvis. \nHe has a strong interest in methodology cultivation and pragmatic efficiency and quality improvement\, and he has given many presentations at various international conferences with great feedback. He has also given courses on FPGA Design and Verification in three different continents.
URL:https://marketingeda.com/event/advanced-testbench-for-a-simple-dut/
CATEGORIES:EDA,IP,Webinar
ATTACH;FMTTYPE=image/jpeg:https://marketingeda.com/wp-content/uploads/Aldec-June-1-2023.jpg
END:VEVENT
BEGIN:VEVENT
DTSTART;TZID=America/Los_Angeles:20230525T090000
DTEND;TZID=America/Los_Angeles:20230525T100000
DTSTAMP:20230522T165126Z
CREATED:20230516T000921Z
LAST-MODIFIED:20230522T165126Z
UID:6400-1685005200-1685008800@marketingeda.com
SUMMARY:Don’t Take the Risk\, Formally Verify Your RISC-V Cores
DESCRIPTION:Synopsys Webinar | Thursday\, May 25\, 2023 | 9:00 a.m. PT \n\n\n\n\n\n\n\n\n\n\n\n\n\nAccording to a recent Semico Research report\, the RISC-V Core IP market is expected to grow at a 34.9% CAGR through year 2027. With increasing popularity\, it is of utmost importance that the RISC-V Core IPs are secure and bug free. ​ \nIn this joint Synopsys webinar with SyoSil\, will discuss how to use formal verification to ensure functional correctness and security of RISC-V Cores. We will cover the high-level formal verification goals and example tasks so attendees can obtain a comprehensive view of the many facets of RISC-V Core verification using formal technologies. We will explore a specific case study that uses the so-called ‘S2QED’ methodology to verify a scalar five-stage RISC-V Core. We will also show a demo for this case study using Synopsys VC Formal. ​ \nThe attendees will walk away with a comprehensive understanding of the formal verification requirements for RISC-V Cores to ensure functionality and security\, as well as specific examples of using formal property verification to find intra- and inter-instruction design bugs. ​ \n\n\n\n\n\n\n\n\n\n\nSpeakers\n\n\nListed below are the industry leaders scheduled to speak. \n\n\n\n\n\n\n\n\n\n\n\n\n\n\n\n\n\n\n\n\n\n\n\n\n\n\nSiddartha Papineni\n\n\nSr Staff Application Engineer\nSynopsys \n\n\n\n\n\n\n\n\n\n\n\nSid Papineni is a Sr. Staff Applications Engineer at Synopsys and works on formal verification consulting services and Synopsys VC Formal SEQ\, DPV\, and product engineering activities. Sid has 11+ years of experience in the formal verification domain\, focused mainly on formal property verification and datapath validation methodologies. \n\n\n\n\n\n\n\n\n\n\n\n\n\n\n\n\n\n\n\n\n\n\n\n\n\n\n\n\n\n\n\nFrederik Möllerström Lauridsen\n\n\nVerification Engineer\nSyoSil \n\n\n\n\n\n\n\n\n\n\n\nFrederik Möllerström Lauridsen is a verification engineer at SyoSil. His technical competences and interests lie within both formal verification and SV/UVM based constrained random verification. Frederik holds a PhD degree in mathematics and computer science and a MSc degree in logic from the University of Amsterdam\, and a BSc in Mathematics from the University of Copenhagen.
URL:https://marketingeda.com/event/dont-take-the-risk-formally-verify-your-risc-v-cores/
CATEGORIES:EDA,Webinar
ATTACH;FMTTYPE=image/jpeg:https://marketingeda.com/wp-content/uploads/Synopsys-May-25-2023.jpg
END:VEVENT
BEGIN:VEVENT
DTSTART;TZID=Asia/Kolkata:20230524T100000
DTEND;TZID=Asia/Kolkata:20230524T104500
DTSTAMP:20230516T025644Z
CREATED:20230515T235833Z
LAST-MODIFIED:20230516T025644Z
UID:6397-1684922400-1684925100@marketingeda.com
SUMMARY:Accelerate Coverage Closure and Debug with Synopsys AI-Driven Verification Solutions
DESCRIPTION:Synopsys Webinar | Wednesday\, May 24\, 2023 | 10:00 – 10:45 a.m. IST \n\n\n\n\n\n\n\n\n\n\n\n\nEngineering resources are getting stretched thinner and thinner as design complexity increases. Automation is a significant driver to help engineers overcome resource constraints and meet critical time-to-market windows. Two of the top three challenges cited by the engineering community in a recent survey are in the areas of coverage closure and system-level debug. How do we efficiently and accurately understand and reach coverage closure and how do we accelerate and maximize the debug process? These challenges can be addressed with the latest Synopsys AI-Driven debug automation and coverage closure technologies. \nIn this webinar\, we’ll discuss Synopsys Verdi Regression Debug Automation (RDA)\, the ground-breaking AI-driven debug technology that includes the necessary predictive analysis to automate the manual and error-prone process of finding the root cause(s) of failures in the design-under-test (DUT) and testbench. \nWe’ll also explore the latest Synopsys simulation technologies – Verification Space Optimization (VSO.ai) and VCS Intelligent Coverage Optimization (ICO). These AI-driven technologies help accelerate and improve coverage\, expose more bugs\, and reduce regression turnaround time. \n\n\n\n\n\n\n\n\n\nSpeaker\n\n\nListed below is the industry leader scheduled to speak. \n\n\n\n\n\n\n\n\n\n\n\n\n\n\n\n\n\n\n\n\n\n\n\n\n\n\nTaruna Reddy\n\n\nProduct Marketing Manager\, Staff \nSynopsys \n\n\n\n\n\n\n\n\n\n\n\n\nTaruna Reddy is a Staff Product Manager in the EDA Group at Synopsys. Taruna has 18 years of experience in EDA and functional verification. Prior to joining Synopsys\, Taruna held field applications and verification engineering positions at Mentor Graphics\, Verilab and Xtreme-EDA. She holds a MSEE from Clemson University and Bachelor of Technology from India.
URL:https://marketingeda.com/event/accelerate-coverage-closure-and-debug-with-synopsys-ai-driven-verification-solutions/
CATEGORIES:EDA,Webinar
ATTACH;FMTTYPE=image/jpeg:https://marketingeda.com/wp-content/uploads/Synopsys-May-24-2023-2.jpg
END:VEVENT
BEGIN:VEVENT
DTSTART;TZID=America/Los_Angeles:20230524T090000
DTEND;TZID=America/Los_Angeles:20230525T120000
DTSTAMP:20230515T234754Z
CREATED:20230515T234719Z
LAST-MODIFIED:20230515T234754Z
UID:6394-1684918800-1685016000@marketingeda.com
SUMMARY:Requirements for Multi-Die System Success
DESCRIPTION:Wednesday\, May 24\, 2023 and Thursday\, May 25\, 2023  \n\n\n\n\n\n\n\n\n\n\nThe industry is moving to multi-die systems to benefit from the greater compute performance\, increased functionality\, and new levels of flexibility. Challenges for multi-die systems are exacerbated and require greater focus on a number of requirements such as early partitioning and thermal planning\, die/package co-design\, secure and robust die-to-die connectivity\, reliability and health\, as well as verification and system validation. Attend this webinar series to find out about some of the essential requirements that can help you overcome multi-die system challenges and make your move to multi-die systems successful. \n\n\nMay 24th presentation topics will include: \n\n9:00 a.m. PDT: Multi-Die System Trends\, Challenges and Requirements\n10:00 a.m. PDT: Benefits of Early Architecture Design for Multi-Die Systems\n11:00 a.m. PDT: Innovations in Multi-Die System Co-Design and System Analysis\n\nMay 25th presentation topics will include: \n\n9:00 a.m. PDT: Successful Connectivity of Heterogeneous Dies with UCIe IP\n10:00 a.m. PDT: Identifying and Overcoming Multi-Die System Verification Challenges\n11:00 a.m. PDT: Optimizing Multi-Die System Health from Die to Package to In-Field\n\n  \nRegister once for access to all the webinars.
URL:https://marketingeda.com/event/requirements-for-multi-die-system-success/
CATEGORIES:EDA,IP,Webinar
ATTACH;FMTTYPE=image/jpeg:https://marketingeda.com/wp-content/uploads/Synopsys-May-24-25-2023.jpg
END:VEVENT
BEGIN:VEVENT
DTSTART;TZID=America/Los_Angeles:20230524T090000
DTEND;TZID=America/Los_Angeles:20230524T100000
DTSTAMP:20230510T164527Z
CREATED:20230510T164527Z
LAST-MODIFIED:20230510T164527Z
UID:6383-1684918800-1684922400@marketingeda.com
SUMMARY:Advancing MRAM Technology with Atomistic Spin Dynamics Simulations
DESCRIPTION:In this event\, experts from Martin-Luther-Universitat Halle Wittenberg\, University of York\, and Synopsys QuantumATK will present how to use ab initio DFT modeling and atomistic spin dynamics simulations of MTJs to guide and accelerate the technological development of magnetic memory such as STT and SOT-MRAM. \n\nInvestigating the potential of novel magnetic tunnel junction (MTJ) materials and concepts for improved magnetic memory performance.\nGenerating realistic MTJ structures with Machine-Learned Force Fields.\nEvaluating the performance based on calculated MTJ spintronic properties\, such as tunnel magnetoresistance (TMR)\, current rectification\, spin-transfer and spin-orbit torques (STT and SOT)\, Gilbert damping\, Curie temp.\, and thermal stability.\nGaining a deeper understanding of magnetization dynamics\, STT and SOT switching mechanisms.\n\nDr. Richard Evans\, Associate Professor\, Developer of Vampire software\, University of York\, UK\nDr. Evans will talk about his group’s work on simulating MTJs with the atomistic spin dynamics code Vampire. He will put a particular focus on showing the capabilities of Vampire to investigate magnetization dynamics and reversal\, STT and SOT switching mechanisms in MTJs for STT-SOT-MRAM\, spin-torque nano oscillators\, and antiferromagnets. \nDr. Troels Markussen\, Manager R&D\, Synopsys QuantumATK\nDr. Markussen will show the integration of Vampire into QuantumATK NanoLab GUI\, making it easy to set up Vampire simulations with precalculated ab initio parameters\, and analyze obtained results.
URL:https://marketingeda.com/event/advancing-mram-technology-with-atomistic-spin-dynamics-simulations/
CATEGORIES:EDA,Webinar
ATTACH;FMTTYPE=image/jpeg:https://marketingeda.com/wp-content/uploads/Synopsys-May-24-2023-1.jpg
END:VEVENT
BEGIN:VEVENT
DTSTART;TZID=America/Los_Angeles:20230524T090000
DTEND;TZID=America/Los_Angeles:20230524T100000
DTSTAMP:20230504T164101Z
CREATED:20230504T164101Z
LAST-MODIFIED:20230504T164101Z
UID:6359-1684918800-1684922400@marketingeda.com
SUMMARY:DENSO discusses Verification of network relay performance using VisualSim
DESCRIPTION:Want to learn how Tier One suppliers are using network modeling and simulation in the design and optimization of network topology and gateway architecture. Then attend this Webinar by DENSO. \nEfficient in-vehicle network development through simulation combining network and ECU hardware and software elements \nTime Zone:\nJapan – 3:00 PM (In Japanese)\nAsia – 3:00 PM Korea | 2:00PM China | 11:30PM India\nEurope – 10:00 CEST\nAmericas – 09:00AM PST | 12:00PM EST
URL:https://marketingeda.com/event/denso-discusses-verification-of-network-relay-performance-using-visualsim/
CATEGORIES:EDA,IP,Webinar
ATTACH;FMTTYPE=image/jpeg:https://marketingeda.com/wp-content/uploads/Mirabilis-May-24-2023.jpg
END:VEVENT
BEGIN:VEVENT
DTSTART;TZID=America/Los_Angeles:20230524T080000
DTEND;TZID=America/Los_Angeles:20230524T100000
DTSTAMP:20230427T170718Z
CREATED:20230427T170718Z
LAST-MODIFIED:20230427T170718Z
UID:6343-1684915200-1684922400@marketingeda.com
SUMMARY:Extending RISC Processors into Flexible Accelerators using ASIP Designer
DESCRIPTION:Case Studies in Low-Power Smart Vision and Post-Quantum Cryptography Applications\n\nThe slow-down of Moore’s law and Dennard scaling triggered an increased awareness for application-specific instruction-set processors (ASIPs). These processors implement a specialized instruction-set architecture (ISA) tailored to the application domain\, often starting from a baseline such as the RISC-V ISA.  ASIPs can replace traditional fixed-function hardware accelerators\, thereby introducing software-programmability in the acceleration domain\, and thus more flexibility and agility in both the design process and the eventual product.  By maintaining a RISC-V ISA baseline\, compatibility with and reuse of existing processor ecosystem elements is facilitated. \nSynopsys ASIP Designer is the industry-leading tool to design\, implement\, program and verify application-specific instruction-set processors. Starting from a single processor specification\, designers immediately obtain an optimizing C/C++ compiler\, cycle-accurate simulator and synthesizable hardware implementation of the ASIP.  Using a unique compiler-in-the-loop™ and synthesis-in-the-loop™ methodology\, the ISA and microarchitecture can be tuned quickly to the application domain. \nThis seminar introduces you to the ASIP Designer tool-suite.  It features two case studies from popular application domains.  The first case study by Lund University shows the design exploration for a RISC-V based VLIW processor for feature extraction in smart vision systems\, using ASIP Designer. The second case study by Synopsys shows an ASIP for post-quantum cryptography. A RISC-V baseline architecture is gradually extended into an ASIP that is optimized for the Kyber encryption mechanism but accelerating also other cryptographic applications. \n  \nWho Should Attend?\nIf you are a design engineer\, algorithm developer\, software engineer\, system architect\, or design manager focusing on advanced SoCs requiring application-specific optimizations\, you won’t want to miss this event. \n\n\n\n\n\nAgenda\n\n\n\n\n\n\n\n\n\n\n\n\n\n\n\n\n\nAn Introduction to Domain-Specific Processors and ASIP Designer\n\n\nPatrick Verbist\, Sr. Product Manager\, Synopsys Belgium \nFalco Munsche\, Technical Marketing Manager\, Synopsys Germany \n08:00am – 8:50am PT \nDomain-specific processors (also referred to as Application-specific processors\, ASIP) combine hardware specialization with flexibility through software programmability. This session will introduce the concept of ASIPs and will provide an overview of Synopsys’ ASIP Designer tool-suite. \n\n\n\n\n\n\n\n\n\n\n\n\n\n\n\n\n\n\n\n\n\n\nCase study: Energy-Efficient Application-Specific Instruction Set Processor for Feature Extraction in Smart Vision Systems\n\n\nLucas Ferreira\, PhD student in the Digital ASIC Research Group in the Electrical and Information Technology (EIT) Department\, Lund University\n \n8:50am – 9:20am PT \nIn computer-vision feature extraction algorithms\, compressing the image into a sparse set of trackable keypoints\, empowers navigation-critical systems such as Simultaneous Localization and Mapping (SLAM) in autonomous robots\, and also other applications such as augmented reality and 3D reconstruction. Most of those applications are performed in battery-powered gadgets featuring in common a very stringent power-budget. Near-to-sensor computing of feature extraction algorithms allows for several design optimizations. First\, the overall on-chip memory requirements can be lessened\, and second\, the internal data movement can be minimized. This work explores the usage of an Application Specific Instruction Set Processor (ASIP)\, designed with Synopsys ASIP Designer\, optimized for performing feature extraction in a real-time and energy-efficient manner. The ASIP features a Very Long Instruction Word (VLIW) architecture comprising one RV32I RISC-V and three vector slots. The on-chip memory sub-system implements parallel multi-bank memories with near-memory data shuffling to enable single-cycle multi-pattern vector access. Oriented FAST and Rotated BRIEF (ORB) is thoroughly explored to validate the proposed architecture\, achieving a throughput of 140 Frames-Per-Second (FPS) for VGA images for one scale\, while reducing the number of memory accesses by 2 orders of magnitude as compared to other embedded general-purpose architectures. \n\n\n\n\n\n\n\n\n\n\n\n\n\n\n\n\n\n\n\n\n\nCase study: An ASIP for Post-Quantum Cryptography\n\n\nFalco Munsche\, Technical Marketing Manager\, Synopsys Germany \n9:20am –10:00am PT \nKyber\, the first standardized key encryption mechanism designed to withstand attacks with future powerful quantum computers\, is computationally very demanding due to extensive use of hashing\, for example. In this case study\, an ASIP optimized for accelerating Kyber was developed\, starting from an open-source implementation compiled and profiled on a RISC-V base model\, gradually adding architectural specializations that go beyond simple RISC-V extension mechanisms. Multiple implementation solutions and their performance-versus-cost tradeoffs were explored with fast turnaround\, using the compiler-in-the-loop and synthesis-in-the-loop optimization flows of ASIP Designer. These flows allow for iterative co-optimization of the application code and the ASIP architecture while verifying their correctness and performance at each step. \nMeet The Speakers\n\n\n\n\nPatrick Verbist \nSr. Product Manager \nSynopsys \n\n\n\n\n\n\n\n\n\nPatrick Verbist is the Product Manager for Synopsys’ ASIP Designer tools. Previously he was Business Development Manager and Field Application Engineer for the ASIP Designer tools and\, prior to the acquisition by Synopsys in 2014\, Director of Sales at Target Compiler Technologies. Before Target\, Patrick worked for 12 years as Business Development Manager for imec in Belgium and San Jose (US). He holds a Master’s degree in Electrical Engineering from KU Leuven\, Belgium. \n\n\n\n\nFalco Munsche \nTechnical Marketing Manager \nSynopsys \n\n\n\n\n\n\n\n\n\nFalco Munsche is the Technical Marketing Manager for Synopsys’ ASIP Designer tools. Previously he worked for a total of 20 years as Application Engineer and Software Engineer of ASIP Design tools for Synopsys and CoWare\, and as a Design Consultant for Synopsys. \nHe holds a Ph.D. (2002) and Dipl-Ing. degree (1995) in Electrical Engineering from RWTH Aachen University. \n\n\n\n\nLucas Ferreira \nPhD student in the Digital ASIC Research Group in the Electrical and Information Technology (EIT) Department \nLund University \n\n\n\n\n\n\n\n\n\nLucas Ferreira was born in São Paulo\, Brazil\, 1993. He received his bachelors both in Science and Technology\, and Automation and Control Engineering respectively at Federal University of ABC 2015-2017 (São Paulo). In 2019 he received his M.Sc. degree in Embedded Electronics from Lund University. \nSince May 2019\, he is working at the department of Electrical and Information Technology\, Lund University as a doctoral candidate. His main focus of research is on domain-specific processor design with focus on computer vision\, machine learning\, and autonomous drones.
URL:https://marketingeda.com/event/extending-risc-processors-into-flexible-accelerators-using-asip-designer/
CATEGORIES:EDA,IP,Webinar
ATTACH;FMTTYPE=image/jpeg:https://marketingeda.com/wp-content/uploads/Synopsys-May-24-2023.jpg
END:VEVENT
BEGIN:VEVENT
DTSTART;TZID=America/New_York:20230518T110000
DTEND;TZID=America/New_York:20230518T120000
DTSTAMP:20230515T173657Z
CREATED:20230515T173657Z
LAST-MODIFIED:20230515T173657Z
UID:6390-1684407600-1684411200@marketingeda.com
SUMMARY:Addressing Silent Data Errors for Resilient Data Centers
DESCRIPTION:Mark your calendar to join us on Thursday\, May 18 at 11 a.m. EDT for an Open Compute Project (OCP) Foundation educational webinar on Addressing Silent Data Errors for Resilient Data Centers. \nDuring the webinar\, you will learn: \n\nWhat is the magnitude of silent data errors (SDE)\nHow does SDE impact end users\nWhat is the cost of detecting SDE using traditional methods\nNovel techniques for detecting and mitigating SDE\nData center efficiencies improvement with better SDE containment\n\n  \nSpeakers: \n\nCliff Grossner\, VP Market Intelligence & Innovation\, OCP \nAshish Nadkarni\, Group Vice President and General Manager\, IDC \nRama Govindaraju\, Director of Engineering\, Google\nWalter Abramsohn\, Director of Product Marketing\, proteanTecs
URL:https://marketingeda.com/event/addressing-silent-data-errors-for-resilient-data-centers/
CATEGORIES:EDA,IP,Webinar
ATTACH;FMTTYPE=image/jpeg:https://marketingeda.com/wp-content/uploads/OCP-May-18-2023.jpg
END:VEVENT
BEGIN:VEVENT
DTSTART;TZID=America/Los_Angeles:20230518T100000
DTEND;TZID=America/Los_Angeles:20230518T103000
DTSTAMP:20230503T205714Z
CREATED:20230503T205714Z
LAST-MODIFIED:20230503T205714Z
UID:6356-1684404000-1684405800@marketingeda.com
SUMMARY:Learn How to Use Victory Process TCAD Geometric Etch Models in FinFET and Memory Applications
DESCRIPTION:When employing process simulation to generate a complex device structure\, TCAD engineers often face the task of reproducing the exact etch profile that has been observed in semiconductor fabrication. Silvaco Victory Process offers several geometric models to efficiently achieve etch geometries that accurately match microscopy images (e.g.\, transmission electron microscopy). \nIn this webinar\, we present geometric etch models in the context of FinFET and memory applications. We demonstrate techniques to realize fin shaping\, non-ideal etch profiles (bowing\, twisting)\, and self-aligned processes (multi-patterning). \nWhat You Will Learn\n\nHow to achieve accurate etch profiles as observed on microscopy images\nHow to efficiently use Silvaco Victory Process to achieve fin shapes in FinFET flows\nHow apply geometric etch modes for trenches and contact holes in memory applications (3D NAND)\nHow to use Silvaco Victory Process’s powerful and adaptable ETCH DRY and ETCH POLYLINE commands\n\n\n\n\n\n\nPresenter\n\n\n\n\nAlexander Toifl\, Development Engineer\, Silvaco TCAD Division \nSince joining Silvaco in 2021\, he has worked on etch and deposition models in Victory Process. Alexander Toifl received a doctoral degree in electrical engineering from the University of Technology Vienna (TU Wien)\, Austria\, and a M.S. degree in microelectronics and photonics from the same institution. \n\n\n\n\n\nWHO SHOULD ATTEND:\n\n\n\n\nEngineers and management looking for solutions to efficiently achieve etch profiles in a process TCAD flow.
URL:https://marketingeda.com/event/learn-how-to-use-victory-process-tcad-geometric-etch-models-in-finfet-and-memory-applications/
CATEGORIES:EDA,Webinar
ATTACH;FMTTYPE=image/jpeg:https://marketingeda.com/wp-content/uploads/Silvaco-May-18-2023.jpg
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BEGIN:VEVENT
DTSTART;TZID=America/New_York:20230517T110000
DTEND;TZID=America/New_York:20230517T120000
DTSTAMP:20230512T184315Z
CREATED:20230512T184315Z
LAST-MODIFIED:20230512T184315Z
UID:6386-1684321200-1684324800@marketingeda.com
SUMMARY:Power Integrity Issues and Solutions for Silicon Interposers
DESCRIPTION:Join us on May 17 for the latest 3D-IC webinar series\, “Power Integrity Challenges and Solutions for Interposer Design.” The discussion will focus on interposer power analysis as an isolated case and in context with the dice instantiated in a 3D-IC device. The presentation will then explore the completed multi-chip design in a system simulation. \nAbout this Webinar\nThe trend in chiplet packaging designs is increased density connections to the dies through micro-bumps or even more dense hybrid bonding. This has introduced larger current densities and variations into the power supply network than seen with a single die packaging. \nIt’s common to use an interposer as the interface between the package and the chiplets. The interposer must be able to supply power to each of the chiplets so that the system of dies functions correctly. This webinar will analyze interposers’ power integrity in the context of the system of dies they support. \nWhat You Will Learn\n\nHow to analyze the power grid of an interposer as a stand-alone die\nHow to analyze an interposer in the context of the system of dies it supports\nHow to create a macro model of the interposer that can be used for system level analysis\n\nWho Should Attend\nSemiconductor and electronics engineers involved in 3D-IC design \nSpeakers\nChris Ortiz is a senior principal application engineer at ANSYS. His interests include chip-level modeling for system-level power\, signal\, and thermal integrity. He has been in the semiconductor industry for over 20 years and received his Ph.D. in physics from the University of Notre Dame.
URL:https://marketingeda.com/event/power-integrity-issues-and-solutions-for-silicon-interposers/
CATEGORIES:EDA,Webinar
ATTACH;FMTTYPE=image/jpeg:https://marketingeda.com/wp-content/uploads/Ansys-May-17-2023.jpg
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BEGIN:VEVENT
DTSTART;TZID=America/Los_Angeles:20230516T100000
DTEND;TZID=America/Los_Angeles:20230516T110000
DTSTAMP:20230418T191148Z
CREATED:20230418T191148Z
LAST-MODIFIED:20230418T191148Z
UID:6289-1684231200-1684234800@marketingeda.com
SUMMARY:Passive Component Synthesis and Optimization for IC Designs
DESCRIPTION:Join us at this webinar to learn more about the Cadence® EMX® Designer\, our newly introduced passive component synthesis and optimization solution. In split seconds\, the EMX Designer generates very flexible DRC-clean parametric cells of passive devices\, such as inductors\, transformers\, and T-coils. Leveraging the EMX Planar 3D Solver\, the industry’s gold-standard electromagnetic modeling engine\, the EMX Designer boosts productivity and enables circuit engineers to create optimal designs.
URL:https://marketingeda.com/event/passive-component-synthesis-and-optimization-for-ic-designs/
CATEGORIES:EDA,Webinar
ATTACH;FMTTYPE=image/jpeg:https://marketingeda.com/wp-content/uploads/Cadence-May-16-2023-1.jpg
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BEGIN:VEVENT
DTSTART;TZID=America/Los_Angeles:20230511T110000
DTEND;TZID=America/Los_Angeles:20230511T120000
DTSTAMP:20230508T223036Z
CREATED:20230508T223036Z
LAST-MODIFIED:20230508T223036Z
UID:6368-1683802800-1683806400@marketingeda.com
SUMMARY:The Power of SystemVerilog's DPI
DESCRIPTION:The programming interfaces of logic simulators are largely the domain of specialists writing proprietary tools and extensions and are only vaguely in the consciousness of many design and verification engineers\, if aware at all. Yet the simplest use of such interfaces opens up a whole world of possibilities in extending what is achievable in verifying logic IP and with the potential for logic and embedded software co-development. \n\nThe Direct Programming Interface (DPI) is part of the IEEE Standard for SystemVerilog Language Reference Manual. In this part 3 of the webinar series\, we will introduce the SystemVerilog DPI and discuss the first steps of crossing from the logic domain to the software domain. We will show various working examples with memory models\, PCIe model and Linux driver co-simulation and PCIE model running over DPI. The real-world examples will be demonstrated to show just what is possible with using these basic logic interface features that are already available\, and well supported\, in the Aldec simulation tools.\n\nAgenda:\n\nIntroduction \nHistory of SystemVerilog DPI interface\nThe DPI-C interface\nAdvantages and use\nReworking of memory model in DPI-C\nReal-world use case of PCIe model and Linux driver co-simulation\nDemo of software PCIe model running over DPI\nConclusions\nQ&A\n\nWebinar Duration\n\n45 min presentation/live demo\n15 min Q&A\n\nBio: \nSimon Southwell has 35 years in Research and Development\, with experience in ASIC design\, FPGA\, and embedded software development. Now spending time contributing IP to the open-source community\, and sharing experience and knowledge through writing articles and mentoring undergraduates and junior engineers. Also currently a collaborator on the OSVVM project\, a verification methodology and VHDL library\, adding and supporting its co-simulation capabilities. Particular areas of interest include processor systems and sub-systems\, system modeling in software\, the software/hardware interface and co-simulation of logic and software. \nAmongst the many areas of experiences are original logic IP design targeting both ASIC and FPGA\, logic verification\, HPC (supercomputers)\, processor systems\, networking (802.3 and proprietary)\, embedded software\, co-simulation technology\, software modeling of SoC systems\, data compression logic\, PCIe endpoint design\, cellular (3G and 4G)\, wireless (802.11 and 802.15.4) and more. Joint or sole author on several logic IP related patents.
URL:https://marketingeda.com/event/the-power-of-systemverilogs-dpi/
CATEGORIES:EDA,Webinar
ATTACH;FMTTYPE=image/jpeg:https://marketingeda.com/wp-content/uploads/Aldec-May-11-2023.jpg
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BEGIN:VEVENT
DTSTART;TZID=America/Los_Angeles:20230510T100000
DTEND;TZID=America/Los_Angeles:20230510T110000
DTSTAMP:20230508T233346Z
CREATED:20230508T233259Z
LAST-MODIFIED:20230508T233346Z
UID:6371-1683712800-1683716400@marketingeda.com
SUMMARY:Synopsys RF / mmWave IC Design Reference Flow with TSMC N6RF and N16FFC Process Nodes
DESCRIPTION:Wireless devices are ubiquitous\, all requiring RF ICs to transmit and receive radio waves via antennas. The radio range can be a few meters for applications such as Bluetooth and WiFi to many kilometers for long range 5G\, satellite and radar applications. Today’s total RF market is growing rapidly with global RF IC sales exceeding $20B in 2022 providing tremendous technology advances and business opportunity. \nThis Synopsys webinar will discuss the capabilities and benefits of the Synopsys RF / mmWave IC Design Reference Flow\, with sub-6GHz LNA/VCO designs on TSMC N6RF (6nm) and mmWave LNA/PA designs on N16FFC (16nm) process nodes. \n\n\n\n\n\n\n\n\n\n\nSpeaker\n\n\nListed below is the industry leader scheduled to speak. \n\n\n\n\n\n\n\n\n\n\n\n\n\n\n\n\n\n\n\n\n\n\n\n\n\n\nJian Yang\n\n\nProduct Management Director\nSynopsys\, Inc. \n\n\n\n\n\n\n\n\n\n\n\nJian Yang joined Synopsys as the RFIC Product Management Director in 2021. Prior to joining Synopsys\, he worked at Keysight/Agilent/HP/EEsof developing RF simulation software. He earned his PhD degree and did post-doctoral research in RF/Microwaves before joining EEsof in 1992.
URL:https://marketingeda.com/event/synopsys-rf-mmwave-ic-design-reference-flow-with-tsmc-n6rf-and-n16ffc-process-nodes/
CATEGORIES:EDA,Webinar
ATTACH;FMTTYPE=image/jpeg:https://marketingeda.com/wp-content/uploads/Synopsys-May-10-2023.jpg
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BEGIN:VEVENT
DTSTART;TZID=America/Los_Angeles:20230504T110000
DTEND;TZID=America/Los_Angeles:20230504T120000
DTSTAMP:20230421T162609Z
CREATED:20230421T162609Z
LAST-MODIFIED:20230421T162609Z
UID:6305-1683198000-1683201600@marketingeda.com
SUMMARY:Basic Testbench for a Simple DUT
DESCRIPTION:Presenter: Espen Tallaksen\, CEO of EmLogic\nAbstract Part 1: \nFunctional simulation using an HDL testbench is the de facto method for proving functional correctness of FPGA designs. In this three-part webinar series we will present a step-by-step approach on how to architect a testbench – progressing from basic to advanced techniques. We will first use a simple DUT then go to a more complex DUT with simultaneous activities on multiple interfaces. \n\nIn part 1 of this webinar series\, we will show you how to verify a relatively simple DUT with low- to mid-quality requirements using a basic testbench without using any verification framework. We will also discuss the elements of a basic testbench infrastructure\, show you examples of how to create self-checking testbenches with verbosity and alert control\, and introduce the use of basic Bus Functional Models (BFMs) to speed up verification and debugging. \nHaving shown you these basic testbench techniques\, we will then introduce an open-source industry verification framework for VHDL designs called UVVM that you can use to verify a simple DUT. \nAgenda: \n\nState of the FPGA community for verification\nAchieving readability\, maintainability and extensibility\nThe elements of a basic testbench infrastructure\nVerbosity control and alert control\nMain testbench architectures\nBasic BFMs\nGetting started with UVVM\nUVVM for basic verification\nQ&A\n\nWebinar Duration \n\n45 min presentation/live demo\n15 min Q&A
URL:https://marketingeda.com/event/basic-testbench-for-a-simple-dut/
CATEGORIES:EDA,Webinar
ATTACH;FMTTYPE=image/jpeg:https://marketingeda.com/wp-content/uploads/Aldec-May-4-2023.jpg
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BEGIN:VEVENT
DTSTART;TZID=Asia/Jerusalem:20230502T140000
DTEND;TZID=Asia/Jerusalem:20230502T170000
DTSTAMP:20230424T174117Z
CREATED:20230424T173840Z
LAST-MODIFIED:20230424T174117Z
UID:6323-1683036000-1683046800@marketingeda.com
SUMMARY:SemIsrael Tech Webinar
DESCRIPTION:Shine Chung\nChairman\nAttopsemi Technology \n\nRevolutionary Metal I-fuse® OTP in FinFET Tech\n\nUmesh Sisodia\nCEO\nCircuitSutra \n\nTransforming Semiconductor Design Using SystemC Based Shift-left ESL Methodologies\n\nRoger Espasa\nCEO & FounderSemidynamics \n\nRISC-V\, Out-of-Order IP Core\, Vector Unit\n\nSiddharth Ravikumar\nTechnical Product Manager\, Solido IP ValidationSiemens EDA \n\nIP\, QA\, Validation\, analog\, digital\, mixed-signal\n\nMichael Seaholm\nProduct Manager for Performance Oscilloscopes and Margin TestingTektronix Inc. \n\nPCIe Gen 3 and Gen 4 testing\nLarry LapidesVP Worldwide SalesImperas Software \n\nRISC-V Verification & Software Development
URL:https://marketingeda.com/event/semisrael-tech-webinar-5/
CATEGORIES:EDA,IP,Webinar
ATTACH;FMTTYPE=image/jpeg:https://marketingeda.com/wp-content/uploads/SemIsrael-May-2-2023.jpg
END:VEVENT
BEGIN:VEVENT
DTSTART;TZID=America/Los_Angeles:20230502T100000
DTEND;TZID=America/Los_Angeles:20230502T110000
DTSTAMP:20230417T181748Z
CREATED:20230417T181748Z
LAST-MODIFIED:20230417T181748Z
UID:6279-1683021600-1683025200@marketingeda.com
SUMMARY:Design Robust IC Packages Faster Using In-Design SI/PI Analysis
DESCRIPTION:IC package design teams and characterization teams have had a “throw-it-over-the-wall” relationship for decades\, which often delays design releases by months. However\, as signal integrity (SI) and power integrity (PI) challenges evolve with multi-die heterogeneous integration\, the need to perform SI/PI analysis as part of the design flow has become a requirement to meet compressed design cycles. \nToday\, in-design analysis empowers IC package design teams to resolve problems and improve design quality long before the SI/PI teams become involved\, ultimately shaving months from the average IC package design cycle. \nThis webinar will educate IC package designers and their managers about Cadence in-design analysis\, which is now part of the market-leading Cadence IC package design technology. It will highlight a guided\, easy-to-use integrated design and analysis workflow that addresses the complexity of electrical challenges\, reduces design iterations\, and saves millions of dollars in engineering time. \n\n\n\n\n\n\n\n\n\n\n\n\nSpeakers: \nJohn Park \nProduct Management Group Director \nJohn Park is Product Management Group Director for Advanced Semiconductor Packaging at EDA industry leader Cadence Design Systems\, where he leads a team responsible for defining cross-domain solutions and methodologies for IC\, package\, and PCB co-design and analysis. His team is especially focused on developing tools and flows for chiplet-based 3D designs. He has over 40 years of experience in the EDA field and is regarded as an international expert on chiplets\, packaging\, and heterogenous integration. \nAndy Haas \nSr. Principal Product Engineer \nAndy Haas is a Product Engineer for In-Design Analysis and SI/PI Signoff at Cadence Design Systems. Andy has more than 20 years of experience in EDA product sales\, support\, architecture and management with particular focus on Signal Integrity\, Power Integrity\, and analog functional verification. He also has 10+ years of Mil-Aero systems\, PCB and custom IC specification\, design and analysis.
URL:https://marketingeda.com/event/design-robust-ic-packages-faster-using-in-design-si-pi-analysis/
CATEGORIES:EDA,Webinar
ATTACH;FMTTYPE=image/jpeg:https://marketingeda.com/wp-content/uploads/Cadence-May-2-2023.jpg
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