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BEGIN:VEVENT
DTSTART;TZID=America/Los_Angeles:20230607T110000
DTEND;TZID=America/Los_Angeles:20230607T120000
DTSTAMP:20230523T172645Z
CREATED:20230523T172645Z
LAST-MODIFIED:20230523T172645Z
UID:6430-1686135600-1686139200@marketingeda.com
SUMMARY:Xcelium: The Key to Unlocking Unmatched Mixed-Signal Performance
DESCRIPTION:Xcelium mixed-signal simulation enables teams to achieve digital simulation speeds of analog models and opens mixed-signal designs to advanced verification techniques typically applied within standard verification flows.  Built on a SystemVerilog Real Number Modeling (RNM) foundation\, Xcelium automates the signal integration of digital and RNM code to achieve digital simulation speeds for mixed-signal designs. This capability is further enhanced using the EEnet package\, which defines a specialized net type useful for passing voltage values across the design. Cadence adds randomization\, coverage\, incremental elaboration\, advanced debugging\, and other techniques to bring advanced verification to mixed-signal system designs. You can attend our webinar to learn more about how you can accelerate your mixed-signal simulations with RNM and EEnet in Xcelium. \n\nLearn about accelerating mixed-signal simulations with RNM and EEnet in Xcelium\nLearn about utilizing a full verification flow of randomization\, coverage\, incremental elaboration\, and advanced debug with mixed-signal designs\nLearn about achieving digital simulation speeds of analog models
URL:https://marketingeda.com/event/xcelium-the-key-to-unlocking-unmatched-mixed-signal-performance/
CATEGORIES:EDA,Webinar
ATTACH;FMTTYPE=image/jpeg:https://marketingeda.com/wp-content/uploads/Cadence-June-7-2023.jpg
END:VEVENT
BEGIN:VEVENT
DTSTART;TZID=America/New_York:20230601T120000
DTEND;TZID=America/New_York:20230601T130000
DTSTAMP:20230522T170521Z
CREATED:20230522T170521Z
LAST-MODIFIED:20230522T170521Z
UID:6419-1685620800-1685624400@marketingeda.com
SUMMARY:Accelerate Software Innovation Through Target-Optimized Code Generation and Virtual Prototypes
DESCRIPTION:Increasingly complex automotive systems are driving the need for new and powerful E/E architectures\, and new technology is emerging that offers a significant computational increase compared to previous generation SoCs. To deliver next-generation\, differentiated software solutions\, model-based design (MBD) workflows must be deployed to handle this new level of complexity. Code generation solutions that optimize microcontroller performance to meet the development and deployment challenges of e-mobility\, advanced control\, and signal processing are a key part of this workflow. This 30-minute Webinar will explore this workflow in which virtual prototypes can substitute the physical target for much of that traditional MBD workflow. \nThis Webinar will include: \n\n  \n\n\nAn overview of the benefits of using advanced virtual prototypes in the MBD workflow\, such as faster turn-around time\, better debug capabilities\, and maximized deployment to developers\n\n\nHighlights of the features and capabilities of support packages for specialized microcontrollers\n\n\n\nLive demonstrations for a hands-on understanding of how fully virtual workflow with virtual prototypes is applied \n\n\n\n\nA Q&A session will follow the technical presentation. \nSpeakers:\n\nKevin Brand\, Principal Engineer\, Synopsys\nKevin Brand\, a Principal R&D Engineer for Synopsys\, has worked in the virtual prototyping field for 18 years. With a strong focus on automotive\, he has concentrated on R&D in recent years\, directly enabling and deploying virtual prototyping solutions at semiconductor\, Tier 1\, and OEM companies. He holds a master’s degree in electronic engineering from Napier University\, Edinburgh\, and previously worked in the aerospace and defense domain. \n  \nDineshkumar Selvaraj\, Lead Principal Engineer\, Infineon Technologies \nDinesh Selvaraj leads virtual prototype development for the AURIX family of microcontrollers at Infineon Technologies. He has more than 18 years of ESL domain experience with a focus on development of virtual prototypes for classical pre-silicon software validation\, RTL co-simulation\, and early performance analysis and optimization using models. Prior to joining Infineon\, Dinesh worked for Intel and Tata Elxsi. He holds an electrical engineering degree from the National Institute of Technology\, Trichy. \nKelly Zhang\, Application Engineer\, MathWorks \nAs an Application Engineer at MathWorks\, Kelly Zhang focuses on model-based design workflows\, Simulink use\, control system design\, code generation\, and verification and validation tools. She holds a bachelor’s and master’s degree in aerospace engineering from the University of Toronto as well as a master’s degree in mechanical engineering with a focus on control and robotic systems from Carnegie Mellon University.
URL:https://marketingeda.com/event/accelerate-software-innovation-through-target-optimized-code-generation-and-virtual-prototypes/
CATEGORIES:EDA,Webinar
ATTACH;FMTTYPE=image/jpeg:https://marketingeda.com/wp-content/uploads/Synopsys-June-1-2023.jpg
END:VEVENT
BEGIN:VEVENT
DTSTART;TZID=America/Los_Angeles:20230601T110000
DTEND;TZID=America/Los_Angeles:20230601T120000
DTSTAMP:20230421T164256Z
CREATED:20230421T164256Z
LAST-MODIFIED:20230421T164256Z
UID:6308-1685617200-1685620800@marketingeda.com
SUMMARY:Advanced Testbench for a Simple DUT
DESCRIPTION:Abstract: \nFunctional simulation using an HDL testbench is the de facto method for proving functional correctness of FPGA designs. In this three-part webinar series\, we will present a step-by-step approach on how to architect a testbench – progressing from basic to advanced techniques. We will first use a simple DUT then go to a more complex DUT with simultaneous activities on multiple interfaces. \nIn part 2 of this webinar series\, we will show you how to verify a relatively simple DUT with high quality requirements using an advanced testbench without using any verification framework. We will also discuss the elements of an advanced testbench infrastructure to verify our simple DUT more efficiently\, check and prove that we have indeed verified our simple DUT more thoroughly\, start to use advanced Bus Functional Models (BFMs) that allow simpler and more advanced interface control\, and introduce functional coverage. \nHaving shown you these more advanced testbench techniques\, we will continue to show how UVVM can be used to implement them in the simplest ways possible and with a focus on readability\, maintainability\, and extensibility. \nAgenda:\nWhat is required when verifying for higher quality?\nThe elements of an advanced testbench infrastructure\nAdvanced BFMs\nBFM vs Protocol Checkers\nBFM limitations\nAdvanced randomization\nSpecification Coverage\, aka Requirements Coverage\nIntroducing functional coverage\nUVVM advanced BFMs\nUVVM for high quality verification\nQ&A \nWebinar Duration\n45 min presentation/live demo\n15 min Q&A \nPresenter Bio: \nSimon Southwell has 35 years in Research and Development\, with experience in ASIC design\, FPGA\, and embedded software development. \nEspen Tallaksen\, CEO of EmLogic \nEspen is also the author and architect of UVVM and founder of previous Bitvis. \nHe has a strong interest in methodology cultivation and pragmatic efficiency and quality improvement\, and he has given many presentations at various international conferences with great feedback. He has also given courses on FPGA Design and Verification in three different continents.
URL:https://marketingeda.com/event/advanced-testbench-for-a-simple-dut/
CATEGORIES:EDA,IP,Webinar
ATTACH;FMTTYPE=image/jpeg:https://marketingeda.com/wp-content/uploads/Aldec-June-1-2023.jpg
END:VEVENT
BEGIN:VEVENT
DTSTART;TZID=America/Los_Angeles:20230525T090000
DTEND;TZID=America/Los_Angeles:20230525T100000
DTSTAMP:20230522T165126Z
CREATED:20230516T000921Z
LAST-MODIFIED:20230522T165126Z
UID:6400-1685005200-1685008800@marketingeda.com
SUMMARY:Don’t Take the Risk\, Formally Verify Your RISC-V Cores
DESCRIPTION:Synopsys Webinar | Thursday\, May 25\, 2023 | 9:00 a.m. PT \n\n\n\n\n\n\n\n\n\n\n\n\n\nAccording to a recent Semico Research report\, the RISC-V Core IP market is expected to grow at a 34.9% CAGR through year 2027. With increasing popularity\, it is of utmost importance that the RISC-V Core IPs are secure and bug free. ​ \nIn this joint Synopsys webinar with SyoSil\, will discuss how to use formal verification to ensure functional correctness and security of RISC-V Cores. We will cover the high-level formal verification goals and example tasks so attendees can obtain a comprehensive view of the many facets of RISC-V Core verification using formal technologies. We will explore a specific case study that uses the so-called ‘S2QED’ methodology to verify a scalar five-stage RISC-V Core. We will also show a demo for this case study using Synopsys VC Formal. ​ \nThe attendees will walk away with a comprehensive understanding of the formal verification requirements for RISC-V Cores to ensure functionality and security\, as well as specific examples of using formal property verification to find intra- and inter-instruction design bugs. ​ \n\n\n\n\n\n\n\n\n\n\nSpeakers\n\n\nListed below are the industry leaders scheduled to speak. \n\n\n\n\n\n\n\n\n\n\n\n\n\n\n\n\n\n\n\n\n\n\n\n\n\n\nSiddartha Papineni\n\n\nSr Staff Application Engineer\nSynopsys \n\n\n\n\n\n\n\n\n\n\n\nSid Papineni is a Sr. Staff Applications Engineer at Synopsys and works on formal verification consulting services and Synopsys VC Formal SEQ\, DPV\, and product engineering activities. Sid has 11+ years of experience in the formal verification domain\, focused mainly on formal property verification and datapath validation methodologies. \n\n\n\n\n\n\n\n\n\n\n\n\n\n\n\n\n\n\n\n\n\n\n\n\n\n\n\n\n\n\n\nFrederik Möllerström Lauridsen\n\n\nVerification Engineer\nSyoSil \n\n\n\n\n\n\n\n\n\n\n\nFrederik Möllerström Lauridsen is a verification engineer at SyoSil. His technical competences and interests lie within both formal verification and SV/UVM based constrained random verification. Frederik holds a PhD degree in mathematics and computer science and a MSc degree in logic from the University of Amsterdam\, and a BSc in Mathematics from the University of Copenhagen.
URL:https://marketingeda.com/event/dont-take-the-risk-formally-verify-your-risc-v-cores/
CATEGORIES:EDA,Webinar
ATTACH;FMTTYPE=image/jpeg:https://marketingeda.com/wp-content/uploads/Synopsys-May-25-2023.jpg
END:VEVENT
BEGIN:VEVENT
DTSTART;TZID=Asia/Kolkata:20230524T100000
DTEND;TZID=Asia/Kolkata:20230524T104500
DTSTAMP:20230516T025644Z
CREATED:20230515T235833Z
LAST-MODIFIED:20230516T025644Z
UID:6397-1684922400-1684925100@marketingeda.com
SUMMARY:Accelerate Coverage Closure and Debug with Synopsys AI-Driven Verification Solutions
DESCRIPTION:Synopsys Webinar | Wednesday\, May 24\, 2023 | 10:00 – 10:45 a.m. IST \n\n\n\n\n\n\n\n\n\n\n\n\nEngineering resources are getting stretched thinner and thinner as design complexity increases. Automation is a significant driver to help engineers overcome resource constraints and meet critical time-to-market windows. Two of the top three challenges cited by the engineering community in a recent survey are in the areas of coverage closure and system-level debug. How do we efficiently and accurately understand and reach coverage closure and how do we accelerate and maximize the debug process? These challenges can be addressed with the latest Synopsys AI-Driven debug automation and coverage closure technologies. \nIn this webinar\, we’ll discuss Synopsys Verdi Regression Debug Automation (RDA)\, the ground-breaking AI-driven debug technology that includes the necessary predictive analysis to automate the manual and error-prone process of finding the root cause(s) of failures in the design-under-test (DUT) and testbench. \nWe’ll also explore the latest Synopsys simulation technologies – Verification Space Optimization (VSO.ai) and VCS Intelligent Coverage Optimization (ICO). These AI-driven technologies help accelerate and improve coverage\, expose more bugs\, and reduce regression turnaround time. \n\n\n\n\n\n\n\n\n\nSpeaker\n\n\nListed below is the industry leader scheduled to speak. \n\n\n\n\n\n\n\n\n\n\n\n\n\n\n\n\n\n\n\n\n\n\n\n\n\n\nTaruna Reddy\n\n\nProduct Marketing Manager\, Staff \nSynopsys \n\n\n\n\n\n\n\n\n\n\n\n\nTaruna Reddy is a Staff Product Manager in the EDA Group at Synopsys. Taruna has 18 years of experience in EDA and functional verification. Prior to joining Synopsys\, Taruna held field applications and verification engineering positions at Mentor Graphics\, Verilab and Xtreme-EDA. She holds a MSEE from Clemson University and Bachelor of Technology from India.
URL:https://marketingeda.com/event/accelerate-coverage-closure-and-debug-with-synopsys-ai-driven-verification-solutions/
CATEGORIES:EDA,Webinar
ATTACH;FMTTYPE=image/jpeg:https://marketingeda.com/wp-content/uploads/Synopsys-May-24-2023-2.jpg
END:VEVENT
BEGIN:VEVENT
DTSTART;TZID=America/Los_Angeles:20230524T090000
DTEND;TZID=America/Los_Angeles:20230525T120000
DTSTAMP:20230515T234754Z
CREATED:20230515T234719Z
LAST-MODIFIED:20230515T234754Z
UID:6394-1684918800-1685016000@marketingeda.com
SUMMARY:Requirements for Multi-Die System Success
DESCRIPTION:Wednesday\, May 24\, 2023 and Thursday\, May 25\, 2023  \n\n\n\n\n\n\n\n\n\n\nThe industry is moving to multi-die systems to benefit from the greater compute performance\, increased functionality\, and new levels of flexibility. Challenges for multi-die systems are exacerbated and require greater focus on a number of requirements such as early partitioning and thermal planning\, die/package co-design\, secure and robust die-to-die connectivity\, reliability and health\, as well as verification and system validation. Attend this webinar series to find out about some of the essential requirements that can help you overcome multi-die system challenges and make your move to multi-die systems successful. \n\n\nMay 24th presentation topics will include: \n\n9:00 a.m. PDT: Multi-Die System Trends\, Challenges and Requirements\n10:00 a.m. PDT: Benefits of Early Architecture Design for Multi-Die Systems\n11:00 a.m. PDT: Innovations in Multi-Die System Co-Design and System Analysis\n\nMay 25th presentation topics will include: \n\n9:00 a.m. PDT: Successful Connectivity of Heterogeneous Dies with UCIe IP\n10:00 a.m. PDT: Identifying and Overcoming Multi-Die System Verification Challenges\n11:00 a.m. PDT: Optimizing Multi-Die System Health from Die to Package to In-Field\n\n  \nRegister once for access to all the webinars.
URL:https://marketingeda.com/event/requirements-for-multi-die-system-success/
CATEGORIES:EDA,IP,Webinar
ATTACH;FMTTYPE=image/jpeg:https://marketingeda.com/wp-content/uploads/Synopsys-May-24-25-2023.jpg
END:VEVENT
BEGIN:VEVENT
DTSTART;TZID=America/Los_Angeles:20230524T090000
DTEND;TZID=America/Los_Angeles:20230524T100000
DTSTAMP:20230510T164527Z
CREATED:20230510T164527Z
LAST-MODIFIED:20230510T164527Z
UID:6383-1684918800-1684922400@marketingeda.com
SUMMARY:Advancing MRAM Technology with Atomistic Spin Dynamics Simulations
DESCRIPTION:In this event\, experts from Martin-Luther-Universitat Halle Wittenberg\, University of York\, and Synopsys QuantumATK will present how to use ab initio DFT modeling and atomistic spin dynamics simulations of MTJs to guide and accelerate the technological development of magnetic memory such as STT and SOT-MRAM. \n\nInvestigating the potential of novel magnetic tunnel junction (MTJ) materials and concepts for improved magnetic memory performance.\nGenerating realistic MTJ structures with Machine-Learned Force Fields.\nEvaluating the performance based on calculated MTJ spintronic properties\, such as tunnel magnetoresistance (TMR)\, current rectification\, spin-transfer and spin-orbit torques (STT and SOT)\, Gilbert damping\, Curie temp.\, and thermal stability.\nGaining a deeper understanding of magnetization dynamics\, STT and SOT switching mechanisms.\n\nDr. Richard Evans\, Associate Professor\, Developer of Vampire software\, University of York\, UK\nDr. Evans will talk about his group’s work on simulating MTJs with the atomistic spin dynamics code Vampire. He will put a particular focus on showing the capabilities of Vampire to investigate magnetization dynamics and reversal\, STT and SOT switching mechanisms in MTJs for STT-SOT-MRAM\, spin-torque nano oscillators\, and antiferromagnets. \nDr. Troels Markussen\, Manager R&D\, Synopsys QuantumATK\nDr. Markussen will show the integration of Vampire into QuantumATK NanoLab GUI\, making it easy to set up Vampire simulations with precalculated ab initio parameters\, and analyze obtained results.
URL:https://marketingeda.com/event/advancing-mram-technology-with-atomistic-spin-dynamics-simulations/
CATEGORIES:EDA,Webinar
ATTACH;FMTTYPE=image/jpeg:https://marketingeda.com/wp-content/uploads/Synopsys-May-24-2023-1.jpg
END:VEVENT
BEGIN:VEVENT
DTSTART;TZID=America/Los_Angeles:20230524T090000
DTEND;TZID=America/Los_Angeles:20230524T100000
DTSTAMP:20230504T164101Z
CREATED:20230504T164101Z
LAST-MODIFIED:20230504T164101Z
UID:6359-1684918800-1684922400@marketingeda.com
SUMMARY:DENSO discusses Verification of network relay performance using VisualSim
DESCRIPTION:Want to learn how Tier One suppliers are using network modeling and simulation in the design and optimization of network topology and gateway architecture. Then attend this Webinar by DENSO. \nEfficient in-vehicle network development through simulation combining network and ECU hardware and software elements \nTime Zone:\nJapan – 3:00 PM (In Japanese)\nAsia – 3:00 PM Korea | 2:00PM China | 11:30PM India\nEurope – 10:00 CEST\nAmericas – 09:00AM PST | 12:00PM EST
URL:https://marketingeda.com/event/denso-discusses-verification-of-network-relay-performance-using-visualsim/
CATEGORIES:EDA,IP,Webinar
ATTACH;FMTTYPE=image/jpeg:https://marketingeda.com/wp-content/uploads/Mirabilis-May-24-2023.jpg
END:VEVENT
BEGIN:VEVENT
DTSTART;TZID=America/Los_Angeles:20230524T080000
DTEND;TZID=America/Los_Angeles:20230524T100000
DTSTAMP:20230427T170718Z
CREATED:20230427T170718Z
LAST-MODIFIED:20230427T170718Z
UID:6343-1684915200-1684922400@marketingeda.com
SUMMARY:Extending RISC Processors into Flexible Accelerators using ASIP Designer
DESCRIPTION:Case Studies in Low-Power Smart Vision and Post-Quantum Cryptography Applications\n\nThe slow-down of Moore’s law and Dennard scaling triggered an increased awareness for application-specific instruction-set processors (ASIPs). These processors implement a specialized instruction-set architecture (ISA) tailored to the application domain\, often starting from a baseline such as the RISC-V ISA.  ASIPs can replace traditional fixed-function hardware accelerators\, thereby introducing software-programmability in the acceleration domain\, and thus more flexibility and agility in both the design process and the eventual product.  By maintaining a RISC-V ISA baseline\, compatibility with and reuse of existing processor ecosystem elements is facilitated. \nSynopsys ASIP Designer is the industry-leading tool to design\, implement\, program and verify application-specific instruction-set processors. Starting from a single processor specification\, designers immediately obtain an optimizing C/C++ compiler\, cycle-accurate simulator and synthesizable hardware implementation of the ASIP.  Using a unique compiler-in-the-loop™ and synthesis-in-the-loop™ methodology\, the ISA and microarchitecture can be tuned quickly to the application domain. \nThis seminar introduces you to the ASIP Designer tool-suite.  It features two case studies from popular application domains.  The first case study by Lund University shows the design exploration for a RISC-V based VLIW processor for feature extraction in smart vision systems\, using ASIP Designer. The second case study by Synopsys shows an ASIP for post-quantum cryptography. A RISC-V baseline architecture is gradually extended into an ASIP that is optimized for the Kyber encryption mechanism but accelerating also other cryptographic applications. \n  \nWho Should Attend?\nIf you are a design engineer\, algorithm developer\, software engineer\, system architect\, or design manager focusing on advanced SoCs requiring application-specific optimizations\, you won’t want to miss this event. \n\n\n\n\n\nAgenda\n\n\n\n\n\n\n\n\n\n\n\n\n\n\n\n\n\nAn Introduction to Domain-Specific Processors and ASIP Designer\n\n\nPatrick Verbist\, Sr. Product Manager\, Synopsys Belgium \nFalco Munsche\, Technical Marketing Manager\, Synopsys Germany \n08:00am – 8:50am PT \nDomain-specific processors (also referred to as Application-specific processors\, ASIP) combine hardware specialization with flexibility through software programmability. This session will introduce the concept of ASIPs and will provide an overview of Synopsys’ ASIP Designer tool-suite. \n\n\n\n\n\n\n\n\n\n\n\n\n\n\n\n\n\n\n\n\n\n\nCase study: Energy-Efficient Application-Specific Instruction Set Processor for Feature Extraction in Smart Vision Systems\n\n\nLucas Ferreira\, PhD student in the Digital ASIC Research Group in the Electrical and Information Technology (EIT) Department\, Lund University\n \n8:50am – 9:20am PT \nIn computer-vision feature extraction algorithms\, compressing the image into a sparse set of trackable keypoints\, empowers navigation-critical systems such as Simultaneous Localization and Mapping (SLAM) in autonomous robots\, and also other applications such as augmented reality and 3D reconstruction. Most of those applications are performed in battery-powered gadgets featuring in common a very stringent power-budget. Near-to-sensor computing of feature extraction algorithms allows for several design optimizations. First\, the overall on-chip memory requirements can be lessened\, and second\, the internal data movement can be minimized. This work explores the usage of an Application Specific Instruction Set Processor (ASIP)\, designed with Synopsys ASIP Designer\, optimized for performing feature extraction in a real-time and energy-efficient manner. The ASIP features a Very Long Instruction Word (VLIW) architecture comprising one RV32I RISC-V and three vector slots. The on-chip memory sub-system implements parallel multi-bank memories with near-memory data shuffling to enable single-cycle multi-pattern vector access. Oriented FAST and Rotated BRIEF (ORB) is thoroughly explored to validate the proposed architecture\, achieving a throughput of 140 Frames-Per-Second (FPS) for VGA images for one scale\, while reducing the number of memory accesses by 2 orders of magnitude as compared to other embedded general-purpose architectures. \n\n\n\n\n\n\n\n\n\n\n\n\n\n\n\n\n\n\n\n\n\nCase study: An ASIP for Post-Quantum Cryptography\n\n\nFalco Munsche\, Technical Marketing Manager\, Synopsys Germany \n9:20am –10:00am PT \nKyber\, the first standardized key encryption mechanism designed to withstand attacks with future powerful quantum computers\, is computationally very demanding due to extensive use of hashing\, for example. In this case study\, an ASIP optimized for accelerating Kyber was developed\, starting from an open-source implementation compiled and profiled on a RISC-V base model\, gradually adding architectural specializations that go beyond simple RISC-V extension mechanisms. Multiple implementation solutions and their performance-versus-cost tradeoffs were explored with fast turnaround\, using the compiler-in-the-loop and synthesis-in-the-loop optimization flows of ASIP Designer. These flows allow for iterative co-optimization of the application code and the ASIP architecture while verifying their correctness and performance at each step. \nMeet The Speakers\n\n\n\n\nPatrick Verbist \nSr. Product Manager \nSynopsys \n\n\n\n\n\n\n\n\n\nPatrick Verbist is the Product Manager for Synopsys’ ASIP Designer tools. Previously he was Business Development Manager and Field Application Engineer for the ASIP Designer tools and\, prior to the acquisition by Synopsys in 2014\, Director of Sales at Target Compiler Technologies. Before Target\, Patrick worked for 12 years as Business Development Manager for imec in Belgium and San Jose (US). He holds a Master’s degree in Electrical Engineering from KU Leuven\, Belgium. \n\n\n\n\nFalco Munsche \nTechnical Marketing Manager \nSynopsys \n\n\n\n\n\n\n\n\n\nFalco Munsche is the Technical Marketing Manager for Synopsys’ ASIP Designer tools. Previously he worked for a total of 20 years as Application Engineer and Software Engineer of ASIP Design tools for Synopsys and CoWare\, and as a Design Consultant for Synopsys. \nHe holds a Ph.D. (2002) and Dipl-Ing. degree (1995) in Electrical Engineering from RWTH Aachen University. \n\n\n\n\nLucas Ferreira \nPhD student in the Digital ASIC Research Group in the Electrical and Information Technology (EIT) Department \nLund University \n\n\n\n\n\n\n\n\n\nLucas Ferreira was born in São Paulo\, Brazil\, 1993. He received his bachelors both in Science and Technology\, and Automation and Control Engineering respectively at Federal University of ABC 2015-2017 (São Paulo). In 2019 he received his M.Sc. degree in Embedded Electronics from Lund University. \nSince May 2019\, he is working at the department of Electrical and Information Technology\, Lund University as a doctoral candidate. His main focus of research is on domain-specific processor design with focus on computer vision\, machine learning\, and autonomous drones.
URL:https://marketingeda.com/event/extending-risc-processors-into-flexible-accelerators-using-asip-designer/
CATEGORIES:EDA,IP,Webinar
ATTACH;FMTTYPE=image/jpeg:https://marketingeda.com/wp-content/uploads/Synopsys-May-24-2023.jpg
END:VEVENT
BEGIN:VEVENT
DTSTART;TZID=America/New_York:20230518T110000
DTEND;TZID=America/New_York:20230518T120000
DTSTAMP:20230515T173657Z
CREATED:20230515T173657Z
LAST-MODIFIED:20230515T173657Z
UID:6390-1684407600-1684411200@marketingeda.com
SUMMARY:Addressing Silent Data Errors for Resilient Data Centers
DESCRIPTION:Mark your calendar to join us on Thursday\, May 18 at 11 a.m. EDT for an Open Compute Project (OCP) Foundation educational webinar on Addressing Silent Data Errors for Resilient Data Centers. \nDuring the webinar\, you will learn: \n\nWhat is the magnitude of silent data errors (SDE)\nHow does SDE impact end users\nWhat is the cost of detecting SDE using traditional methods\nNovel techniques for detecting and mitigating SDE\nData center efficiencies improvement with better SDE containment\n\n  \nSpeakers: \n\nCliff Grossner\, VP Market Intelligence & Innovation\, OCP \nAshish Nadkarni\, Group Vice President and General Manager\, IDC \nRama Govindaraju\, Director of Engineering\, Google\nWalter Abramsohn\, Director of Product Marketing\, proteanTecs
URL:https://marketingeda.com/event/addressing-silent-data-errors-for-resilient-data-centers/
CATEGORIES:EDA,IP,Webinar
ATTACH;FMTTYPE=image/jpeg:https://marketingeda.com/wp-content/uploads/OCP-May-18-2023.jpg
END:VEVENT
BEGIN:VEVENT
DTSTART;TZID=America/Los_Angeles:20230518T100000
DTEND;TZID=America/Los_Angeles:20230518T103000
DTSTAMP:20230503T205714Z
CREATED:20230503T205714Z
LAST-MODIFIED:20230503T205714Z
UID:6356-1684404000-1684405800@marketingeda.com
SUMMARY:Learn How to Use Victory Process TCAD Geometric Etch Models in FinFET and Memory Applications
DESCRIPTION:When employing process simulation to generate a complex device structure\, TCAD engineers often face the task of reproducing the exact etch profile that has been observed in semiconductor fabrication. Silvaco Victory Process offers several geometric models to efficiently achieve etch geometries that accurately match microscopy images (e.g.\, transmission electron microscopy). \nIn this webinar\, we present geometric etch models in the context of FinFET and memory applications. We demonstrate techniques to realize fin shaping\, non-ideal etch profiles (bowing\, twisting)\, and self-aligned processes (multi-patterning). \nWhat You Will Learn\n\nHow to achieve accurate etch profiles as observed on microscopy images\nHow to efficiently use Silvaco Victory Process to achieve fin shapes in FinFET flows\nHow apply geometric etch modes for trenches and contact holes in memory applications (3D NAND)\nHow to use Silvaco Victory Process’s powerful and adaptable ETCH DRY and ETCH POLYLINE commands\n\n\n\n\n\n\nPresenter\n\n\n\n\nAlexander Toifl\, Development Engineer\, Silvaco TCAD Division \nSince joining Silvaco in 2021\, he has worked on etch and deposition models in Victory Process. Alexander Toifl received a doctoral degree in electrical engineering from the University of Technology Vienna (TU Wien)\, Austria\, and a M.S. degree in microelectronics and photonics from the same institution. \n\n\n\n\n\nWHO SHOULD ATTEND:\n\n\n\n\nEngineers and management looking for solutions to efficiently achieve etch profiles in a process TCAD flow.
URL:https://marketingeda.com/event/learn-how-to-use-victory-process-tcad-geometric-etch-models-in-finfet-and-memory-applications/
CATEGORIES:EDA,Webinar
ATTACH;FMTTYPE=image/jpeg:https://marketingeda.com/wp-content/uploads/Silvaco-May-18-2023.jpg
END:VEVENT
BEGIN:VEVENT
DTSTART;TZID=America/New_York:20230517T110000
DTEND;TZID=America/New_York:20230517T120000
DTSTAMP:20230512T184315Z
CREATED:20230512T184315Z
LAST-MODIFIED:20230512T184315Z
UID:6386-1684321200-1684324800@marketingeda.com
SUMMARY:Power Integrity Issues and Solutions for Silicon Interposers
DESCRIPTION:Join us on May 17 for the latest 3D-IC webinar series\, “Power Integrity Challenges and Solutions for Interposer Design.” The discussion will focus on interposer power analysis as an isolated case and in context with the dice instantiated in a 3D-IC device. The presentation will then explore the completed multi-chip design in a system simulation. \nAbout this Webinar\nThe trend in chiplet packaging designs is increased density connections to the dies through micro-bumps or even more dense hybrid bonding. This has introduced larger current densities and variations into the power supply network than seen with a single die packaging. \nIt’s common to use an interposer as the interface between the package and the chiplets. The interposer must be able to supply power to each of the chiplets so that the system of dies functions correctly. This webinar will analyze interposers’ power integrity in the context of the system of dies they support. \nWhat You Will Learn\n\nHow to analyze the power grid of an interposer as a stand-alone die\nHow to analyze an interposer in the context of the system of dies it supports\nHow to create a macro model of the interposer that can be used for system level analysis\n\nWho Should Attend\nSemiconductor and electronics engineers involved in 3D-IC design \nSpeakers\nChris Ortiz is a senior principal application engineer at ANSYS. His interests include chip-level modeling for system-level power\, signal\, and thermal integrity. He has been in the semiconductor industry for over 20 years and received his Ph.D. in physics from the University of Notre Dame.
URL:https://marketingeda.com/event/power-integrity-issues-and-solutions-for-silicon-interposers/
CATEGORIES:EDA,Webinar
ATTACH;FMTTYPE=image/jpeg:https://marketingeda.com/wp-content/uploads/Ansys-May-17-2023.jpg
END:VEVENT
BEGIN:VEVENT
DTSTART;TZID=America/Los_Angeles:20230516T100000
DTEND;TZID=America/Los_Angeles:20230516T110000
DTSTAMP:20230418T191148Z
CREATED:20230418T191148Z
LAST-MODIFIED:20230418T191148Z
UID:6289-1684231200-1684234800@marketingeda.com
SUMMARY:Passive Component Synthesis and Optimization for IC Designs
DESCRIPTION:Join us at this webinar to learn more about the Cadence® EMX® Designer\, our newly introduced passive component synthesis and optimization solution. In split seconds\, the EMX Designer generates very flexible DRC-clean parametric cells of passive devices\, such as inductors\, transformers\, and T-coils. Leveraging the EMX Planar 3D Solver\, the industry’s gold-standard electromagnetic modeling engine\, the EMX Designer boosts productivity and enables circuit engineers to create optimal designs.
URL:https://marketingeda.com/event/passive-component-synthesis-and-optimization-for-ic-designs/
CATEGORIES:EDA,Webinar
ATTACH;FMTTYPE=image/jpeg:https://marketingeda.com/wp-content/uploads/Cadence-May-16-2023-1.jpg
END:VEVENT
BEGIN:VEVENT
DTSTART;TZID=America/Los_Angeles:20230511T110000
DTEND;TZID=America/Los_Angeles:20230511T120000
DTSTAMP:20230508T223036Z
CREATED:20230508T223036Z
LAST-MODIFIED:20230508T223036Z
UID:6368-1683802800-1683806400@marketingeda.com
SUMMARY:The Power of SystemVerilog's DPI
DESCRIPTION:The programming interfaces of logic simulators are largely the domain of specialists writing proprietary tools and extensions and are only vaguely in the consciousness of many design and verification engineers\, if aware at all. Yet the simplest use of such interfaces opens up a whole world of possibilities in extending what is achievable in verifying logic IP and with the potential for logic and embedded software co-development. \n\nThe Direct Programming Interface (DPI) is part of the IEEE Standard for SystemVerilog Language Reference Manual. In this part 3 of the webinar series\, we will introduce the SystemVerilog DPI and discuss the first steps of crossing from the logic domain to the software domain. We will show various working examples with memory models\, PCIe model and Linux driver co-simulation and PCIE model running over DPI. The real-world examples will be demonstrated to show just what is possible with using these basic logic interface features that are already available\, and well supported\, in the Aldec simulation tools.\n\nAgenda:\n\nIntroduction \nHistory of SystemVerilog DPI interface\nThe DPI-C interface\nAdvantages and use\nReworking of memory model in DPI-C\nReal-world use case of PCIe model and Linux driver co-simulation\nDemo of software PCIe model running over DPI\nConclusions\nQ&A\n\nWebinar Duration\n\n45 min presentation/live demo\n15 min Q&A\n\nBio: \nSimon Southwell has 35 years in Research and Development\, with experience in ASIC design\, FPGA\, and embedded software development. Now spending time contributing IP to the open-source community\, and sharing experience and knowledge through writing articles and mentoring undergraduates and junior engineers. Also currently a collaborator on the OSVVM project\, a verification methodology and VHDL library\, adding and supporting its co-simulation capabilities. Particular areas of interest include processor systems and sub-systems\, system modeling in software\, the software/hardware interface and co-simulation of logic and software. \nAmongst the many areas of experiences are original logic IP design targeting both ASIC and FPGA\, logic verification\, HPC (supercomputers)\, processor systems\, networking (802.3 and proprietary)\, embedded software\, co-simulation technology\, software modeling of SoC systems\, data compression logic\, PCIe endpoint design\, cellular (3G and 4G)\, wireless (802.11 and 802.15.4) and more. Joint or sole author on several logic IP related patents.
URL:https://marketingeda.com/event/the-power-of-systemverilogs-dpi/
CATEGORIES:EDA,Webinar
ATTACH;FMTTYPE=image/jpeg:https://marketingeda.com/wp-content/uploads/Aldec-May-11-2023.jpg
END:VEVENT
BEGIN:VEVENT
DTSTART;TZID=America/Los_Angeles:20230510T100000
DTEND;TZID=America/Los_Angeles:20230510T110000
DTSTAMP:20230508T233346Z
CREATED:20230508T233259Z
LAST-MODIFIED:20230508T233346Z
UID:6371-1683712800-1683716400@marketingeda.com
SUMMARY:Synopsys RF / mmWave IC Design Reference Flow with TSMC N6RF and N16FFC Process Nodes
DESCRIPTION:Wireless devices are ubiquitous\, all requiring RF ICs to transmit and receive radio waves via antennas. The radio range can be a few meters for applications such as Bluetooth and WiFi to many kilometers for long range 5G\, satellite and radar applications. Today’s total RF market is growing rapidly with global RF IC sales exceeding $20B in 2022 providing tremendous technology advances and business opportunity. \nThis Synopsys webinar will discuss the capabilities and benefits of the Synopsys RF / mmWave IC Design Reference Flow\, with sub-6GHz LNA/VCO designs on TSMC N6RF (6nm) and mmWave LNA/PA designs on N16FFC (16nm) process nodes. \n\n\n\n\n\n\n\n\n\n\nSpeaker\n\n\nListed below is the industry leader scheduled to speak. \n\n\n\n\n\n\n\n\n\n\n\n\n\n\n\n\n\n\n\n\n\n\n\n\n\n\nJian Yang\n\n\nProduct Management Director\nSynopsys\, Inc. \n\n\n\n\n\n\n\n\n\n\n\nJian Yang joined Synopsys as the RFIC Product Management Director in 2021. Prior to joining Synopsys\, he worked at Keysight/Agilent/HP/EEsof developing RF simulation software. He earned his PhD degree and did post-doctoral research in RF/Microwaves before joining EEsof in 1992.
URL:https://marketingeda.com/event/synopsys-rf-mmwave-ic-design-reference-flow-with-tsmc-n6rf-and-n16ffc-process-nodes/
CATEGORIES:EDA,Webinar
ATTACH;FMTTYPE=image/jpeg:https://marketingeda.com/wp-content/uploads/Synopsys-May-10-2023.jpg
END:VEVENT
BEGIN:VEVENT
DTSTART;TZID=America/Los_Angeles:20230504T110000
DTEND;TZID=America/Los_Angeles:20230504T120000
DTSTAMP:20230421T162609Z
CREATED:20230421T162609Z
LAST-MODIFIED:20230421T162609Z
UID:6305-1683198000-1683201600@marketingeda.com
SUMMARY:Basic Testbench for a Simple DUT
DESCRIPTION:Presenter: Espen Tallaksen\, CEO of EmLogic\nAbstract Part 1: \nFunctional simulation using an HDL testbench is the de facto method for proving functional correctness of FPGA designs. In this three-part webinar series we will present a step-by-step approach on how to architect a testbench – progressing from basic to advanced techniques. We will first use a simple DUT then go to a more complex DUT with simultaneous activities on multiple interfaces. \n\nIn part 1 of this webinar series\, we will show you how to verify a relatively simple DUT with low- to mid-quality requirements using a basic testbench without using any verification framework. We will also discuss the elements of a basic testbench infrastructure\, show you examples of how to create self-checking testbenches with verbosity and alert control\, and introduce the use of basic Bus Functional Models (BFMs) to speed up verification and debugging. \nHaving shown you these basic testbench techniques\, we will then introduce an open-source industry verification framework for VHDL designs called UVVM that you can use to verify a simple DUT. \nAgenda: \n\nState of the FPGA community for verification\nAchieving readability\, maintainability and extensibility\nThe elements of a basic testbench infrastructure\nVerbosity control and alert control\nMain testbench architectures\nBasic BFMs\nGetting started with UVVM\nUVVM for basic verification\nQ&A\n\nWebinar Duration \n\n45 min presentation/live demo\n15 min Q&A
URL:https://marketingeda.com/event/basic-testbench-for-a-simple-dut/
CATEGORIES:EDA,Webinar
ATTACH;FMTTYPE=image/jpeg:https://marketingeda.com/wp-content/uploads/Aldec-May-4-2023.jpg
END:VEVENT
BEGIN:VEVENT
DTSTART;TZID=Asia/Jerusalem:20230502T140000
DTEND;TZID=Asia/Jerusalem:20230502T170000
DTSTAMP:20230424T174117Z
CREATED:20230424T173840Z
LAST-MODIFIED:20230424T174117Z
UID:6323-1683036000-1683046800@marketingeda.com
SUMMARY:SemIsrael Tech Webinar
DESCRIPTION:Shine Chung\nChairman\nAttopsemi Technology \n\nRevolutionary Metal I-fuse® OTP in FinFET Tech\n\nUmesh Sisodia\nCEO\nCircuitSutra \n\nTransforming Semiconductor Design Using SystemC Based Shift-left ESL Methodologies\n\nRoger Espasa\nCEO & FounderSemidynamics \n\nRISC-V\, Out-of-Order IP Core\, Vector Unit\n\nSiddharth Ravikumar\nTechnical Product Manager\, Solido IP ValidationSiemens EDA \n\nIP\, QA\, Validation\, analog\, digital\, mixed-signal\n\nMichael Seaholm\nProduct Manager for Performance Oscilloscopes and Margin TestingTektronix Inc. \n\nPCIe Gen 3 and Gen 4 testing\nLarry LapidesVP Worldwide SalesImperas Software \n\nRISC-V Verification & Software Development
URL:https://marketingeda.com/event/semisrael-tech-webinar-5/
CATEGORIES:EDA,IP,Webinar
ATTACH;FMTTYPE=image/jpeg:https://marketingeda.com/wp-content/uploads/SemIsrael-May-2-2023.jpg
END:VEVENT
BEGIN:VEVENT
DTSTART;TZID=America/Los_Angeles:20230502T100000
DTEND;TZID=America/Los_Angeles:20230502T110000
DTSTAMP:20230417T181748Z
CREATED:20230417T181748Z
LAST-MODIFIED:20230417T181748Z
UID:6279-1683021600-1683025200@marketingeda.com
SUMMARY:Design Robust IC Packages Faster Using In-Design SI/PI Analysis
DESCRIPTION:IC package design teams and characterization teams have had a “throw-it-over-the-wall” relationship for decades\, which often delays design releases by months. However\, as signal integrity (SI) and power integrity (PI) challenges evolve with multi-die heterogeneous integration\, the need to perform SI/PI analysis as part of the design flow has become a requirement to meet compressed design cycles. \nToday\, in-design analysis empowers IC package design teams to resolve problems and improve design quality long before the SI/PI teams become involved\, ultimately shaving months from the average IC package design cycle. \nThis webinar will educate IC package designers and their managers about Cadence in-design analysis\, which is now part of the market-leading Cadence IC package design technology. It will highlight a guided\, easy-to-use integrated design and analysis workflow that addresses the complexity of electrical challenges\, reduces design iterations\, and saves millions of dollars in engineering time. \n\n\n\n\n\n\n\n\n\n\n\n\nSpeakers: \nJohn Park \nProduct Management Group Director \nJohn Park is Product Management Group Director for Advanced Semiconductor Packaging at EDA industry leader Cadence Design Systems\, where he leads a team responsible for defining cross-domain solutions and methodologies for IC\, package\, and PCB co-design and analysis. His team is especially focused on developing tools and flows for chiplet-based 3D designs. He has over 40 years of experience in the EDA field and is regarded as an international expert on chiplets\, packaging\, and heterogenous integration. \nAndy Haas \nSr. Principal Product Engineer \nAndy Haas is a Product Engineer for In-Design Analysis and SI/PI Signoff at Cadence Design Systems. Andy has more than 20 years of experience in EDA product sales\, support\, architecture and management with particular focus on Signal Integrity\, Power Integrity\, and analog functional verification. He also has 10+ years of Mil-Aero systems\, PCB and custom IC specification\, design and analysis.
URL:https://marketingeda.com/event/design-robust-ic-packages-faster-using-in-design-si-pi-analysis/
CATEGORIES:EDA,Webinar
ATTACH;FMTTYPE=image/jpeg:https://marketingeda.com/wp-content/uploads/Cadence-May-2-2023.jpg
END:VEVENT
BEGIN:VEVENT
DTSTART;TZID=America/Los_Angeles:20230427T110000
DTEND;TZID=America/Los_Angeles:20230427T120000
DTSTAMP:20230403T163925Z
CREATED:20230403T163925Z
LAST-MODIFIED:20230403T163925Z
UID:6223-1682593200-1682596800@marketingeda.com
SUMMARY:The Power of VHDL’s VHPI
DESCRIPTION:The programming interfaces of logic simulators are largely the domain of specialists writing proprietary tools and extensions and are only vaguely in the consciousness of many design and verification engineers\, if aware at all. Yet the simplest use of such interfaces opens up a whole world of possibilities in extending what is achievable in verifying logic IP and with the potential for logic and embedded software co-development. \n\nThe VHDL Procedural Interface (VHPI) is part of the IEEE Standard for VHDL Language Reference Manual. In this part 2 of the webinar series\, we will introduce the VHDL VHPI and discuss the first steps of crossing from the logic domain to the software domain. We will show various working examples with OSVVM co-simulation\, RISC-V ISS running in logic simulation and external programs connected via TCP/IP socket\, sufficient to allow engineers to start creating their own solutions. The real-world examples will be demonstrated to show just what is possible with using these basic logic interface features that are already available\, and well supported\, in the Aldec simulation tools.\n\nAgenda:\n\nIntroduction \nVHDL VHPI\nOSVVM co-simulation VHPI interface\nOSVVM co-simulation environment\nDemo of RISC-V software ISS running in logic simulation\nDemo of external program connected via TCP/IP socket\nConclusions\nQ&A\n\nWebinar Duration\n\n45 min presentation/live demo\n15 min Q&A
URL:https://marketingeda.com/event/the-power-of-vhdls-vhpi/
CATEGORIES:EDA,Webinar
ATTACH;FMTTYPE=image/jpeg:https://marketingeda.com/wp-content/uploads/Aldec-April-27-2023.jpg
END:VEVENT
BEGIN:VEVENT
DTSTART;TZID=America/Los_Angeles:20230427T100000
DTEND;TZID=America/Los_Angeles:20230427T110000
DTSTAMP:20230424T163637Z
CREATED:20230424T163637Z
LAST-MODIFIED:20230424T163637Z
UID:6317-1682589600-1682593200@marketingeda.com
SUMMARY:The Path to 1.6TbE with 224G Ethernet PHY IP
DESCRIPTION:The need for faster and more efficient Ethernet solutions has never been greater\, as the demands of high-performance computing and the rise of big data continue to grow. Join us as we explore the main challenges faced in scaling Ethernet to 1.6T and how the high-performance computing is changing the Ethernet landscape. In this webinar\, you will learn about the latest trends in 1.6T Ethernet\, when you can expect this standard\, and the deployment challenges. Discover the new electro-optical interfaces and how Synopsys 1.6T/800G Ethernet IP solution can help ensure your product is first to market. \n\n\n\n\n\n\n\n\n\n\nSpeakers\n\n\n\n\n\n\n\n\n\n\n\n\n\n\n\n\n\n\n\n\n\n\n\n\n\n\n\nJohn Swanson\n\n\nHPC Controller & Datapath Product Line Manager\nSynopsys \n\n\n\n\n\n\n\n\n\n\n\nJohn Swanson is the HPC Controller & Datapath Product Line Manager in Synopsys Solutions Group. John has worked in the development and deployment of verification\, integration\, and implementation tools\, IP\, standards\, and methodologies used in IP based design for over 25 years. His assignments have encompassed engineering\, methodology\, business development\, and marketing. John has also been involved in various standards activities including Chair of the Verification Technical Working Group in the SPIRIT Consortium; Synopsys representative on the Power.org technical subcommittee and is active in many IEEE and consortium groups today. Prior to joining Synopsys\, he worked for Amoco Oil working on wellhead automation and control systems. He is an Honor graduate from DeVry Institute of Technology where he completed his Engineering degree with Presidents List Honors. \n\n\n\n\n\n\n\n\n\n\n\n\n\n\n\n\n\n\n\n\n\n\n\n\n\n\n\n\n\n\n\nPriyank Shukla\n\n\nSr. Staff Product Manager for the Synopsys High Speed Serdes IP portfolio\nSynopsys \n\n\n\n\n\n\n\n\n\n\n\nPriyank Shukla is a Sr. Staff Product Manager for the Synopsys High Speed Serdes IP portfolio. He has broad experience in analog\, mixed-signal design with strong focus on high performance compute\, mobile and automotive SoCs. He is a contributing member to 802.3dj task force and a IEEE802.3 voter. Priyank has a US patent on low power RTC design.  He received an Electrical Engineering degree from the Indian Institute of Technology-Madras.
URL:https://marketingeda.com/event/the-path-to-1-6tbe-with-224g-ethernet-phy-ip/
CATEGORIES:IP,Webinar
ATTACH;FMTTYPE=image/jpeg:https://marketingeda.com/wp-content/uploads/Synopsys-April-27-2023.jpg
END:VEVENT
BEGIN:VEVENT
DTSTART;TZID=America/Los_Angeles:20230427T100000
DTEND;TZID=America/Los_Angeles:20230427T110000
DTSTAMP:20230323T003724Z
CREATED:20230323T003724Z
LAST-MODIFIED:20230323T003724Z
UID:6202-1682589600-1682593200@marketingeda.com
SUMMARY:CadenceTECHTALK: System-Level Thermal Signoff from Chips Through to Racks
DESCRIPTION:Today’s modern electronic designs require ever more functionality and performance to meet consumer demand. These challenges become more critical and complex when resistive losses in PCB and package structures are significant since resistive losses are temperature dependent. \nIn this webinar\, we will look at an electrothermal co-simulation solution for the full hierarchy of electronic systems from ICs to physical enclosures using Cadence’s Celsius technologies. By combining FEA for solid structures with computational fluid dynamics (CFD) for both liquid and gas\, as well as airflow\, designers can perform complete system analysis in a single tool. The combined workflow that ties the Celsius Thermal Solver with the Celsius Electronic Cooling Solver results in even higher accuracy and faster simulation time in the modeling of electronics equipment. \nSpeakers: \n\nMelika Roshandell\, Product Management Director\, Cadence Design Systems\nKarthick Gopalakrishnan\, Product Director\, Cadence Design Systems\n\nFor questions and inquiries\, or issues with registration\, send an email to events@cadence.com. \n\n\n\n\n\n\nMelika Roshandell\nProduct Management Director\, Cadence Design Systems \n\n\n\n\n\n\n\n\n\n\n\n\nDr. Melika Roshandell is the product management director for Celsius Thermal Solver software at Cadence. Prior to Cadence\, she held positions as a system-on-chip (SoC) thermal engineer at Qualcomm for nine years and thermal engineer at Broadcom for two years. Dr. Roshandell earned her BS in mechanical engineering at the University of California\, San Diego\, and her MS and Ph.D. in mechanical engineering at the University of California\, Irvine. \nKarthick Gopalakrishnan \nProduct Director\, Cadence Design Systems \nKarthick Gopalakrishnan is a product engineer for Celsius Thermal Solver at Cadence Design Systems. He holds a Master’s Degree in Mechanical Engineering from North Carolina State University\, specializing in thermal and fluid sciences.
URL:https://marketingeda.com/event/cadencetechtalk-system-level-thermal-signoff-from-chips-through-to-racks/
CATEGORIES:EDA,Webinar
ATTACH;FMTTYPE=image/jpeg:https://marketingeda.com/wp-content/uploads/Cadence-April-27-2023.jpg
END:VEVENT
BEGIN:VEVENT
DTSTART;TZID=America/Los_Angeles:20230427T090000
DTEND;TZID=America/Los_Angeles:20230427T093000
DTSTAMP:20230418T171043Z
CREATED:20230418T170959Z
LAST-MODIFIED:20230418T171043Z
UID:6286-1682586000-1682587800@marketingeda.com
SUMMARY:How Deep Data Analytics Accelerates SoC Time-To-Market by 6 Months
DESCRIPTION:This webinar will cover how using deep data analytics: \n\nAccelerates time-to-market by 20-25% (equivalent to six months in this example)\, ensuring the product is first to market and able to capitalize on this advantage.\nReduces design and development costs by nearly $25M\, amounting to a 9% cost savings.\nLeads to a higher quality product by improving performance by 15-18%\, depending on the device complexity and process technology used.\n\n  \nSemico Research will present a head-to-head comparison of two companies designing a similar multicore SoC on a 5nm technology node. \n  \nSpeakers: \n\nRich Wawrzyniak\, Principal Analyst: ASIC and SoC\, Semico Research\nMarc Hutner\, Senior Director\, Product Marketing\, proteanTecs
URL:https://marketingeda.com/event/how-deep-data-analytics-accelerates-soc-time-to-market-by-6-months/
CATEGORIES:EDA,Webinar
ATTACH;FMTTYPE=image/jpeg:https://marketingeda.com/wp-content/uploads/proteacnTecs-April-27-2023.jpg
END:VEVENT
BEGIN:VEVENT
DTSTART;TZID=America/Los_Angeles:20230426T100000
DTEND;TZID=America/Los_Angeles:20230426T110000
DTSTAMP:20230424T162003Z
CREATED:20230424T162003Z
LAST-MODIFIED:20230424T162003Z
UID:6314-1682503200-1682506800@marketingeda.com
SUMMARY:Maximize Performance and Efficiency of Multi-die Data Center Chip Designs with Arm CoreLink CMN-700 and Synopsys Platform Architect
DESCRIPTION:This webinar will showcase the design\, analysis\, and optimization of a multi-die fabric architecture based on the next generation Arm® CoreLink™ CMN-700 interconnect\, a high-performance cache coherent interconnect solution designed for complex multi-die system-on-chip (SoC)\, such as those found in data centers. Attendees will learn how to use the Arm CMN-700 Performance Model in Synopsys Platform Architect™ to improve the overall architecture of the multi-die system. \nA case study will illustrate how characteristic workload models can be used to analyze the performance of the architecture and identify potential bottlenecks. This webinar will provide attendees with valuable insights into removing these bottlenecks thereby providing high-bandwidth\, low-latency movement of data between processor cores\, IO and memory. Additional configuration\, debug and visualization capabilities of Synopsys Platform Architect that enable these optimizations will be demonstrated. \nWhether you are a chip architect or a system designer\, this webinar will provide valuable insights on how to design and optimize your high-performance\, multi-die chip architecture. \n\n\n\n\n\n\n\n\n\n\nSpeakers\n\n\nListed below are the industry leaders scheduled to speak. \n\n\n\n\n\n\n\n\n\n\n\n\n\n\n\n\n\n\n\n\n\n\n\n\n\n\nBarry Spotts\n\n\nPrincipal Specialty FAE \nArm \n\n\n\n\n\n\n\n\n\n\n\nBarry is a Field Application Engineer at Arm specializing in semiconductor interconnect solutions.  Barry works directly with Arm partners to assist in developing a IP strategy for their semiconductor architecture project requirements.  He works in tandem to bring design solutions to meet their project goals in relation to ARM Based Subsystems and Interconnect. Barry’s prior roles in the semiconductor industry has EDA knowledge and experience in SPICE\, Verilog\, System-C\, and Co-Verification simulation technologies. \n\n\n\n\n\n\n\n\n\n\n\n\n\n\n\n\n\n\n\n\n\n\n\n\n\n\n\n\n\n\n\nHolger Keding\n\n\nSolutions Application Engineer \nSynopsys \n\n\n\n\n\n\n\n\n\n\n\nHolger is a Solutions Application Engineer in the Systems Design Group at Synopsys\, focusing on Virtual Prototyping for early SoC architecture exploration and optimization. Holger is working with Synopsys customers and partners worldwide on system-level virtual prototyping solutions for early architecture exploration\, performance and power analysis\, and system validation. From his prior roles in the Synopsys Verification and Solutions Groups Holger also has a technical background in communication design and HDL Verification.
URL:https://marketingeda.com/event/maximize-performance-and-efficiency-of-multi-die-data-center-chip-designs-with-arm-corelink-cmn-700-and-synopsys-platform-architect/
CATEGORIES:EDA,IP,Webinar
ATTACH;FMTTYPE=image/jpeg:https://marketingeda.com/wp-content/uploads/Synopsys-April-26-2023-1.jpg
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BEGIN:VEVENT
DTSTART;TZID=America/Los_Angeles:20230426T090000
DTEND;TZID=America/Los_Angeles:20230426T100000
DTSTAMP:20230412T221728Z
CREATED:20230412T221728Z
LAST-MODIFIED:20230412T221728Z
UID:6266-1682499600-1682503200@marketingeda.com
SUMMARY:Advancing Magnetic Memory Technology with Atomistic Modeling
DESCRIPTION:In this event\, experts from Martin-Luther-Universitat Halle Wittenberg\, University of York\, and Synopsys QuantumATK will present how to use ab initio DFT modeling and atomistic spin dynamics simulations of MTJs to guide and accelerate the technological development of magnetic memory such as STT and SOT-MRAM. \n\nInvestigating the potential of novel magnetic tunnel junction (MTJ) materials and concepts for improved magnetic memory performance.\nGenerating realistic MTJ structures with Machine-Learned Force Fields.\nEvaluating the performance based on calculated MTJ spintronic properties\, such as tunnel magnetoresistance (TMR)\, current rectification\, spin-transfer and spin-orbit torques (STT and SOT)\, Gilbert damping\, Curie temp.\, and thermal stability.\nGaining a deeper understanding of magnetization dynamics\, STT and SOT switching mechanisms.\n\nSpeakers \nDr. Ersoy Sasioglu\, Senior Research Scientist\, Martin-Luther-Universitat Halle Wittenberg\, Germany \nDr. Sasioglu will introduce a new MTJ concept based on novel half-metallic magnets and spin-gapless semiconducting Heusler compounds. The new MTJ concept exhibits a significant advantage due to the current rectification functionality and reconfigurable I-V characteristics\, therefore showing potential for logic-in-memory computing. Proposed MTJ devices have been simulated with QuantumATK\, realized experimentally\, and patented. \nDr. Troels Markussen\, Manager R&D\, Synopsys QuantumATK\nDr. Markussen will present a study of investigating different capping layer materials in a double spin-torque MTJ for STT-MRAM.
URL:https://marketingeda.com/event/advancing-magnetic-memory-technology-with-atomistic-modeling/
CATEGORIES:EDA,Webinar
ATTACH;FMTTYPE=image/jpeg:https://marketingeda.com/wp-content/uploads/Synopsys-April-26-2023.jpg
END:VEVENT
BEGIN:VEVENT
DTSTART;TZID=Europe/London:20230425T120000
DTEND;TZID=Europe/London:20230425T133000
DTSTAMP:20230320T170931Z
CREATED:20230320T170931Z
LAST-MODIFIED:20230320T170931Z
UID:6194-1682424000-1682429400@marketingeda.com
SUMMARY:DVClub Europe - Performance Testing and Analysis
DESCRIPTION:Discuss the performance verification challenges posed by complex SoC with distributed cache from cluster\, to interconnect to die-to-die. \nAgenda (BST)\n12:00 Welcome and Introduction – Mike Bartley\, Tessolve \n12:00 Nick Heaton\, Cadence Design Systems – SoC Verification in a Multi-chip\, Multi-die world \n12:30 TBD \n13:00 TBD \n13:30 Close \nAdditional Information\nFor additional information please visit the Tessolve DVClub Europe page for this event. \nSponsors\nDVClub Europe is made possible through the generous support of our sponsors: Agnisys Inc \, ARM\, Breker Verification Systems\, Cadence\, Imperas Software\, OneSpin Solutions\, Siemens\, ST Microelectronics and Synopsys. \nTessolve reserves the right to cancel registration at its discretion.
URL:https://marketingeda.com/event/dvclub-europe-performance-testing-and-analysis/
CATEGORIES:EDA,Webinar
ATTACH;FMTTYPE=image/jpeg:https://marketingeda.com/wp-content/uploads/DVClub-25-April-2023.jpg
END:VEVENT
BEGIN:VEVENT
DTSTART;TZID=America/Los_Angeles:20230425T090000
DTEND;TZID=America/Los_Angeles:20230425T100000
DTSTAMP:20230316T182857Z
CREATED:20230316T182857Z
LAST-MODIFIED:20230316T182857Z
UID:6168-1682413200-1682416800@marketingeda.com
SUMMARY:The ROI of User Experience Design: Increase Sales and Minimize Costs
DESCRIPTION:In today’s competitive landscape for IoT\, edge\, and cloud solutions\, User Experience (UX) design has become more crucial than ever in achieving customer and business goals. During this live webinar\, we will explore how UX design affects everything from sales\, customer retention\, time-to-market\, to internal support and development costs. We’ll delve into key principles of user-centered design\, and discuss how they drive more complete product and purpose-built solutions that differentiate you from competitors\, and accelerate your customers through engineering to ramp more quickly into production. \nSpeaker: \nIn today’s competitive landscape for IoT\, edge\, and cloud solutions\, User Experience (UX) design has become more crucial than ever in achieving customer and business goals. During this live webinar\, we will explore how UX design affects everything from sales\, customer retention\, time-to-market\, to internal support and development costs. We’ll delve into key principles of user-centered design\, and discuss how they drive more complete product and purpose-built solutions that differentiate you from competitors\, and accelerate your customers through engineering to ramp more quickly into production. \nMatt founded Planorama Design\, a user experience design professional services company to design complex\, technical software and systems that are simple and intuitive to use while reducing internal development and support costs. Staffed with seasoned engineers and UX designers\, the company is headquartered in Austin\, Texas\, USA. \n*This webinar is in partnership between SemiWiki and Planorama Design*
URL:https://marketingeda.com/event/the-roi-of-user-experience-design-increase-sales-and-minimize-costs/
CATEGORIES:IoT,Webinar
ATTACH;FMTTYPE=image/webp:https://marketingeda.com/wp-content/uploads/Planorama-Design-April-25-2023.webp
END:VEVENT
BEGIN:VEVENT
DTSTART;TZID=America/Los_Angeles:20230420T100000
DTEND;TZID=America/Los_Angeles:20230420T110000
DTSTAMP:20230410T210633Z
CREATED:20230410T210633Z
LAST-MODIFIED:20230410T210633Z
UID:6253-1681984800-1681988400@marketingeda.com
SUMMARY:Taking the Risk out of RISC-V with Fast\, Architecture-Driven\, PPA Optimization
DESCRIPTION:The use of the RISC-V ISA to develop processors for SoCs is a growing trend. An important driver is the ability to customize or create ISA and micro-architectural extensions to differentiate designs across application areas including AI\, machine learning\, automotive\, data center\, mobile\, and consumer. Traditionally\, designing proprietary cores with the right extensions has been challenging given the high degree of complexity and the high level of expertise required. Evaluating the impact of design decisions on power\, performance and area (PPA) can pose a significant hurdle. This webinar will cover two products from Synopsys’ portfolio of industry leading tools: Synopsys ASIP Designer and Synopsys RTL Architect. These tools help designers create highly customized processors faster while meeting the desired PPA targets with confidence. The solutions facilitate the Synthesis-in-the-Loop design approach\, both during earlier architectural design stages with processor model modifications and during RTL implementation. A real-world case study will highlight their interoperability and the results that can be achieved. \nJim Schultz  \nJim is a Senior Product Manager at Synopsys. As a designer\, his experience includes physical verification\, design planning and design implementation on CPUs\, networking\, and security chips. As a product engineer\, he supported design implementation\, design planning\, and package design at various EDA companies. \nMaria Auras-Rodriguez  \nMaria joined the ASIP Designer R&D Team in 2019 where she focuses on the ASIP Designer’s HDL Generator tool\, including synthesis support for ASIPs. Before joining Synopsys\, she worked as a researcher at the Institute for Communication Technologies and Embedded Systems (ICE) at RWTH Aachen University. \n*This webinar is in partnership with SemiWiki and Synopsys*
URL:https://marketingeda.com/event/taking-the-risk-out-of-risc-v-with-fast-architecture-driven-ppa-optimization/
CATEGORIES:EDA,IP,Webinar
ATTACH;FMTTYPE=image/jpeg:https://marketingeda.com/wp-content/uploads/Synopsys-April-20-2023.jpg
END:VEVENT
BEGIN:VEVENT
DTSTART;TZID=America/Los_Angeles:20230413T110000
DTEND;TZID=America/Los_Angeles:20230413T120000
DTSTAMP:20230316T180323Z
CREATED:20230316T180238Z
LAST-MODIFIED:20230316T180323Z
UID:6163-1681383600-1681387200@marketingeda.com
SUMMARY:The Power of Verilog’s PLI and VPI for FPGA Designs
DESCRIPTION:A logic simulator’s programming interfaces can be used for not only verifying logic IP but also the co-development of logic and embedded software. \nOur ‘Introducing Logic Simulator Programming Interfaces for FPGA designs’ three-part webinar series starts on April 13. \nOur guest presenter for this series is Simon Southwell\, from Anita Simulators\, and the schedule is as follows: \nPart 1: The Power of Verilog’s PLI and VPI – April 13.\nPart 2: The Power of VHDL’s VHPI – April 27.\nPart 3: The Power of SystemVerilog’s DPI – May 11. \nAll three webinars will be live and held twice – at 15:00 CEST and 11:00 PDT. Each will include a Q&A session. \nThe programming interfaces of logic simulators are largely the domain of specialists writing proprietary tools and extensions and are only vaguely in the consciousness of many design and verification engineers\, if aware at all. Yet the simplest use of such interfaces opens up a whole world of possibilities in extending what is achievable in verifying logic IP and with the potential for logic and embedded software co-development. \n  \nThe Programming Language Interface (PLI/VPI) is part of the IEEE Standard for SystemVerilog Language Reference Manual. In this part 1 of the webinar series\, we will introduce the Verilog PLI and VPI and discuss the first steps of crossing from the logic domain to the software domain. We will show various working examples with memory models and virtual processors\, sufficient to allow engineers to start creating their own solutions. The real-world examples will be demonstrated to show just what is possible with using these basic logic interface features that are already available\, and well supported\, in the Aldec simulation tools. \n  \nAgenda: \n\nIntroduction\nVerilog PLI\nSparse memory model example\nVerilog VPI\nReworked memory model\nVirtual Processor\nDemo of Virtual Processor and memory model\nConclusions\nQ&A\n\n  \nWebinar Duration: \n\n45 min presentation/live demo\n15 min Q&A\n\nPresenter BIO \nSimon Southwell has 35 years in Research and Development\, with experience in ASIC design\, FPGA\, and embedded software development. Now spending time contributing IP to the open-source community\, and sharing experience and knowledge through writing articles and mentoring undergraduates and junior engineers. Also currently a collaborator on the OSVVM project\, a verification methodology and VHDL library\, adding and supporting its co-simulation capabilities. Particular areas of interest include processor systems and sub-systems\, system modeling in software\, the software/hardware interface and co-simulation of logic and software. \nAmongst the many areas of experiences are original logic IP design targeting both ASIC and FPGA\, logic verification\, HPC (supercomputers)\, processor systems\, networking (802.3 and proprietary)\, embedded software\, co-simulation technology\, software modeling of SoC systems\, data compression logic\, PCIe endpoint design\, cellular (3G and 4G)\, wireless (802.11 and 802.15.4) and more. Joint or sole author on several logic IP related patents.
URL:https://marketingeda.com/event/the-power-of-verilogs-pli-and-vpi/
CATEGORIES:EDA,Webinar
ATTACH;FMTTYPE=image/jpeg:https://marketingeda.com/wp-content/uploads/Aldec-April-13-2023.jpg
END:VEVENT
BEGIN:VEVENT
DTSTART;TZID=America/Los_Angeles:20230413T090000
DTEND;TZID=America/Los_Angeles:20230413T100000
DTSTAMP:20230411T182846Z
CREATED:20230411T182846Z
LAST-MODIFIED:20230411T182846Z
UID:6257-1681376400-1681380000@marketingeda.com
SUMMARY:Analog Layout with Thomas Parry and Tim Edwards
DESCRIPTION:In this webinar we will take the comparator circuit from last time and look at how to do the layout with the 2 most used open source layout tools. We will send the link to the webinar recording to those who registered. \nWe will cover: \n\nCreation of the transistors\nLayout with Magic\nLayout with Klayout\nCircuit extraction with Magic\nLVS with Netgen\n\nWe will have opportunity for Q&A during the webinar.
URL:https://marketingeda.com/event/analog-layout-with-thomas-parry-and-tim-edwards/
CATEGORIES:EDA,IP,Webinar
ATTACH;FMTTYPE=image/png:https://marketingeda.com/wp-content/uploads/efabless-April-13-2023.png
END:VEVENT
BEGIN:VEVENT
DTSTART;TZID=America/Los_Angeles:20230411T100000
DTEND;TZID=America/Los_Angeles:20230411T110000
DTSTAMP:20230316T183442Z
CREATED:20230316T183341Z
LAST-MODIFIED:20230316T183442Z
UID:6172-1681207200-1681210800@marketingeda.com
SUMMARY:Enhance Productivity with Machine Learning in the Analog Front-End Design Flow
DESCRIPTION:Advanced semiconductor nanometer technology nodes\, together with smart IC design applications enable today very complex and powerful systems for communication\, automotive\, data transmission\, AI\, IoT\, medical\, industry\, energy harvesting\, and many more. However\, more aggressive time-to-market and higher performance requirements force IC designers to look for advanced and seamless design flows\, tools & methodologies to meet design requirements in a tight design schedule. Automated circuit sizing and optimization is becoming a very important tool to achieve that. \nMunEDA provides the necessary features to enhance designers’ productivity by circuit optimization within its EDA design tool suite WiCkeD. \nIn this webinar we’ll discuss state-of-the-art circuit optimization methodology\, and particularly how to use it most efficiently in order to enhance design quality and designers’ productivity. \nSpeakers: \nMichael Pronath. Michael is VP of Products & Solutions at MunEDA\, and author and co-author of several international publications about methods of analog integrated circuit design and testing of mixed-signal circuits. \nDave Johnson is President of FirstShift Technologies which represents MunEDA in North America. He has also worked at worked at NXP\, Neolinear\, and Cadence. Dave started his career as an I/O library circuit designer. \n*This webinar is in partnership with SemiWiki and MunEDA*
URL:https://marketingeda.com/event/enhance-productivity-with-machine-learning-in-the-analog-front-end-design-flow/
CATEGORIES:EDA,IP,Webinar
ATTACH;FMTTYPE=image/webp:https://marketingeda.com/wp-content/uploads/MunEDA-April-11-2023.webp
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END:VCALENDAR