BEGIN:VCALENDAR VERSION:2.0 PRODID:-//Marketing EDA - ECPv6.16.4.1//NONSGML v1.0//EN CALSCALE:GREGORIAN METHOD:PUBLISH X-ORIGINAL-URL:https://marketingeda.com X-WR-CALDESC:Events for Marketing EDA REFRESH-INTERVAL;VALUE=DURATION:PT1H X-Robots-Tag:noindex X-PUBLISHED-TTL:PT1H BEGIN:VTIMEZONE TZID:America/Los_Angeles BEGIN:DAYLIGHT TZOFFSETFROM:-0800 TZOFFSETTO:-0700 TZNAME:PDT DTSTART:20230312T100000 END:DAYLIGHT BEGIN:STANDARD TZOFFSETFROM:-0700 TZOFFSETTO:-0800 TZNAME:PST DTSTART:20231105T090000 END:STANDARD BEGIN:DAYLIGHT TZOFFSETFROM:-0800 TZOFFSETTO:-0700 TZNAME:PDT DTSTART:20240310T100000 END:DAYLIGHT BEGIN:STANDARD TZOFFSETFROM:-0700 TZOFFSETTO:-0800 TZNAME:PST DTSTART:20241103T090000 END:STANDARD BEGIN:DAYLIGHT TZOFFSETFROM:-0800 TZOFFSETTO:-0700 TZNAME:PDT DTSTART:20250309T100000 END:DAYLIGHT BEGIN:STANDARD TZOFFSETFROM:-0700 TZOFFSETTO:-0800 TZNAME:PST DTSTART:20251102T090000 END:STANDARD END:VTIMEZONE BEGIN:VTIMEZONE TZID:Europe/London BEGIN:DAYLIGHT TZOFFSETFROM:+0000 TZOFFSETTO:+0100 TZNAME:BST DTSTART:20230326T010000 END:DAYLIGHT BEGIN:STANDARD TZOFFSETFROM:+0100 TZOFFSETTO:+0000 TZNAME:GMT DTSTART:20231029T010000 END:STANDARD BEGIN:DAYLIGHT TZOFFSETFROM:+0000 TZOFFSETTO:+0100 TZNAME:BST DTSTART:20240331T010000 END:DAYLIGHT BEGIN:STANDARD TZOFFSETFROM:+0100 TZOFFSETTO:+0000 TZNAME:GMT DTSTART:20241027T010000 END:STANDARD BEGIN:DAYLIGHT TZOFFSETFROM:+0000 TZOFFSETTO:+0100 TZNAME:BST DTSTART:20250330T010000 END:DAYLIGHT BEGIN:STANDARD TZOFFSETFROM:+0100 TZOFFSETTO:+0000 TZNAME:GMT DTSTART:20251026T010000 END:STANDARD END:VTIMEZONE BEGIN:VTIMEZONE TZID:America/New_York BEGIN:DAYLIGHT TZOFFSETFROM:-0500 TZOFFSETTO:-0400 TZNAME:EDT DTSTART:20230312T070000 END:DAYLIGHT BEGIN:STANDARD TZOFFSETFROM:-0400 TZOFFSETTO:-0500 TZNAME:EST DTSTART:20231105T060000 END:STANDARD BEGIN:DAYLIGHT TZOFFSETFROM:-0500 TZOFFSETTO:-0400 TZNAME:EDT DTSTART:20240310T070000 END:DAYLIGHT BEGIN:STANDARD TZOFFSETFROM:-0400 TZOFFSETTO:-0500 TZNAME:EST DTSTART:20241103T060000 END:STANDARD BEGIN:DAYLIGHT TZOFFSETFROM:-0500 TZOFFSETTO:-0400 TZNAME:EDT DTSTART:20250309T070000 END:DAYLIGHT BEGIN:STANDARD TZOFFSETFROM:-0400 TZOFFSETTO:-0500 TZNAME:EST DTSTART:20251102T060000 END:STANDARD END:VTIMEZONE BEGIN:VEVENT DTSTART;TZID=America/Los_Angeles:20241107T070000 DTEND;TZID=America/Los_Angeles:20241107T080000 DTSTAMP:20241023T171101Z CREATED:20241023T171101Z LAST-MODIFIED:20241023T171101Z UID:8449-1730962800-1730966400@marketingeda.com SUMMARY:Navigating COTS-IP in DO-254: Strategies for Safe and Efficient FPGA Design DESCRIPTION:The integration of COTS-IP (Commercial Off-The-Shelf Intellectual Property) components in FPGA-based Avionics systems can significantly speed up development and enhance performance. However\, it also introduces unique challenges\, as these components may not align with the strict aviation development assurance standards required for DO-254 compliance. This webinar will guide you through the process of balancing the benefits and risks associated with COTS-IP in Avionics designs. \nIn this joint webinar with friends and partners\, Aldec\, we’ll explore different types of IPs available on the market\, their roles in the design assurance process\, and practical strategies for integrating them safely. You’ll discover key factors for choosing the right vendor and IP\, best practices for verification\, and effective planning and execution techniques to ensure your systems meet safety requirements. \nWhat you’ll learn:\n1. COTS-IP usage:\na. What are COTS-IPs and what are the different IP types\nb. Applicable guidance for COTS-IP\nc. Verification strategies and methods\nd. Methods for achieving coverage\ne. Putting it all together and showing compliance \nSpeakers: \nMartin Beeby\, Head of Advanced Avionics Systems and Managing Director of ConsuNova EU\, ConsuNova With over 35 years of experience in the development of avionics Systems\, Hardware and Software\, Martin has a wealth of certification experience with systems ranging from DAL-A to DAL-D. Martin is an active contributor to many industry standard working groups developing new guidance for Avionics development and is an active CVE on multiple European programs. \nJanusz Kitel\, DO-254 Program Manager\, Aldec Janusz brings over 18 years of experience in software and hardware design and verification\, with more than a decade dedicated to mastering DO-254 compliance. His work ensures that Aldec products meet the strict standards of the aerospace industry\, while also providing customers with valuable support in overcoming tooling challenges in airborne electronic hardware (AEH) projects. \nShare this:\n Share on LinkedIn (Opens in new window)\n LinkedIn\n \n Share on X (Opens in new window)\n X\n \n Share on Facebook (Opens in new window)\n Facebook\n Like this:Like Loading… URL:https://marketingeda.com/event/navigating-cots-ip-in-do-254-strategies-for-safe-and-efficient-fpga-design/ CATEGORIES:EDA,IP,Webinar ATTACH;FMTTYPE=image/jpeg:https://marketingeda.com/wp-content/uploads/Aldec-November-7-2024.jpg END:VEVENT BEGIN:VEVENT DTSTART;TZID=America/Los_Angeles:20241106T100000 DTEND;TZID=America/Los_Angeles:20241106T110000 DTSTAMP:20241018T165537Z CREATED:20241018T165537Z LAST-MODIFIED:20241018T165537Z UID:8433-1730887200-1730890800@marketingeda.com SUMMARY:Navigating Trends and Tools in Automotive Design with Cadence DESCRIPTION:Join us for our first webinar in this insightful series\, where we explore the rapidly evolving automotive landscape. We will focus on the rise of autonomous and electric vehicles\, highlighting key trends such as ADAS\, software-defined vehicles\, and zonal architectures. \nLearn how Cadence’s advanced automotive solutions are addressing the increasing compute demands and in-vehicle networking requirements while prioritizing power efficiency and safety. \nEquip yourself with the knowledge to thrive in this dynamic environment. We look forward to traveling this road together! \nWhat will be covered: \n\nEmerging trends in ADAS\, software-defined vehicles\, zonal architectures\, connectivity\, and electrification\nHow high-performance centralized computing\, cloud-native software development\, power management\, safety design support\, and system design and analysis are creating new opportunities for industry players and reshaping automotive design.\n\nWho Should Attend: \n\nThis free event is a terrific opportunity for design/CAD engineers\, CAD managers\, IT managers\, and business leaders seeking to optimize their design flow and technology infrastructure within the automotive industry.\n\nShare this:\n Share on LinkedIn (Opens in new window)\n LinkedIn\n \n Share on X (Opens in new window)\n X\n \n Share on Facebook (Opens in new window)\n Facebook\n Like this:Like Loading… URL:https://marketingeda.com/event/navigating-trends-and-tools-in-automotive-design-with-cadence/ CATEGORIES:EDA,Webinar ATTACH;FMTTYPE=image/jpeg:https://marketingeda.com/wp-content/uploads/Cadence-Nnovember-6-2024.jpg END:VEVENT BEGIN:VEVENT DTSTART;TZID=America/Los_Angeles:20241030T090000 DTEND;TZID=America/Los_Angeles:20241030T100000 DTSTAMP:20241016T180601Z CREATED:20241016T180601Z LAST-MODIFIED:20241016T180601Z UID:8419-1730278800-1730282400@marketingeda.com SUMMARY:Verifying the next generation High Bandwidth Memory controllers for AI and HPC applications DESCRIPTION:High Bandwidth Memory (HBM) has revolutionized AI\, machine learning\, and High-Performance Computing by significantly increasing data transfer speeds and alleviating performance bottlenecks. The introduction of next-generation HBM4 is especially transformative\, enabling faster training and execution of complex AI models. JEDEC has announced that the HBM4 specification is nearing finalization. In this webinar\, you will learn how Siemens’s scalable and customizable Avery HBM Verification IP helps companies like Rambus verify their industry-leading HBM4 Controller IP through rigorous testing to ensure reliability and performance. \n\n  \nWhat You Will Learn:  \n\nWhat’s new in HBM4\nChallenges involved in verifying advanced HBM generations\nUnique features in Siemens’s HBM4 memory models\nRambus’s newly-announced HBM4 memory controller IP\n\nWho Should Attend:  \n\nDesign & Verification Engineers\, Architects\nManagers and Directors for memory controllers\n\nWhat/Which Products are Covered:   \n\nSiemens Avery HBM4 Verification IP\nRambus HBM4 Memory Controller\n\nSpeakers:\n\n\n\n\n\n\nKamlesh Mulchandani\nApplication Engineering Consultant\, Siemens EDA\n\n\n\n\nKamlesh Mulchandani is an Application Engineering Consultant at Siemens EDA. In his role as a Verification IP AE\, Kamlesh bridges the gap between Verification IP technology and customer needs through collaboration\, technical support and by tailoring Siemens solutions for specific user applications. Prior to Siemens\, Kamlesh worked at Cadence as a Memory Subsystem Design & Verification Engineer where he worked on verifying LPDDRx/DDRx & GDDRx IPs. \n\n\n\n\n\n\n\nNidish Kamath\nDirector of Product Management for Memory Interface IP\, Rambus\n\n\n\n\nNidish Kamath is the Director of Product Management for Memory Interface IP at Rambus.  He previously held marketing and product management roles at AMD\, Kioxia (formerly Toshiba Memory)\, Avalanche Technologies\, Brocade and Qualcomm\, where he worked on computational storage\, SmartNICs and GPU cluster networking solutions. He has served in various standards and industry associations such as SNIA\, Center for Open Source Software (CROSS)\, CXL Consortium\, UEC and JEDEC. \n\n\n\nShare this:\n Share on LinkedIn (Opens in new window)\n LinkedIn\n \n Share on X (Opens in new window)\n X\n \n Share on Facebook (Opens in new window)\n Facebook\n Like this:Like Loading… URL:https://marketingeda.com/event/verifying-the-next-generation-high-bandwidth-memory-controllers-for-ai-and-hpc-applications/ CATEGORIES:EDA,Webinar ATTACH;FMTTYPE=image/jpeg:https://marketingeda.com/wp-content/uploads/Siemens-October-30-2024.jpg END:VEVENT BEGIN:VEVENT DTSTART;TZID=America/Los_Angeles:20241023T090000 DTEND;TZID=America/Los_Angeles:20241023T100000 DTSTAMP:20241009T193236Z CREATED:20241009T193236Z LAST-MODIFIED:20241009T193236Z UID:8402-1729674000-1729677600@marketingeda.com SUMMARY:Hardware Verification using VirtuaLAB DESCRIPTION:VirtuaLAB protocol solutions offer a full-stack testing environment with seamless connectivity and stimulus traffic generation for designs under test. It operates autonomously\, adapting to scenarios without requiring protocol knowledge from the user. VirtuaLAB significantly reduces test and compliance suite regression times\, running at high emulation speeds\, integrated with Protocol Analyzer for complete protocol visibility and performance metrics. Supporting any scenario\, it enables users to focus on their design’s unique value while ensuring reliable standard protocol interactions. \nWho Should Attend: \n\nEngineers and Managers responsible for System Design Verification of complex SoCs\nEngineers and Managers responsible for design performance verification\n\nWhat you will learn: \n\nAttendees will learn how VirtuaLAB protocol solutions provide a full stack from the physical to the application layer to connect to your design under test and create stimulus traffic as a host\, or respond to commands in the form of a compliant device.\nAttendees will learn the ease of bring-up of a VirtuaLAB environment with no testbench required\, but how to use real-world software to create workloads exactly matching the end-user of your silicon.\nAttendees will see a demonstration of VirtuaLAB running a back-to-back UFS4 host model and RTL SSD model DUT\, running the LLAMA 3.1 LLM\, and providing query responses in real-time.\n\nSpeaker:\n\n\n\n\n\n\nBen Whitehead\nDirector of Product Management\, Siemens EDA\n\n\n\n\n\nShare this:\n Share on LinkedIn (Opens in new window)\n LinkedIn\n \n Share on X (Opens in new window)\n X\n \n Share on Facebook (Opens in new window)\n Facebook\n Like this:Like Loading… URL:https://marketingeda.com/event/hardware-verification-using-virtualab/ CATEGORIES:EDA,Webinar ATTACH;FMTTYPE=image/jpeg:https://marketingeda.com/wp-content/uploads/Siemens-October-23-2024.jpg END:VEVENT BEGIN:VEVENT DTSTART;TZID=America/Los_Angeles:20241017T110000 DTEND;TZID=America/Los_Angeles:20241017T120000 DTSTAMP:20241014T214312Z CREATED:20241014T214312Z LAST-MODIFIED:20241014T214312Z UID:8416-1729162800-1729166400@marketingeda.com SUMMARY:Static and Dynamic CDC Verification of AXI4 Stream-based IPs DESCRIPTION:The AXI4 Stream protocol is used as a standard interface to exchange data between connected IPs within FPGA designs. For crossing clock domains\, the AXI4 Stream interconnect is based on switches capable of transferring data to another asynchronous clock domain. The alternative solution is a dual-port AXI4 Stream IP\, capable of changing clock domains when packet routing is not required. \nStatic and dynamic clock domain crossing (CDC) verification methods complement each other to ensure flawless operation of multi-clock designs. ALDEC_CDC rules plugin contains 58 rules for checking design quality\, design constraints\, and clock and reset trees. It is also used for validating design synchronization circuits. However\, static CDC verification methods alone may not guarantee the completeness of the CDC verification task. Dynamic CDC verification is crucial. The two main methods for dynamic CDC verification are checking with CDC assertions and modeling of random delay insertion on clock domain crossings.\n\nIn this webinar\, we will introduce both static and dynamic verification methods for CDC verification of AXI4 Stream-based IPs. We will discuss the CDC assertions that are auto-generated from ALINT-PRO\, and we will also demonstrate the design and usage of the synchronizer models with random delay insertion.\n\nAgenda:\n\nCDC verification process overview\n\nStatic CDC verification checks\nAssertions usage in CDC verification\nThe concept of delay randomization at CDC crossing in functional simulation\n\n\nAXI Stream protocol overview\nAXI CDC Port Verification\n\nRunning CDC static checks with ALINT-PRO\nGeneration SV Assertion with ALINT-PRO\nDeveloping the testbench for AXI CDC Port dynamic verification\nSimulating design with generated CDC assertions\nSimulating design with random delay insertion in synchronizer models\n\n\nConclusion\nQ&A\n\n\nWebinar Duration\n\n45 min presentation/live demo\n\nBio: \nAlex Gnusin\, Aldec’s ALINT-PRO Product Manager \nAlex accumulated 27 years of hands-on experience in various aspects of ASIC and FPGA design and verification. As a verification prime for a multi-million gates project in companies such as IBM\, Nortel\, Ericsson and Synopsys Inc\, he combined various verification methods such as static linting\, formal property checking\, dynamic simulation and hardware-assisted acceleration to efficiently achieve design verification goals. He received his M.S. in Electronics from Technion\, Israel Institute of Technology. \nShare this:\n Share on LinkedIn (Opens in new window)\n LinkedIn\n \n Share on X (Opens in new window)\n X\n \n Share on Facebook (Opens in new window)\n Facebook\n Like this:Like Loading… URL:https://marketingeda.com/event/static-and-dynamic-cdc-verification-of-axi4-stream-based-ips/ CATEGORIES:EDA,IP,Webinar ATTACH;FMTTYPE=image/jpeg:https://marketingeda.com/wp-content/uploads/Aldec-October-17-2024.jpg END:VEVENT BEGIN:VEVENT DTSTART;TZID=America/Los_Angeles:20241015T100000 DTEND;TZID=America/Los_Angeles:20241015T110000 DTSTAMP:20241008T164139Z CREATED:20241008T164139Z LAST-MODIFIED:20241008T164139Z UID:8399-1728986400-1728990000@marketingeda.com SUMMARY:ARM corelink\, Arteris NoC\, UCIe\, Bunch-of-wires\, CXL and PCIe- Designing the interconnect is not for the weak-hearted DESCRIPTION:There are so many options for Network-on-Chip: ARM-Corelink CMN700\, Arteris FlexNoC\, open-source NoC interconnect\, and of course developing home-grown fully customized solutions. Where does each solution fit? Where do we use it- backplane vs inside domains? How does AMBA AXI or PCIe or CXL fit in the mix? With the advent of chiplet\, do we go with UCIe or bunch-of-wires. Where do we locate the DRAM and the task scheduler? Lots of questions need to be answered before the SoC or chiplets can be implemented. \nIn this Webinar\, we will take the mystery out of these architecture decisions by demonstrating how system modeling can provide quantitative metrics to validate and optimize these requirements. For this purpose we will use the mapping of a CNN- Resnet 50 on an AI processor\, Open Architecture Management (OAM) system\, heterogeneous compute SoC-FPGA and development of a custom NoC. \nTo measure the quality of the design\, we will show the running of standard and synthetic workloads. Quantitative metrics generated will include latency\, throughput\, buffer occupancy\, peak power consumed\, heat generated\, cache hit-miss and memory bandwidth. We will also show how the source of bottlenecks can be identified. The design can be experimented with different routing schemes\, schedulers\, buffer size\, clock speeds\, flits\, clock domains\, flow control credit and quality-of-service. \nShare this:\n Share on LinkedIn (Opens in new window)\n LinkedIn\n \n Share on X (Opens in new window)\n X\n \n Share on Facebook (Opens in new window)\n Facebook\n Like this:Like Loading… URL:https://marketingeda.com/event/arm-corelink-arteris-noc-ucie-bunch-of-wires-cxl-and-pcie-designing-the-interconnect-is-not-for-the-weak-hearted/ CATEGORIES:EDA,IP,Webinar ATTACH;FMTTYPE=image/jpeg:https://marketingeda.com/wp-content/uploads/Mirabilis-October-15-2024.jpg END:VEVENT BEGIN:VEVENT DTSTART;TZID=America/Los_Angeles:20241010T110000 DTEND;TZID=America/Los_Angeles:20241010T120000 DTSTAMP:20241007T181311Z CREATED:20241007T181311Z LAST-MODIFIED:20241007T181311Z UID:8383-1728558000-1728561600@marketingeda.com SUMMARY:The Development and Evolution of Verilog & SystemVerilog DESCRIPTION:Abstract: \nSystemVerilog is a super next-generation Verilog with a fancy marketing name. SystemVerilog leveraged many of its features from other languages and methodologies. Class-based capabilities\, constrained random testing (CRT)\, and functional coverage were all features that were added to SystemVerilog and incorporated into the Universal Verification Methodology (UVM). UVM has become the most dominant and powerful verification methodology used to verify designs by engineers today. \nCliff Cummings has been a member of the Verilog & SystemVerilog Standards Groups since 1994 and will offer his unique and historical perspective on how features were added to SystemVerilog\, why the features were added\, and the origins of many of those features.\n\nAgenda:\n\nVerilog HDL and Its Ancestors and Descendants (reference paper)\nBrief History of Verilog & SystemVerilog\nHILO\, Verilog\, C\, PLI\nSDF\, Synthesis\, VHDL\, VPI\nSuperlog\, IHDL (Intel)\, SystemC\, Vera\nOOP\, e-Specman\, SystemVerilog\, C++\nOVL\, PSL\, SVA\nOVM / UVM history\nSimulation & Functional Coverage\nQ&A\n\n\nWebinar Duration\n\n45 min presentation/live demo\n15 min Q&A\n\nBio: \nClifford E. Cummings\, \nVice President of Training at Paradigm Works and Founder of Sunburst Design \nCliff Cummings is Vice President of Training at Paradigm Works and Founder of Sunburst Design. Cliff teaches world-class SystemVerilog\, UVM\, CDC and synthesis training classes. Cliff has 42 years of ASIC\, FPGA and system design experience and 32 years of combined Verilog\, SystemVerilog\, UVM verification\, synthesis\, and methodology training experience.  Cliff has taught expert Verilog\, SystemVerilog\, Design Synthesis\, CDC and UVM Verification to thousands of engineers world-wide and has presented more than 50 papers on these topics.  Cliff holds a BSEE from Brigham Young University and an MSEE from Oregon State University. \nShare this:\n Share on LinkedIn (Opens in new window)\n LinkedIn\n \n Share on X (Opens in new window)\n X\n \n Share on Facebook (Opens in new window)\n Facebook\n Like this:Like Loading… URL:https://marketingeda.com/event/the-development-and-evolution-of-verilog-systemverilog/ CATEGORIES:EDA,Webinar ATTACH;FMTTYPE=image/jpeg:https://marketingeda.com/wp-content/uploads/Aldec-October-10-2024.jpg END:VEVENT BEGIN:VEVENT DTSTART;TZID=Europe/London:20241008T120000 DTEND;TZID=Europe/London:20241008T130000 DTSTAMP:20240911T161307Z CREATED:20240911T161307Z LAST-MODIFIED:20240911T161307Z UID:8325-1728388800-1728392400@marketingeda.com SUMMARY:Cocotb 2.0: Modernize your testbenches for even more productivity DESCRIPTION:Cocotb 2.0 is the latest major version of cocotb\, ironing out many quirks that have accumulated over the years. With only small changes to your testbenches\, you can benefit from improved typing and less surprising corner cases. In this talk\, we’ll show what’s new in cocotb 2.0\, and how you can modernize your code bases to make best use of it.  We also have a presentation from a cocotb user performing HDL simulation with python cocotb\, with a Transaction Level Modelling (TLM) approach with a completely free and open source chain (GHDL simulator and WSL Linux). \n\n\n\n\n\n\n\n\n\n\n\n\n\n\n\n\n\n\n\n\n\n\n\n\n\n\n\n\n\n\n\n\n\n\n\n\n\n\n\n\nAgenda (BST):\n\n\n\n\n\n\n\nTime\nSession Description\nSlides\nVideos\n\n\n12.00 BST\nWelcome and Introduction \nMike Bartley\,Tessolve\n\n\n\n\n12.00 BST\nSimple yet powerful: Open-source HDL simulation with Cocotb \nHayder Al-Hakeem ( Wärtsilä Finland)\n\n\n\n\n12.30 BST\nCocotb 2.0: Modernize your testbenches for even more productivity \nPhilipp Wagner ( FOSSi Foundation)\n\n\n\n\n13.00 BST\n  \nClose\n\n\n\n\n\n\n\n\n\n\n\n\n\n\n\n\n\n\n\n\n\n\n\n\n\n\n\n\n\nAbout DVClub\n\n\n\n\nThe principal goal of each DVCLUB meeting is to have fun while helping build the European verification community through regular educational and networking events. Attendance at DVClub Europe meetings is free and is open to all non-service provider semiconductor professionals. Each meeting addresses a specific issue faced by the design and verification community and whatever your speciality provides an excellent opportunity for updating knowledge as well as share experiences\, insights and issues with other members of the verification community. \n\n\n\n\n\n\n\nShare this:\n Share on LinkedIn (Opens in new window)\n LinkedIn\n \n Share on X (Opens in new window)\n X\n \n Share on Facebook (Opens in new window)\n Facebook\n Like this:Like Loading… URL:https://marketingeda.com/event/cocotb-2-0-modernize-your-testbenches-for-even-more-productivity/ CATEGORIES:EDA,Webinar ATTACH;FMTTYPE=image/jpeg:https://marketingeda.com/wp-content/uploads/DVCon-Europe-October-2024.jpg END:VEVENT BEGIN:VEVENT DTSTART;TZID=America/Los_Angeles:20241002T090000 DTEND;TZID=America/Los_Angeles:20241002T100000 DTSTAMP:20240906T215750Z CREATED:20240906T215750Z LAST-MODIFIED:20240906T215750Z UID:8307-1727859600-1727863200@marketingeda.com SUMMARY:Redefining Mobile Experiences with AI - Session 2 DESCRIPTION:The Arm platform is providing the foundation for the next wave of AI smartphones and laptops. As AI models rapidly evolve\, we’re seeing that software begins to outpace hardware\, requiring additional innovation at all levels of the compute stack. \nTo meet these growing demands\, the Arm platform offers a new compute solution for maximum performance and efficiency\, on leading process nodes. Join this webinar series to learn more about this solution\, including the latest Arm Armv9 CPUs and GPUs\, the benefits and opportunities of running AI on device\, and how to innovate and speed time to market. \nThe CPU Cluster on Wednesday\, Oct 2\, 2024\n\n9:00 a.m. BST / 4:00 p.m. Beijing\n5:00 p.m. BST / 9:00 a.m. PT\n\nThis webinar covers: \n\nAn overview of Arm’s most performant\, efficient\, and versatile CPU cluster based on the Armv9 architecture for maximum performance and power efficiency.\nFeatures\, benefits\, and performance enhancements of Arm Cortex-X925\, Cortex-A725 CPU\, Cortex-A520 CPU and Arm DSU-120.\nHow this CPU cluster can improve consumer experiences on mobile devices.\n\nSpeaker: Manish Pandey\, Senior Product Manager\, Arm \nFirst Session – September 18th \nShare this:\n Share on LinkedIn (Opens in new window)\n LinkedIn\n \n Share on X (Opens in new window)\n X\n \n Share on Facebook (Opens in new window)\n Facebook\n Like this:Like Loading… URL:https://marketingeda.com/event/redefining-mobile-experiences-with-ai-session-2/ CATEGORIES:IP,Webinar ATTACH;FMTTYPE=image/jpeg:https://marketingeda.com/wp-content/uploads/Arm-September-18-2024.jpg END:VEVENT BEGIN:VEVENT DTSTART;TZID=America/Los_Angeles:20241001T110000 DTEND;TZID=America/Los_Angeles:20241001T113000 DTSTAMP:20240930T220024Z CREATED:20240930T220024Z LAST-MODIFIED:20240930T220024Z UID:8361-1727780400-1727782200@marketingeda.com SUMMARY:Interactive SPICE Model Verification Platform ME-Pro DESCRIPTION:ME-Pro™ is a unified tool for designers\, process developers\, modeling engineers\, and PDK engineer providing robust simulation and analysis capabilities for semiconductor device model verification and evaluation. \nThis comprehensive platform supports evaluation across device\, circuit\, and process domains enabling interactive development and offering critical feedback for process improvements. With decades of Primarius’ expertise\, ME-Pro™ features pre-configured templates\, hundreds of verification data entries\, and the built-in NanoSpice parallel simulator that is all designed to streamline setup and reduce learning curves. \nPresenter\nErik Supnet is a Senior Application Engineer at Primarius for two years supporting pre-sales and post-sales activities for modeling and simulation products. He earned his B.S. in Computer Engineering and M.A in Education at the University of the Pacific. Prior to his current role\, he held design engineering positions as D.E.C\, SiByte\, Broadcom\, and Intel\, and has a background in custom circuit design\, automation\, methodologies\, and education. \nShare this:\n Share on LinkedIn (Opens in new window)\n LinkedIn\n \n Share on X (Opens in new window)\n X\n \n Share on Facebook (Opens in new window)\n Facebook\n Like this:Like Loading… URL:https://marketingeda.com/event/interactive-spice-model-verification-platform-me-pro/ CATEGORIES:EDA,Webinar ATTACH;FMTTYPE=image/jpeg:https://marketingeda.com/wp-content/uploads/primarius-October-1-2024.jpg END:VEVENT BEGIN:VEVENT DTSTART;TZID=America/Los_Angeles:20240926T100000 DTEND;TZID=America/Los_Angeles:20240926T110000 DTSTAMP:20240911T233717Z CREATED:20240911T233717Z LAST-MODIFIED:20240911T233717Z UID:8333-1727344800-1727348400@marketingeda.com SUMMARY:Learn How to Simulate 2D-TMD-Channel FETs with Atomistic Precision DESCRIPTION:Are 2D-TMD-channel transistors suitable candidates for the replacement of silicon ? Considering the extreme scaling down to a few atomic layers of the FET channel\, only an atomistic solution looks viable. In this context\, we show how the Victory Atomistic tool can answer this essential question thanks to quantum mechanics\, offering valuable support for the prototyping effort of a 2D transistor in a professional TCAD environment. \nWhat You Will Learn\n\nAn understanding of the physics and engineering of 2D TMD NR architectures at the atomic scale\nWhy to use Atomistic TCAD\nHow to simulate and prototype at the atomic level\nExample of a 2D-TMD TFET\n\n\n\n\n\n\nPresenter\n\n\n\n\nDr. Philippe Blaise\, Senior Application Engineer\, Silvaco\, Inc. \nDr. Philippe Blaise has been a senior application engineer in atomistic simulation at Silvaco’s TCAD Division for three years. Prior to joining Silvaco\, Dr. Blaise was a senior engineer specialized in atomistic simulation of new memory devices and transistors at CEA/LETI for 15 years. He is a former member of the IEEE IEDM Modelling and Simulation Committee. He is co-author of more than 50 papers in peer-review journals in the field and 30 contributions to conferences and workshops\, plus 5 patents and one book chapter.\nDr. Blaise holds a Master’s degree in applied mathematics from ENSIMAG engineering school and a Ph.D. in solid states physics from the Université Grenoble Alpes\, France. \n\n\n\n\n\nWHO SHOULD ATTEND:\n\n\n\n\nTCAD engineers\, device engineers\, process engineers\, product managers\, and engineering management. \n\n\nShare this:\n Share on LinkedIn (Opens in new window)\n LinkedIn\n \n Share on X (Opens in new window)\n X\n \n Share on Facebook (Opens in new window)\n Facebook\n Like this:Like Loading… URL:https://marketingeda.com/event/learn-how-to-simulate-2d-tmd-channel-fets-with-atomistic-precision/ CATEGORIES:EDA,Webinar ATTACH;FMTTYPE=image/jpeg:https://marketingeda.com/wp-content/uploads/Silvaco-September-26-2024.jpg END:VEVENT BEGIN:VEVENT DTSTART;TZID=America/New_York:20240918T100000 DTEND;TZID=America/New_York:20240918T110000 DTSTAMP:20240820T165235Z CREATED:20240820T165149Z LAST-MODIFIED:20240820T165235Z UID:8255-1726653600-1726657200@marketingeda.com SUMMARY:A Beginner's Guide to RTL-to-GDSII Front-End Flow DESCRIPTION:In this Training Webinar\, explore the concepts of RTL design\, design verification\, and coverage analysis while unveiling the exciting world of front-end design flow. Walk through the essential steps in creating integrated circuits\, the building blocks of modern electronics. \nThis webinar provides practical knowledge\, making it your gateway to understanding the magic behind RTL-to-GDSII front-end design flow. \nWe’ll break down the process into manageable stages\, from defining the chip’s functionality to its physical realization. We’ll investigate the front-end part of the RTL-to-GDSII flow—from specification to functional verification and design coverage—and explore: \n\nKey concepts of specifying chip behavior and performance\nHow to translate ideas into a digital blueprint and transform that into a design\nHow to ensure your design is free of errors\n\nWebinar: A Beginner’s Guide to RTL-to-GDSII Front-End Flow\nDate: Wednesday\, September 18\, 2024\nTime: 07:00 PDT San Jose / 10:00 EDT New York / 15:00 BST London / 16:00 CEST Munich / 17:00 IDT Jerusalem / 19:30 IST Bangalore / 22:00 CST Beijing \nShare this:\n Share on LinkedIn (Opens in new window)\n LinkedIn\n \n Share on X (Opens in new window)\n X\n \n Share on Facebook (Opens in new window)\n Facebook\n Like this:Like Loading… URL:https://marketingeda.com/event/beginners-guide-rtl-gdsii-front-end-flow/ CATEGORIES:EDA,Webinar ATTACH;FMTTYPE=image/jpeg:https://marketingeda.com/wp-content/uploads/Cadence-September-18-2024-1.jpg END:VEVENT BEGIN:VEVENT DTSTART;TZID=America/Los_Angeles:20240918T090000 DTEND;TZID=America/Los_Angeles:20240918T100000 DTSTAMP:20240906T215837Z CREATED:20240906T215234Z LAST-MODIFIED:20240906T215837Z UID:8304-1726650000-1726653600@marketingeda.com SUMMARY:Redefining Mobile Experiences with AI DESCRIPTION:The Arm platform is providing the foundation for the next wave of AI smartphones and laptops. As AI models rapidly evolve\, we’re seeing that software begins to outpace hardware\, requiring additional innovation at all levels of the compute stack. \nTo meet these growing demands\, the Arm platform offers a new compute solution for maximum performance and efficiency\, on leading process nodes. Join this webinar series to learn more about this solution\, including the latest Arm Armv9 CPUs and GPUs\, the benefits and opportunities of running AI on device\, and how to innovate and speed time to market. \nSession 1: The Arm Platform on Wednesday\, Sept 18\, 2024\n\n9:00 a.m. BST / 4:00 p.m. Beijing\n5:00 p.m. BST / 9:00 a.m. PT\n\nThis webinar covers: \n\nThe latest Arm technology\, Arm Compute Subsystems (CSS) for Client\, which helps push the boundaries of premium mobile experiences.\nFeatures\, benefits\, and performance enhancements of Armv9 based Arm Cortex CPUs and Immortalis and Mali GPUs.\nHow Arm partners can rapidly innovate and speed time to market.\nPerformance and efficiency enhancements that increase the responsiveness of GenAI.\nHow to unlock 3 nm PPA benefits with physical implementations.\n\nSpeaker: Kinjal Dave\, Senior Director Product Management\, Arm \nSecond Session – October 2nd \nShare this:\n Share on LinkedIn (Opens in new window)\n LinkedIn\n \n Share on X (Opens in new window)\n X\n \n Share on Facebook (Opens in new window)\n Facebook\n Like this:Like Loading… URL:https://marketingeda.com/event/redefining-mobile-experiences-with-ai/ CATEGORIES:IP,Webinar ATTACH;FMTTYPE=image/jpeg:https://marketingeda.com/wp-content/uploads/Arm-September-18-2024.jpg END:VEVENT BEGIN:VEVENT DTSTART;TZID=America/Los_Angeles:20240918T080000 DTEND;TZID=America/Los_Angeles:20240918T090000 DTSTAMP:20240813T192856Z CREATED:20240813T192856Z LAST-MODIFIED:20240813T192856Z UID:8231-1726646400-1726650000@marketingeda.com SUMMARY:Managing Constraints Like a Pro in OrCAD X DESCRIPTION:Join us in this constraint-focused webinar to learn all the best practices for managing constraints in your design with OrCAD X Presto PCB Editor. \nWe’ll cover everything from the basics of setting up spacing and physical constraints to advanced electrical constraints\, which are critical for HDI designs. \nThe webinar will feature a brief presentation\, a live demonstration using the NVIDIA Jetson Xavier Developer Kit Carrier Board\, and a Q&A session. \nTopics Covered:\n\nNavigating the constraint manager and reusing constraints\nCreating constraint sets\nSetting up physical and spacing constraints\nSetting up advanced constraints for HDI\nElectrical constraints (Propagation Delay\, Net Scheduling\, Differential Pairs)\nSetting up blind\, buried\, and microvias\nAnalysis setup\nPreview of the new constraints panel in OrCAD X Presto PCB Editor\n\n\nWe welcome PCB designers of all experience levels to join us. Enhance your expertise in managing basic and advanced constraints in your OrCAD X Presto designs! \n\nSPEAKERS: \nAdam Fuchs\, Principal Product Engineer\, Cadence \nHOST: \nSupreeth Mannava\, Senior Principal Product Manager\, Cadence \nShare this:\n Share on LinkedIn (Opens in new window)\n LinkedIn\n \n Share on X (Opens in new window)\n X\n \n Share on Facebook (Opens in new window)\n Facebook\n Like this:Like Loading… URL:https://marketingeda.com/event/managing-constraints-like-a-pro-in-orcad-x/ CATEGORIES:EDA,Webinar ATTACH;FMTTYPE=image/jpeg:https://marketingeda.com/wp-content/uploads/Cadence-September-18-2024.jpg END:VEVENT BEGIN:VEVENT DTSTART;TZID=America/Los_Angeles:20240912T120000 DTEND;TZID=America/Los_Angeles:20240912T130000 DTSTAMP:20240823T181126Z CREATED:20240823T181114Z LAST-MODIFIED:20240823T181126Z UID:8265-1726142400-1726146000@marketingeda.com SUMMARY:Unleash Performance\, Save Power: Mastering Processor Customization with the Tensilica Instruction Extension (TIE) Language DESCRIPTION:Join us for an engaging webinar where we show you how to turbocharge performance and minimize power consumption by harnessing the power of custom instructions using the TIE language. Don’t miss this opportunity to optimize your processors like never before! \nTIE enables you to compute and move data many times faster than conventional processors\, resulting in faster yet more power-efficient cores while maintaining full programmability and debugability. \nThis webinar will introduce users to the easy-to-use TIE language and techniques for accelerating computation that can be used to optimize processors for specific target applications. \nLearn how Tensilica TIE language can be implemented to: \n\nSignificantly save SOC Power\nTurbocharge SOC Performance\nMaster processor customization with custom instructions\n\nShare this:\n Share on LinkedIn (Opens in new window)\n LinkedIn\n \n Share on X (Opens in new window)\n X\n \n Share on Facebook (Opens in new window)\n Facebook\n Like this:Like Loading… URL:https://marketingeda.com/event/unleash-performance-save-power-mastering-processor-customization-with-the-tensilica-instruction-extension-tie-language/ CATEGORIES:EDA,IP,Webinar ATTACH;FMTTYPE=image/jpeg:https://marketingeda.com/wp-content/uploads/Cadence-September-12-2024-1.jpg END:VEVENT BEGIN:VEVENT DTSTART;TZID=America/Los_Angeles:20240912T100000 DTEND;TZID=America/Los_Angeles:20240912T110000 DTSTAMP:20240814T174526Z CREATED:20240814T174526Z LAST-MODIFIED:20240814T174526Z UID:8237-1726135200-1726138800@marketingeda.com SUMMARY:Leveraging Verisium Debug to Debug Digital-Mixed Signal Designs DESCRIPTION:Many of today’s designs that are primarily digital also contain analog components. We refer to such designs as “Digital-Mixed-Signal” or DMS designs. In this webinar\, we will demonstrate using the Verisium Debug App to debug such DMS designs. \n\n\n\n\n\n\n\n\n\n\n\n\nWhat You Will Learn \n\n\n\n\n\n\n\n\n\n\n\n\n\nHow Verisium Debug supports debugging Xcelium (Real Number Modeling) RNM and mixed Xcelium and Spectre simulations\nHow Verisium Debug can be used to debug User-Defined Nets (UDNs)\nThe analog waveform debug features of Verisium Debug\n\n\n\n\n\n\n\n\n\n\n\n\n\nWho Should Attend \n\n\n\n\n\n\n\n\n\n\n\n\nThis webinar is designed for design and verification engineers of all levels who need to debug Digital-Mixed-Signal designs when simulating using Xcelium Real Number Modeling (RNM) or mixed Xcelium/Spectre Digital-Mixed-Signal simulations. \n\n\n\n\n\n\n\n\n\n\n\n\nSpeakers \n\n\n\n\n\n\n\n\n\n\n\n\n\nDoug Koslow\, Product Engineering Architect\, Cadence\nRich Chang\, Product Marketing Director\, Cadence\n\n\n\n\n\n\n\nShare this:\n Share on LinkedIn (Opens in new window)\n LinkedIn\n \n Share on X (Opens in new window)\n X\n \n Share on Facebook (Opens in new window)\n Facebook\n Like this:Like Loading… URL:https://marketingeda.com/event/leveraging-verisium-debug-to-debug-digital-mixed-signal-designs/ CATEGORIES:EDA,Webinar ATTACH;FMTTYPE=image/jpeg:https://marketingeda.com/wp-content/uploads/Cadence-September-12-2024.jpeg END:VEVENT BEGIN:VEVENT DTSTART;TZID=America/Los_Angeles:20240912T100000 DTEND;TZID=America/Los_Angeles:20240912T110000 DTSTAMP:20240813T193558Z CREATED:20240813T193538Z LAST-MODIFIED:20240813T193558Z UID:8234-1726135200-1726138800@marketingeda.com SUMMARY:Addressing 3D-IC Power Integrity Design Challenges DESCRIPTION:Power network design and analysis of 3D-ICs is a major challenge because of the complex nature and large size of the power network. In addition\, designers must deal with the complexity of routing power through the interposer\, multiple dies\, through-silicon vias (TSVs)\, and through-dielectric vias (TDVs). In this webinar\, you will learn how the Cadence Integrity 3D-IC Platform and Voltus IC Power Integrity Solution provides: \n\nFully integrated solution for early planning and analysis of 3D-IC power networks\n3D-IC chip-centric power integrity signoff\nHierarchical methods that significantly improve the capacity and performance of power integrity signoff while maintaining a very high level of accuracy at signoff\n\nShare this:\n Share on LinkedIn (Opens in new window)\n LinkedIn\n \n Share on X (Opens in new window)\n X\n \n Share on Facebook (Opens in new window)\n Facebook\n Like this:Like Loading… URL:https://marketingeda.com/event/addressing-3d-ic-power-integrity-design-challenges/ CATEGORIES:EDA,IP,Webinar ATTACH;FMTTYPE=image/jpeg:https://marketingeda.com/wp-content/uploads/Cadence-September-12-2024.jpg END:VEVENT BEGIN:VEVENT DTSTART;TZID=America/Los_Angeles:20240911T080000 DTEND;TZID=America/Los_Angeles:20240911T090000 DTSTAMP:20240821T163437Z CREATED:20240821T163437Z LAST-MODIFIED:20240821T163437Z UID:8259-1726041600-1726045200@marketingeda.com SUMMARY:Questa Formal Verification IP AMBA: Achieve Protocol Compliance in Designs DESCRIPTION:Delve into how Questa Formal Verification IP (VIP) for the AMBA protocol ensures that designs incorporating AMBA adhere strictly to the protocol; all without the need for simulation. The solution integrates comprehensive protocol knowledge and provides user-friendly interfaces\, significantly reducing the setup time for verification environments. Optimized for top-tier performance and scalability\, Questa Formal VIP AMBA is the ideal tool for achieving high-efficiency and accurate protocol compliance. Don’t miss this opportunity to learn how to streamline your verification process and enhance your design workflows. \n  \nWhat You Will Learn:  \n\nChallenges in IP Integration\nUnderstand the common obstacles faced by designers and verification teams during IP integration and how to overcome them.\nBenefits of Formal Verification Ips\nDiscover the advantages of using formal verification IPs\, including enhanced accuracy and reduced need for simulation.\nCapabilities and Supported Protocols\nExplore the extensive capabilities of Questa Formal VIP AMBA and the range of protocols it supports.\nFrom Specification to Formal Properties\nLearn how protocol specifications are transformed into formal properties for effective verification.\nDebugging Protocol Violations\nGain insights into debugging techniques for protocol violations to ensure compliance and reliability.\n\n            \nWho Should Attend:  \n\nRTL Design Engineers\nDesign Integrators\nDesign Verification Engineers\n\nWhat/Which Products are Covered:   \n\nQuesta Formal VIP AMBA\nQuesta Formal VIP OnChip\nQuesta Check Register\n\n\n\nSpeaker:\n\n\n\n\n\n\nNicolae Tusinschi\nFormal Verification Solutions Product Manager\, Siemens EDA\n\n\n\n\nNicolae Tusinschi is a product manager for formal verification solutions at Siemens EDA. He holds a master’s degree combined between the University of Southampton and the University of Kaiserslautern. After a master’s thesis at Continental\, Nicolae joined OneSpin\, where he worked in QA\, then as a product specialist and later served as product owner for design verification tools at OneSpin. His key projects include integrating simulation coverage with formal metrics\, leveraging coverage results in the verification process\, formal verification of RISC-V cores. \n\n\n\nShare this:\n Share on LinkedIn (Opens in new window)\n LinkedIn\n \n Share on X (Opens in new window)\n X\n \n Share on Facebook (Opens in new window)\n Facebook\n Like this:Like Loading… URL:https://marketingeda.com/event/questa-formal-verification-ip-amba-achieve-protocol-compliance-in-designs/ CATEGORIES:EDA,IP,Webinar ATTACH;FMTTYPE=image/jpeg:https://marketingeda.com/wp-content/uploads/Siemens-Setember-11-2024.jpg END:VEVENT BEGIN:VEVENT DTSTART;TZID=America/Los_Angeles:20240910T100000 DTEND;TZID=America/Los_Angeles:20240910T110000 DTSTAMP:20240909T174044Z CREATED:20240909T174044Z LAST-MODIFIED:20240909T174044Z UID:8317-1725962400-1725966000@marketingeda.com SUMMARY:Faster Design TAT and Upscaled Team Productivity with Cadence’s True Hybrid Cloud DESCRIPTION:Join us for an informative webinar as we unveil the new hybrid cloud capabilities of our cloud solutions designed to revolutionize EDA workloads. Whether you need peak capacity for a short duration or want a front-to-back turnkey cloud environment\, our cloud solutions offer unparalleled flexibility and efficiency. \nWe will discuss how Cadence True Hybrid Cloud and Cadence Managed Cloud can optimize cost-efficiency and productivity for your design projects. \nDon’t miss our live demonstrations\, where we’ll showcase the rapid deployment of peak capacity in the cloud\, productivity benefits\, and robust security features. Plus\, discover how you can kickstart your journey with a 30-day free trial. \n\n\n\n\n\n\n\n\n\n\n\n\nWho Should Attend \n\n\n\n\n\n\n\n\n\n\n\n\nThis webinar is designed for chip designers\, Cloud IT architects\, CAD platform teams\, and business decision makers. \n\n\n\n\n\n\n\n\n\n\n\n\nSpeakers \n\n\n\n\n\n\n\n\n\n\n\n\n\nKetan Joshi\, Sr. Business Development Group Director\, Cadence\nMichael Reed\, Sr. Staff Systems Engineer\, Cadence\n\n\n\n\n\n\n\nShare this:\n Share on LinkedIn (Opens in new window)\n LinkedIn\n \n Share on X (Opens in new window)\n X\n \n Share on Facebook (Opens in new window)\n Facebook\n Like this:Like Loading… URL:https://marketingeda.com/event/faster-design-tat-and-upscaled-team-productivity-with-cadences-true-hybrid-cloud/ CATEGORIES:EDA,Webinar ATTACH;FMTTYPE=image/jpeg:https://marketingeda.com/wp-content/uploads/Cadence-September-10-2024.jpg END:VEVENT BEGIN:VEVENT DTSTART;TZID=America/Los_Angeles:20240910T090000 DTEND;TZID=America/Los_Angeles:20240910T100000 DTSTAMP:20240820T162341Z CREATED:20240820T162341Z LAST-MODIFIED:20240820T162341Z UID:8252-1725958800-1725962400@marketingeda.com SUMMARY:Can AI make cameras see in the dark? DESCRIPTION:Abstract\n  \n\nAs cameras become ubiquitous in applications such as surveillance\, mobile\, drones\, and automotive systems\, achieving clear vision 24/7 under any condition—including extreme low light and high dynamic range scenarios—has become essential. By leveraging Edge AI processors\, a software ISP based on neural network technology can process and optimize video in real-time\, surpassing human vision capabilities in these challenging conditions.\nIn this webinar\, we will explore how to harness the power of Ceva’s NPU alongside Visionary.ai’s advanced AI software Image Signal Processing (ISP) to significantly enhance video quality across various camera-enabled applications. Visionary.ai utilizes Neural Processing Units (NPUs) to boost camera performance\, especially in demanding environments like extreme low-light and high dynamic range (HDR) scenarios.\nFinally\, we will introduce an available reference design for this joint solution and showcase the impressive results achieved. \nJoin Ceva and Visionary.ai experts to learn about: \n\nThe power of Edge AI for computer vision\nModern NPU architecture fundamentals\nTrue Night Vision software ISP\nThe role of video denoising in solving the low-light challenge\nThe technical challenges to implement an AI based ISP on an NPU\nHow can Ceva and Visionary.ai enhance your camera enabled application\n\n\nTarget Audience\n  \nVision system architects\, hardware and software engineers\, and product managers targeting camera enabled devices\, that are looking to enhance their product ability to cope with extreme low-light conditions using the power of Edge AI.\n\nSpeakers\n\n\n\n\n\n\n\nRonny Vatelmacher\nDirector of Product Marketing\, Vision and AI\, Ceva\n\n\n\n\n\n\n\n\n\nDavid Jarmon\nSVP Worldwide Sales\, Visionary.ai\n\n\n\nShare this:\n Share on LinkedIn (Opens in new window)\n LinkedIn\n \n Share on X (Opens in new window)\n X\n \n Share on Facebook (Opens in new window)\n Facebook\n Like this:Like Loading… URL:https://marketingeda.com/event/can-ai-make-cameras-see-in-the-dark/ CATEGORIES:IP,Webinar ATTACH;FMTTYPE=image/jpeg:https://marketingeda.com/wp-content/uploads/Ceva-September-10-2024.jpg END:VEVENT BEGIN:VEVENT DTSTART;TZID=America/Los_Angeles:20240905T110000 DTEND;TZID=America/Los_Angeles:20240905T120000 DTSTAMP:20240903T175441Z CREATED:20240903T175441Z LAST-MODIFIED:20240903T175441Z UID:8291-1725534000-1725537600@marketingeda.com SUMMARY:Using OSVVM’s AXI4 Verification Components DESCRIPTION:Abstract: \nThis “Getting Started” presentation is for engineers who need to use the OSVVM AXI4 verification components (VCs) in their testbenches. Part 2 of this presentation focuses on how to write tests and configure the AXI4 VCs. \nAXI4 VCs are probably the most complex VCs in the OSVVM library. This complexity is due to the AXI4 interface having 5 independent interfaces: Write Address\, Write Data\, Write Response\, Read Address\, and Read Data.   Going further\, the interface supports user configurable optional aspects of the interface – such as the ID and User fields. \nIn this presentation we examine the structure of OSVVM test cases\, the AXI4 transaction API\, how to do byte transfers\, how to do burst transfers\, how to handle arrays of VCs\, how to configure AXI4 VC options\, how to randomize delays for xValid or xReady\, and how the test case can directly read or write values in the Axi4Memory. \nAs we look at the OSVVM transaction API we will note that it does not specify the byte enables. Instead\, OSVVM determines the byte enables by looking at the width of the data and the lower bits of the address. \nOSVVM’s burst interface is supported by FIFOs that are in the transaction interface. These FIFOs allow any size of std_logic_vector value to be pushed into them. This allows the burst interface to be used in either byte mode or word mode. In byte mode\, the burst is a sequence of bytes that are assembled by the VC into interface words. This allows OSVVM to create test cases that are independent of the actual data bus width. \nAbout OSVVM \n\nOSVVM is a suite of libraries designed to streamline your VHDL entire verification process\, boosting productivity and reducing development time. Each library provides independent capabilities\, allowing selective adoption and a learn-as-you-go approach. Whether using directed or random testing\, OSVVM facilitates writing concise and readable test cases for both unit/RTL tests and complex FPGA and ASIC tests. \nOSVVM provides VHDL with verification capabilities that rival SystemVerilog + UVM. These include transaction-level modeling\, verification components\, co-simulation with software\, randomized test generation\, self-checking test support\, verification data structures\, comprehensive test reporting in HTML and text\, and synchronization primitives.\n\nWith OSVVM and a good team lead\, any VHDL engineer can do verification – and have fun doing it. As a result\, having your entire team united in using OSVVM will simplify deploying VHDL engineers to projects.\n\nSynthWorks has been using OSVVM for 25+ years in our training classes and consulting work. During that time\, we have innovated new capabilities and evolved our existing ones to increase re-use and reduce effort and time spent.\n\nWhy VHDL for verification? According to the 2022 Wilson Research Group Functional Verification Study\, in the FPGA market\, 66% use VHDL for design\, 58% use VHDL for verification\, and 28% use OSVVM. Hence\, VHDL is #1 for FPGA development and OSVVM is #1 for VHDL verification.\n\nWebinar Duration:  \n\n50 min presentation/live demo\n15 min Q&A\n\nPresenter Bio: \n \nJim Lewis\, VHDL Design and Verification Expert\, Trainer\, OSVVM developer\, and IEEE VHDL Chair \nJim Lewis is an innovator and leader in the VHDL community. He has 30 plus years of design and teaching experience. He is the Chair of the IEEE 1076 VHDL Standards Working Group. He is a co-founder of the Open Source VHDL Verification Methodology (OSVVM) and the chief architect of the packages and methodology. He is an expert VHDL trainer for SynthWorks Design Inc. In his design practice\, he has created designs for print servers\, IMA E1/T1 networking\, fighter jets\, video phones\, and space craft. \nWhether teaching\, developing OSVVM\, consulting on VHDL design and verification projects\, or working on the IEEE VHDL standard\, Mr. Lewis brings a deep understanding of VHDL to architect solutions that solve difficult problems in simple ways. \nShare this:\n Share on LinkedIn (Opens in new window)\n LinkedIn\n \n Share on X (Opens in new window)\n X\n \n Share on Facebook (Opens in new window)\n Facebook\n Like this:Like Loading… URL:https://marketingeda.com/event/using-osvvms-axi4-verification-components/ CATEGORIES:EDA,Webinar ATTACH;FMTTYPE=image/jpeg:https://marketingeda.com/wp-content/uploads/Aldec-September-5-2024.jpg END:VEVENT BEGIN:VEVENT DTSTART;TZID=America/New_York:20240905T100000 DTEND;TZID=America/New_York:20240905T110000 DTSTAMP:20240807T213739Z CREATED:20240807T213739Z LAST-MODIFIED:20240807T213739Z UID:8219-1725530400-1725534000@marketingeda.com SUMMARY:Enhanced Packaging Performance and Manufacturing with Physics-Based 3D Simulation DESCRIPTION:About this webinar\nDigital engineering is ramping up across the CPG\, healthcare and wider packaging sector. Packaging engineers are tasked with producing fit-for-purpose packaging that is optimised for customer-use\, transportation\, storage and for production-line filling/handling. In addition\, manufacturing the packaging containers as optimally as possible to avoid defects is vitally important. All in the landscape of sustainability. \nAnsys provides leading physics-based 3D simulation tools applicable to a wide range of scenarios from filling of liquids and solids\, drop-testing\, thermal management\, vibration under transportation\, top-load strength testing\, conveying\, package crimping\, blow moulding\, thermoforming\, heat-sealing and board-creasing. \nJoin this webinar to be updated on the latest virtual engineering simulation capabilities from Ansys in the packaging domain. \n  \nWhat you will learn\n\nThe use of physics-based 3D simulation to gain engineering insight into the performance of packaging whilst in the hands of an end-user\, in storage\, under transportation and during manufacture.\nThe state of the art from an Ansys perspective on the use of digital engineering to drive innovation\, efficiency and sustainability in the packaging sector.\nThe use of Ansys Granta Selector software for smarter material selection\n\n  \nWho should attend\n\nPackaging engineers and designers interested in the use of simulation in the packaging industry.\nMaterial scientists involved in the selection of materials for packaging.\nCurrent users of CFD\, Discrete Element Modelling\, structural and thermal simulation FEA tools in the packaging domain.\n\n  \nSpeakers\n\nMikael Schill\, Senior Manager and Application Engineering\, Ansys\nMarcus Redhe\, Director Application Engineering\, Ansys\n\nShare this:\n Share on LinkedIn (Opens in new window)\n LinkedIn\n \n Share on X (Opens in new window)\n X\n \n Share on Facebook (Opens in new window)\n Facebook\n Like this:Like Loading… URL:https://marketingeda.com/event/enhanced-packaging-performance-and-manufacturing-with-physics-based-3d-simulation/ CATEGORIES:EDA,Webinar ATTACH;FMTTYPE=image/jpeg:https://marketingeda.com/wp-content/uploads/Ansys-September-5-2024.jpg END:VEVENT BEGIN:VEVENT DTSTART;TZID=America/New_York:20240904T100000 DTEND;TZID=America/New_York:20240904T110000 DTSTAMP:20240815T155544Z CREATED:20240815T155544Z LAST-MODIFIED:20240815T155544Z UID:8245-1725444000-1725447600@marketingeda.com SUMMARY:Hardware-Accurate Digital Twins in Defense: Case Study DESCRIPTION:The defense industry is increasingly seeking innovative approaches to accelerate system development while ensuring reliability. Hardware-accurate digital twins offer a promising solution. This webinar will explore the concept of hardware-accurate digital twins and their application in defense. \nJoin Cadence and Northrop Grumman as we delve into a real-world case study demonstrating the power of digital twins in defense program execution. Discover how hardware-accurate digital twins can be leveraged to streamline development processes\, reduce risks\, and improve overall system performance. This case study will give you practical insights into implementing digital twins in your next program development. \n\nAttendees Will Learn \n\nThe definition and benefits of hardware-accurate digital twins\nPractical applications in the defense industry\nA detailed case study showcasing successful implementation\nBest practices for adopting digital twin technology\n\n\nSpeakers \nAdam Sherer\, Account Technical Director\, Cadence\nMichael Gowan\, Verification Engineer\, Northrop Grumman\nBilly Gomez\, Sr. Principal Engineer Embedded Software\, Northrop Grumman \nShare this:\n Share on LinkedIn (Opens in new window)\n LinkedIn\n \n Share on X (Opens in new window)\n X\n \n Share on Facebook (Opens in new window)\n Facebook\n Like this:Like Loading… URL:https://marketingeda.com/event/hardware-accurate-digital-twins-in-defense-case-study/ CATEGORIES:EDA,Webinar ATTACH;FMTTYPE=image/jpeg:https://marketingeda.com/wp-content/uploads/Cadence-September-4-2025.jpg END:VEVENT BEGIN:VEVENT DTSTART;TZID=America/Los_Angeles:20240904T090000 DTEND;TZID=America/Los_Angeles:20240904T100000 DTSTAMP:20240806T194128Z CREATED:20240806T194128Z LAST-MODIFIED:20240806T194128Z UID:8205-1725440400-1725444000@marketingeda.com SUMMARY:Elevate Your Analog Layout Design to New Heights DESCRIPTION:Are you ready to transform your career and become a master of analog layout design? Look no further than The Advanced Analog Layout Course! This course is meticulously crafted to enhance your physical design skills\, guiding you through the advanced techniques essential for creating top-notch\, well-matched\, and noise-resistant layouts on a CMOS process. \nLearn Anytime\, Anywhere! Our course is delivered through a user-friendly online portal\, granting you the power to learn at your own pace. Enjoy the flexibility of completing modules and watching nearly 100 instructional videos whenever it suits you best. \nTailored for Excellence! Whether you’re a seasoned layout engineer aiming to refine your skills or a front-end schematic designer eager to enhance your design methods\, this course is designed for you. With over 19 hours of content\, including seven comprehensive modules and regular assessments\, you’ll be equipped to produce more efficient and superior quality layouts. \nComprehensive Learning Experience! Dive into a wealth of knowledge with our extensive video library\, totalling over 19 hours of expert content. Our regular assessments ensure that you’re on track\, solidifying your understanding and boosting your confidence. \nJoin the ranks of the industry’s best and make your mark in the world of analog layout design. Enroll in The Advanced Analog Layout Course today and start your journey to becoming an analog layout virtuoso! \nReady to take the next step in your career? Join this webinar to learn more and sign up for the course that will set you apart in the competitive field of analog layout design. \nShare this:\n Share on LinkedIn (Opens in new window)\n LinkedIn\n \n Share on X (Opens in new window)\n X\n \n Share on Facebook (Opens in new window)\n Facebook\n Like this:Like Loading… URL:https://marketingeda.com/event/elevate-your-analog-layout-design-to-new-heights/ CATEGORIES:IP,Webinar ATTACH;FMTTYPE=image/jpeg:https://marketingeda.com/wp-content/uploads/IC-Mask-Design-September-2024.jpg END:VEVENT BEGIN:VEVENT DTSTART;TZID=Europe/London:20240903T120000 DTEND;TZID=Europe/London:20240903T130000 DTSTAMP:20240731T161732Z CREATED:20240731T161715Z LAST-MODIFIED:20240731T161732Z UID:8191-1725364800-1725368400@marketingeda.com SUMMARY:DVClub Europe - September 2024 DESCRIPTION:This DVClub event will have talks on verification of low power features of VLSI designs\, discussing strategies for accurately measuring power consumption and ensuring that power-saving mechanisms are effective. Additionally\, speakers will share insights on how to simulate and analyze different power scenarios to identify potential issues and optimize power management techniques. Attendees will have the opportunity to learn best practices for low power verification and gain valuable knowledge on how to successfully implement energy-efficient designs in their projects. Overall\, this event promises to provide valuable insights and practical strategies for ensuring the success of low power verification in VLSI designs. \nAgenda (BST)\n12:00 Welcome and Introduction – Mike Bartley\, Tessolve\n12:00 Satinder Paul\n12:20 Synopsys\n12:40 TBD\n13:00 Close \nShare this:\n Share on LinkedIn (Opens in new window)\n LinkedIn\n \n Share on X (Opens in new window)\n X\n \n Share on Facebook (Opens in new window)\n Facebook\n Like this:Like Loading… URL:https://marketingeda.com/event/dvclub-europe-september-2024/ CATEGORIES:EDA,Webinar ATTACH;FMTTYPE=image/jpeg:https://marketingeda.com/wp-content/uploads/DVClub-Europe-2024.jpg END:VEVENT BEGIN:VEVENT DTSTART;TZID=America/Los_Angeles:20240829T100000 DTEND;TZID=America/Los_Angeles:20240829T110000 DTSTAMP:20240808T172706Z CREATED:20240808T172706Z LAST-MODIFIED:20240808T172706Z UID:8222-1724925600-1724929200@marketingeda.com SUMMARY:Micron Utilizes Silvaco’s Fab Technology Co-Optimization for Development and Manufacturing of Memory Technologies DESCRIPTION:Memory products from Micron Technology\, such as DRAM components and 3D NAND\, are propelling the advancement of process technologies. Innovative modeling methods are required to tackle the complexities in fabricating structures and to evaluate process variation effects on electrical performance. \nThis webinar highlights how Micron Technology utilizes Silvaco’s Fab Technology Co-Optimization (FTCOTM) platform for the development and manufacturing of advanced memory technologies. Use cases demonstrate the application of virtual process models\, sensitivity analysis\, and stress modeling to optimize semiconductor processes. The collaborative effort between Silvaco and Micron shows how to build a digital twin of a fabrication process\, enabling a transformative solution for scaling memory technologies. \n\n\n\n\nPresenter\n\n\n\n\nSumeet Pandey\, Distinguished Member of Technical Staff\, Micron Technology \n\n\n\n\nWHO SHOULD ATTEND:\n\n\n\n\nTCAD engineers\, fab engineers\, process engineers\, product managers\, and engineering management. \n\n\nShare this:\n Share on LinkedIn (Opens in new window)\n LinkedIn\n \n Share on X (Opens in new window)\n X\n \n Share on Facebook (Opens in new window)\n Facebook\n Like this:Like Loading… URL:https://marketingeda.com/event/micron-utilizes-silvacos-fab-technology-co-optimization-for-development-and-manufacturing-of-memory-technologies/ CATEGORIES:EDA,Webinar ATTACH;FMTTYPE=image/jpeg:https://marketingeda.com/wp-content/uploads/Silvaco-August-29-2024.jpg END:VEVENT BEGIN:VEVENT DTSTART;TZID=America/Los_Angeles:20240828T080000 DTEND;TZID=America/Los_Angeles:20240828T090000 DTSTAMP:20240809T162606Z CREATED:20240809T162606Z LAST-MODIFIED:20240809T162606Z UID:8225-1724832000-1724835600@marketingeda.com SUMMARY:Design\, Integrate\, Analyze and Manage with Allegro X DESCRIPTION:Designing PCBs in today’s world means using multiple tools to get the job done. The Allegro X Design Platform allows you to access all these tools in one unified design environment. \nJoin us to discuss how you can reduce your cycle time\, ensure product reliability and get first-time-right designs with Allegro X. \n\nTopics we’ll cover during the webinar: \n\nHierarchical and multi-board design\nReliability analysis covering electrical overstress (EOS) and mean time between failure (MTBF)\nFloor planning and in-design analysis with integrated Cadence Celsius Solver\nConstraint-driven design to ensure functionality and manufacturability\nAnd how to utilize DesignTrue DFM to reduce costly manufacturing failures\n\n\nSpeakers: \nSaankhya Parekh\, Lead Product Engineer\, Cadence \nPablo Barraza\, Lead Application Engineer\, Cadence \nHost: \nSupreeth Mannava\, Sr. Principal Product Manager\, Cadence \nShare this:\n Share on LinkedIn (Opens in new window)\n LinkedIn\n \n Share on X (Opens in new window)\n X\n \n Share on Facebook (Opens in new window)\n Facebook\n Like this:Like Loading… URL:https://marketingeda.com/event/design-integrate-analyze-and-manage-with-allegro-x/ CATEGORIES:EDA,Webinar ATTACH;FMTTYPE=image/jpeg:https://marketingeda.com/wp-content/uploads/Cadence-August-28-2024.jpg END:VEVENT BEGIN:VEVENT DTSTART;TZID=America/Los_Angeles:20240822T110000 DTEND;TZID=America/Los_Angeles:20240822T120000 DTSTAMP:20240819T162836Z CREATED:20240819T162836Z LAST-MODIFIED:20240819T162836Z UID:8248-1724324400-1724328000@marketingeda.com SUMMARY:Using OSVVM’s AXI4 Verification Components: Pt 1 Creating the AXI4 Testbench / Test Harness DESCRIPTION:European Session \nAbstract: \nThis “Getting Started” presentation is for engineers who need to use the OSVVM AXI4 verification components (VCs) in their testbenches. Part 1 of this presentation provides a detailed walkthrough of creating a testbench environment that uses AXI4 VCs. \nAXI4 VCs are probably the most complex VCs in the OSVVM library. This complexity is due to the AXI4 interface having five independent interfaces: Write Address\, Write Data\, Write Response\, Read Address\, and Read Data. Going further\, the interface supports user configurable optional aspects of the interface – such as the ID and User fields. \nIn this presentation we examine the details of the test harness including the required context references\, configuring the transaction interface\, configuring the AXI interface\, creating clock and reset\, connecting the DUT to the OSVVM AXI interface record\, and connecting to the AXI VCs. \nWe continue by examining how to size the AXI4 interface by sizing the unconstrained record elements of the AXI4 interface and OSVVM transaction interface records. \nWe wrap up by looking at how to use AXI4 VCs inside a DUT – such as with Zynq. In this situation\, the DUT does not have a port for the transaction interface(s). To address this use model\, OSVVM provides another set of AXI4 VCs that use OSVVM’s virtual transaction interface (VTI). These VCs all have Vti in their name\, such as Axi4ManagerVti.vhd. \nThe Zynq subordinate interfaces (such as Axi4Memory) can share the same memory space. As a result\, we look at how OSVVM configures multiple instances of the Axi4Memory to share their internal address space. \n\nAbout OSVVM \nOSVVM is a suite of libraries designed to streamline your VHDL entire verification process\, boosting productivity and reducing development time. Each library provides independent capabilities\, allowing selective adoption and a learn-as-you-go approach. Whether using directed or random testing\, OSVVM facilitates writing concise and readable test cases for both unit/RTL tests and complex FPGA and ASIC tests. \nOSVVM provides VHDL with verification capabilities that rival SystemVerilog + UVM. These include transaction-level modeling\, verification components\, co-simulation with software\, randomized test generation\, self-checking test support\, verification data structures\, comprehensive test reporting in HTML and text\, and synchronization primitives.\n\nWith OSVVM and a good team lead\, any VHDL engineer can do verification – and have fun doing it. As a result\, having your entire team united in using OSVVM will simplify deploying VHDL engineers to projects.\n\nSynthWorks has been using OSVVM for 25+ years in our training classes and consulting work. During that time\, we have innovated new capabilities and evolved our existing ones to increase re-use and reduce effort and time spent.\n\nWhy VHDL for verification? According to the 2022 Wilson Research Group Functional Verification Study\, in the FPGA market\, 66% use VHDL for design\, 58% use VHDL for verification\, and 28% use OSVVM. Hence\, VHDL is #1 for FPGA development and OSVVM is #1 for VHDL verification.\n  \n\nAgenda\n\n50 min presentation/live demo\n10 min Q&A\n\nPresenter Bio: \n \nJim Lewis\, VHDL Design and Verification Expert\, Trainer\, OSVVM developer\, and IEEE VHDL Chair \nJim Lewis is an innovator and leader in the VHDL community. He has 30 plus years of design and teaching experience. He is the Chair of the IEEE 1076 VHDL Standards Working Group. He is a co-founder of the Open Source VHDL Verification Methodology (OSVVM) and the chief architect of the packages and methodology. He is an expert VHDL trainer for SynthWorks Design Inc. In his design practice\, he has created designs for print servers\, IMA E1/T1 networking\, fighter jets\, video phones\, and space craft. \nWhether teaching\, developing OSVVM\, consulting on VHDL design and verification projects\, or working on the IEEE VHDL standard\, Mr. Lewis brings a deep understanding of VHDL to architect solutions that solve difficult problems in simple ways. \nShare this:\n Share on LinkedIn (Opens in new window)\n LinkedIn\n \n Share on X (Opens in new window)\n X\n \n Share on Facebook (Opens in new window)\n Facebook\n Like this:Like Loading… URL:https://marketingeda.com/event/using-osvvms-axi4-verification-components-pt-1-creating-the-axi4-testbench-test-harness/ CATEGORIES:EDA,Webinar ATTACH;FMTTYPE=image/jpeg:https://marketingeda.com/wp-content/uploads/Aldec-August-22-2024.jpg END:VEVENT BEGIN:VEVENT DTSTART;TZID=America/Los_Angeles:20240820T110000 DTEND;TZID=America/Los_Angeles:20240820T130000 DTSTAMP:20240725T163046Z CREATED:20240725T163046Z LAST-MODIFIED:20240725T163046Z UID:8180-1724151600-1724158800@marketingeda.com SUMMARY:Mastering EMC Simulations for Electronic Designs DESCRIPTION:Overview\nElectromagnetic Compatibility (EMC) simulation is critical for ensuring that electronic devices comply with regulatory standards and perform optimally in their intended environments. As the complexity of electronic systems increases\, the importance of EMC simulation grows\, allowing engineers to predict and mitigate potential electromagnetic interference (EMI) issues before physical prototypes are built. \nFor EMC and product design engineers\, it can be challenging to understand how to effectively use simulation tools. This hands-on session with experts in full-device simulation offers a unique opportunity for engineers to dive into the world of EMC simulation. This session will provide practical experience\, demystifying the simulation process and empowering engineers with the knowledge to implement simulations early in the design phase. Experts will offer insights into best practices\, common pitfalls to avoid\, and strategies for interpreting simulation results. \nBy participating in such a session\, engineers can gain a deeper understanding of the nuances of EMC simulation. They learn to set up simulations that model their products’ real-world behavior\, identify potential EMI issues\, and explore design modifications to enhance EMC performance. This proactive approach ensures compliance with regulatory standards and contributes to the final product’s overall reliability and quality. \nEMC simulation is more than just a compliance checkbox; it’s a strategic tool that\, when used effectively\, can significantly improve product design. Join this hands-on session guided by experts created for engineers looking to master EMC simulation and integrate it into their design process. It’s an investment in knowledge that will pay dividends throughout the product’s lifecycle. \n  \nWhat attendees will learn\n\nCAD File Preparation: Master importing mechanical CAD designs\, assigning materials\, and preparing for simulations.\n\n\nPCB and Package Setup: Discover the steps to import electronic design files for PCBs and packages\, including automation of the setup process.\n\n\nCable Specification: Gain hands-on experience in defining cables through co-simulation with multi-conductor transmission line solvers.\n\n\nComponent Modeling: Understand how to represent components using ideal or SPICE circuit models for co-simulation with 3D geometries.\n\n\nPerformance Evaluation: Learn to transform simulation results into formats that facilitate comparison with standard measurements for device performance assessment.\n\n  \nWho should attend\n\nFor Electromagnetic Compatibility Engineers: If your expertise lies in heuristic design guidelines and physical testing for compliance\, are you considering enhancing your capabilities with engineering simulation?\n\n\nFor Mechanical Design Engineers: Engaged in creating products with EMC requirements? Explore user-friendly simulation tools that can guide you toward compliance.\n\n\nFor RF Engineers: Charged with safeguarding your RF designs from the inadvertent interference of surrounding electronics? Discover methods to assess and mitigate RF desensitization risks earlier in the design process.\n\n\nFor Electrical Engineers Involved in designing PCBs and integrating components that must adhere to EMC regulations: Assess the need to account for the influence of enclosures and cables on EMC and signal and power integrity.\n\nShare this:\n Share on LinkedIn (Opens in new window)\n LinkedIn\n \n Share on X (Opens in new window)\n X\n \n Share on Facebook (Opens in new window)\n Facebook\n Like this:Like Loading… URL:https://marketingeda.com/event/mastering-emc-simulations-for-electronic-designs/ CATEGORIES:EDA,Webinar ATTACH;FMTTYPE=image/jpeg:https://marketingeda.com/wp-content/uploads/Ansys-august-20-2024.jpg END:VEVENT BEGIN:VEVENT DTSTART;TZID=America/Los_Angeles:20240815T110000 DTEND;TZID=America/Los_Angeles:20240815T120000 DTSTAMP:20240809T165235Z CREATED:20240809T165235Z LAST-MODIFIED:20240809T165235Z UID:8228-1723719600-1723723200@marketingeda.com SUMMARY:Why Should Our Team be Using VHDL + OSVVM for Verification? DESCRIPTION:Abstract: \nThis is a high-level presentation that identifies the key aspects of a modern verification methodology and shows how to achieve them with OSVVM. This is a great presentation to share with your management about why OSVVM (and OSVVM training) is important for your team. \nDescription: \nDeveloping and deploying a verification methodology can be costly and time consuming. Going without one will be even more costly due to bugs escaping into production hardware systems.\n\nOpen Source VHDL Verification Methodology (OSVVM) provides the VHDL community with an already developed\, open-source solution. OSVVM implements all of the capabilities of a modern verification methodology: transaction-based testing\, a verification framework\, verification components\, self-checking tests\, messaging handling\, error tracking\, requirements tracking\, constrained random testing\, scoreboards\, functional coverage\, co simulation with software\, test automation\, and a comprehensive set of test reports.\n\nThis presentation examines how these capabilities will benefit your projects.\n\nSystemVerilog+UVM also provides a similar set of capabilities. Unfortunately\, SV+UVM ended up absurdly complex to use – instead of using a module (entity/architecture in VHDL) with its built-in concurrency\, SV+UVM uses OO\, sequential code\, and fork and join (to get concurrency). As a result\, SV has failed to unify the design and verification communities.\n\nVHDL+OSVVM on the other hand uses entity/architectures to create verification components and libraries of subprograms (procedures and functions) to extend VHDL into a complete verification language. In doing this\, OSVVM creates verification capabilities that rival SystemVerilog+UVM while at the same time it uses VHDL language elements that are familiar to VHDL design engineers.\n\nAs a result\, with VHDL+OSVVM and a good verification lead\, any VHDL engineer can do verification as well as RTL design.\n\n\nAbout OSVVM \nOSVVM is a suite of libraries designed to streamline your VHDL entire verification process\, boosting productivity and reducing development time. Each library provides independent capabilities\, allowing selective adoption and a learn-as-you-go approach. Whether using directed or random testing\, OSVVM facilitates writing concise and readable test cases for both unit/RTL tests and complex FPGA and ASIC tests. \nOSVVM provides VHDL with verification capabilities that rival SystemVerilog + UVM. These include transaction-level modeling\, verification components\, co-simulation with software\, randomized test generation\, self-checking test support\, verification data structures\, comprehensive test reporting in HTML and text\, and synchronization primitives.\n\nWith OSVVM and a good team lead\, any VHDL engineer can do verification – and have fun doing it. As a result\, having your entire team united in using OSVVM will simplify deploying VHDL engineers to projects.\n\nSynthWorks has been using OSVVM for 25+ years in our training classes and consulting work. During that time\, we have innovated new capabilities and evolved our existing ones to increase re-use and reduce effort and time spent.\n\nWhy VHDL for verification? According to the 2022 Wilson Research Group Functional Verification Study\, in the FPGA market\, 66% use VHDL for design\, 58% use VHDL for verification\, and 28% use OSVVM. Hence\, VHDL is #1 for FPGA development and OSVVM is #1 for VHDL verification.\n  \n\nAgenda\n\n50 min presentation/live demo\n10 min Q&A\n\n  \n\n\n\n\n\n\n\n\n\n\n\n\n\n\n\n\n\n\n\n\n\n\n\n\n\n\n\n\n\n\n\n\n\nPresenter Bio: \n \nJim Lewis\, VHDL Design and Verification Expert\, Trainer\, OSVVM developer\, and IEEE VHDL Chair \nJim Lewis is an innovator and leader in the VHDL community. He has 30 plus years of design and teaching experience. He is the Chair of the IEEE 1076 VHDL Standards Working Group. He is a co-founder of the Open Source VHDL Verification Methodology (OSVVM) and the chief architect of the packages and methodology. He is an expert VHDL trainer for SynthWorks Design Inc. In his design practice\, he has created designs for print servers\, IMA E1/T1 networking\, fighter jets\, video phones\, and space craft.\nWhether teaching\, developing OSVVM\, consulting on VHDL design and verification projects\, or working on the IEEE VHDL standard\, Mr. Lewis brings a deep understanding of VHDL to architect solutions that solve difficult problems in simple ways. \n\n\n\n\n\n\n\nShare this:\n Share on LinkedIn (Opens in new window)\n LinkedIn\n \n Share on X (Opens in new window)\n X\n \n Share on Facebook (Opens in new window)\n Facebook\n Like this:Like Loading… URL:https://marketingeda.com/event/why-should-our-team-be-using-vhdl-osvvm-for-verification/ CATEGORIES:EDA,Webinar ATTACH;FMTTYPE=image/jpeg:https://marketingeda.com/wp-content/uploads/Aldec-AUgust-15-2024.jpg END:VEVENT END:VCALENDAR