BEGIN:VCALENDAR VERSION:2.0 PRODID:-//Marketing EDA - ECPv6.16.4.1//NONSGML v1.0//EN CALSCALE:GREGORIAN METHOD:PUBLISH X-WR-CALNAME:Marketing EDA X-ORIGINAL-URL:https://marketingeda.com X-WR-CALDESC:Events for Marketing EDA REFRESH-INTERVAL;VALUE=DURATION:PT1H X-Robots-Tag:noindex X-PUBLISHED-TTL:PT1H BEGIN:VTIMEZONE TZID:America/Los_Angeles BEGIN:DAYLIGHT TZOFFSETFROM:-0800 TZOFFSETTO:-0700 TZNAME:PDT DTSTART:20230312T100000 END:DAYLIGHT BEGIN:STANDARD TZOFFSETFROM:-0700 TZOFFSETTO:-0800 TZNAME:PST DTSTART:20231105T090000 END:STANDARD BEGIN:DAYLIGHT TZOFFSETFROM:-0800 TZOFFSETTO:-0700 TZNAME:PDT DTSTART:20240310T100000 END:DAYLIGHT BEGIN:STANDARD TZOFFSETFROM:-0700 TZOFFSETTO:-0800 TZNAME:PST DTSTART:20241103T090000 END:STANDARD BEGIN:DAYLIGHT TZOFFSETFROM:-0800 TZOFFSETTO:-0700 TZNAME:PDT DTSTART:20250309T100000 END:DAYLIGHT BEGIN:STANDARD TZOFFSETFROM:-0700 TZOFFSETTO:-0800 TZNAME:PST DTSTART:20251102T090000 END:STANDARD END:VTIMEZONE BEGIN:VTIMEZONE TZID:America/New_York BEGIN:DAYLIGHT TZOFFSETFROM:-0500 TZOFFSETTO:-0400 TZNAME:EDT DTSTART:20230312T070000 END:DAYLIGHT BEGIN:STANDARD TZOFFSETFROM:-0400 TZOFFSETTO:-0500 TZNAME:EST DTSTART:20231105T060000 END:STANDARD BEGIN:DAYLIGHT TZOFFSETFROM:-0500 TZOFFSETTO:-0400 TZNAME:EDT DTSTART:20240310T070000 END:DAYLIGHT BEGIN:STANDARD TZOFFSETFROM:-0400 TZOFFSETTO:-0500 TZNAME:EST DTSTART:20241103T060000 END:STANDARD BEGIN:DAYLIGHT TZOFFSETFROM:-0500 TZOFFSETTO:-0400 TZNAME:EDT DTSTART:20250309T070000 END:DAYLIGHT BEGIN:STANDARD TZOFFSETFROM:-0400 TZOFFSETTO:-0500 TZNAME:EST DTSTART:20251102T060000 END:STANDARD END:VTIMEZONE BEGIN:VTIMEZONE TZID:Europe/London BEGIN:DAYLIGHT TZOFFSETFROM:+0000 TZOFFSETTO:+0100 TZNAME:BST DTSTART:20230326T010000 END:DAYLIGHT BEGIN:STANDARD TZOFFSETFROM:+0100 TZOFFSETTO:+0000 TZNAME:GMT DTSTART:20231029T010000 END:STANDARD BEGIN:DAYLIGHT TZOFFSETFROM:+0000 TZOFFSETTO:+0100 TZNAME:BST DTSTART:20240331T010000 END:DAYLIGHT BEGIN:STANDARD TZOFFSETFROM:+0100 TZOFFSETTO:+0000 TZNAME:GMT DTSTART:20241027T010000 END:STANDARD BEGIN:DAYLIGHT TZOFFSETFROM:+0000 TZOFFSETTO:+0100 TZNAME:BST DTSTART:20250330T010000 END:DAYLIGHT BEGIN:STANDARD TZOFFSETFROM:+0100 TZOFFSETTO:+0000 TZNAME:GMT DTSTART:20251026T010000 END:STANDARD END:VTIMEZONE BEGIN:VTIMEZONE TZID:Asia/Kolkata BEGIN:STANDARD TZOFFSETFROM:+0530 TZOFFSETTO:+0530 TZNAME:IST DTSTART:20230101T000000 END:STANDARD END:VTIMEZONE BEGIN:VEVENT DTSTART;TZID=America/Los_Angeles:20240918T090000 DTEND;TZID=America/Los_Angeles:20240918T100000 DTSTAMP:20240906T215837Z CREATED:20240906T215234Z LAST-MODIFIED:20240906T215837Z UID:8304-1726650000-1726653600@marketingeda.com SUMMARY:Redefining Mobile Experiences with AI DESCRIPTION:The Arm platform is providing the foundation for the next wave of AI smartphones and laptops. As AI models rapidly evolve\, we’re seeing that software begins to outpace hardware\, requiring additional innovation at all levels of the compute stack. \nTo meet these growing demands\, the Arm platform offers a new compute solution for maximum performance and efficiency\, on leading process nodes. Join this webinar series to learn more about this solution\, including the latest Arm Armv9 CPUs and GPUs\, the benefits and opportunities of running AI on device\, and how to innovate and speed time to market. \nSession 1: The Arm Platform on Wednesday\, Sept 18\, 2024\n\n9:00 a.m. BST / 4:00 p.m. Beijing\n5:00 p.m. BST / 9:00 a.m. PT\n\nThis webinar covers: \n\nThe latest Arm technology\, Arm Compute Subsystems (CSS) for Client\, which helps push the boundaries of premium mobile experiences.\nFeatures\, benefits\, and performance enhancements of Armv9 based Arm Cortex CPUs and Immortalis and Mali GPUs.\nHow Arm partners can rapidly innovate and speed time to market.\nPerformance and efficiency enhancements that increase the responsiveness of GenAI.\nHow to unlock 3 nm PPA benefits with physical implementations.\n\nSpeaker: Kinjal Dave\, Senior Director Product Management\, Arm \nSecond Session – October 2nd \nShare this:\n Share on LinkedIn (Opens in new window)\n LinkedIn\n \n Share on X (Opens in new window)\n X\n \n Share on Facebook (Opens in new window)\n Facebook\n Like this:Like Loading… URL:https://marketingeda.com/event/redefining-mobile-experiences-with-ai/ CATEGORIES:IP,Webinar ATTACH;FMTTYPE=image/jpeg:https://marketingeda.com/wp-content/uploads/Arm-September-18-2024.jpg END:VEVENT BEGIN:VEVENT DTSTART;TZID=America/Los_Angeles:20240918T080000 DTEND;TZID=America/Los_Angeles:20240918T090000 DTSTAMP:20240813T192856Z CREATED:20240813T192856Z LAST-MODIFIED:20240813T192856Z UID:8231-1726646400-1726650000@marketingeda.com SUMMARY:Managing Constraints Like a Pro in OrCAD X DESCRIPTION:Join us in this constraint-focused webinar to learn all the best practices for managing constraints in your design with OrCAD X Presto PCB Editor. \nWe’ll cover everything from the basics of setting up spacing and physical constraints to advanced electrical constraints\, which are critical for HDI designs. \nThe webinar will feature a brief presentation\, a live demonstration using the NVIDIA Jetson Xavier Developer Kit Carrier Board\, and a Q&A session. \nTopics Covered:\n\nNavigating the constraint manager and reusing constraints\nCreating constraint sets\nSetting up physical and spacing constraints\nSetting up advanced constraints for HDI\nElectrical constraints (Propagation Delay\, Net Scheduling\, Differential Pairs)\nSetting up blind\, buried\, and microvias\nAnalysis setup\nPreview of the new constraints panel in OrCAD X Presto PCB Editor\n\n\nWe welcome PCB designers of all experience levels to join us. Enhance your expertise in managing basic and advanced constraints in your OrCAD X Presto designs! \n\nSPEAKERS: \nAdam Fuchs\, Principal Product Engineer\, Cadence \nHOST: \nSupreeth Mannava\, Senior Principal Product Manager\, Cadence \nShare this:\n Share on LinkedIn (Opens in new window)\n LinkedIn\n \n Share on X (Opens in new window)\n X\n \n Share on Facebook (Opens in new window)\n Facebook\n Like this:Like Loading… URL:https://marketingeda.com/event/managing-constraints-like-a-pro-in-orcad-x/ CATEGORIES:EDA,Webinar ATTACH;FMTTYPE=image/jpeg:https://marketingeda.com/wp-content/uploads/Cadence-September-18-2024.jpg END:VEVENT BEGIN:VEVENT DTSTART;TZID=America/Los_Angeles:20240912T120000 DTEND;TZID=America/Los_Angeles:20240912T130000 DTSTAMP:20240823T181126Z CREATED:20240823T181114Z LAST-MODIFIED:20240823T181126Z UID:8265-1726142400-1726146000@marketingeda.com SUMMARY:Unleash Performance\, Save Power: Mastering Processor Customization with the Tensilica Instruction Extension (TIE) Language DESCRIPTION:Join us for an engaging webinar where we show you how to turbocharge performance and minimize power consumption by harnessing the power of custom instructions using the TIE language. Don’t miss this opportunity to optimize your processors like never before! \nTIE enables you to compute and move data many times faster than conventional processors\, resulting in faster yet more power-efficient cores while maintaining full programmability and debugability. \nThis webinar will introduce users to the easy-to-use TIE language and techniques for accelerating computation that can be used to optimize processors for specific target applications. \nLearn how Tensilica TIE language can be implemented to: \n\nSignificantly save SOC Power\nTurbocharge SOC Performance\nMaster processor customization with custom instructions\n\nShare this:\n Share on LinkedIn (Opens in new window)\n LinkedIn\n \n Share on X (Opens in new window)\n X\n \n Share on Facebook (Opens in new window)\n Facebook\n Like this:Like Loading… URL:https://marketingeda.com/event/unleash-performance-save-power-mastering-processor-customization-with-the-tensilica-instruction-extension-tie-language/ CATEGORIES:EDA,IP,Webinar ATTACH;FMTTYPE=image/jpeg:https://marketingeda.com/wp-content/uploads/Cadence-September-12-2024-1.jpg END:VEVENT BEGIN:VEVENT DTSTART;TZID=America/Los_Angeles:20240912T100000 DTEND;TZID=America/Los_Angeles:20240912T110000 DTSTAMP:20240814T174526Z CREATED:20240814T174526Z LAST-MODIFIED:20240814T174526Z UID:8237-1726135200-1726138800@marketingeda.com SUMMARY:Leveraging Verisium Debug to Debug Digital-Mixed Signal Designs DESCRIPTION:Many of today’s designs that are primarily digital also contain analog components. We refer to such designs as “Digital-Mixed-Signal” or DMS designs. In this webinar\, we will demonstrate using the Verisium Debug App to debug such DMS designs. \n\n\n\n\n\n\n\n\n\n\n\n\nWhat You Will Learn \n\n\n\n\n\n\n\n\n\n\n\n\n\nHow Verisium Debug supports debugging Xcelium (Real Number Modeling) RNM and mixed Xcelium and Spectre simulations\nHow Verisium Debug can be used to debug User-Defined Nets (UDNs)\nThe analog waveform debug features of Verisium Debug\n\n\n\n\n\n\n\n\n\n\n\n\n\nWho Should Attend \n\n\n\n\n\n\n\n\n\n\n\n\nThis webinar is designed for design and verification engineers of all levels who need to debug Digital-Mixed-Signal designs when simulating using Xcelium Real Number Modeling (RNM) or mixed Xcelium/Spectre Digital-Mixed-Signal simulations. \n\n\n\n\n\n\n\n\n\n\n\n\nSpeakers \n\n\n\n\n\n\n\n\n\n\n\n\n\nDoug Koslow\, Product Engineering Architect\, Cadence\nRich Chang\, Product Marketing Director\, Cadence\n\n\n\n\n\n\n\nShare this:\n Share on LinkedIn (Opens in new window)\n LinkedIn\n \n Share on X (Opens in new window)\n X\n \n Share on Facebook (Opens in new window)\n Facebook\n Like this:Like Loading… URL:https://marketingeda.com/event/leveraging-verisium-debug-to-debug-digital-mixed-signal-designs/ CATEGORIES:EDA,Webinar ATTACH;FMTTYPE=image/jpeg:https://marketingeda.com/wp-content/uploads/Cadence-September-12-2024.jpeg END:VEVENT BEGIN:VEVENT DTSTART;TZID=America/Los_Angeles:20240912T100000 DTEND;TZID=America/Los_Angeles:20240912T110000 DTSTAMP:20240813T193558Z CREATED:20240813T193538Z LAST-MODIFIED:20240813T193558Z UID:8234-1726135200-1726138800@marketingeda.com SUMMARY:Addressing 3D-IC Power Integrity Design Challenges DESCRIPTION:Power network design and analysis of 3D-ICs is a major challenge because of the complex nature and large size of the power network. In addition\, designers must deal with the complexity of routing power through the interposer\, multiple dies\, through-silicon vias (TSVs)\, and through-dielectric vias (TDVs). In this webinar\, you will learn how the Cadence Integrity 3D-IC Platform and Voltus IC Power Integrity Solution provides: \n\nFully integrated solution for early planning and analysis of 3D-IC power networks\n3D-IC chip-centric power integrity signoff\nHierarchical methods that significantly improve the capacity and performance of power integrity signoff while maintaining a very high level of accuracy at signoff\n\nShare this:\n Share on LinkedIn (Opens in new window)\n LinkedIn\n \n Share on X (Opens in new window)\n X\n \n Share on Facebook (Opens in new window)\n Facebook\n Like this:Like Loading… URL:https://marketingeda.com/event/addressing-3d-ic-power-integrity-design-challenges/ CATEGORIES:EDA,IP,Webinar ATTACH;FMTTYPE=image/jpeg:https://marketingeda.com/wp-content/uploads/Cadence-September-12-2024.jpg END:VEVENT BEGIN:VEVENT DTSTART;TZID=America/Los_Angeles:20240911T080000 DTEND;TZID=America/Los_Angeles:20240911T090000 DTSTAMP:20240821T163437Z CREATED:20240821T163437Z LAST-MODIFIED:20240821T163437Z UID:8259-1726041600-1726045200@marketingeda.com SUMMARY:Questa Formal Verification IP AMBA: Achieve Protocol Compliance in Designs DESCRIPTION:Delve into how Questa Formal Verification IP (VIP) for the AMBA protocol ensures that designs incorporating AMBA adhere strictly to the protocol; all without the need for simulation. The solution integrates comprehensive protocol knowledge and provides user-friendly interfaces\, significantly reducing the setup time for verification environments. Optimized for top-tier performance and scalability\, Questa Formal VIP AMBA is the ideal tool for achieving high-efficiency and accurate protocol compliance. Don’t miss this opportunity to learn how to streamline your verification process and enhance your design workflows. \n  \nWhat You Will Learn:  \n\nChallenges in IP Integration\nUnderstand the common obstacles faced by designers and verification teams during IP integration and how to overcome them.\nBenefits of Formal Verification Ips\nDiscover the advantages of using formal verification IPs\, including enhanced accuracy and reduced need for simulation.\nCapabilities and Supported Protocols\nExplore the extensive capabilities of Questa Formal VIP AMBA and the range of protocols it supports.\nFrom Specification to Formal Properties\nLearn how protocol specifications are transformed into formal properties for effective verification.\nDebugging Protocol Violations\nGain insights into debugging techniques for protocol violations to ensure compliance and reliability.\n\n            \nWho Should Attend:  \n\nRTL Design Engineers\nDesign Integrators\nDesign Verification Engineers\n\nWhat/Which Products are Covered:   \n\nQuesta Formal VIP AMBA\nQuesta Formal VIP OnChip\nQuesta Check Register\n\n\n\nSpeaker:\n\n\n\n\n\n\nNicolae Tusinschi\nFormal Verification Solutions Product Manager\, Siemens EDA\n\n\n\n\nNicolae Tusinschi is a product manager for formal verification solutions at Siemens EDA. He holds a master’s degree combined between the University of Southampton and the University of Kaiserslautern. After a master’s thesis at Continental\, Nicolae joined OneSpin\, where he worked in QA\, then as a product specialist and later served as product owner for design verification tools at OneSpin. His key projects include integrating simulation coverage with formal metrics\, leveraging coverage results in the verification process\, formal verification of RISC-V cores. \n\n\n\nShare this:\n Share on LinkedIn (Opens in new window)\n LinkedIn\n \n Share on X (Opens in new window)\n X\n \n Share on Facebook (Opens in new window)\n Facebook\n Like this:Like Loading… URL:https://marketingeda.com/event/questa-formal-verification-ip-amba-achieve-protocol-compliance-in-designs/ CATEGORIES:EDA,IP,Webinar ATTACH;FMTTYPE=image/jpeg:https://marketingeda.com/wp-content/uploads/Siemens-Setember-11-2024.jpg END:VEVENT BEGIN:VEVENT DTSTART;TZID=America/Los_Angeles:20240910T100000 DTEND;TZID=America/Los_Angeles:20240910T110000 DTSTAMP:20240909T174044Z CREATED:20240909T174044Z LAST-MODIFIED:20240909T174044Z UID:8317-1725962400-1725966000@marketingeda.com SUMMARY:Faster Design TAT and Upscaled Team Productivity with Cadence’s True Hybrid Cloud DESCRIPTION:Join us for an informative webinar as we unveil the new hybrid cloud capabilities of our cloud solutions designed to revolutionize EDA workloads. Whether you need peak capacity for a short duration or want a front-to-back turnkey cloud environment\, our cloud solutions offer unparalleled flexibility and efficiency. \nWe will discuss how Cadence True Hybrid Cloud and Cadence Managed Cloud can optimize cost-efficiency and productivity for your design projects. \nDon’t miss our live demonstrations\, where we’ll showcase the rapid deployment of peak capacity in the cloud\, productivity benefits\, and robust security features. Plus\, discover how you can kickstart your journey with a 30-day free trial. \n\n\n\n\n\n\n\n\n\n\n\n\nWho Should Attend \n\n\n\n\n\n\n\n\n\n\n\n\nThis webinar is designed for chip designers\, Cloud IT architects\, CAD platform teams\, and business decision makers. \n\n\n\n\n\n\n\n\n\n\n\n\nSpeakers \n\n\n\n\n\n\n\n\n\n\n\n\n\nKetan Joshi\, Sr. Business Development Group Director\, Cadence\nMichael Reed\, Sr. Staff Systems Engineer\, Cadence\n\n\n\n\n\n\n\nShare this:\n Share on LinkedIn (Opens in new window)\n LinkedIn\n \n Share on X (Opens in new window)\n X\n \n Share on Facebook (Opens in new window)\n Facebook\n Like this:Like Loading… URL:https://marketingeda.com/event/faster-design-tat-and-upscaled-team-productivity-with-cadences-true-hybrid-cloud/ CATEGORIES:EDA,Webinar ATTACH;FMTTYPE=image/jpeg:https://marketingeda.com/wp-content/uploads/Cadence-September-10-2024.jpg END:VEVENT BEGIN:VEVENT DTSTART;TZID=America/Los_Angeles:20240910T090000 DTEND;TZID=America/Los_Angeles:20240910T100000 DTSTAMP:20240820T162341Z CREATED:20240820T162341Z LAST-MODIFIED:20240820T162341Z UID:8252-1725958800-1725962400@marketingeda.com SUMMARY:Can AI make cameras see in the dark? DESCRIPTION:Abstract\n  \n\nAs cameras become ubiquitous in applications such as surveillance\, mobile\, drones\, and automotive systems\, achieving clear vision 24/7 under any condition—including extreme low light and high dynamic range scenarios—has become essential. By leveraging Edge AI processors\, a software ISP based on neural network technology can process and optimize video in real-time\, surpassing human vision capabilities in these challenging conditions.\nIn this webinar\, we will explore how to harness the power of Ceva’s NPU alongside Visionary.ai’s advanced AI software Image Signal Processing (ISP) to significantly enhance video quality across various camera-enabled applications. Visionary.ai utilizes Neural Processing Units (NPUs) to boost camera performance\, especially in demanding environments like extreme low-light and high dynamic range (HDR) scenarios.\nFinally\, we will introduce an available reference design for this joint solution and showcase the impressive results achieved. \nJoin Ceva and Visionary.ai experts to learn about: \n\nThe power of Edge AI for computer vision\nModern NPU architecture fundamentals\nTrue Night Vision software ISP\nThe role of video denoising in solving the low-light challenge\nThe technical challenges to implement an AI based ISP on an NPU\nHow can Ceva and Visionary.ai enhance your camera enabled application\n\n\nTarget Audience\n  \nVision system architects\, hardware and software engineers\, and product managers targeting camera enabled devices\, that are looking to enhance their product ability to cope with extreme low-light conditions using the power of Edge AI.\n\nSpeakers\n\n\n\n\n\n\n\nRonny Vatelmacher\nDirector of Product Marketing\, Vision and AI\, Ceva\n\n\n\n\n\n\n\n\n\nDavid Jarmon\nSVP Worldwide Sales\, Visionary.ai\n\n\n\nShare this:\n Share on LinkedIn (Opens in new window)\n LinkedIn\n \n Share on X (Opens in new window)\n X\n \n Share on Facebook (Opens in new window)\n Facebook\n Like this:Like Loading… URL:https://marketingeda.com/event/can-ai-make-cameras-see-in-the-dark/ CATEGORIES:IP,Webinar ATTACH;FMTTYPE=image/jpeg:https://marketingeda.com/wp-content/uploads/Ceva-September-10-2024.jpg END:VEVENT BEGIN:VEVENT DTSTART;TZID=America/Los_Angeles:20240905T110000 DTEND;TZID=America/Los_Angeles:20240905T120000 DTSTAMP:20240903T175441Z CREATED:20240903T175441Z LAST-MODIFIED:20240903T175441Z UID:8291-1725534000-1725537600@marketingeda.com SUMMARY:Using OSVVM’s AXI4 Verification Components DESCRIPTION:Abstract: \nThis “Getting Started” presentation is for engineers who need to use the OSVVM AXI4 verification components (VCs) in their testbenches. Part 2 of this presentation focuses on how to write tests and configure the AXI4 VCs. \nAXI4 VCs are probably the most complex VCs in the OSVVM library. This complexity is due to the AXI4 interface having 5 independent interfaces: Write Address\, Write Data\, Write Response\, Read Address\, and Read Data.   Going further\, the interface supports user configurable optional aspects of the interface – such as the ID and User fields. \nIn this presentation we examine the structure of OSVVM test cases\, the AXI4 transaction API\, how to do byte transfers\, how to do burst transfers\, how to handle arrays of VCs\, how to configure AXI4 VC options\, how to randomize delays for xValid or xReady\, and how the test case can directly read or write values in the Axi4Memory. \nAs we look at the OSVVM transaction API we will note that it does not specify the byte enables. Instead\, OSVVM determines the byte enables by looking at the width of the data and the lower bits of the address. \nOSVVM’s burst interface is supported by FIFOs that are in the transaction interface. These FIFOs allow any size of std_logic_vector value to be pushed into them. This allows the burst interface to be used in either byte mode or word mode. In byte mode\, the burst is a sequence of bytes that are assembled by the VC into interface words. This allows OSVVM to create test cases that are independent of the actual data bus width. \nAbout OSVVM \n\nOSVVM is a suite of libraries designed to streamline your VHDL entire verification process\, boosting productivity and reducing development time. Each library provides independent capabilities\, allowing selective adoption and a learn-as-you-go approach. Whether using directed or random testing\, OSVVM facilitates writing concise and readable test cases for both unit/RTL tests and complex FPGA and ASIC tests. \nOSVVM provides VHDL with verification capabilities that rival SystemVerilog + UVM. These include transaction-level modeling\, verification components\, co-simulation with software\, randomized test generation\, self-checking test support\, verification data structures\, comprehensive test reporting in HTML and text\, and synchronization primitives.\n\nWith OSVVM and a good team lead\, any VHDL engineer can do verification – and have fun doing it. As a result\, having your entire team united in using OSVVM will simplify deploying VHDL engineers to projects.\n\nSynthWorks has been using OSVVM for 25+ years in our training classes and consulting work. During that time\, we have innovated new capabilities and evolved our existing ones to increase re-use and reduce effort and time spent.\n\nWhy VHDL for verification? According to the 2022 Wilson Research Group Functional Verification Study\, in the FPGA market\, 66% use VHDL for design\, 58% use VHDL for verification\, and 28% use OSVVM. Hence\, VHDL is #1 for FPGA development and OSVVM is #1 for VHDL verification.\n\nWebinar Duration:  \n\n50 min presentation/live demo\n15 min Q&A\n\nPresenter Bio: \n \nJim Lewis\, VHDL Design and Verification Expert\, Trainer\, OSVVM developer\, and IEEE VHDL Chair \nJim Lewis is an innovator and leader in the VHDL community. He has 30 plus years of design and teaching experience. He is the Chair of the IEEE 1076 VHDL Standards Working Group. He is a co-founder of the Open Source VHDL Verification Methodology (OSVVM) and the chief architect of the packages and methodology. He is an expert VHDL trainer for SynthWorks Design Inc. In his design practice\, he has created designs for print servers\, IMA E1/T1 networking\, fighter jets\, video phones\, and space craft. \nWhether teaching\, developing OSVVM\, consulting on VHDL design and verification projects\, or working on the IEEE VHDL standard\, Mr. Lewis brings a deep understanding of VHDL to architect solutions that solve difficult problems in simple ways. \nShare this:\n Share on LinkedIn (Opens in new window)\n LinkedIn\n \n Share on X (Opens in new window)\n X\n \n Share on Facebook (Opens in new window)\n Facebook\n Like this:Like Loading… URL:https://marketingeda.com/event/using-osvvms-axi4-verification-components/ CATEGORIES:EDA,Webinar ATTACH;FMTTYPE=image/jpeg:https://marketingeda.com/wp-content/uploads/Aldec-September-5-2024.jpg END:VEVENT BEGIN:VEVENT DTSTART;TZID=America/New_York:20240905T100000 DTEND;TZID=America/New_York:20240905T110000 DTSTAMP:20240807T213739Z CREATED:20240807T213739Z LAST-MODIFIED:20240807T213739Z UID:8219-1725530400-1725534000@marketingeda.com SUMMARY:Enhanced Packaging Performance and Manufacturing with Physics-Based 3D Simulation DESCRIPTION:About this webinar\nDigital engineering is ramping up across the CPG\, healthcare and wider packaging sector. Packaging engineers are tasked with producing fit-for-purpose packaging that is optimised for customer-use\, transportation\, storage and for production-line filling/handling. In addition\, manufacturing the packaging containers as optimally as possible to avoid defects is vitally important. All in the landscape of sustainability. \nAnsys provides leading physics-based 3D simulation tools applicable to a wide range of scenarios from filling of liquids and solids\, drop-testing\, thermal management\, vibration under transportation\, top-load strength testing\, conveying\, package crimping\, blow moulding\, thermoforming\, heat-sealing and board-creasing. \nJoin this webinar to be updated on the latest virtual engineering simulation capabilities from Ansys in the packaging domain. \n  \nWhat you will learn\n\nThe use of physics-based 3D simulation to gain engineering insight into the performance of packaging whilst in the hands of an end-user\, in storage\, under transportation and during manufacture.\nThe state of the art from an Ansys perspective on the use of digital engineering to drive innovation\, efficiency and sustainability in the packaging sector.\nThe use of Ansys Granta Selector software for smarter material selection\n\n  \nWho should attend\n\nPackaging engineers and designers interested in the use of simulation in the packaging industry.\nMaterial scientists involved in the selection of materials for packaging.\nCurrent users of CFD\, Discrete Element Modelling\, structural and thermal simulation FEA tools in the packaging domain.\n\n  \nSpeakers\n\nMikael Schill\, Senior Manager and Application Engineering\, Ansys\nMarcus Redhe\, Director Application Engineering\, Ansys\n\nShare this:\n Share on LinkedIn (Opens in new window)\n LinkedIn\n \n Share on X (Opens in new window)\n X\n \n Share on Facebook (Opens in new window)\n Facebook\n Like this:Like Loading… URL:https://marketingeda.com/event/enhanced-packaging-performance-and-manufacturing-with-physics-based-3d-simulation/ CATEGORIES:EDA,Webinar ATTACH;FMTTYPE=image/jpeg:https://marketingeda.com/wp-content/uploads/Ansys-September-5-2024.jpg END:VEVENT BEGIN:VEVENT DTSTART;TZID=America/New_York:20240904T100000 DTEND;TZID=America/New_York:20240904T110000 DTSTAMP:20240815T155544Z CREATED:20240815T155544Z LAST-MODIFIED:20240815T155544Z UID:8245-1725444000-1725447600@marketingeda.com SUMMARY:Hardware-Accurate Digital Twins in Defense: Case Study DESCRIPTION:The defense industry is increasingly seeking innovative approaches to accelerate system development while ensuring reliability. Hardware-accurate digital twins offer a promising solution. This webinar will explore the concept of hardware-accurate digital twins and their application in defense. \nJoin Cadence and Northrop Grumman as we delve into a real-world case study demonstrating the power of digital twins in defense program execution. Discover how hardware-accurate digital twins can be leveraged to streamline development processes\, reduce risks\, and improve overall system performance. This case study will give you practical insights into implementing digital twins in your next program development. \n\nAttendees Will Learn \n\nThe definition and benefits of hardware-accurate digital twins\nPractical applications in the defense industry\nA detailed case study showcasing successful implementation\nBest practices for adopting digital twin technology\n\n\nSpeakers \nAdam Sherer\, Account Technical Director\, Cadence\nMichael Gowan\, Verification Engineer\, Northrop Grumman\nBilly Gomez\, Sr. Principal Engineer Embedded Software\, Northrop Grumman \nShare this:\n Share on LinkedIn (Opens in new window)\n LinkedIn\n \n Share on X (Opens in new window)\n X\n \n Share on Facebook (Opens in new window)\n Facebook\n Like this:Like Loading… URL:https://marketingeda.com/event/hardware-accurate-digital-twins-in-defense-case-study/ CATEGORIES:EDA,Webinar ATTACH;FMTTYPE=image/jpeg:https://marketingeda.com/wp-content/uploads/Cadence-September-4-2025.jpg END:VEVENT BEGIN:VEVENT DTSTART;TZID=America/Los_Angeles:20240904T090000 DTEND;TZID=America/Los_Angeles:20240904T100000 DTSTAMP:20240806T194128Z CREATED:20240806T194128Z LAST-MODIFIED:20240806T194128Z UID:8205-1725440400-1725444000@marketingeda.com SUMMARY:Elevate Your Analog Layout Design to New Heights DESCRIPTION:Are you ready to transform your career and become a master of analog layout design? Look no further than The Advanced Analog Layout Course! This course is meticulously crafted to enhance your physical design skills\, guiding you through the advanced techniques essential for creating top-notch\, well-matched\, and noise-resistant layouts on a CMOS process. \nLearn Anytime\, Anywhere! Our course is delivered through a user-friendly online portal\, granting you the power to learn at your own pace. Enjoy the flexibility of completing modules and watching nearly 100 instructional videos whenever it suits you best. \nTailored for Excellence! Whether you’re a seasoned layout engineer aiming to refine your skills or a front-end schematic designer eager to enhance your design methods\, this course is designed for you. With over 19 hours of content\, including seven comprehensive modules and regular assessments\, you’ll be equipped to produce more efficient and superior quality layouts. \nComprehensive Learning Experience! Dive into a wealth of knowledge with our extensive video library\, totalling over 19 hours of expert content. Our regular assessments ensure that you’re on track\, solidifying your understanding and boosting your confidence. \nJoin the ranks of the industry’s best and make your mark in the world of analog layout design. Enroll in The Advanced Analog Layout Course today and start your journey to becoming an analog layout virtuoso! \nReady to take the next step in your career? Join this webinar to learn more and sign up for the course that will set you apart in the competitive field of analog layout design. \nShare this:\n Share on LinkedIn (Opens in new window)\n LinkedIn\n \n Share on X (Opens in new window)\n X\n \n Share on Facebook (Opens in new window)\n Facebook\n Like this:Like Loading… URL:https://marketingeda.com/event/elevate-your-analog-layout-design-to-new-heights/ CATEGORIES:IP,Webinar ATTACH;FMTTYPE=image/jpeg:https://marketingeda.com/wp-content/uploads/IC-Mask-Design-September-2024.jpg END:VEVENT BEGIN:VEVENT DTSTART;TZID=Europe/London:20240903T120000 DTEND;TZID=Europe/London:20240903T130000 DTSTAMP:20240731T161732Z CREATED:20240731T161715Z LAST-MODIFIED:20240731T161732Z UID:8191-1725364800-1725368400@marketingeda.com SUMMARY:DVClub Europe - September 2024 DESCRIPTION:This DVClub event will have talks on verification of low power features of VLSI designs\, discussing strategies for accurately measuring power consumption and ensuring that power-saving mechanisms are effective. Additionally\, speakers will share insights on how to simulate and analyze different power scenarios to identify potential issues and optimize power management techniques. Attendees will have the opportunity to learn best practices for low power verification and gain valuable knowledge on how to successfully implement energy-efficient designs in their projects. Overall\, this event promises to provide valuable insights and practical strategies for ensuring the success of low power verification in VLSI designs. \nAgenda (BST)\n12:00 Welcome and Introduction – Mike Bartley\, Tessolve\n12:00 Satinder Paul\n12:20 Synopsys\n12:40 TBD\n13:00 Close \nShare this:\n Share on LinkedIn (Opens in new window)\n LinkedIn\n \n Share on X (Opens in new window)\n X\n \n Share on Facebook (Opens in new window)\n Facebook\n Like this:Like Loading… URL:https://marketingeda.com/event/dvclub-europe-september-2024/ CATEGORIES:EDA,Webinar ATTACH;FMTTYPE=image/jpeg:https://marketingeda.com/wp-content/uploads/DVClub-Europe-2024.jpg END:VEVENT BEGIN:VEVENT DTSTART;TZID=America/Los_Angeles:20240829T100000 DTEND;TZID=America/Los_Angeles:20240829T110000 DTSTAMP:20240808T172706Z CREATED:20240808T172706Z LAST-MODIFIED:20240808T172706Z UID:8222-1724925600-1724929200@marketingeda.com SUMMARY:Micron Utilizes Silvaco’s Fab Technology Co-Optimization for Development and Manufacturing of Memory Technologies DESCRIPTION:Memory products from Micron Technology\, such as DRAM components and 3D NAND\, are propelling the advancement of process technologies. Innovative modeling methods are required to tackle the complexities in fabricating structures and to evaluate process variation effects on electrical performance. \nThis webinar highlights how Micron Technology utilizes Silvaco’s Fab Technology Co-Optimization (FTCOTM) platform for the development and manufacturing of advanced memory technologies. Use cases demonstrate the application of virtual process models\, sensitivity analysis\, and stress modeling to optimize semiconductor processes. The collaborative effort between Silvaco and Micron shows how to build a digital twin of a fabrication process\, enabling a transformative solution for scaling memory technologies. \n\n\n\n\nPresenter\n\n\n\n\nSumeet Pandey\, Distinguished Member of Technical Staff\, Micron Technology \n\n\n\n\nWHO SHOULD ATTEND:\n\n\n\n\nTCAD engineers\, fab engineers\, process engineers\, product managers\, and engineering management. \n\n\nShare this:\n Share on LinkedIn (Opens in new window)\n LinkedIn\n \n Share on X (Opens in new window)\n X\n \n Share on Facebook (Opens in new window)\n Facebook\n Like this:Like Loading… URL:https://marketingeda.com/event/micron-utilizes-silvacos-fab-technology-co-optimization-for-development-and-manufacturing-of-memory-technologies/ CATEGORIES:EDA,Webinar ATTACH;FMTTYPE=image/jpeg:https://marketingeda.com/wp-content/uploads/Silvaco-August-29-2024.jpg END:VEVENT BEGIN:VEVENT DTSTART;TZID=America/Los_Angeles:20240828T080000 DTEND;TZID=America/Los_Angeles:20240828T090000 DTSTAMP:20240809T162606Z CREATED:20240809T162606Z LAST-MODIFIED:20240809T162606Z UID:8225-1724832000-1724835600@marketingeda.com SUMMARY:Design\, Integrate\, Analyze and Manage with Allegro X DESCRIPTION:Designing PCBs in today’s world means using multiple tools to get the job done. The Allegro X Design Platform allows you to access all these tools in one unified design environment. \nJoin us to discuss how you can reduce your cycle time\, ensure product reliability and get first-time-right designs with Allegro X. \n\nTopics we’ll cover during the webinar: \n\nHierarchical and multi-board design\nReliability analysis covering electrical overstress (EOS) and mean time between failure (MTBF)\nFloor planning and in-design analysis with integrated Cadence Celsius Solver\nConstraint-driven design to ensure functionality and manufacturability\nAnd how to utilize DesignTrue DFM to reduce costly manufacturing failures\n\n\nSpeakers: \nSaankhya Parekh\, Lead Product Engineer\, Cadence \nPablo Barraza\, Lead Application Engineer\, Cadence \nHost: \nSupreeth Mannava\, Sr. Principal Product Manager\, Cadence \nShare this:\n Share on LinkedIn (Opens in new window)\n LinkedIn\n \n Share on X (Opens in new window)\n X\n \n Share on Facebook (Opens in new window)\n Facebook\n Like this:Like Loading… URL:https://marketingeda.com/event/design-integrate-analyze-and-manage-with-allegro-x/ CATEGORIES:EDA,Webinar ATTACH;FMTTYPE=image/jpeg:https://marketingeda.com/wp-content/uploads/Cadence-August-28-2024.jpg END:VEVENT BEGIN:VEVENT DTSTART;TZID=America/Los_Angeles:20240822T110000 DTEND;TZID=America/Los_Angeles:20240822T120000 DTSTAMP:20240819T162836Z CREATED:20240819T162836Z LAST-MODIFIED:20240819T162836Z UID:8248-1724324400-1724328000@marketingeda.com SUMMARY:Using OSVVM’s AXI4 Verification Components: Pt 1 Creating the AXI4 Testbench / Test Harness DESCRIPTION:European Session \nAbstract: \nThis “Getting Started” presentation is for engineers who need to use the OSVVM AXI4 verification components (VCs) in their testbenches. Part 1 of this presentation provides a detailed walkthrough of creating a testbench environment that uses AXI4 VCs. \nAXI4 VCs are probably the most complex VCs in the OSVVM library. This complexity is due to the AXI4 interface having five independent interfaces: Write Address\, Write Data\, Write Response\, Read Address\, and Read Data. Going further\, the interface supports user configurable optional aspects of the interface – such as the ID and User fields. \nIn this presentation we examine the details of the test harness including the required context references\, configuring the transaction interface\, configuring the AXI interface\, creating clock and reset\, connecting the DUT to the OSVVM AXI interface record\, and connecting to the AXI VCs. \nWe continue by examining how to size the AXI4 interface by sizing the unconstrained record elements of the AXI4 interface and OSVVM transaction interface records. \nWe wrap up by looking at how to use AXI4 VCs inside a DUT – such as with Zynq. In this situation\, the DUT does not have a port for the transaction interface(s). To address this use model\, OSVVM provides another set of AXI4 VCs that use OSVVM’s virtual transaction interface (VTI). These VCs all have Vti in their name\, such as Axi4ManagerVti.vhd. \nThe Zynq subordinate interfaces (such as Axi4Memory) can share the same memory space. As a result\, we look at how OSVVM configures multiple instances of the Axi4Memory to share their internal address space. \n\nAbout OSVVM \nOSVVM is a suite of libraries designed to streamline your VHDL entire verification process\, boosting productivity and reducing development time. Each library provides independent capabilities\, allowing selective adoption and a learn-as-you-go approach. Whether using directed or random testing\, OSVVM facilitates writing concise and readable test cases for both unit/RTL tests and complex FPGA and ASIC tests. \nOSVVM provides VHDL with verification capabilities that rival SystemVerilog + UVM. These include transaction-level modeling\, verification components\, co-simulation with software\, randomized test generation\, self-checking test support\, verification data structures\, comprehensive test reporting in HTML and text\, and synchronization primitives.\n\nWith OSVVM and a good team lead\, any VHDL engineer can do verification – and have fun doing it. As a result\, having your entire team united in using OSVVM will simplify deploying VHDL engineers to projects.\n\nSynthWorks has been using OSVVM for 25+ years in our training classes and consulting work. During that time\, we have innovated new capabilities and evolved our existing ones to increase re-use and reduce effort and time spent.\n\nWhy VHDL for verification? According to the 2022 Wilson Research Group Functional Verification Study\, in the FPGA market\, 66% use VHDL for design\, 58% use VHDL for verification\, and 28% use OSVVM. Hence\, VHDL is #1 for FPGA development and OSVVM is #1 for VHDL verification.\n  \n\nAgenda\n\n50 min presentation/live demo\n10 min Q&A\n\nPresenter Bio: \n \nJim Lewis\, VHDL Design and Verification Expert\, Trainer\, OSVVM developer\, and IEEE VHDL Chair \nJim Lewis is an innovator and leader in the VHDL community. He has 30 plus years of design and teaching experience. He is the Chair of the IEEE 1076 VHDL Standards Working Group. He is a co-founder of the Open Source VHDL Verification Methodology (OSVVM) and the chief architect of the packages and methodology. He is an expert VHDL trainer for SynthWorks Design Inc. In his design practice\, he has created designs for print servers\, IMA E1/T1 networking\, fighter jets\, video phones\, and space craft. \nWhether teaching\, developing OSVVM\, consulting on VHDL design and verification projects\, or working on the IEEE VHDL standard\, Mr. Lewis brings a deep understanding of VHDL to architect solutions that solve difficult problems in simple ways. \nShare this:\n Share on LinkedIn (Opens in new window)\n LinkedIn\n \n Share on X (Opens in new window)\n X\n \n Share on Facebook (Opens in new window)\n Facebook\n Like this:Like Loading… URL:https://marketingeda.com/event/using-osvvms-axi4-verification-components-pt-1-creating-the-axi4-testbench-test-harness/ CATEGORIES:EDA,Webinar ATTACH;FMTTYPE=image/jpeg:https://marketingeda.com/wp-content/uploads/Aldec-August-22-2024.jpg END:VEVENT BEGIN:VEVENT DTSTART;TZID=America/Los_Angeles:20240820T110000 DTEND;TZID=America/Los_Angeles:20240820T130000 DTSTAMP:20240725T163046Z CREATED:20240725T163046Z LAST-MODIFIED:20240725T163046Z UID:8180-1724151600-1724158800@marketingeda.com SUMMARY:Mastering EMC Simulations for Electronic Designs DESCRIPTION:Overview\nElectromagnetic Compatibility (EMC) simulation is critical for ensuring that electronic devices comply with regulatory standards and perform optimally in their intended environments. As the complexity of electronic systems increases\, the importance of EMC simulation grows\, allowing engineers to predict and mitigate potential electromagnetic interference (EMI) issues before physical prototypes are built. \nFor EMC and product design engineers\, it can be challenging to understand how to effectively use simulation tools. This hands-on session with experts in full-device simulation offers a unique opportunity for engineers to dive into the world of EMC simulation. This session will provide practical experience\, demystifying the simulation process and empowering engineers with the knowledge to implement simulations early in the design phase. Experts will offer insights into best practices\, common pitfalls to avoid\, and strategies for interpreting simulation results. \nBy participating in such a session\, engineers can gain a deeper understanding of the nuances of EMC simulation. They learn to set up simulations that model their products’ real-world behavior\, identify potential EMI issues\, and explore design modifications to enhance EMC performance. This proactive approach ensures compliance with regulatory standards and contributes to the final product’s overall reliability and quality. \nEMC simulation is more than just a compliance checkbox; it’s a strategic tool that\, when used effectively\, can significantly improve product design. Join this hands-on session guided by experts created for engineers looking to master EMC simulation and integrate it into their design process. It’s an investment in knowledge that will pay dividends throughout the product’s lifecycle. \n  \nWhat attendees will learn\n\nCAD File Preparation: Master importing mechanical CAD designs\, assigning materials\, and preparing for simulations.\n\n\nPCB and Package Setup: Discover the steps to import electronic design files for PCBs and packages\, including automation of the setup process.\n\n\nCable Specification: Gain hands-on experience in defining cables through co-simulation with multi-conductor transmission line solvers.\n\n\nComponent Modeling: Understand how to represent components using ideal or SPICE circuit models for co-simulation with 3D geometries.\n\n\nPerformance Evaluation: Learn to transform simulation results into formats that facilitate comparison with standard measurements for device performance assessment.\n\n  \nWho should attend\n\nFor Electromagnetic Compatibility Engineers: If your expertise lies in heuristic design guidelines and physical testing for compliance\, are you considering enhancing your capabilities with engineering simulation?\n\n\nFor Mechanical Design Engineers: Engaged in creating products with EMC requirements? Explore user-friendly simulation tools that can guide you toward compliance.\n\n\nFor RF Engineers: Charged with safeguarding your RF designs from the inadvertent interference of surrounding electronics? Discover methods to assess and mitigate RF desensitization risks earlier in the design process.\n\n\nFor Electrical Engineers Involved in designing PCBs and integrating components that must adhere to EMC regulations: Assess the need to account for the influence of enclosures and cables on EMC and signal and power integrity.\n\nShare this:\n Share on LinkedIn (Opens in new window)\n LinkedIn\n \n Share on X (Opens in new window)\n X\n \n Share on Facebook (Opens in new window)\n Facebook\n Like this:Like Loading… URL:https://marketingeda.com/event/mastering-emc-simulations-for-electronic-designs/ CATEGORIES:EDA,Webinar ATTACH;FMTTYPE=image/jpeg:https://marketingeda.com/wp-content/uploads/Ansys-august-20-2024.jpg END:VEVENT BEGIN:VEVENT DTSTART;TZID=America/Los_Angeles:20240815T110000 DTEND;TZID=America/Los_Angeles:20240815T120000 DTSTAMP:20240809T165235Z CREATED:20240809T165235Z LAST-MODIFIED:20240809T165235Z UID:8228-1723719600-1723723200@marketingeda.com SUMMARY:Why Should Our Team be Using VHDL + OSVVM for Verification? DESCRIPTION:Abstract: \nThis is a high-level presentation that identifies the key aspects of a modern verification methodology and shows how to achieve them with OSVVM. This is a great presentation to share with your management about why OSVVM (and OSVVM training) is important for your team. \nDescription: \nDeveloping and deploying a verification methodology can be costly and time consuming. Going without one will be even more costly due to bugs escaping into production hardware systems.\n\nOpen Source VHDL Verification Methodology (OSVVM) provides the VHDL community with an already developed\, open-source solution. OSVVM implements all of the capabilities of a modern verification methodology: transaction-based testing\, a verification framework\, verification components\, self-checking tests\, messaging handling\, error tracking\, requirements tracking\, constrained random testing\, scoreboards\, functional coverage\, co simulation with software\, test automation\, and a comprehensive set of test reports.\n\nThis presentation examines how these capabilities will benefit your projects.\n\nSystemVerilog+UVM also provides a similar set of capabilities. Unfortunately\, SV+UVM ended up absurdly complex to use – instead of using a module (entity/architecture in VHDL) with its built-in concurrency\, SV+UVM uses OO\, sequential code\, and fork and join (to get concurrency). As a result\, SV has failed to unify the design and verification communities.\n\nVHDL+OSVVM on the other hand uses entity/architectures to create verification components and libraries of subprograms (procedures and functions) to extend VHDL into a complete verification language. In doing this\, OSVVM creates verification capabilities that rival SystemVerilog+UVM while at the same time it uses VHDL language elements that are familiar to VHDL design engineers.\n\nAs a result\, with VHDL+OSVVM and a good verification lead\, any VHDL engineer can do verification as well as RTL design.\n\n\nAbout OSVVM \nOSVVM is a suite of libraries designed to streamline your VHDL entire verification process\, boosting productivity and reducing development time. Each library provides independent capabilities\, allowing selective adoption and a learn-as-you-go approach. Whether using directed or random testing\, OSVVM facilitates writing concise and readable test cases for both unit/RTL tests and complex FPGA and ASIC tests. \nOSVVM provides VHDL with verification capabilities that rival SystemVerilog + UVM. These include transaction-level modeling\, verification components\, co-simulation with software\, randomized test generation\, self-checking test support\, verification data structures\, comprehensive test reporting in HTML and text\, and synchronization primitives.\n\nWith OSVVM and a good team lead\, any VHDL engineer can do verification – and have fun doing it. As a result\, having your entire team united in using OSVVM will simplify deploying VHDL engineers to projects.\n\nSynthWorks has been using OSVVM for 25+ years in our training classes and consulting work. During that time\, we have innovated new capabilities and evolved our existing ones to increase re-use and reduce effort and time spent.\n\nWhy VHDL for verification? According to the 2022 Wilson Research Group Functional Verification Study\, in the FPGA market\, 66% use VHDL for design\, 58% use VHDL for verification\, and 28% use OSVVM. Hence\, VHDL is #1 for FPGA development and OSVVM is #1 for VHDL verification.\n  \n\nAgenda\n\n50 min presentation/live demo\n10 min Q&A\n\n  \n\n\n\n\n\n\n\n\n\n\n\n\n\n\n\n\n\n\n\n\n\n\n\n\n\n\n\n\n\n\n\n\n\nPresenter Bio: \n \nJim Lewis\, VHDL Design and Verification Expert\, Trainer\, OSVVM developer\, and IEEE VHDL Chair \nJim Lewis is an innovator and leader in the VHDL community. He has 30 plus years of design and teaching experience. He is the Chair of the IEEE 1076 VHDL Standards Working Group. He is a co-founder of the Open Source VHDL Verification Methodology (OSVVM) and the chief architect of the packages and methodology. He is an expert VHDL trainer for SynthWorks Design Inc. In his design practice\, he has created designs for print servers\, IMA E1/T1 networking\, fighter jets\, video phones\, and space craft.\nWhether teaching\, developing OSVVM\, consulting on VHDL design and verification projects\, or working on the IEEE VHDL standard\, Mr. Lewis brings a deep understanding of VHDL to architect solutions that solve difficult problems in simple ways. \n\n\n\n\n\n\n\nShare this:\n Share on LinkedIn (Opens in new window)\n LinkedIn\n \n Share on X (Opens in new window)\n X\n \n Share on Facebook (Opens in new window)\n Facebook\n Like this:Like Loading… URL:https://marketingeda.com/event/why-should-our-team-be-using-vhdl-osvvm-for-verification/ CATEGORIES:EDA,Webinar ATTACH;FMTTYPE=image/jpeg:https://marketingeda.com/wp-content/uploads/Aldec-AUgust-15-2024.jpg END:VEVENT BEGIN:VEVENT DTSTART;TZID=America/Los_Angeles:20240812T150000 DTEND;TZID=America/Los_Angeles:20240812T160000 DTSTAMP:20240731T170816Z CREATED:20240731T170816Z LAST-MODIFIED:20240731T170816Z UID:8194-1723474800-1723478400@marketingeda.com SUMMARY:Modeling and Simulation of Silicon Photonics Systems in SystemVerilog DESCRIPTION:Silicon photonics systems integrate photonic components such as optical waveguides\, couplers\, resonators\, photodetectors\, etc. along with electronic components on the same silicon chip to realize high-bandwidth\, high-density\, and low-power communication via wavelength-division multiplexing (WDM). This talk will address the challenges of modeling and simulating silicon photonics WDM transceivers in SystemVerilog\, which contain photonic devices for WDM signaling\, analog interface circuits for pulse-amplitude modulation (PAM)\, and digital controllers for temperature calibration. It will show that the XMODEL’s way of expressing analog signals in the Laplace domain and computing them in an event-driven fashion can be extended to simulating optical waves\, even when they are treated as ~200 THz frequency signals. The talk will be given from a circuit designer’s perspective\, and those without prior background in silicon photonics are all welcome to join. \nShare this:\n Share on LinkedIn (Opens in new window)\n LinkedIn\n \n Share on X (Opens in new window)\n X\n \n Share on Facebook (Opens in new window)\n Facebook\n Like this:Like Loading… URL:https://marketingeda.com/event/modeling-and-simulation-of-silicon-photonics-systems-in-systemverilog/ CATEGORIES:EDA,Webinar ATTACH;FMTTYPE=image/jpeg:https://marketingeda.com/wp-content/uploads/Scientific-Analog-August-12-2024.jpg END:VEVENT BEGIN:VEVENT DTSTART;TZID=America/Los_Angeles:20240806T100000 DTEND;TZID=America/Los_Angeles:20240806T110000 DTSTAMP:20240528T173110Z CREATED:20240528T173009Z LAST-MODIFIED:20240528T173110Z UID:8063-1722938400-1722942000@marketingeda.com SUMMARY:Fab.da: Comprehensive AI-Driven Process Analytics for Faster Ramp and Efficient High-Volume Manufacturing DESCRIPTION:The challenges before semiconductor fabs are expansive and evolving. As the size of chips shrinks from nanometers to eventually angstroms\, the complexity of the manufacturing process increases in response. To combat the complexity and sheer intricacy of semiconductor manufacturing\, innovative software solutions are required. Synopsys Fab.da is a comprehensive process control solution that utilizes artificial intelligence (AI) and machine learning (ML) to allow for faster production ramp and efficient high-volume manufacturing. Fab.da is a part of the Synopsys.da Data Analytics solutions\, which brings together data analytics and insights from the entire chip lifecycle. It can analyze many petabytes of data originating from thousands of equipment in semiconductor fabs with zero downtime. Join the webcast to learn more about the Synopsys Fab.da. \n\n\n\n\n\n\n\n\n\n\nSpeakers\n\n\nListed below are the industry leaders scheduled to speak. \n\n\n\n\n\n\n\n\n\n\n\n\n\n\n\n\n\n\n\n\n\n\n\n\n\n\nVivek Jain\n\n\nProduct Management\, Principal\nSynopsys \n\n\n\n\n\n\n\n\n\n\n\nVivek Jain is an accomplished product management professional at Synopsys with a career distinguished by strong leadership and a proven record of contribution to lithography\, metrology\, and inspection products. He holds four issued patents in technologies that improve semiconductor fab efficiency and has a number of papers in publications. Vivek graduated from the Indian Institute of Technologies with a major in chemical engineering and\, since 2019\, has been a member of the technical committee of SEMI Advanced Semiconductor Manufacturing Conference (ASMC). \n\n\n\n\n\n\n\n\n\n\nShare this:\n Share on LinkedIn (Opens in new window)\n LinkedIn\n \n Share on X (Opens in new window)\n X\n \n Share on Facebook (Opens in new window)\n Facebook\n Like this:Like Loading… URL:https://marketingeda.com/event/fab-da-comprehensive-ai-driven-process-analytics-for-faster-ramp-and-efficient-high-volume-manufacturing/ CATEGORIES:EDA,Webinar ATTACH;FMTTYPE=image/jpeg:https://marketingeda.com/wp-content/uploads/Synopsys-August-6-2024.jpeg END:VEVENT BEGIN:VEVENT DTSTART;TZID=America/Los_Angeles:20240725T100000 DTEND;TZID=America/Los_Angeles:20240725T110000 DTSTAMP:20240710T173759Z CREATED:20240710T173759Z LAST-MODIFIED:20240710T173759Z UID:8128-1721901600-1721905200@marketingeda.com SUMMARY:Applying Artificial Intelligence in Fab Technology Co-Optimization​​ DESCRIPTION:The common approach to optimize a fabrication process involves process and fab engineers creating and setting up Design of Experiments (DoEs) using a trial-and-error approach. This approach often leads to costly iterations since wafer fabrication is both expensive and time-consuming. Typically\, it can take weeks to months of experimentation\, depending on what process parameters are not meeting their targets. \nThe new approach described in this webinar\, already in production use today\, leverages artificial intelligence (AI) and machine learning (ML) to generate an accurate model of a fabrication step. The approach involves using TCAD digital models of a fab process (digital twin) that consider the actual physics and chemistry involved. This digital twin model is used to test and analyze using the same DoE methodology\, but without the need to fabricate multiple wafers\, thus saving the cycle times and costs associated with the fabrication. \nThis webinar will showcase this FTCO flow with examples to give you more insight into this flow and how you can apply it for you and your team’s needs. \nWhat You Will Learn \n\nIntroduction to FTCO\n\nDigital Twin\nMachine learning\nFab Technology Co-Optimization (FTCO)\nOverview of Silvaco’s tools enabling FTCO\n\n\nFTCO for Process Margin Analysis\n\nUse case example: STI trench modeling and optimization\n\n\nRTSM: A Real-Time 2D Structure Modeling Tool\nOther FTCO examples\n\nBio\nDr. Christian Caillat\, Senior Staff CAE\, Silvaco Inc. \nDr. Christian Caillat is a Senior Staff CAE at Silvaco\, based in Boise\, ID. Prior to joining Silvaco in June 2023\, he was with Micron Technology for 13 years\, where he contributed to various projects including emerging memory program collaboration with imec\, 3D NAND Cell team lead\, and advanced memory modeling. \nDr. Caillat holds an engineering degree in Electronics and a PhD in Microelectronics from the National Polytechnical Institute of Grenoble\, France. \nShare this:\n Share on LinkedIn (Opens in new window)\n LinkedIn\n \n Share on X (Opens in new window)\n X\n \n Share on Facebook (Opens in new window)\n Facebook\n Like this:Like Loading… URL:https://marketingeda.com/event/applying-artificial-intelligence-in-fab-technology-co-optimization/ CATEGORIES:EDA,Webinar ATTACH;FMTTYPE=image/jpeg:https://marketingeda.com/wp-content/uploads/Silvaco-July-25-2024.jpg END:VEVENT BEGIN:VEVENT DTSTART;TZID=America/Los_Angeles:20240724T080000 DTEND;TZID=America/Los_Angeles:20240725T170000 DTSTAMP:20240711T164050Z CREATED:20240711T160540Z LAST-MODIFIED:20240711T164050Z UID:8135-1721808000-1721926800@marketingeda.com SUMMARY:Chiplets: Building the Future of SoCs DESCRIPTION:Chiplets\, also known as heterogeneous multi-die systems\, are increasingly seen as the future of System on Chips (SoCs). They offer a solution to meet the growing demands of high-performance computing in various industries\, particularly fueled by the widespread adoption of AI technology. However\, while the concept of using chiplets to construct larger chips to overcome the limitations associated with building monolithic chips using advanced process technologies is promising in theory\, the practical implementation poses challenges. \nThe “Chiplets: Building the Future of SoCs” virtual event will delve into the complex considerations surrounding chiplet-based systems. Discussions will encompass the entire value chain and ecosystem\, spanning from initial concept and design exploration to packaging and testing. Moreover\, the event will examine the emergence of initiatives aiming to establish a chiplet marketplace\, exploring relevant standards and the actual feasibility of such endeavors. \nKey questions to be addressed include how to effectively integrate multiple dies from various foundries\, the methods for pre-validating these chips\, ensuring they meet specified standards\, and managing the integration of components and software. Additionally\, attention will be given to the development of a system integrator community\, strategies for enabling traceability and security within the chiplet supply chain\, and the potential economic viability of chiplet-based systems. \nCrucially\, the event will assess the industry’s readiness to foster the collaborative ecosystems necessary to support a chiplet economy. Will there be a proliferation of competing standards\, or will the industry converge around a unified standard like UCIe? Moreover\, the feasibility of economically designing chiplet-based systems will be scrutinized\, considering factors such as production costs and market demand. \n  \n\nWhat to expect?\nWith a conference space and resource center\, this event will function similarly to a live exhibition and conference. The conference includes keynotes\, panel discussions\, and technical presentations on a variety of subject matters\, including significant technical trends\, market demand and application areas. \nAttendees can expect an immersive exploration of the dynamic landscape of the chiplet and multi-die systems market. \nJuly 24: We’ll look at chiplet definitions\, standards\, and technologies. \nJuly 25: We’ll explore some real-world implementations of chiplet technologies\, and also the chiplet ecosystem. \n  \n\nWho should attend?\nBuilding future SoCs using chiplets involves a diverse range of disciplines\, making this event relevant to anyone involved in the value chain of constructing 2.5D\, 3D stacked heterogeneous systems that incorporate chiplet-style architectures. Whether you specialize in design\, validation\, packaging\, testing\, or provide services related to building these systems\, there will be valuable insights for you at this event. \nFrom automotive industry system developers to those working in data centers and beyond\, we’ll look to explore the technologies\, challenges\, opportunities\, and solutions. \nThis event caters to engineers\, researchers\, developers\, technical marketing professionals\, and industry professionals keen on understanding the potential opportunities and realities of working with and building chiplet-based systems. \n  \n\n\n\n\n\n\n\n  \n\n\n\n\n\n\n\n\n\n\nAgenda\n\n  \n\n\n\n\n\n\n\nAll Dates\n\n\n\n\n\n\n\n\n\nJuly 24 \n8:00 am – 8:10 am PDT \n\n\n\nOpening and start of the conference track “Chiplet Concepts – Principles and Promise”\n\nWelcome and Opening Nitin Dahad\, Editor-in-Chief\, Embedded.com \n\n\n\n\n\n\n\n\n\n\nJuly 24 \n8:10 am – 8:45 am PDT \n\n\n\n(CC1) Multi-Die Design in the Pervasive Intelligence Era\n\nThis Keynote is presented by Shankar Krishnamoorthy\, General Manager\, EDA Group\, Synopsys \nArtificial intelligence and silicon proliferation are shaping a new era of pervasive intelligence. At the forefront is the shift to multi-die\, driving the advancements of trillion-transistor systems and the march to angstroms. With its promise to enable significant compute performance\, heterogenous integration is a critical requirement in today’s AI-driven world. Join Shankar Krishnamoorthy\, the General Manager of Synopsys’ EDA Group\, as he explores the opportunities presented by multi-die design. \n\nRead More \n\n\n\n\n\n\n\n\n\nJuly 24 \n8:50 am – 9:25 am PDT \n\n\n\n(CC2) Universal Memory Interface (UMI): The solution to break the memory wall for AI ASICs\n\nThis Keynote is presented by Ramin Farjadrad is the founding CEO of Eliyan. \nCompute performance demand has been growing exponentially in recent years\, and with the advent of Generative AI\, this demand is growing even faster. Moore’s law coming to an end as well as the Memory Wall (memory bandwidth & capacity) and IO Wall are the main performance bottlenecks. The chiplet system-in-package (SiP) is the industry’s solution to these bottlenecks. Silicon interposers are industry’s main technology to connect chiplets in SiPs\, but they introduce several new bottlenecks. The largest interposer going to production is 2700mm2\, which is ~1/4 the largest standard package substrate. Thus\, a SiP with silicon interposer has limited compute & memory chiplets\, thus limited performance. This presentation introduces Universal Memory Interface (UMI)\, a high bandwidth efficient D2D connectivity technology between XPU-Memory & XPU-XPU\, which enables innovative architectures that help remove Memory & IO walls for next generation AI\, specifically Gen AI\, systems. \n\nRead More \n\n\n\n\n\n\n\n\n\nJuly 24 \n9:25 am – 9:35 am PDT \n\n\n\nTechnical Resources Time\n\nVisit the Resource Center which includes microsites from leading Chiplet companies with lots of technical information like White Papers\, Webinars\, Datasheets\, etc. \n\n\n\n\n\n\n\n\n\nJuly 24 \n9:35 am – 10:35 am PDT \n\n\n\n(CC3) The A to Z of Multi-Die Design\n\nThis Tutorial is presented by Tim Kogel\, Sr. Director for Technical Product Management\, Synopsys \nThis tutorial explains the intricacies of multi-die design\, covering topics from functional architecture and IP integration to implementation and signoff. It uses case studies to highlight the steps\, considerations\, and new innovations in multi-die designs. \n\n\n\n\n\n\n\n\n\n\nJuly 24 \n10:40 am – 11:25 am PDT \n\n\n\n(CC4) Panel Discussion: Taming Complexity – Building a Successful Open Chiplet Ecosystem\n\nThis Panel Discussion with industry experts is moderated by Nitin Dahad\, Editor-in-Chief\, Embedded.com. \nWhat is the current state of the commercial chiplet ecosystem\, and is a multi-company open ecosystem needed for chiplets to achieve their full potential? As we move from single company effort to a complex\, multi-supplier ecosystem\, we’ll discuss the biggest challenges we face\, including the need to manage and reduce supply chain complexity\, and doing so at reasonable cost. We’ll also talk about some of the practicalities. Do we have sufficient standards in place to enable the chiplet economy\, and is there appetite for industry and vendors to collaborate on these standards? Who takes ownership of the process when chiplets come from multiple suppliers\, and who is responsible for overall yield? And how do we ensure that all parts of the supply chain make money\, including smaller companies and startups? \nPanelists:\n– Ramin Farjadrad \, founding CEO\, Eliyan\n– Mohit Gupta\, Senior Vice President\, Alphawave Semi\n– Nick Ilyadis\, Vice President of Product Planning\, Achronix\n– Kenneth Larsen\, Product Management Director\, EDA Group\, Synopsys \n\nRead More \n\n\n\n\n\n\n\n\n\nJuly 24 \n11:25 am – 11:30 am PDT \n\n\n\nTechnical Resources Time\n\nVisit the Resource Center which includes microsites from leading Automotive companies with lots of technical information like White Papers\, Webinars\, Datasheets\, etc. \n\n\n\n\n\n\n\n\n\nJuly 24 \n11:30 am – 11:50 am PDT \n\n\n\n(CC5) Optimizing Next-Gen I/O Chiplet: Pioneering UCIe D2D Interconnects from 1.6 Terabits to 224 Gigabits\n\nPresented by Letizia Giuliano\, Vice President\, Alphawave Semi \nIn this presentation\, we will explore the benefits of adopting UCIe-enabled chiplet IP subsystems\, featuring state-of-the-art Multi-Standard SerDes I/O connectivity for advanced AI solutions. As the need for more powerful compute capability continues to grow\, the landscape and role of chiplets has become increasingly crucial for providing essential avenues for scalability\, efficiency\, and innovation in the infrastructure of next-generation AI data networks. We will review the obstacles associated with developing an interoperable 112G Multi-Lane and Multi-Standard I/O chiplet\, and share detailed implementation insights and outcomes from Alphawave Semi’s Chiplet portfolio. Furthermore\, we will demonstrate how AI connectivity use cases can be rapidly enhanced through the deployment of I/O Chiplets\, which are vital for today’s multi-Terabit I/O systems. The presentation will conclude with a discussion on the challenges facing the industry and propose solutions for advancing scale-up and scale-out connectivity options to meet the networking bandwidth demands of future AI systems. \n\nRead More \n\n\n\n\n\n\n\n\n\nJuly 24 \n11:50 am – 12:10 pm PDT \n\n\n\n(CC6) Chiplets for Everyone – Modular Re-usable Solution Powered by Patented Technology\n\nPresented by Kash Johal\, CEO and Founder\, YorChip \nToday\, Chiplets are primarily being deployed by MegaCap companies due to economics\, long lead-times\, and the complexity of development. QuickLogic and YorChip present a solution to deploy re-usable off-the-shelf Chiplets for everyone. Our solution empowers engineers at companies of any size to leverage chiplets:\n– Modular Chiplets: Ease connectivity and enable reuse across diverse customer designs.\n– Patented PHY: Supports both advanced and standard packaging\, lowering development cost and production deployment.\n– Legacy-Node PHY: Extends chiplet benefits to mix older process nodes (up to 90nm) with advanced nodes.\n– Routing Link Layer: Reduces Latency and helps eliminate signal integrity challenges.\n– AI Friendly: Chiplets specifically optimized for running Generative AI models at the edge. \nThe QuickLogic and YorChip collaboration empowers engineers at any size company to deploy chiplets for any application quickly and at low cost. \n\nRead More \n\n\n\n\n\n\n\n\n\nJuly 24 \n12:10 pm – 12:30 pm PDT \n\n\n\n(CC7) The Role of EDA as Chips Transform Into 3D Systems\n\nPresented by John Park\, Product Director\, Cadence \nWhat challenges will you face when pivoting from monolithic IC design to 3D heterogenous package design? How can electronic design automation (EDA) address these challenges? As we go from Moore’s Law to More-than-Moore\, technologies begin to converge across IC and systems design. This shift requires new advanced design flows combining EDA tools. These system-level design flows must enable seamless cross-domain co-design and analysis. The days of IC and package designers “throwing data over the wall” are over. Heterogeneous integration presents a new era of electronic product design with collaboration at its core – one that depends on the seamless interaction between analog/digital IC teams and package design teams. The use of advanced packaging technologies to combine smaller\, discrete chiplets into one SiP not only pushes the need for more advanced multi-die packaging\, but also makes packaging part of the process. This significantly reduces dependence on Moore’s Law at a time when building advanced monolithic SoCs is no longer the best option from a cost and technology perspective. \n\nRead More \n\n\n\n\n\n\n\n\n\nJuly 24 \n12:30 pm – 12:50 pm PDT \n\n\n\n(CC8) Taking 3DIC Heterogeneous Integration Mainstream\n\nPresented by Tony Mastroianni\, Advanced Packaging Solutions Director\, Siemens EDA \nHeterogeneous integration itself isn’t new\, but new design and manufacturing technologies\, combined with new product demands from system integrators\, means that heterogeneous integration and 3DIC are now becoming a necessity in mainstream design. This shift however is not without its challenges as 3D IC is not a simple extension of existing packaging solutions but creates a whole new set of Multiphysics integration considerations. The interaction of thermal\, mechanical\, reliability\, test\, and core semiconductor design increases complexity and requires disparate domains to seemly collaborate.In this presentation we will explore the challenges introduced by 3D IC\, the current state of the industry to address those challenges\, the ecosystem needed to support 3DIC\, and how users today can successfully adopt 3D IC leveraging new solutions\, workflows\, and 3D IC Design Kits (3D K) from Siemens EDA that are designed specifically with 3D IC in mind. \n  \n\nRead More \n\n\n\n\n\n\n\n\n\nJuly 24 \n12:50 pm – 1:10 pm PDT \n\n\n\n(CC9) UCIe Standard Versus UCIe Advanced – What Designers Need to Know\n\nPresented by Manuel Mota\, Principal Product Manager\, Synopsys \nThis technical presentation delves into the requirements and considerations for UCIe in standard and advanced packaging\, including density\, testing\, and the power and performance impact on the die-to-die implementation. The presentation will use real examples of UCIe silicon proofs to showcase the two variants of UCIe interfaces. \n\n\n\n\n\n\n\n\n\n\nJuly 24 \n1:10 pm – 1:20 pm PDT \n\n\n\nTechnical Resources Time\n\nVisit the Resource Center which includes microsites from leading Chiplet companies with lots of technical information like White Papers\, Webinars\, Datasheets\, etc. \n\n\n\n\n\n\n\n\n\nJuly 24 \n1:20 pm – 1:40 pm PDT \n\n\n\n(CC10) Celestial AI Photonic Fabric based 14.4Tbps Optical Chiplets for AI XPU Connectivity\n\nPresented by Dave Lazovsky\, CEO\, Celestial AI \nWith the growth in GenAI\, AI infrastructure is not just about the System on Chip but about the System of Chips. The bottleneck is no longer compute performance of a single XPU but scale-up interconnect bandwidth\, memory bandwidth and capacity. Photonic Fabric is the next generation optical interconnect technology offering >10X more performance than any competitive technology. Chiplets based on the Photonic Fabric and incorporating D2D interfaces like UCIe\, MAX3 etc are built in TSMC 5nm process and are fully compatible with standard 2.5D packaging flows for easy integration with XPUs. This enables XPUs to have optical interconnects for compute-to-compute and compute-to-memory fabrics that deliver Tbps bandwidth with nano-second latencies. XPUs can also seamlessly integrate with Photonic Fabric based memory solutions offering TBs of memory capacity at full HBM3 bandwidth. This innovation empowers hyperscalers to optimize the number of XPUs needed for training & inference\, improving the efficiency and economics of AI processing with significantly lower TCO2 impact. \n\nRead More \n\n\n\n\n\n\n\n\n\nJuly 24 \n1:40 pm – 2:00 pm PDT \n\n\n\n(CC11) Traceability and security for chiplet supply chain\n\nPresented by Jun Kawaguchi\, Marketing Executive\, Winbond \nThis presentation describes the issues relating to authenticity of individual chiplet and how to ensure the supply chain security is assured. A secure supply chain is becoming increasingly critical topic to counter cybersecurity concerns and the operation of critical systems such as infrastructure systems and autonomous vehicle application. There are trusted certification organizations that will audit and assure the supply chain to be intact\, however this becomes complex as multiple chiplets enter the supply chain. We will discuss these issues in the context of certified\, secure memory product that Winbond provides. \n\nRead More \n\n\n\n\n\n\n\n\n\nJuly 24 \n2:00 pm – 2:20 pm PDT \n\n\n\n(CC12) Innovations in AI Chip Packaging: Advanced Processes & Equipment Technologies\n\nPresented by Aaron Fellis\, Corporate Vice President\, Lam Research \nAs artificial intelligence (AI) continues to permeate diverse sectors\, from autonomous vehicles to healthcare\, there is increasing demand for more powerful and efficient AI chips. This has led to a paradigm shift\, with a focus not only on the performance of AI chips but also on their packaging. As the demand for higher processing power and energy efficiency grows\, advanced packaging becomes more essential to support these requirements\, driving sophisticated processes and equipment technologies that can handle the complexity of packaging AI chips. The presentation will shed light on equipment innovations and packaging methodologies that are shaping the future of AI chip technology. \n\nRead More \n\n\n\n\n\n\n\n\n\nJuly 24 \n2:20 pm – 2:55 pm PDT \n\n\n\n(CC13) Packaging matters: extending Moore’s law with “re-aggregation”\n\nThis Keynote is presented by Lalitha Immaneni\, VP of Semiconductor R&D\, Intel \nWith the arrival of ChatGPT\, Large Language Models (LLMs) have transformed AI into an interactive and accessible technology that recursively builds on its prior accomplishments\, fueling a new gold rush era of applications. AI models have exploded in complexity and size\, exerting demand pressure on both compute and memory. Over time\, Moore’s law has yielded a roughly 2x increase in compute every 2 years\, compared to the enormous 750x per year growth demand from the LLMs. Memory is an even trickier problem as it needs to address capacity\, speed and cost of data transport. Packaging plays a pivotal role in this era\, architecting bespoke solutions for a highly differentiated set of applications. We take a look at the role of disaggregation\, chiplets and interconnects in enabling the future of AI and HPC and illustrate this with solutions that can help create unique functionality\, performance\, and cost while enabling reuse and modularity. \n\nRead More \n\n\n\n\n\n\n\n\n\nJuly 24 \n2:55 pm – 3:15 pm PDT \n\n\n\n(CC14) Emerging Chiplet Ecosystems Enable Innovative Multi-Vendor Designs\n\nPresented by Elad Alon\, CEO and Co-Founder\, Blue Cheetah Analog Design \nChiplets reduce the rising costs of innovation. Heterogeneous compute\, especially AI applications\, stands to gain the most from chiplet-based designs. System architects are discovering that the keys to successful chiplet integration are an application-appropriate ecosystem and a customizable die-to-die (D2D) interconnect tailored for their end applications. \n\n\n\n\n\n\n\n\n\n\nJuly 25 \n8:00 am – 8:10 am PDT \n\n\n\nOpening and start of the conference track “Chiplet Technologies – Practicalities and Performance”\n\nWelcome and Opening by Sally Ward-Foxton\, Senior Reporter\, EE Times \n\n\n\n\n\n\n\n\n\n\nJuly 25 \n8:10 am – 8:45 am PDT \n\n\n\n(CP1) Jumpstart Your Chiplets Journey with End-to-End System Silicon Solutions\n\nThis Keynote is presented by David Glasco\, Vice President\, Compute Solutions Group\, Cadence. \nExplore the chiplet journey and gain insights into the reasons behind the increasing adoption of chiplets and the vital role that partners play in helping engineers succeed in their chiplet journey.  Learn how the right IP portfolio and IP teams can deliver on this journey with multiple engineering engagement models and strong industry partnerships.  See how design automation flows can help accelerate product time-to-market and reduce engineering costs. Understand how the design process can be automated and how virtual platforms and package design flows can significantly improve the engineering efficiency of chiplets. Join this keynote to discover the advantages and future potential of chiplets and how partners can help you succeed. \n\nRead More \n\n\n\n\n\n\n\n\n\nJuly 25 \n8:50 am – 9:25 am PDT \n\n\n\n(CP2) Chipletonomics : Economic foundation of future AI and HPC supercomputing.\n\nThis Keynote is presented by Sambit Sahu\, Senior Vice President at Krutrim\, an Ola company. \nThere is a huge surge in AI and HPC supercomputing currently and this will continue to accelerate. Generative AI explosion and associated multi-trillion dollar impact to revenue is triggering huge innovations in the AI space. HPC computing is on a rapid growth path with multiple supercomputers (multiple chips interconnected with high bandwidth and highly reliable network fabric and infrastructure) being built worldwide. Chiplets\, which are small pieces of silicon dies targeting a particular functionality\, are evolving rapidly as a concept and implementation style. In this presentation\, we will talk about how chiplets are going to address some of the key challenges of building next generation AI and HPC supercomputers. We will also demonstrate the significant economic advantages of chiplets architecture over conventional monolithic architectures. We will also demonstrate methodologies and approaches on how to use chiplets for your cost advantage. We will walk through how we are capitalizing on the chiplet strategy for economic advantage in building our high end AI server\, scaling upto a supercomputer. We will walk through strategies in optimizing NRE costs\, optimizing TCO\, optimizing on scaleout costs\, and optimizing on time to market\, and extending the benefits to additional products. \n\nRead More \n\n\n\n\n\n\n\n\n\nJuly 25 \n9:25 am – 9:35 am PDT \n\n\n\nTechnical Resources Time\n\nVisit the Resource Center which includes microsites from leading Chiplet companies with lots of technical information like White Papers\, Webinars\, Datasheets\, etc. \n\n\n\n\n\n\n\n\n\nJuly 25 \n9:35 am – 10:35 am PDT \n\n\n\n(CP3) Semiconductor design: Linking design to manufacturing for a sustainable semiconductor future\n\nTechnical Talk with Michael Munsey\, Vice President\, Siemens EDA and Sally Ward-Foxton\, Senior Reporter\, EE Times \nSemiconductor sustainability starts with design and the decisions made during the design process affect sustainability. This is amplified as we transition to the heterogeneous integration of chiplets using advanced substrate platforms such as 2.5/3D in order to continue silicon scaling. By linking the digital twins for semiconductor design to the digital twin of a semiconductor fab\, design details can be fed forward to optimize fabs for sustainability and manufacturing data can be fed back to optimize design libraries and decisions. In this talk\, we will talk about the evolution of the digital twin\, how new solutions aid design and manufacturability\, and the start of a new semiconductor era. \n\nRead More \n\n\n\n\n\n\n\n\n\nJuly 25 \n10:40 am – 11:25 am PDT \n\n\n\n(CP4) Panel Discussion: Lowering Barriers – Making Chiplets Work Together\n\nThis Panel Discussion with industry experts is moderated by Sally Ward-Foxton\, Senior Reporter\, EE Times. \nChiplets are attracting a lot of attention\, but which industries or verticals will benefit most from chiplets in the short term\, and why? We’ll start by talking about applications for chiplets and how they will evolve as the technology matures.We’ll discuss the biggest challenges to designing successful multi-die systems today. How do we ensure dies from different processes work together\, and what about dies designed by different companies? Are standards ready for this challenge\, and how are design tool vendors\, silicon vendors and IP providers taking it on? We’ll cover topics like multi-die system simulation\, emulation and verification\, and whether the complexity of these processes is limiting the size and scope of multi-die designs today. \nPanelists:\n– David Glasco\, Vice President\, Compute Solutions Group\, Cadence\n– Andreas Olofsson\, CEO\, Zero ASIC\n– Sambit Sahu\, Senior Vice President\, Krutrim\, an Ola company\n– John Sotir\, Senior Director\, Altera\, an Intel Company \n\nRead More \n\n\n\n\n\n\n\n\n\nJuly 25 \n11:25 am – 11:35 am PDT \n\n\n\nTechnical Resources Time\n\nVisit the Resource Center which includes microsites from leading Chiplet companies with lots of technical information like White Papers\, Webinars\, Datasheets\, etc. \n\n\n\n\n\n\n\n\n\nJuly 25 \n11:35 am – 12:10 pm PDT \n\n\n\n(CP5) Using composable chiplets to reduce ASIC design costs\n\nThis Keynote is presented by Andreas Olofsson\, CEO and founder of Zero ASIC. \nThe compounding effect of monolithic miniaturization on electronics has been nothing short of miraculous. Fifty plus years of Moore’s Law has resulted in a million fold improvement in computing cost and efficiency. Now that physical device scaling is approaching hard atomic limits\, the question is: Where will the next million fold computing efficiency improvement come from? Extreme domain specific circuit specialization can provide the next 1\,000 bost\, but the path is blocked by the prohibitive cost and complexity of ASIC design. Chiplets offer a compelling solution to reducing the cost and time of ASIC design\, but challenges remain. In this talk\, I will present my experience with chiplets over the last decade\, review the current obstacles\, and propose some potential paths for the future. \n\nRead More \n\n\n\n\n\n\n\n\n\nJuly 25 \n12:15 pm – 1:15 pm PDT \n\n\n\n(CP6) Unleashing AI Potential Through Advanced Chiplet Architecture\n\nThis Tutorial is presented by Dr. Tony Chan Carusone\, Chief Technology Officer\, Alphawave Semi \nIn this tutorial\, Tony Chan Carusone\, CTO of Alphawave Semi\, explores the crucial advancements required to propel the next generation of computing\, with a particular emphasis on AI as a transformative force reshaping our daily lives and data management systems. He highlights how pervasive connectivity\, from extensive optical fiber networks to intricate chiplet wirings\, is critical for AI functionalities. The discussion traces AI’s evolution over the last two decades. These developments are pivotal in meeting the computational demands\, from teraflops to petaflops\, while focusing on sustainability through chiplet-based designs. Additionally\, he will delve deeper into the chiplet architecture\, discussing how it revolutionizes cost and power efficiencies in AI applications. Tony will detail Alphawave Semi’s leadership in providing connectivity solutions specifically designed for chiplet architectures\, including the groundbreaking UCIe interface that offers a path up to 10 Tbps/mm bandwidth density. The session will further examine how AI is transforming data infrastructure connectivity\, highlighting the necessity for robust inter-chip links within datacenters and the reengineering of optical networks that cater to AI’s specific needs. The session wraps up by addressing the trend toward disaggregated computing and distributed data centers\, facilitated by low-latency connectivity. \n\nRead More \n\n\n\n\n\n\n\n\n\nJuly 25 \n1:15 pm – 1:25 pm PDT \n\n\n\nTechnical Resources Time\n\nVisit the Resource Center which includes microsites from leading Chiplet companies with lots of technical information like White Papers\, Webinars\, Datasheets\, etc. \n\n\n\n\n\n\n\n\n\nJuly 25 \n1:25 pm – 1:45 pm PDT \n\n\n\n(CP7) MIPS Accelerating the Chiplet Revolution: Powering the Future of GenAI\n\nPresented by Durgesh Srivastava\, Chief Technology Officer\, MIPS \nCompute requirements have outpaced supply by 10x. Historically\, HW advancements consistently outpaced SW. However\, the advent of GenAI has reversed this trend\, with SW developments now outstripping HW. Advanced algorithms\, especially those involving deep learning and large-scale data processing\, require vast processing power\, memory\, and efficient data handling. The computational demands of training and running GenAI models have pushed traditional silicon-based processors to their limits\, necessitating new hardware designs. Concurrently\, the slowdown of Moore’s Law has worsened these challenges. The chiplet architecture has emerged as a promising solution. This presentation will discuss how MIPS’ data-centric approach\, with the integration of the RISC-V ISA\, is driving the chiplet revolution\, optimizing data flow and processing efficiency to bridge the HW-SW gap and ensure ongoing computational advancements. \n\nRead More \n\n\n\n\n\n\n\n\n\nJuly 25 \n1:45 pm – 2:05 pm PDT \n\n\n\n(CP8) Multi-Die Health Management\n\nPresented by Dr. Yervant Zorian\, Chief Architect and Fellow\, Synopsys \nThis technical presentation discusses four multi-die health management solutions for different chiplet-to-chiplet configurations: Using IEEE 1838 for testing interconnects and dies (or chiplets) in a GPIO-based configuration\, using Synopsys SLM SMS EXT-RAM for test and repair of interconnects and DRAMs in an HBM-based logic-to-memory chiplet configuration\, using MTR for monitoring\, test\, and repair of interconnects in a UCIe-based chiplet-to-chiplet configuration\, using lane test and repair (LTR) for monitoring\, test\, and repair of light I/O in a TSV-based hybrid bonding configuration. \n\nRead More \n\n\n\n\n\n\n\n\n\nJuly 25 \n2:05 pm – 2:25 pm PDT \n\n\n\n(CP9) The Rise of Chiplets in Advanced AI/ML/High Performance Compute SoCs\n\nPresented by Jeff Twombly\, VP Business Development\, Credo \nThis presentation will cover critical SerDes IP development\, chiplet productization\, testing considerations to enable volume at scale\, and how Credo’s experience and infrastructure will enable more chiplet variants required for emerging I/O standards such as UCIe. Credo is a proven industry leader in providing high-performance\, low power chiplet solutions. Credo has two 3.2Tbps chiplets shipping in production. Credo developed all the necessary IP inhouse and combined our purpose built SerDes blocks to create the chiplet products. The 3.2Tbps Nutcracker device utilizes 32-lanes of 112G XSR SerDes to connect to the ASIC/SoC die and 32-lanes of 112G MR SerDes for the off-package\, line-side connectivity. The XSR interface can connect up to 50mm trace lengths on standard organic packaging substrates. The 3.2Tbps BlueJay device was developed to enable multi-chip module solutions using TSMCs CoWoS\, InFO\, and/or SoIC 3DFabric configuration technology. Credo developed a BoW (bunch of wires) interface to connect to the ASIC/SoC die and enables the off-package\, line-side connectivity with 64-lanes of 56Gbps LR SerDes. \n\nRead More \n\n\n\n\n\n\n\n\n\nJuly 25 \n2:25 pm – 2:45 pm PDT \n\n\n\n(CP10) Architecture challenges in meeting power\, thermal and performance needs in partitioning Chiplets for rapid deployment\n\nPresented by Deepak Shankar\, Founder and Chief Visionary\, Mirabilis Design \nDesign of chiplet architectures must transition from silicon-centric to system-centric. Early application-specific architecture exploration provides power\, latency\, throughput and thermal impact statistics to measure quality and efficiency. The exploration covers partitioning of heterogeneous compute resources onto chiplets\, task assignment\, maximize throughput and minimize latency\, manage power and thermal below the threshold for corner cases\, and scalability across workloads and tasks. System modeling using IP blocks enables this using multi-abstraction methodology with rapid modeling\, extensive exploration with constraints and optimization of the specification. During the session\, we will explain the exploration of real-life examples using system modeling. How to determine the best assignment of caches and memory at the host processor vs chiplet hub vs accelerator? How do you ensure chiplets are of the same dimension and thermal is equally distributed? How do you decide between UCIe standard vs advanced\, number of UCIe interfaces\, memory request distribution and coherency on performance? \n\nRead More \n\n\n\n\n\n\n\n\n\nJuly 25 \n2:45 pm – 2:55 pm PDT \n\n\n\nWrap-Up Session\n\n\n\n\n\n\n\n\nShare this:\n Share on LinkedIn (Opens in new window)\n LinkedIn\n \n Share on X (Opens in new window)\n X\n \n Share on Facebook (Opens in new window)\n Facebook\n Like this:Like Loading… URL:https://marketingeda.com/event/chiplets-building-the-future-of-socs/ CATEGORIES:EDA,IP,Webinar ATTACH;FMTTYPE=image/jpeg:https://marketingeda.com/wp-content/uploads/EE-Times-July-24-25-2024.jpg END:VEVENT BEGIN:VEVENT DTSTART;TZID=America/Los_Angeles:20240724T080000 DTEND;TZID=America/Los_Angeles:20240724T090000 DTSTAMP:20240710T164355Z CREATED:20240710T164355Z LAST-MODIFIED:20240710T164355Z UID:8118-1721808000-1721811600@marketingeda.com SUMMARY:Simulating AMD's next-gen Versal Adaptive SoC devices using Questasim DESCRIPTION:Versal Adaptive SoC\, a revolutionary adaptable platform developed by AMD\, integrates several key components such as the AI Engine (AIE)\, Processing System (PS)\, Programmable Logic (PL)\, Network on Chip (NoC)\, and a diverse array of specialized IPs. This innovative platform facilitates the efficient execution of intricate algorithms spanning from machine learning to high-performance computing tasks. In our upcoming webinar\, we aim to provide an in-depth guide on running simulation flows for a Versal Adaptive SoC. Additionally\, we’ll delve into QEMU\, the open-source system emulator\, and its co-simulation interface with Questa. Demonstrating how to conduct a system simulation of a Versal example design will be a focal point\, showcasing Questa’s support for system simulation of Versal designs based on the Vitis™ hardware emulation flow. This comprehensive setup\, including hardware emulation and system integration\, is seamlessly achieved within the Vitis environment. It incorporates the AIE simulator for graph applications\, Questasim for PL kernels\, and QEMU for PS host applications. \nWhat you will learn: \n‌\nHow to use Questa to simulate AMD’s Versal Adaptive SoC designs\n‌ \nWho should attend: \nUsers Looking into the latest AMD Versal devices and wanting to simulate the designs using a commercial simulator \nWhat/Which Products are Covered:   \n\nQuestasim\n\nSpeaker:\n\n\n\n\n\n\nFan Zhang\nProduct Engineer\, Siemens EDA\n\n\n\n\nFan Zhang is currently a Product Engineer at Siemens EDA Software. He has been working in Design and Verification\, and EDA companies for the last 16 years. He graduated with a MS in Computer Engineering from Texas A&M University. \nHe previously worked at AMD as a Design Engineer\, Nvidia and Cadence as a Verification Engineer before joining Siemens as a Product Engineer. \nFan likes to go hiking and camping in his spare time and loves to swim. \n\n\n\nShare this:\n Share on LinkedIn (Opens in new window)\n LinkedIn\n \n Share on X (Opens in new window)\n X\n \n Share on Facebook (Opens in new window)\n Facebook\n Like this:Like Loading… URL:https://marketingeda.com/event/simulating-amds-next-gen-versal-adaptive-soc-devices-using-questasim/ CATEGORIES:EDA,Webinar ATTACH;FMTTYPE=image/jpeg:https://marketingeda.com/wp-content/uploads/Siemens-July-24-2024.jpg END:VEVENT BEGIN:VEVENT DTSTART;TZID=America/Los_Angeles:20240717T100000 DTEND;TZID=America/Los_Angeles:20240717T110000 DTSTAMP:20240715T161354Z CREATED:20240715T161354Z LAST-MODIFIED:20240715T161354Z UID:8149-1721210400-1721214000@marketingeda.com SUMMARY:Enhancing Manufacturing Test Flows with Synopsys VC Z01X DESCRIPTION:Leveraging functional patterns is crucial for achieving high defect coverage and reducing defective parts per million (DPPM) levels. Synopsys VC Z01X fault simulator offers enhanced fault coverage in manufacturing test flows\, complementing ATPG tools like Synopsys TestMAX ATPG. In this presentation we will delve into unique coverage scenarios\, such as resets and clocks blocked during ATPG mode. We’ll also highlight the benefits of VC Z01X robust support of the SystemVerilog language. Finally\, a practical flow discussion will equip viewers with best practices to get started. \n\n\n\n\n\n\n\n\n\n\nSpeakers\n\n\nListed below are the industry leaders scheduled to speak. \n\n\n\n\n\n\n\n\n\n\n\n\n\n\n\n\n\n\n\n\n\n\n\n\n\n\nRobert Ruiz\n\n\nProduct Management Director\nSynopsys \n\n\n\n\n\n\n\n\n\n\n\nRobert Ruiz is a product management director responsible for strategy and business growth of several verification products at Synopsys. Robert has held various marketing and technical positions for leading functional verification and test automation products at various companies including Synopsys\, Novas Software\, and Viewlogic Systems. He has more than 30 years of experience in advanced EDA technologies and methodologies and spent several years designing application-specific integrated circuits (ASICs). Robert has a BSEE degree from Stanford University. \n\n\n\n\n\n\n\n\n\n\n\n\n\n\n\n\n\n\n\n\n\n\n\n\n\n\n\n\n\n\n\nKirankumar Karanam\n\n\nApplications Engineer\, Manager\nSynopsys \n\n\n\n\n\n\n\n\n\n\n\nKirankumar Karanam is Staff Application Engineer at Synopsys. He currently oversees various customer deployments of Synopsys FuSa verification solutions worldwide. He also works with Synopsys functional verification offerings such as VCS\, Verdi\, and more. He holds M.S in Software Systems from BITS\, Pilani. \n\n\n\n\n\n\n\n\n\n\nShare this:\n Share on LinkedIn (Opens in new window)\n LinkedIn\n \n Share on X (Opens in new window)\n X\n \n Share on Facebook (Opens in new window)\n Facebook\n Like this:Like Loading… URL:https://marketingeda.com/event/enhancing-manufacturing-test-flows-with-synopsys-vc-z01x/ CATEGORIES:EDA,Webinar ATTACH;FMTTYPE=image/jpeg:https://marketingeda.com/wp-content/uploads/Synopsys-July-17-2024.jpg END:VEVENT BEGIN:VEVENT DTSTART;TZID=America/Los_Angeles:20240717T100000 DTEND;TZID=America/Los_Angeles:20240717T110000 DTSTAMP:20240628T030757Z CREATED:20240628T030757Z LAST-MODIFIED:20240628T030757Z UID:8107-1721210400-1721214000@marketingeda.com SUMMARY:Efficient Way to UVM Constraint Randomization Debug DESCRIPTION:Become skilled at the art of UVM randomization debugging! \n\n\n\n\n\n\n\n\n\n\n\n\nDate: Wednesday\, July 17\, 2024 \nTime: 10:00am PDT | 1:00pm EDT \nThis webinar equips you with effective strategies to tackle randomization-related errors within your UVM verification environment. We’ll explore the power of Cadence’s Verisium Debug\, a tool designed to simplify the debugging process. \n\n\n\n\n\n\n\n\n\n\n\n\nWhat You Will Learn \n\n\n\n\n\n\n\n\n\n\n\n\n\nPractical techniques for isolating and resolving randomization-related errors\nOptimize your UVM verification environment for robust functionality\nGain valuable insights into best practices for UVM randomization debugging\n\n\n\n\n\n\n\n\n\n\n\n\n\nWho Should Attend \n\n\n\n\n\n\n\n\n\n\n\n\nThis webinar is designed for verification engineers of all levels who want to become skilled in the art of UVM randomization debugging. \n\n\n\n\n\n\n\n\n\n\n\n\nSpeakers \n\n\n\n\n\n\n\n\n\n\n\n\n\nNadav Chazen\, Product Engineering Architect\, Cadence\nRich Chang\, Product Marketing Director\, Cadence\n\n\n\n\n\n\n\nShare this:\n Share on LinkedIn (Opens in new window)\n LinkedIn\n \n Share on X (Opens in new window)\n X\n \n Share on Facebook (Opens in new window)\n Facebook\n Like this:Like Loading… URL:https://marketingeda.com/event/efficient-way-to-uvm-constraint-randomization-debug/ CATEGORIES:EDA,Webinar ATTACH;FMTTYPE=image/jpeg:https://marketingeda.com/wp-content/uploads/Cadence-July-17-2024.jpg END:VEVENT BEGIN:VEVENT DTSTART;TZID=America/Los_Angeles:20240716T100000 DTEND;TZID=America/Los_Angeles:20240716T110000 DTSTAMP:20240528T172552Z CREATED:20240528T172552Z LAST-MODIFIED:20240528T172552Z UID:8060-1721124000-1721127600@marketingeda.com SUMMARY:Maximize Productivity with Deep Insights into PPA Trajectories DESCRIPTION:The digital chip design flow carries with it an enormous wealth of untapped information regarding the health and status of your SoC design. The ability to efficiently mine this data provides chip designers with comprehensive visibility and actionable insights to uncover PPA opportunities. This webinar will introduce you to Synopsys Design.da\, the industry’s first comprehensive data-visibility and analytic-driven design optimization and signoff closure solution. We’ll show you how to leverage vast datasets to bring unmatched productivity and a better\, faster\, and smarter way to design. We’ll highlight how to siphon metrics data while curating associate analysis data efficiently and automatically to pinpoint areas of focus in real-time. We’ll show you how the Synopsys Design.da solution performs analysis to identify PPA bottlenecks and the root-cause. The solution automatically classifies design trends\, identifies limitations\, and provides prescriptive guided root-cause analysis across the entire design flow. \n\n\n\n\n\n\n\n\n\n\nSpeakers\n\n\nListed below are the industry leaders scheduled to speak. \n\n\n\n\n\n\n\n\n\n\n\n\n\n\n\n\n\n\n\n\n\n\n\n\n\n\nJim Schultz\n\n\nProduct Mgmt Mgr\, Sr Staff\nSynopsys \n\n\n\n\n\n\n\n\n\n\n\nJim Schultz is a senior staff product manager for the Synopsys EDA Group. He holds a B.S. in electrical engineering from the University of California\, Davis with an emphasis in electromagnetics. His design engineering experience includes physical verification\, design planning and design implementation on CPUs\, networking and security chips. As a product engineer\, he has supported design implementation\, design planning and package design at various EDA companies. \n\n\n\n\n\n\n\n\n\n\nShare this:\n Share on LinkedIn (Opens in new window)\n LinkedIn\n \n Share on X (Opens in new window)\n X\n \n Share on Facebook (Opens in new window)\n Facebook\n Like this:Like Loading… URL:https://marketingeda.com/event/maximize-productivity-with-deep-insights-into-ppa-trajectories/ CATEGORIES:EDA,Webinar ATTACH;FMTTYPE=image/jpeg:https://marketingeda.com/wp-content/uploads/Synopsys-July-16-2024.jpeg END:VEVENT BEGIN:VEVENT DTSTART;TZID=Asia/Kolkata:20240709T120000 DTEND;TZID=Asia/Kolkata:20240709T160000 DTSTAMP:20240621T162414Z CREATED:20240621T162353Z LAST-MODIFIED:20240621T162414Z UID:8103-1720526400-1720540800@marketingeda.com SUMMARY:Ensuring my Design Verification is ISO26262 Compliant DESCRIPTION:With the widespread of the modern automobiles\, run and regulated by automotive ECUs\, the need for advanced safety features has also become inevitable. And this is why today modern vehicles are required to adhere to the safety standards listed within the Automotive Safety Integrity Level (ASIL).In this DVClub meeting our speakers will share best practices in Verification of automotive designs that need to be ISO26262 compliant. \nAgenda (IST)\n12:00    Welcome and Introduction – Tessolve\n12:00    External Speaker\n12:30    External Speaker\n13:00    Lunch & Networking\n14:00    Sundararajan Ananthakrishnan\, Cadence Design System – Ensuring my Design Verification is ISO26262 Compliant\n15:00  Dr. Mike Bartley & Marmik Soni\, Tessolve Semiconductor Pvt Ltd – Refining ISO 26262 practices by adopting GenAI\n16:00     Refreshments & Networking \nRegister now to become a part of this event. Free to attend in-person & online. \n\nTicket Tailor- DVClub India \nDVClub India is made possible through the generous support of our sponsors: Cadence & Tessolve \n\nShare this:\n Share on LinkedIn (Opens in new window)\n LinkedIn\n \n Share on X (Opens in new window)\n X\n \n Share on Facebook (Opens in new window)\n Facebook\n Like this:Like Loading… URL:https://marketingeda.com/event/ensuring-my-design-verification-is-iso26262-compliant/ LOCATION:Cadence\, Bengaluru\, Sarjapur Outer Ring Road\, Bengaluru\, 560103\, India CATEGORIES:EDA,Symposium,Webinar ATTACH;FMTTYPE=image/jpeg:https://marketingeda.com/wp-content/uploads/DVClub-India-2024.jpg END:VEVENT BEGIN:VEVENT DTSTART;TZID=America/Los_Angeles:20240709T090000 DTEND;TZID=America/Los_Angeles:20240709T100000 DTSTAMP:20240618T194728Z CREATED:20240618T194728Z LAST-MODIFIED:20240618T194728Z UID:8098-1720515600-1720519200@marketingeda.com SUMMARY:How to Reduce Thousands of False Errors in 15 Minutes DESCRIPTION:Analyzing electrical errors across an IP or a SoC at top level\, can be a painful and long process\, often requiring extensive setup time and hundred of hours to distinguish real issues from false positives. \nTo address this challenge\, Aniah developed OneCheck\, a formal analysis tool capable of detecting 100% of electrical errors at the transistor level. With intelligent features\, it reduces false positives and groups replicated errors by root cause. \nJoin our webinar for an in-depth look at Aniah OneCheck and its SmartClustering technology\, presented by CEO Vincent Bligny. Through a live demo on a 20 million transistor SoC design\, you’ll witness OneCheck’s powerful formal analysis and SmartClustering capabilities in action\, streamlining setup\, processing\, and analysis. \nDiscover in this insightful session for technical experts how modern Electrical Rules Checking solution\, with SmartClustering intelligence can transform your verification workflows. \nSpeaker Bio :\nVincent Bligny is a renowned expert in mixed-signal verification\, particularly with transistor-level formal techniques. He spent 15 years in this industry\, mainly within STMicroelectronics’ design and verification teams\, allowing him to understand the challenges and opportunities of the EDA field. In 2019\, Vincent co-founded Aniah with the vision of delivering an ERC tool that empowers 100% of designers to find 100% of errors efficiently. Driven by a designer-centric approach\, Aniah’s tool for ERC aims to improve the verification process and bring products to market more effectively\, while simplifying the lives of designers! \n*This webinar is in partnership with SemiWiki and Aniah \nShare this:\n Share on LinkedIn (Opens in new window)\n LinkedIn\n \n Share on X (Opens in new window)\n X\n \n Share on Facebook (Opens in new window)\n Facebook\n Like this:Like Loading… URL:https://marketingeda.com/event/how-to-reduce-thousands-of-false-errors-in-15-minutes/ CATEGORIES:EDA,Webinar ATTACH;FMTTYPE=image/png:https://marketingeda.com/wp-content/uploads/Aniah-July-9-2024.png END:VEVENT BEGIN:VEVENT DTSTART;TZID=America/Los_Angeles:20240625T100000 DTEND;TZID=America/Los_Angeles:20240625T110000 DTSTAMP:20240612T164153Z CREATED:20240612T164153Z LAST-MODIFIED:20240612T164153Z UID:8090-1719309600-1719313200@marketingeda.com SUMMARY:Developing Silicon Carbide DMOSFETS: A Digital Twin Design Reference Flow DESCRIPTION:This webinar presents a comprehensive methodology for the design and optimization of a 1200V Silicon Carbide (SiC) Double-Diffused Metal-Oxide-Semiconductor Field-Effect Transistor (DMOS FET) utilizing Silvaco’s TCAD platform. Adhering to industry best practices\, the construction of an accurate digital twin is also presented\, ensuring conformity to real-world performance characteristics. Moreover\, we outline strategies to streamline simulation workflows\, emphasizing techniques to boost design efficiency and productivity. \nIn parallel\, this webinar explores the transformative impact of Machine Learning (ML) on traditional device design practices. By harnessing ML algorithms\, a fundamental shift occurs in the approach towards device design\, enabling process and device engineers to extract insights from vast datasets\, optimize performance\, and expedite the design iteration process. \nAdditionally\, the necessity of incorporating compact modeling into the design flow is underscored. Compact modeling serves as a crucial component in capturing device behavior accurately\, enabling efficient circuit-level simulations and facilitating rapid prototyping of devices. The integration of compact modeling enhances the design process\, facilitating a more holistic understanding of device behavior and performance characteristics. \nThrough the integration of TCAD\, simulation optimization\, ML techniques\, and compact modeling\, this webinar demonstrates a synergistic approach towards device design\, fostering innovation\, precision\, and efficiency. \nShare this:\n Share on LinkedIn (Opens in new window)\n LinkedIn\n \n Share on X (Opens in new window)\n X\n \n Share on Facebook (Opens in new window)\n Facebook\n Like this:Like Loading… URL:https://marketingeda.com/event/developing-silicon-carbide-dmosfets-a-digital-twin-design-reference-flow/ CATEGORIES:EDA,Webinar ATTACH;FMTTYPE=image/jpeg:https://marketingeda.com/wp-content/uploads/Silvaco-June-25-2024-1.jpg END:VEVENT BEGIN:VEVENT DTSTART;TZID=America/Los_Angeles:20240625T100000 DTEND;TZID=America/Los_Angeles:20240625T110000 DTSTAMP:20240529T185102Z CREATED:20240529T185102Z LAST-MODIFIED:20240529T185102Z UID:8070-1719309600-1719313200@marketingeda.com SUMMARY:Developing Silicon Carbide DMOSFETS: A Digital Twin Reference Flow DESCRIPTION:This webinar presents a comprehensive methodology for the design and optimization of a 1200V Silicon Carbide (SiC) Double-Diffused Metal-Oxide-Semiconductor Field-Effect Transistor (DMOS FET) utilizing Silvaco’s TCAD platform. Adhering to industry best practices\, the construction of an accurate digital twin is also presented\, ensuring conformity to real-world performance characteristics. Moreover\, we outline strategies to streamline simulation workflows\, emphasizing techniques to boost design efficiency and productivity. \nIn parallel\, this webinar explores the transformative impact of Machine Learning (ML) on traditional device design practices. By harnessing ML algorithms\, a fundamental shift occurs in the approach towards device design\, enabling process and device engineers to extract insights from vast datasets\, optimize performance\, and expedite the design iteration process. \nAdditionally\, the necessity of incorporating compact modeling into the design flow is underscored. Compact modeling serves as a crucial component in capturing device behavior accurately\, enabling efficient circuit-level simulations and facilitating rapid prototyping of devices. The integration of compact modeling enhances the design process\, facilitating a more holistic understanding of device behavior and performance characteristics. \nThrough the integration of TCAD\, simulation optimization\, ML techniques\, and compact modeling\, this webinar demonstrates a synergistic approach towards device design\, fostering innovation\, precision\, and efficiency. \nThis Virtual Webinar is from 10:00-11:00am PT. \n  \nShare this:\n Share on LinkedIn (Opens in new window)\n LinkedIn\n \n Share on X (Opens in new window)\n X\n \n Share on Facebook (Opens in new window)\n Facebook\n Like this:Like Loading… URL:https://marketingeda.com/event/developing-silicon-carbide-dmosfets-a-digital-twin-reference-flow/ CATEGORIES:EDA,Webinar ATTACH;FMTTYPE=image/jpeg:https://marketingeda.com/wp-content/uploads/Silvaco-June-25-2024.jpg END:VEVENT END:VCALENDAR