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BEGIN:VEVENT
DTSTART;TZID=America/Los_Angeles:20240717T100000
DTEND;TZID=America/Los_Angeles:20240717T110000
DTSTAMP:20240628T030757Z
CREATED:20240628T030757Z
LAST-MODIFIED:20240628T030757Z
UID:8107-1721210400-1721214000@marketingeda.com
SUMMARY:Efficient Way to UVM Constraint Randomization Debug
DESCRIPTION:Become skilled at the art of UVM randomization debugging! \n\n\n\n\n\n\n\n\n\n\n\n\nDate: Wednesday\, July 17\, 2024 \nTime: 10:00am PDT | 1:00pm EDT \nThis webinar equips you with effective strategies to tackle randomization-related errors within your UVM verification environment. We’ll explore the power of Cadence’s Verisium Debug\, a tool designed to simplify the debugging process. \n\n\n\n\n\n\n\n\n\n\n\n\nWhat You Will Learn \n\n\n\n\n\n\n\n\n\n\n\n\n\nPractical techniques for isolating and resolving randomization-related errors\nOptimize your UVM verification environment for robust functionality\nGain valuable insights into best practices for UVM randomization debugging\n\n\n\n\n\n\n\n\n\n\n\n\n\nWho Should Attend \n\n\n\n\n\n\n\n\n\n\n\n\nThis webinar is designed for verification engineers of all levels who want to become skilled in the art of UVM randomization debugging. \n\n\n\n\n\n\n\n\n\n\n\n\nSpeakers \n\n\n\n\n\n\n\n\n\n\n\n\n\nNadav Chazen\, Product Engineering Architect\, Cadence\nRich Chang\, Product Marketing Director\, Cadence\n\n\n\n\n\n\n\nShare this:\n				Share on LinkedIn (Opens in new window)\n				LinkedIn\n			\n				Share on X (Opens in new window)\n				X\n			\n				Share on Facebook (Opens in new window)\n				Facebook\n			Like this:Like Loading…
URL:https://marketingeda.com/event/efficient-way-to-uvm-constraint-randomization-debug/
CATEGORIES:EDA,Webinar
ATTACH;FMTTYPE=image/jpeg:https://marketingeda.com/wp-content/uploads/Cadence-July-17-2024.jpg
END:VEVENT
BEGIN:VEVENT
DTSTART;TZID=America/Los_Angeles:20240716T100000
DTEND;TZID=America/Los_Angeles:20240716T110000
DTSTAMP:20240528T172552Z
CREATED:20240528T172552Z
LAST-MODIFIED:20240528T172552Z
UID:8060-1721124000-1721127600@marketingeda.com
SUMMARY:Maximize Productivity with Deep Insights into PPA Trajectories
DESCRIPTION:The digital chip design flow carries with it an enormous wealth of untapped information regarding the health and status of your SoC design. The ability to efficiently mine this data provides chip designers with comprehensive visibility and actionable insights to uncover PPA opportunities. This webinar will introduce you to Synopsys Design.da\, the industry’s first comprehensive data-visibility and analytic-driven design optimization and signoff closure solution. We’ll show you how to leverage vast datasets to bring unmatched productivity and a better\, faster\, and smarter way to design. We’ll highlight how to siphon metrics data while curating associate analysis data efficiently and automatically to pinpoint areas of focus in real-time. We’ll show you how the Synopsys Design.da solution performs analysis to identify PPA bottlenecks and the root-cause. The solution automatically classifies design trends\, identifies limitations\, and provides prescriptive guided root-cause analysis across the entire design flow. \n\n\n\n\n\n\n\n\n\n\nSpeakers\n\n\nListed below are the industry leaders scheduled to speak. \n\n\n\n\n\n\n\n\n\n\n\n\n\n\n\n\n\n\n\n\n\n\n\n\n\n\nJim Schultz\n\n\nProduct Mgmt Mgr\, Sr Staff\nSynopsys \n\n\n\n\n\n\n\n\n\n\n\nJim Schultz is a senior staff product manager for the Synopsys EDA Group. He holds a B.S. in electrical engineering from the University of California\, Davis with an emphasis in electromagnetics. His design engineering experience includes physical verification\, design planning and design implementation on CPUs\, networking and security chips. As a product engineer\, he has supported design implementation\, design planning and package design at various EDA companies. \n\n\n\n\n\n\n\n\n\n\nShare this:\n				Share on LinkedIn (Opens in new window)\n				LinkedIn\n			\n				Share on X (Opens in new window)\n				X\n			\n				Share on Facebook (Opens in new window)\n				Facebook\n			Like this:Like Loading…
URL:https://marketingeda.com/event/maximize-productivity-with-deep-insights-into-ppa-trajectories/
CATEGORIES:EDA,Webinar
ATTACH;FMTTYPE=image/jpeg:https://marketingeda.com/wp-content/uploads/Synopsys-July-16-2024.jpeg
END:VEVENT
BEGIN:VEVENT
DTSTART;TZID=Asia/Kolkata:20240709T120000
DTEND;TZID=Asia/Kolkata:20240709T160000
DTSTAMP:20240621T162414Z
CREATED:20240621T162353Z
LAST-MODIFIED:20240621T162414Z
UID:8103-1720526400-1720540800@marketingeda.com
SUMMARY:Ensuring my Design Verification is ISO26262 Compliant
DESCRIPTION:With the widespread of the modern automobiles\, run and regulated by automotive ECUs\, the need for advanced safety features has also become inevitable. And this is why today modern vehicles are required to adhere to the safety standards listed within the Automotive Safety Integrity Level (ASIL).In this DVClub meeting our speakers will share best practices in Verification of automotive designs that need to be ISO26262 compliant. \nAgenda (IST)\n12:00    Welcome and Introduction – Tessolve\n12:00    External Speaker\n12:30    External Speaker\n13:00    Lunch & Networking\n14:00    Sundararajan Ananthakrishnan\, Cadence Design System – Ensuring my Design Verification is ISO26262 Compliant\n15:00  Dr. Mike Bartley & Marmik Soni\, Tessolve Semiconductor Pvt Ltd – Refining ISO 26262 practices by adopting GenAI\n16:00     Refreshments & Networking \nRegister now to become a part of this event. Free to attend in-person & online. \n\nTicket Tailor- DVClub India \nDVClub India is made possible through the generous support of our sponsors: Cadence & Tessolve \n\nShare this:\n				Share on LinkedIn (Opens in new window)\n				LinkedIn\n			\n				Share on X (Opens in new window)\n				X\n			\n				Share on Facebook (Opens in new window)\n				Facebook\n			Like this:Like Loading…
URL:https://marketingeda.com/event/ensuring-my-design-verification-is-iso26262-compliant/
LOCATION:Cadence\, Bengaluru\, Sarjapur Outer Ring Road\, Bengaluru\, 560103\, India
CATEGORIES:EDA,Symposium,Webinar
ATTACH;FMTTYPE=image/jpeg:https://marketingeda.com/wp-content/uploads/DVClub-India-2024.jpg
END:VEVENT
BEGIN:VEVENT
DTSTART;TZID=America/Los_Angeles:20240709T090000
DTEND;TZID=America/Los_Angeles:20240709T100000
DTSTAMP:20240618T194728Z
CREATED:20240618T194728Z
LAST-MODIFIED:20240618T194728Z
UID:8098-1720515600-1720519200@marketingeda.com
SUMMARY:How to Reduce Thousands of False Errors in 15 Minutes
DESCRIPTION:Analyzing electrical errors across an IP or a SoC at top level\, can be a painful and long process\, often requiring extensive setup time and hundred of hours to distinguish real issues from false positives. \nTo address this challenge\, Aniah developed OneCheck\, a formal analysis tool capable of detecting 100% of electrical errors at the transistor level. With intelligent features\, it reduces false positives and groups replicated errors by root cause. \nJoin our webinar for an in-depth look at Aniah OneCheck and its SmartClustering technology\, presented by CEO Vincent Bligny. Through a live demo on a 20 million transistor SoC design\, you’ll witness OneCheck’s powerful formal analysis and SmartClustering capabilities in action\, streamlining setup\, processing\, and analysis. \nDiscover in this insightful session for technical experts how modern Electrical Rules Checking solution\, with SmartClustering intelligence can transform your verification workflows. \nSpeaker Bio :\nVincent Bligny is a renowned expert in mixed-signal verification\, particularly with transistor-level formal techniques. He spent 15 years in this industry\, mainly within STMicroelectronics’ design and verification teams\, allowing him to understand the challenges and opportunities of the EDA field. In 2019\, Vincent co-founded Aniah with the vision of delivering an ERC tool that empowers 100% of designers to find 100% of errors efficiently. Driven by a designer-centric approach\, Aniah’s tool for ERC aims to improve the verification process and bring products to market more effectively\, while simplifying the lives of designers! \n*This webinar is in partnership with SemiWiki and Aniah \nShare this:\n				Share on LinkedIn (Opens in new window)\n				LinkedIn\n			\n				Share on X (Opens in new window)\n				X\n			\n				Share on Facebook (Opens in new window)\n				Facebook\n			Like this:Like Loading…
URL:https://marketingeda.com/event/how-to-reduce-thousands-of-false-errors-in-15-minutes/
CATEGORIES:EDA,Webinar
ATTACH;FMTTYPE=image/png:https://marketingeda.com/wp-content/uploads/Aniah-July-9-2024.png
END:VEVENT
BEGIN:VEVENT
DTSTART;TZID=America/Los_Angeles:20240625T100000
DTEND;TZID=America/Los_Angeles:20240625T110000
DTSTAMP:20240612T164153Z
CREATED:20240612T164153Z
LAST-MODIFIED:20240612T164153Z
UID:8090-1719309600-1719313200@marketingeda.com
SUMMARY:Developing Silicon Carbide DMOSFETS: A Digital Twin Design Reference Flow
DESCRIPTION:This webinar presents a comprehensive methodology for the design and optimization of a 1200V Silicon Carbide (SiC) Double-Diffused Metal-Oxide-Semiconductor Field-Effect Transistor (DMOS FET) utilizing Silvaco’s TCAD platform. Adhering to industry best practices\, the construction of an accurate digital twin is also presented\, ensuring conformity to real-world performance characteristics. Moreover\, we outline strategies to streamline simulation workflows\, emphasizing techniques to boost design efficiency and productivity. \nIn parallel\, this webinar explores the transformative impact of Machine Learning (ML) on traditional device design practices. By harnessing ML algorithms\, a fundamental shift occurs in the approach towards device design\, enabling process and device engineers to extract insights from vast datasets\, optimize performance\, and expedite the design iteration process. \nAdditionally\, the necessity of incorporating compact modeling into the design flow is underscored. Compact modeling serves as a crucial component in capturing device behavior accurately\, enabling efficient circuit-level simulations and facilitating rapid prototyping of devices. The integration of compact modeling enhances the design process\, facilitating a more holistic understanding of device behavior and performance characteristics. \nThrough the integration of TCAD\, simulation optimization\, ML techniques\, and compact modeling\, this webinar demonstrates a synergistic approach towards device design\, fostering innovation\, precision\, and efficiency. \nShare this:\n				Share on LinkedIn (Opens in new window)\n				LinkedIn\n			\n				Share on X (Opens in new window)\n				X\n			\n				Share on Facebook (Opens in new window)\n				Facebook\n			Like this:Like Loading…
URL:https://marketingeda.com/event/developing-silicon-carbide-dmosfets-a-digital-twin-design-reference-flow/
CATEGORIES:EDA,Webinar
ATTACH;FMTTYPE=image/jpeg:https://marketingeda.com/wp-content/uploads/Silvaco-June-25-2024-1.jpg
END:VEVENT
BEGIN:VEVENT
DTSTART;TZID=America/Los_Angeles:20240625T100000
DTEND;TZID=America/Los_Angeles:20240625T110000
DTSTAMP:20240529T185102Z
CREATED:20240529T185102Z
LAST-MODIFIED:20240529T185102Z
UID:8070-1719309600-1719313200@marketingeda.com
SUMMARY:Developing Silicon Carbide DMOSFETS: A Digital Twin Reference Flow
DESCRIPTION:This webinar presents a comprehensive methodology for the design and optimization of a 1200V Silicon Carbide (SiC) Double-Diffused Metal-Oxide-Semiconductor Field-Effect Transistor (DMOS FET) utilizing Silvaco’s TCAD platform. Adhering to industry best practices\, the construction of an accurate digital twin is also presented\, ensuring conformity to real-world performance characteristics. Moreover\, we outline strategies to streamline simulation workflows\, emphasizing techniques to boost design efficiency and productivity. \nIn parallel\, this webinar explores the transformative impact of Machine Learning (ML) on traditional device design practices. By harnessing ML algorithms\, a fundamental shift occurs in the approach towards device design\, enabling process and device engineers to extract insights from vast datasets\, optimize performance\, and expedite the design iteration process. \nAdditionally\, the necessity of incorporating compact modeling into the design flow is underscored. Compact modeling serves as a crucial component in capturing device behavior accurately\, enabling efficient circuit-level simulations and facilitating rapid prototyping of devices. The integration of compact modeling enhances the design process\, facilitating a more holistic understanding of device behavior and performance characteristics. \nThrough the integration of TCAD\, simulation optimization\, ML techniques\, and compact modeling\, this webinar demonstrates a synergistic approach towards device design\, fostering innovation\, precision\, and efficiency. \nThis Virtual Webinar is from 10:00-11:00am PT. \n  \nShare this:\n				Share on LinkedIn (Opens in new window)\n				LinkedIn\n			\n				Share on X (Opens in new window)\n				X\n			\n				Share on Facebook (Opens in new window)\n				Facebook\n			Like this:Like Loading…
URL:https://marketingeda.com/event/developing-silicon-carbide-dmosfets-a-digital-twin-reference-flow/
CATEGORIES:EDA,Webinar
ATTACH;FMTTYPE=image/jpeg:https://marketingeda.com/wp-content/uploads/Silvaco-June-25-2024.jpg
END:VEVENT
BEGIN:VEVENT
DTSTART;TZID=America/Los_Angeles:20240619T080000
DTEND;TZID=America/Los_Angeles:20240619T090000
DTSTAMP:20240605T162435Z
CREATED:20240605T162435Z
LAST-MODIFIED:20240605T162435Z
UID:8076-1718784000-1718787600@marketingeda.com
SUMMARY:Design\, Manage\, and Share Data with OrCAD X Cloud Workspaces
DESCRIPTION:The OrCAD X platform allows you to manage and collaborate throughout the PCB design process. The cloud workspaces are available out-of-the-box without any additional setup of internal/external server dependencies. If you are a Librarian\, Electrical Engineer\, or a member of the PCB design team\, \nJoin us for this webinar to learn more about library and design data management within the OrCAD X platform. \n\nIn this webinar\, you will learn about: \n PCB design flow collaboration \n\nCreating a team library and sharing It with your team over cloud\nCreating a team workspace\nAccess control within the team workspace\nCollaborating on a PCB design across teams with\n\nElectrical engineers\nAnalysis engineers\nPCB designers\n\n\nDesign data management\n\nView/restore the version history of components and CAD data\nView/Restore the version history of PCB projects\n\n\n\n\nSPEAKERS: \nNitin Thapliyal\, Principal Product Engineer\, Cadence \nHOST: \nSupreeth Mannava\, Senior Principal Product Manager\, Cadence \nShare this:\n				Share on LinkedIn (Opens in new window)\n				LinkedIn\n			\n				Share on X (Opens in new window)\n				X\n			\n				Share on Facebook (Opens in new window)\n				Facebook\n			Like this:Like Loading…
URL:https://marketingeda.com/event/design-manage-and-share-data-with-orcad-x-cloud-workspaces/
CATEGORIES:EDA,Webinar
ATTACH;FMTTYPE=image/jpeg:https://marketingeda.com/wp-content/uploads/Cadence-June-19-2024.jpg
END:VEVENT
BEGIN:VEVENT
DTSTART;TZID=America/Los_Angeles:20240606T100000
DTEND;TZID=America/Los_Angeles:20240606T110000
DTSTAMP:20240524T015255Z
CREATED:20240524T015255Z
LAST-MODIFIED:20240524T015255Z
UID:8034-1717668000-1717671600@marketingeda.com
SUMMARY:Addressing Thermal Stress and Warpage Challenges in 3D-IC Designs
DESCRIPTION:Thermal stress analysis plays a crucial role in the design and performance optimization of packaging materials and boards\, especially in industries where temperature variations are significant. This webinar presents a comprehensive overview of recent developments in the newly-introduced Cadence Celsius Studio AI-enabled multiphysics thermal platform to solve today’s thermal stress and warpage analysis in 3D-ICs. \nCelsius Studio offers support for linear and nonlinear material structural models as well as static and quasi-static solvers for warpage and stress analysis and a moisture solver and high-temperature\, high-humidity (HTHH) analysis. Designers can perform multi-stage simulations for the design assembly process and material failure and reliability analysis. There are global and local models for 3D-IC warpage/stress simulation. \nYou will learn about: \n\nRecent developments in Celsius Studio that address thermal stress and warpage analysis in 3D-ICs\, including die-to-die sacking\, packing\, and boards warpage\nKey methods that can be used to address factors affecting thermal stress\, including nonlinear material properties\, geometric configuration\, and environmental conditions\nExample models for 3D-IC warpage/stress simulation\n\nShare this:\n				Share on LinkedIn (Opens in new window)\n				LinkedIn\n			\n				Share on X (Opens in new window)\n				X\n			\n				Share on Facebook (Opens in new window)\n				Facebook\n			Like this:Like Loading…
URL:https://marketingeda.com/event/addressing-thermal-stress-and-warpage-challenges-in-3d-ic-designs/
CATEGORIES:EDA,Webinar
ATTACH;FMTTYPE=image/jpeg:https://marketingeda.com/wp-content/uploads/Cadence-June-6-2024.jpg
END:VEVENT
BEGIN:VEVENT
DTSTART;TZID=America/Los_Angeles:20240604T100000
DTEND;TZID=America/Los_Angeles:20240604T110000
DTSTAMP:20240524T203508Z
CREATED:20240524T203431Z
LAST-MODIFIED:20240524T203508Z
UID:8046-1717495200-1717498800@marketingeda.com
SUMMARY:Silicon.da: The First Integrated SLM Analytics Solution from Design Through Manufacturing
DESCRIPTION:Today’s advanced node chip designs are faced with many new complexities which require more verification\, more validation and more analysis. The resulting data from these added steps has also grown exponentially and engineers need a way to efficiently analyze this information. The result is a new paradigm shift which has led to data overload requiring tools to collect huge amounts of data from design\, test and manufacturing (petabytes)\, analyze the data\, and provide actionable insights on that data. \nPart of the Synopsys.da AI analytics tools\,  Synopsys’ Silicon.da is the first integrated SLM analytics solution that addresses post-silicon challenges by increasing engineering productivity\, improving silicon efficiency and providing the tool scalability needed for today’s advanced SoC’s. Silicon.da serves a critical role as part of an overall SLM solution dedicated to improving the health and operational metrics of a silicon device across its complete lifecycle. \nIn this presentation\, Mr. Anti Tseng\, Senior Manager at MediaTek\, will explain how Silicon.da’s volume diagnostics feature identified systematic issues more efficiently than traditional methods by providing very accurate failure locations within the silicon resulting in improved yield by a single digit percentage and in a shorter amount of time – from weeks to days. Mr. Tseng will also further discuss how utilizing this volume diagnosis analysis technology improves the foundry process for advanced nodes resulting in millions of dollars of cost savings through high volume chip production for fabless companies. \n\n\n\n\n\n\n\n\n\n\nSpeakers\n\n\nListed below are the industry leaders scheduled to speak. \n\n\n\n\n\n\n\n\n\n\n\n\n\n\n\nAnti Tseng\n\n\nSenior Manager\nMediaTek \n\n\n\n\n\n\n\n\n\n\n\nAnti Tseng has been with MediaTek for 16 years and mainly covered three categories: CPU implementation/DFT/MBIST\, silicon speed binning & manufacture process debug\, in-house data platform & CAD flow development. His current focus is to enable smooth mass production of first advanced process node in MediaTek by exploring next-generation DFT architecture\, ATPG & diagnosis flow\, and AI-based data analysis. \n\n\n\n\n\n\n\n\n\n\n\n\n\n\n\n\n\n\n\n\nGuy Cortez\n\n\nProduct Management\, Principal\nSynopsys \n\n\n\n\n\n\n\n\n\n\n\nGuy Cortez is principal\, product management at Synopsys. His marketing career spans over 25 years where he has held various marketing positions including technical\, product/solution\, channel/field\, integrated/corporate\, alliance and business development for companies such as Synopsys\, Cadence\, VMware and Optimal+. Prior to that he spent 12 years as a test engineer at Hughes Aircraft Company (now Boeing)\, and later at Sunrise Test Systems (which became Viewlogic and later Synopsys). At Hughes\, he was responsible for generating all of the manufacturing test programs for the ASICs developed in the Missile Systems Group division. At Sunrise\, Cortez was a pre- and post-sales applications engineer\, and also doubled as the company’s instructor. \n\n\n\n\n\n\n\n\n\n\nShare this:\n				Share on LinkedIn (Opens in new window)\n				LinkedIn\n			\n				Share on X (Opens in new window)\n				X\n			\n				Share on Facebook (Opens in new window)\n				Facebook\n			Like this:Like Loading…
URL:https://marketingeda.com/event/silicon-da-the-first-integrated-slm-analytics-solution-from-design-through-manufacturing/
CATEGORIES:EDA,Webinar
ATTACH;FMTTYPE=image/jpeg:https://marketingeda.com/wp-content/uploads/Synopsys-June-4-2024.jpg
END:VEVENT
BEGIN:VEVENT
DTSTART;TZID=America/Los_Angeles:20240530T100000
DTEND;TZID=America/Los_Angeles:20240530T110000
DTSTAMP:20240521T001952Z
CREATED:20240521T001952Z
LAST-MODIFIED:20240521T001952Z
UID:8004-1717063200-1717066800@marketingeda.com
SUMMARY:Addressing Real-Time Workloads in Automotive Applications with Efficient ARC-V Processors
DESCRIPTION:Many automotive applications require processing workloads with minimum latency and precise timing budgets.  This is especially true for safety-critical applications like adaptive cruise control and anti-lock braking\, where human life may be jeopardized.  These systems require processing elements that can respond to events within specific (predictable) time constraints. System reliability and availability depend on the effectiveness of this real-time processing. \nIn this webinar\, we will outline examples of safety-critical applications and why real-time processing is required to maintain the highest levels of safety and reliability.  We will also discuss Synopsys’ ARC-V™ RHX processor series and how these power/performance efficient processors address the real-time requirements of these applications. \n\n\n\n\n\n\n\n\n\n\nSpeaker\n\n\n\n\n\n\n\n\n\n\n\n\n\n\n\n\nRich Collins\n\n\nSr. Product Management Director\nSynopsys \n\n\n\n\n\n\n\n\n\n\n\nRich Collins is senior product managemet director for the ARC-V  RISC-V based processor portfolio at Synopsys and has over 30 years of experience in embedded semiconductor R&D\, product marketing and business development. Rich holds an MBA from Duke University’s Fuqua School of Business and a BSE in Electrical Engineering from Duke University. \n\n\n\n\n\n\n\n\n\n\nShare this:\n				Share on LinkedIn (Opens in new window)\n				LinkedIn\n			\n				Share on X (Opens in new window)\n				X\n			\n				Share on Facebook (Opens in new window)\n				Facebook\n			Like this:Like Loading…
URL:https://marketingeda.com/event/addressing-real-time-workloads-in-automotive-applications-with-efficient-arc-v-processors/
CATEGORIES:IP,Webinar
ATTACH;FMTTYPE=image/jpeg:https://marketingeda.com/wp-content/uploads/Synopsys-May-30-2024.jpg
END:VEVENT
BEGIN:VEVENT
DTSTART;TZID=America/Los_Angeles:20240530T080000
DTEND;TZID=America/Los_Angeles:20240530T090000
DTSTAMP:20240521T162703Z
CREATED:20240521T162703Z
LAST-MODIFIED:20240521T162703Z
UID:8011-1717056000-1717059600@marketingeda.com
SUMMARY:Optimizing connectivity between Xpedition and HFSS for RF systems design
DESCRIPTION:In today’s fast-paced technological landscape\, seamless integration between design and simulation tools is crucial for accelerating product development cycles and ensuring optimal performance of electronics\, especially RF systems. Siemens Xpedition and Ansys HFSS stand as pillars in their respective domains\, offering powerful capabilities for electronic design and electromagnetic simulation. \nIn this live conversation\, Sara Louie from Ansys and Per Viklund from Siemens will describe the two-way connectivity between Siemens Xpedition and Ansys HFSS\, revolutionizing the electronic design and simulation workflow. We delve into the details of bidirectional data exchange\, enabling engineers to seamlessly transfer layout geometries and parameters between the two platforms. \nShare this:\n				Share on LinkedIn (Opens in new window)\n				LinkedIn\n			\n				Share on X (Opens in new window)\n				X\n			\n				Share on Facebook (Opens in new window)\n				Facebook\n			Like this:Like Loading…
URL:https://marketingeda.com/event/optimizing-connectivity-between-xpedition-and-hfss-for-rf-systems-design/
CATEGORIES:EDA,Webinar
ATTACH;FMTTYPE=image/jpeg:https://marketingeda.com/wp-content/uploads/Xpedition-HFSS-May-30-2024.jpg
END:VEVENT
BEGIN:VEVENT
DTSTART;TZID=America/Los_Angeles:20240529T100000
DTEND;TZID=America/Los_Angeles:20240529T110000
DTSTAMP:20240521T001409Z
CREATED:20240521T001409Z
LAST-MODIFIED:20240521T001409Z
UID:8001-1716976800-1716980400@marketingeda.com
SUMMARY:Reimagining Synopsys SLM PVT Monitoring IP for Advanced Node GAA Process
DESCRIPTION:Synopsys’ SLM PVT Monitor (process detector\, voltage monitor\, temperature sensor) IP can collect voltage\, temperature\, and process parameters from different blocks within the IC in real time. These data can be analyzed and used to take meaningful action to optimize the performance of the chip at any stage of silicon lifecycle. This webinar focuses on how the monitors need to move from analog to digital sensing paradigm due to the design constraints introduced by GAA nodes. \nIn this webinar\, you will learn: \n\nSilicon Lifecycle Management (SLM) overview and the crucial role of PVT IP\nOverview of each component in the PVT IP portfolio – rearchitecting from analog to digital sensing\nPVT IP use cases in data centers\, 5G\, consumer electronics\, and automotive applications\n\n\n\n\n\n\n\n\n\n\n\nSpeaker\n\n\nListed below is the industry leader scheduled to speak. \n\n\n\n\n\n\n\n\n\n\n\n\n\n\n\n\n\n\n\n\n\n\n\n\n\n\nRohan Bhatnagar\n\n\nProduct Manager\, Senior Staff\nSynopsys\, Inc. \n\n\n\n\n\n\n\n\n\n\n\nRohan Bhatnagar is a Product Manager\, Senior Staff at Synopsys in the Silicon Lifecycle Management business group and manages the PVT Monitor IP products. He is responsible for total product management including market research and strategy for new product roadmap definition\, go-to-market planning\, product collateral generation for customer engagements and sales trainings. He has more than a decade and a half of experience in the Electronic Design Automation (EDA) industry focusing on the analog and mixed-signal design space. Rohan holds a Master’s degree in Electrical Engineering from The University of Texas. \n\n\n\n\n\n\n\n\n\n\nShare this:\n				Share on LinkedIn (Opens in new window)\n				LinkedIn\n			\n				Share on X (Opens in new window)\n				X\n			\n				Share on Facebook (Opens in new window)\n				Facebook\n			Like this:Like Loading…
URL:https://marketingeda.com/event/reimagining-synopsys-slm-pvt-monitoring-ip-for-advanced-node-gaa-process/
CATEGORIES:IP,Webinar
ATTACH;FMTTYPE=image/jpeg:https://marketingeda.com/wp-content/uploads/Synopsys-May-29-2024.jpg
END:VEVENT
BEGIN:VEVENT
DTSTART;TZID=America/New_York:20240523T080000
DTEND;TZID=America/New_York:20240523T170000
DTSTAMP:20240506T171106Z
CREATED:20240506T171106Z
LAST-MODIFIED:20240506T171106Z
UID:7946-1716451200-1716483600@marketingeda.com
SUMMARY:5 New Ways to Maximize Your Hardware Security Resilience
DESCRIPTION:Be sure to register for this high tech security webinar. You’ll learn how to identify threat scenarios quickly and why a model-based\, system-oriented solution is needed to protect your hardware. \n\n\n\n\nOverview\nConnected vehicles offer a range of benefits\, such as real-time data sharing\, app-to-car connectivity\, advanced driver assistance systems (ADAS)\, and critical safety features like location tracking\, remote parking\, and in-vehicle infotainment systems (IVIs). These advancements aim to enhance the overall driving and riding experience. However\, it is crucial to acknowledge that equipping vehicles with smart features also exposes them to potential cyberattacks. These attacks can result in customer data leakage or even compromise critical safety functionalities. \nIt’s expected to discover vulnerabilities after the product is released\, which could have been easily prevented. For instance\, as reported by Bloomberg\, a recent increase in car thefts was attributed to the absence of anti-theft computer chips in vehicle critical systems. Therefore\, it is imperative to proactively consider and address potential attack vectors right from the initial stages of development. \nThis cybersecurity vulnerability applies to many other industrial applications\, such as industrial IoT\, SmartCity\, and digital healthcare\, where every device or system is connected\, and every connection is a vulnerability. \nDesign for security is becoming mainstream and should be part of today’s standard design methodologies. \nWhat you will learn\n\nWhy a model-based and system-oriented solution is needed for automotive cybersecurity\nHow to quickly identify threat scenarios\nWhy a pre-silicon security verification flow is essential for secure ICs\nUsing AI to mitigate side-channel vulnerabilities\n\nWho should attend this presentation\nThis webinar is valuable to anyone who works with product design\, connectivity and security. \nSpeakers\nChief Technologist Christophe Bianchi \n\n\nShare this:\n				Share on LinkedIn (Opens in new window)\n				LinkedIn\n			\n				Share on X (Opens in new window)\n				X\n			\n				Share on Facebook (Opens in new window)\n				Facebook\n			Like this:Like Loading…
URL:https://marketingeda.com/event/5-new-ways-to-maximize-your-hardware-security-resilience/
CATEGORIES:EDA,Webinar
ATTACH;FMTTYPE=image/jpeg:https://marketingeda.com/wp-content/uploads/Ansys-May-23-2024.jpg
END:VEVENT
BEGIN:VEVENT
DTSTART;TZID=America/Los_Angeles:20240522T210000
DTEND;TZID=America/Los_Angeles:20240522T220000
DTSTAMP:20240521T182515Z
CREATED:20240521T182515Z
LAST-MODIFIED:20240521T182515Z
UID:8015-1716411600-1716415200@marketingeda.com
SUMMARY:RapidGPT: Meet Your New AI-Powered Design Assistant
DESCRIPTION:Join us for our upcoming webinar introducing RapidGPT\, a revolutionary tool developed by PrimisAI that is reshaping the field of AI-driven EDA. RapidGPT is changing the game in hardware engineering with its groundbreaking generative AI approach. Offering a natural language interface\, RapidGPT empowers designers to boost productivity and shorten time-to-market. During this session\, explore how RapidGPT simplifies the design journey for hardware engineers\, from initial concept to RTL\, transcending conventional automation and revolutionizing the hardware engineering process. \nShare this:\n				Share on LinkedIn (Opens in new window)\n				LinkedIn\n			\n				Share on X (Opens in new window)\n				X\n			\n				Share on Facebook (Opens in new window)\n				Facebook\n			Like this:Like Loading…
URL:https://marketingeda.com/event/rapidgpt-meet-your-new-ai-powered-design-assistant/
CATEGORIES:EDA,Webinar
ATTACH;FMTTYPE=image/jpeg:https://marketingeda.com/wp-content/uploads/PrimisAI-May-22-2024.jpg
END:VEVENT
BEGIN:VEVENT
DTSTART;TZID=America/Los_Angeles:20240522T100000
DTEND;TZID=America/Los_Angeles:20240522T110000
DTSTAMP:20240510T222103Z
CREATED:20240510T222103Z
LAST-MODIFIED:20240510T222103Z
UID:7985-1716372000-1716375600@marketingeda.com
SUMMARY:Debugging Features of UVM
DESCRIPTION:A UVM testbench is a large and complex piece of software. Like any other large and complex piece of software\, a verification environment written using UVM will require debugging at some stage. There are various debugging features built into UVM to help with this. \nIn this one-hour webinar\, Doulos Senior Member Technical Staff Doug Smith explores the various features in UVM to help you debug your UVM environment\, test cases\, and design under test. \nTopics include: \n\nDebugging the Testbench\nDebugging Stimulus\nDebugging the Design\n\nAt the end of the webinar\, we will also look at an example of the tool support features for debugging UVM using the Cadence Xcelium Logic Simulator. \nShare this:\n				Share on LinkedIn (Opens in new window)\n				LinkedIn\n			\n				Share on X (Opens in new window)\n				X\n			\n				Share on Facebook (Opens in new window)\n				Facebook\n			Like this:Like Loading…
URL:https://marketingeda.com/event/debugging-features-of-uvm-2/
CATEGORIES:EDA,Webinar
ATTACH;FMTTYPE=image/jpeg:https://marketingeda.com/wp-content/uploads/Cadence-May-22-2024-1.jpg
END:VEVENT
BEGIN:VEVENT
DTSTART;TZID=America/Los_Angeles:20240522T080000
DTEND;TZID=America/Los_Angeles:20240522T090000
DTSTAMP:20240508T181719Z
CREATED:20240508T181719Z
LAST-MODIFIED:20240508T181719Z
UID:7969-1716364800-1716368400@marketingeda.com
SUMMARY:Addressing the Challenges of PCB Design for Manufacturing
DESCRIPTION:Manufacturing issues can be a big reason why your project timelines get derailed and even result in costly failures. By understanding common errors that occur while designing or creating your fabrication and assembly documentation\, you can avoid making the same mistakes on future designs. With access to over 80 comprehensive Design for Test (DFT)\, Design for Assembly (DFA)\, and Design for Fabrication (DFF) checks\, automated documentation that is always synced to your layout data\, and single output manufacturing\, OrCAD X helps ensure that your designs are robust and functional from the start. \nWhether you’re a seasoned professional or new to PCB manufacturing\, this webinar will go into the power of OrCAD X and how it will streamline your manufacturing output process\, helping you eliminate late-stage PCB manufacturing problems. \n\nJoin us to learn about: \n\nCommon DFx issues seen by manufacturers/fabricators\nDFx design guidelines to follow\nIn-design DFM checking with DesignTrue DFM technology\nAutomating manufacturing documentation with Live DOC\nGenerating manufacturing outputs\n\n\nSPEAKERS: \nJohn Carney\, Product Engineering Architect\, Cadence \nKent Balius\, Director of Pre-Production Engineering. Summit Interconnect \nHOST: \nSupreeth Mannava\, Senior Principal Product Manager\, Cadence \nShare this:\n				Share on LinkedIn (Opens in new window)\n				LinkedIn\n			\n				Share on X (Opens in new window)\n				X\n			\n				Share on Facebook (Opens in new window)\n				Facebook\n			Like this:Like Loading…
URL:https://marketingeda.com/event/addressing-the-challenges-of-pcb-design-for-manufacturing/
CATEGORIES:EDA,Webinar
ATTACH;FMTTYPE=image/jpeg:https://marketingeda.com/wp-content/uploads/Cadence-May-22-2024.jpg
END:VEVENT
BEGIN:VEVENT
DTSTART;TZID=America/Los_Angeles:20240522T080000
DTEND;TZID=America/Los_Angeles:20240522T090000
DTSTAMP:20240502T173621Z
CREATED:20240502T173621Z
LAST-MODIFIED:20240502T173621Z
UID:7937-1716364800-1716368400@marketingeda.com
SUMMARY:Questa RDC Assist – Improving designer productivity and enabling faster RDC verification closure with machine learning
DESCRIPTION:In 2021 Siemens EDA released CDC Assist. CDC Assist is an ML powered feature that empowers users to configure\, debug\, and close CDC on designs more rapidly. Following the success of CDC Assist\, Siemens introduced RDC Assist in 2023.\n‌\nUsing the same ML technology in CDC Assist\, RDC Assist dramatically improves the time and effort required to configure\, debug\, and close reset domain crossing analysis.\n‌\nSince RDC violations often have a common cause\, RDC Assist helps users to identify the root cause for the RDC violations and errors through data mining and machine learning techniques.\n‌\nWe will discuss use models and best practices to utilize RDC Assist\, and walk through a demo showing its power.\nWhat you will learn: \n\n‌How RDC Assist helps users expedite their RDC Analysis\nHow to run RDC Assist\nHow to analyze RDC Assist results in the UI\nHow to use RDC Assist to focus on major hotspots first\nTechniques presented are applicable to both CDC and RDC analysis\n‌\n\nWho should attend: \nRTL designers\, anyone that runs CDC or RDC\, design team leads \nSpeaker:\n\n\n\n\n\n\nFarhad Ahmed\nPrincipal Product Engineer\, Siemens EDA\n\n\n\n\nFarhad Ahmed currently is a Principal Product Engineer at Siemens EDA Software.​ \nHe has been working in Chip Design and EDA companies for last 30+ years. He graduated with a B.Sc.(EE) degree from Bangladesh University of Engg. & Technology and a M.Sc.(EE) from Washington State University.​ \nHe started his career as an RTL Logic Designer for Sun Microsystems working on SPARC microprocessors.​ \nFarhad loves to read books on history\, an avid swimmer\, Squash player\, does hiking regularly and also loves kayaking.​ \n\n\n\nShare this:\n				Share on LinkedIn (Opens in new window)\n				LinkedIn\n			\n				Share on X (Opens in new window)\n				X\n			\n				Share on Facebook (Opens in new window)\n				Facebook\n			Like this:Like Loading…
URL:https://marketingeda.com/event/questa-rdc-assist-improving-designer-productivity-and-enabling-faster-rdc-verification-closure-with-machine-learning/
CATEGORIES:EDA,Webinar
ATTACH;FMTTYPE=image/jpeg:https://marketingeda.com/wp-content/uploads/Siemens-May-22-2024.jpg
END:VEVENT
BEGIN:VEVENT
DTSTART;TZID=America/Los_Angeles:20240522T070000
DTEND;TZID=America/Los_Angeles:20240522T090000
DTSTAMP:20240424T164124Z
CREATED:20240424T164124Z
LAST-MODIFIED:20240424T164124Z
UID:7910-1716361200-1716368400@marketingeda.com
SUMMARY:Accelerating AI Applications Using Custom RISC-V based SIMD/VLIW DSPs
DESCRIPTION:The revolution in AI triggers an increased awareness for application-specific instruction-set processors (ASIPs). These processors implement a specialized instruction-set architecture (ISA) tailored to the AI application domain\, often starting from a baseline such as the RISC-V ISA.  ASIPs can replace traditional fixed-function hardware accelerators\, thereby introducing software-programmability in the AI acceleration domain\, and thus more flexibility and agility in both the design process and the eventual product.  By maintaining a RISC-V ISA baseline\, compatibility with and reuse of existing processor ecosystem elements is facilitated. \nSynopsys ASIP Designer is the industry-leading tool to design\, implement\, program and verify application-specific instruction-set processors. Starting from a single processor specification\, designers immediately obtain an optimizing C/C++ compiler\, cycle-accurate simulator and synthesizable hardware implementation of the ASIP.  Using a unique compiler-in-the-loop™ and synthesis-in-the-loop™ methodology\, the ISA and microarchitecture can be tuned quickly to the application domain. \nThis seminar introduces you to the ASIP Designer tool-suite. It features a tutorial and two case studies from AI application domains. The tutorial introduces the typical architectural features needed to accelerate AI algorithms\, such as specialization\, SIMD\, and VLIW\, and how ASIP Designer supports them. The first case study demonstrates a SIMD/VLIW architecture with a RISC-V baseline processor for accelerating activation functions. The second case study shows a RISC-V based ASIP for medium-throughput convolutional neural networks (CNN) with programming support for TensorFlowLite for Microcontrollers (TFLM). \n\n\n\nWho Should Attend? \nIf you are a design engineer\, algorithm developer\, software engineer\, system architect\, or design manager focusing on advanced SoCs requiring application-specific optimizations\, you won’t want to miss this event. \n\n\n\n\nShare this:\n				Share on LinkedIn (Opens in new window)\n				LinkedIn\n			\n				Share on X (Opens in new window)\n				X\n			\n				Share on Facebook (Opens in new window)\n				Facebook\n			Like this:Like Loading…
URL:https://marketingeda.com/event/accelerating-ai-applications-using-custom-risc-v-based-simd-vliw-dsps/
CATEGORIES:EDA,IP,Webinar
ATTACH;FMTTYPE=image/jpeg:https://marketingeda.com/wp-content/uploads/Synopsys-May-22-2024.jpg
END:VEVENT
BEGIN:VEVENT
DTSTART;TZID=America/Los_Angeles:20240521T100000
DTEND;TZID=America/Los_Angeles:20240521T110000
DTSTAMP:20240503T190402Z
CREATED:20240503T190402Z
LAST-MODIFIED:20240503T190402Z
UID:7943-1716285600-1716289200@marketingeda.com
SUMMARY:The Next Generation of 3DIC Interposer/InFO Design
DESCRIPTION:In recent years\, the semiconductor industry has experienced a breakthrough in the onset of 2.5D and 3D chiplet-based products. These products promise to extend the limits of Moore’s Law while demolishing limitations on speed and capacity for our highest tiers of compute. But for all the adulation we heap upon the 3DIC paradigm\, we seemingly pay very little attention to the humble interposer die that enables communication between these groundbreaking chiplets. \n  \nWhat Attendees Will Learn: \nSynopsys tools can now improve the construction and signoff process for all styles of interposers. AMD has tested these tools and will present a comprehensive update on what we see as a step forward in interposer design. This flow is driven primarily within the Synopsys 3DIC Compiler platform\, though other noteworthy tools and engines are employed at key stages to ensure a high standard of quality. The Synopsys webinar begins with a brief overview of the current interposer design flow\, including pros and cons to the current approach and opportunities for new development. We’ll then cover an end-to-end design flow that addresses these opportunities across the span of floorplanning\, construction\, extraction\, and signoff. Finally\, we’ll wrap up with conclusions and future work. \n\n\n\n\n\n\n\n\n\n\nSpeakers\n\n\nListed below are the industry leaders scheduled to speak. \n\n\n\n\n\n\n\n\n\n\n\n\n\n\n\n\n\n\n\n\n\n\n\n\n\n\nKenneth Larsen\n\n\nProduct Management\, Sr Director\nSynopsys \n\n\n\n\n\n\n\n\nKenneth Larsen is a director of product management in the EDA Group at Synopsys\, focusing on 3D Heterogeneous Integration and Advanced Packaging. He has 30 years of experience in IC design verification and validation. Before joining Synopsys\, Kenneth was worldwide senior technical director at Mentor. \n\n\n\n\n\n\n\n\n\n\n\n\n\n\n\n\n\n\n\n\n\n\n\n\n\n\n\n\n\n\n\nNitin Navale\n\n\nPrincipal Member of Technical Staff\nAMD \n\n\n\n\n\n\n\n\nNitin Navale has worked across AMD & Xilinx since 2008 and currently serves as Principal Member of Technical Staff in the CAD/Methodology team. His current role is Technical Lead for 3DIC Methodology\, though he has previously also worked on design automation that ranges across STA\, EM/IR\, Thermal\, ESD\, SOC Floorplanning & Construction\, IP Management\, Netlisting\, and Characterization. Nitin earned his BS and MS in Electrical Engineering from the University of Illinois\, Urbana-Champaign. Outside of work\, he is consumed by his devotion to board games and strategy. He’s also an avid musician who plays multiple instruments with an active interest in music theory. \n\n\n\n\n\n\n\n\n\n\n\n\n\n\n\n\n\n\n\n\n\n\n\n\n\n\n\n\n\n\nAkshata Sonnad\n\n\nMember of Technical Staff\nAMD \n\n\n\n\n\n\n\n\nAkshata Sonnad is a Member of Technical Staff at AMD\, working on developing methodologies and flows for floor planning\, signoff\, and interposer/ InFO routing for next-generation multi-die systems. She graduated from University of Southern California with a Master’s degree in Electrical Engineering and worked as a CAD engineer on the physical design and verification of block level IPs and SOCs\, before making a transition to 3DIC Design Methodology. \n\n\n\n\n\n\n\n\n\n\n\n\n\n\n\n\n\n\nShare this:\n				Share on LinkedIn (Opens in new window)\n				LinkedIn\n			\n				Share on X (Opens in new window)\n				X\n			\n				Share on Facebook (Opens in new window)\n				Facebook\n			Like this:Like Loading…
URL:https://marketingeda.com/event/the-next-generation-of-3dic-interposer-info-design/
CATEGORIES:EDA,Webinar
ATTACH;FMTTYPE=image/jpeg:https://marketingeda.com/wp-content/uploads/Synopsys-May-21-2024.jpg
END:VEVENT
BEGIN:VEVENT
DTSTART;TZID=America/Los_Angeles:20240516T100000
DTEND;TZID=America/Los_Angeles:20240516T110000
DTSTAMP:20240221T175436Z
CREATED:20240221T175436Z
LAST-MODIFIED:20240221T175436Z
UID:7667-1715853600-1715857200@marketingeda.com
SUMMARY:AI-Driven EM-IR Design Closure
DESCRIPTION:IR drop closure is becoming a major challenge for designers on advanced nodes. The number of violations at signoff has increased significantly\, leading to longer turnaround time (TAT) or violations being waived. To solve this challenge\, IR drop needs to be addressed early in the implementation phase with an automated IR prevention and fixing methodology. \nIn this webinar\, we will present an AI-driven EM-IR closure solution integrated into the implementation flow. This solution uses AI methods to automatically root cause the IR drop violations and selects the most efficient PPA- and DRC-aware methods to fix the IR drop issues. The solution also uses AI models to enable fast incremental IR inferencing to validate the benefit of the design improvements. \nCome learn about this breakthrough solution that will significantly improve your IR drop closure TAT. \nShare this:\n				Share on LinkedIn (Opens in new window)\n				LinkedIn\n			\n				Share on X (Opens in new window)\n				X\n			\n				Share on Facebook (Opens in new window)\n				Facebook\n			Like this:Like Loading…
URL:https://marketingeda.com/event/ai-driven-em-ir-design-closure/
CATEGORIES:EDA,Webinar
ATTACH;FMTTYPE=image/jpeg:https://marketingeda.com/wp-content/uploads/Cadence-May-16-2024.jpg
END:VEVENT
BEGIN:VEVENT
DTSTART;TZID=America/Los_Angeles:20240515T130000
DTEND;TZID=America/Los_Angeles:20240515T140000
DTSTAMP:20240508T233014Z
CREATED:20240508T233014Z
LAST-MODIFIED:20240508T233014Z
UID:7977-1715778000-1715781600@marketingeda.com
SUMMARY:Innovative Technologies\, Tools\, and Methodologies for Space Applications
DESCRIPTION:In the world of space applications\, reliability is paramount. As the space sector continues to experience rapid growth and evolution\, new challenges are emerging to meet the demands of various mission types and requirements\, such as robust functional safety protections\, high reliability\, and dependable operation. Join us for an exclusive panel discussion hosted by Lattice Semiconductor\, where we delve into the dynamic landscape of the space industry and the indispensable role of the groundbreaking technology solutions enabling the growing demands of mission-critical requirements and application development. \nSpeakers \nJim T.\, Business Development\, Lattice Semiconductor\nKhalid Khan\, Directory of Applications Engineer\, Synopsys\nMelanie Berg\, Founder and CEO\, Space R3 \nShare this:\n				Share on LinkedIn (Opens in new window)\n				LinkedIn\n			\n				Share on X (Opens in new window)\n				X\n			\n				Share on Facebook (Opens in new window)\n				Facebook\n			Like this:Like Loading…
URL:https://marketingeda.com/event/innovative-technologies-tools-and-methodologies-for-space-applications/
CATEGORIES:EDA,IP,Webinar
ATTACH;FMTTYPE=image/jpeg:https://marketingeda.com/wp-content/uploads/Lattice-May-15-2024.jpg
END:VEVENT
BEGIN:VEVENT
DTSTART;TZID=Asia/Tokyo:20240509T150000
DTEND;TZID=Asia/Tokyo:20240509T160000
DTSTAMP:20240429T161300Z
CREATED:20240429T161300Z
LAST-MODIFIED:20240429T161300Z
UID:7922-1715266800-1715270400@marketingeda.com
SUMMARY:Innovative Approach to SoC Power Optimization
DESCRIPTION:Power is the biggest factor impacting semiconductors from custom silicon to CPU/GPU products. System-level Power modeling and simulation is needed to measure power accurately and efficiently. The scope of power studies has expanded to include the software\, thermal and generation to feed into the UVM/UPF methodology. At this Webinar we will highlight a new system-level power methodology that integrates micro-architecture power storage\, consumption\, management and thermal assessments. Case studies will be presented on Chiplet power\, mapping strategy of DNN on AI Engines and Tensor cores\, hardware-software partitioning\, and testing power management for mobile and low-power devices. \nShare this:\n				Share on LinkedIn (Opens in new window)\n				LinkedIn\n			\n				Share on X (Opens in new window)\n				X\n			\n				Share on Facebook (Opens in new window)\n				Facebook\n			Like this:Like Loading…
URL:https://marketingeda.com/event/innovative-approach-to-soc-power-optimization/
CATEGORIES:EDA,IP,Webinar
ATTACH;FMTTYPE=image/jpeg:https://marketingeda.com/wp-content/uploads/Mirabilis-May-9-2024.jpg
END:VEVENT
BEGIN:VEVENT
DTSTART;TZID=America/Los_Angeles:20240509T100000
DTEND;TZID=America/Los_Angeles:20240509T110000
DTSTAMP:20240429T161925Z
CREATED:20240429T161925Z
LAST-MODIFIED:20240429T161925Z
UID:7925-1715248800-1715252400@marketingeda.com
SUMMARY:Cracking the Power Code: Innovative Approach to SoC Power Optimization
DESCRIPTION:Power is the biggest factor impacting semiconductors from custom silicon to CPU/GPU products. System-level Power modeling and simulation is needed to measure power accurately and efficiently. The scope of power studies has expanded to include the software\, thermal and generation to feed into the UVM/UPF methodology. At this Webinar we will highlight a new system-level power methodology that integrates micro-architecture power storage\, consumption\, management and thermal assessments. Case studies will be presented on Chiplet power\, mapping strategy of DNN on AI Engines and Tensor cores\, hardware-software partitioning\, and testing power management for mobile and low-power devices. \nShare this:\n				Share on LinkedIn (Opens in new window)\n				LinkedIn\n			\n				Share on X (Opens in new window)\n				X\n			\n				Share on Facebook (Opens in new window)\n				Facebook\n			Like this:Like Loading…
URL:https://marketingeda.com/event/cracking-the-power-code-innovative-approach-to-soc-power-optimization/
CATEGORIES:EDA,Webinar
ATTACH;FMTTYPE=image/jpeg:https://marketingeda.com/wp-content/uploads/Mirabilis-May-9-2024-USA.jpg
END:VEVENT
BEGIN:VEVENT
DTSTART;TZID=America/Los_Angeles:20240509T100000
DTEND;TZID=America/Los_Angeles:20240509T110000
DTSTAMP:20240419T172547Z
CREATED:20240419T172547Z
LAST-MODIFIED:20240419T172547Z
UID:7883-1715248800-1715252400@marketingeda.com
SUMMARY:AI-Driven 3D System Analysis & Optimization for EM Antenna/RF Problems
DESCRIPTION:Antenna/RF design problems often involve the optimization of many variables\, requiring numerous evaluations (EM simulations) using traditional optimization methods. Design engineers need an intelligent\, accurate\, and easy-to-use simulation platform and analysis solution that reduces repetitive design cycles while increasing user productivity and efficiency. \nLeveraging an advanced AI-enabled methodology\, the Cadence Optimality Intelligent System Explorer delivers quality results leading to the optimal performance of electrical systems. Optimality Explorer utilizes a novel surrogate model-aware mechanism that significantly reduces the number of required EM simulations. In addition\, the seamless integration between different Cadence solver technologies (Clarity 3D Solver\, AWR Microwave Office\, and Optimality Explorer) enables full-cycle circuit-field co-simulation and optimization for RF/antenna design problems. \nWith the integration of Clarity 3D Solver and AWR Microwave Office\, RF/antenna designers will have ready access to high-capacity EM analysis for design verification and signoff of large\, complex RF mixed-signal systems beyond the capabilities offered by conventional solvers thanks to the Clarity distributed multiprocessing technology. \nThis webinar demonstrates the efficacy of the Optimality Explorer and Clarity 3D Solver engines for several complex high-dimensional antenna/RF problems. \nKey takeaways: \n\nOptimality Explorer leverages an advanced AI-enabled methodology to deliver quality results leading to the optimal performance of electrical systems\nThe seamless integration between Clarity 3D Solver\, AWR Microwave Office\, and Optimality Explorer enables full-cycle circuit-field co-simulation and optimization for RF/antenna design problems\nDemonstration of the efficacy of the Optimality Explorer and Clarity 3D Solver engines for several complex high-dimensional antenna/RF problems\n\nShare this:\n				Share on LinkedIn (Opens in new window)\n				LinkedIn\n			\n				Share on X (Opens in new window)\n				X\n			\n				Share on Facebook (Opens in new window)\n				Facebook\n			Like this:Like Loading…
URL:https://marketingeda.com/event/ai-driven-3d-system-analysis-optimization-for-em-antenna-rf-problems/
CATEGORIES:EDA,Webinar
ATTACH;FMTTYPE=image/jpeg:https://marketingeda.com/wp-content/uploads/Cadence-May-9-2024.jpg
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BEGIN:VEVENT
DTSTART;TZID=America/Los_Angeles:20240502T090000
DTEND;TZID=America/Los_Angeles:20240502T100000
DTSTAMP:20240422T161648Z
CREATED:20240422T161648Z
LAST-MODIFIED:20240422T161648Z
UID:7886-1714640400-1714644000@marketingeda.com
SUMMARY:Smart methods for DFT chip architecture & validation
DESCRIPTION:Combining market-leading design-for-test (DFT) technologies with best-in-class netlist synthesis allows you to achieve DFT success more quickly. Many customers\, including those for emulation and IC test\, have challenges with scaling architectures. This webinar describes how Siemens emulation and silicon test solutions can work together to provide a smart DFT plug-and-play architecture for Veloce ICs. \nThe Veloce hardware-assisted verification system can efficiently handle large\, full-chip GLE designs. Tessent Streaming Scan Network (SSN)\, a once-in-a-decade technology\, packetizes test data to dramatically reduce DFT implementation effort and reduce manufacturing test cost. The Veloce DFT application enables SSN\, as well as other test functions such as TestKompress\, BIST pattern validation\, functional fault grading\, power profiling and estimation\, by accelerating multiple orders of magnitude faster than traditional software simulation. Combining Veloce Strato and Tessent SSN can accelerate your time to DFT success. \nTarget audience: \n\nDFT Engineers\nDFT Managers\nProduct and Test Engineers and Managers\n\nWhat you will learn: \n\nIntroduction to Veloce DFT App and how it helps validate Tessent DFT logic/patterns\nDFT Power Profiling and Fault grading using Veloce Power App\nApplying SSN to solve the Veloce chip design challenges\n\n\n\nSpeakers:\n\n\n\n\n\n\nRobert Serphillips\nProduct Manager\, Verification\, Siemens EDA\n\n\n\n\nRobert Serphillips has worked in the pre-silicon verification\, post-silicon validation\, and production design-for-test (DFT) fields. He has designed and debugged ATE test patterns on multiple stand alone and SoC devices spanning close to 20 years in the semiconductor industry. The products include a mix of consumer\, automotive\, industrial\, military\, networking and mixed signal. Robert is currently a product manager with the Siemens EDA hardware-assisted verification business unit. \n\n\n\n\n\n\n\nRon Press\nSr. Director of Technology Enablement\, Tessent\, Siemens EDA – Tessent\n\n\n\n\nRon Press\, a 30-year veteran of the test and DFT industry\, is a member of the International Test Conference (ITC) Steering Committee\, a Golden Core member of the IEEE Computer Society and a Senior Member of IEEE. Ron has patents on reduced-pin-count testing\, glitch-free clock switching and on 3D DFT. He started his work in the test industry at Raytheon Company working on test and consulting throughout the company on test and built-in test. He co-developed the Testability Design Rating System (TDRS) for the US Air Force and received the Raytheon inventor’s award for a built-in test analysis system. Ron led the development of a state-of-the-art RF/digital tester at Harris RF starting in 1995. \n\n\n\nShare this:\n				Share on LinkedIn (Opens in new window)\n				LinkedIn\n			\n				Share on X (Opens in new window)\n				X\n			\n				Share on Facebook (Opens in new window)\n				Facebook\n			Like this:Like Loading…
URL:https://marketingeda.com/event/smart-methods-for-dft-chip-architecture-validation/
CATEGORIES:EDA,Webinar
ATTACH;FMTTYPE=image/jpeg:https://marketingeda.com/wp-content/uploads/Siemens-May-2-2024.jpg
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BEGIN:VEVENT
DTSTART;TZID=America/Los_Angeles:20240430T060000
DTEND;TZID=America/Los_Angeles:20240430T070000
DTSTAMP:20240416T003939Z
CREATED:20240416T003939Z
LAST-MODIFIED:20240416T003939Z
UID:7858-1714456800-1714460400@marketingeda.com
SUMMARY:DFT for chiplets & 3D ICs using Tessent Multi-die
DESCRIPTION:3D IC (2.5D/3D) designs are on the rise. Design for Test (DFT) for chiplets must be general purpose so they can be tested stand alone and easy to test after assembly into 2.5D or 3D devices. In this webinar you will learn how to use Tessent Multi-die and still adhere to standards like IEEE 1149.1\, IEEE 1500\, IEEE 1687\, and IEEE 1838. \nWho should attend:\n\nAnyone planning to implement chiplets\, 2.5D/3D designs and would like to learn about design for test.\nDFT Engineers\nDFT Managers\nDesign Engineers\nTest Engineers\nProject Managers for ASIC/design\n\nWhat you will learn:\n\nHow Tessent Multi-die will aid in 3D IC design for test\nIntro to what IEEE 1838 standard is and how Tessent solution can be used. Use of Tessent Streaming Scan Network (SSN) as flexible parallel port (FPP)\nHow in 2.5D device\, boundary scan-based interconnect test can be performed with Tessent Multi-die\n\n\n\nSpeaker:\n\n\n\n\n\n\nItamar Tsachi\nEurope DFT Manager\, Siemens EDA\n\n\n\n\nItamar Tsachi has more than 20 years of experience in the semiconductor industry and has collaborated with many local and international Siemens EDA customers on a wide range of solutions targeting DFT and RTL->GDSII flows. Before joining Mentor Graphics\, Itamar ramped up IBM’s Physical Design Group in Israel developing SoCs using IBM’s leading-edge technology. Itamar was also a Physical Implementation Consultant and Leader at multiple startups like Mysticom\, BrightCom technologies and Silicon Value\, where he began his chip design career in a variety of roles\, from Digital / Analog layout design to Place & Route and CAD development. Itamar holds one Patent” Placement Driving Routing (PDR) – “A method and apparatus for placement driven routing with a minimum number of changes in the placement.” \n\n\n\nShare this:\n				Share on LinkedIn (Opens in new window)\n				LinkedIn\n			\n				Share on X (Opens in new window)\n				X\n			\n				Share on Facebook (Opens in new window)\n				Facebook\n			Like this:Like Loading…
URL:https://marketingeda.com/event/dft-for-chiplets-3d-ics-using-tessent-multi-die/
CATEGORIES:EDA,Webinar
ATTACH;FMTTYPE=image/jpeg:https://marketingeda.com/wp-content/uploads/Siemens-April-30-2024.jpg
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BEGIN:VEVENT
DTSTART;TZID=America/New_York:20240425T110000
DTEND;TZID=America/New_York:20240425T120000
DTSTAMP:20240401T181039Z
CREATED:20240401T181039Z
LAST-MODIFIED:20240401T181039Z
UID:7800-1714042800-1714046400@marketingeda.com
SUMMARY:Improving Semiconductor Wafer Fabrication Process Efficiencies Using Ansys Solutions
DESCRIPTION:Ansys Semiconductor Manufacturing Webinar Series: Part 1 of 3. \nJoin us on Thursday\, April 25th for an in-depth view of multi-physics simulation in the semiconductor fabrication process. \nOverview\nAccurate design and optimization of the semiconductor fabrication process/equipment for yield improvements and faster time-to-market require multiphysics simulation\, which can address various physical interactions and phenomena. By encompassing factors from contamination challenges to ensuring uniform product outcomes\, engineers can leverage such simulations to generate innovative ideas for optimized processes and cutting-edge solutions in semiconductor fabrication. \nThis webinar will demonstrate the practical application of Ansys tools in understanding the impact of various parameters on diverse wafer fabrication processes and fine-tuning them to improve yields and reduce wafer cycle time. \nWhat you will learn\n\nImportance of simulation in fabrication processes\nReduce wafer cycle time\nModel fabrication process with Ansys tools\nOptimize of fabrication processes\nSystem-level modeling of fabrication processes\n\nWho should attend\nEngineers and Engineering Managers/Directors\, Manufacturing teams\, Etch teams\, Deposition teams\, NPI teams and Aftermarket teams \nSpeaker\n\nNima Bohlooli\, Senior Application Engineer\, Ansys\n\nShare this:\n				Share on LinkedIn (Opens in new window)\n				LinkedIn\n			\n				Share on X (Opens in new window)\n				X\n			\n				Share on Facebook (Opens in new window)\n				Facebook\n			Like this:Like Loading…
URL:https://marketingeda.com/event/improving-semiconductor-wafer-fabrication-process-efficiencies-using-ansys-solutions/
CATEGORIES:EDA,Semiconductor,Webinar
ATTACH;FMTTYPE=image/jpeg:https://marketingeda.com/wp-content/uploads/April-25-2024-Ansys.jpg
END:VEVENT
BEGIN:VEVENT
DTSTART;TZID=America/New_York:20240425T090000
DTEND;TZID=America/New_York:20240425T100000
DTSTAMP:20240401T180250Z
CREATED:20240401T180042Z
LAST-MODIFIED:20240401T180250Z
UID:7797-1714035600-1714039200@marketingeda.com
SUMMARY:The Era of Software-Defined Everything: Chiplets and Bespoke Silicon
DESCRIPTION:From fintech to automotive\, defense to healthcare\, everyone wants bespoke computing platforms to build “software-defined solutions” that are differentiated in their respective markets. Sign up and save your spot for this special presentation. \nOverview\nWith the advent of 3D ICs and heterogeneous semiconductor integration\, mapping a system on a customized chip/hardware is accessible to “everyone.” \nThe semiconductor suppliers are gearing themselves for the change\, and\, as Jensen Huang (NVIDIA CEO) was recently quoted\, “2024 is the year where every industry is becoming a high-tech industry.” \nFrom fintech to automotive\, defense to healthcare\, everyone wants bespoke computing platforms to build “software-defined solutions” that are differentiated in their respective markets. \nBut this (r)evolution faces a multitude of challenges\, such as \n\nIs the workforce (engineering community at large) ready for this massive deployment of semiconductor technologies?\nAre the design methodologies\, both semiconductor and system\, ready and enabling?\nWhat is the level of over-engineering that drives this sequence?\n\nWhat you will learn\n\nHow to harness 3D-IC and chiplets to accelerate the transition to software-defined everything\nHow chiplets can give your business a competitive edge\nWhat is the best use of AI for the transition?\n\nWho should attend and why\nIf you are responsible for an engineering department or in charge of NPI and Product Development /Strategy\, sign up for this online webinar. \nSpeaker\n\nChief Technologist Christopher Bianchi\n\nShare this:\n				Share on LinkedIn (Opens in new window)\n				LinkedIn\n			\n				Share on X (Opens in new window)\n				X\n			\n				Share on Facebook (Opens in new window)\n				Facebook\n			Like this:Like Loading…
URL:https://marketingeda.com/event/the-era-of-software-defined-everything-chiplets-and-bespoke-silicon/
CATEGORIES:EDA,IP,Webinar
ATTACH;FMTTYPE=image/jpeg:https://marketingeda.com/wp-content/uploads/Ansys-April-25-2024.jpg
END:VEVENT
BEGIN:VEVENT
DTSTART;TZID=America/Los_Angeles:20240424T080000
DTEND;TZID=America/Los_Angeles:20240424T090000
DTSTAMP:20240416T183848Z
CREATED:20240416T183848Z
LAST-MODIFIED:20240416T183848Z
UID:7863-1713945600-1713949200@marketingeda.com
SUMMARY:Deploying Solido Design Environment AI Workflows on AWS
DESCRIPTION:Utilizing AWS cloud resources to accelerate variation-aware verification   \n\nAI-powered Solido Design Environment provides SPICE-accurate variation-aware verification for 3\, 4\, 5\, 6 and higher sigma targets\, orders of magnitude faster than traditional brute-force methods. With cloud computing made more accessible than before\, many teams are considering running design and verification workloads\, including Solido Design Environment\, on the cloud. \nSiemens and AWS’ strategic collaboration enables a Siemens EDA portfolio that is even more accessible\, scalable\, flexible\, and secure on AWS. Today\, Solido Design Environment users can leverage the power of AWS cloud computing to manage and deploy SPICE-level verification\, resulting in accelerated verification schedules and significantly higher capacity for peak workload demands. \nIn this Masterclass webinar\, co-presented by Siemens EDA and AWS\, we explore best practices and resources available for deploying Solido Design Environment on AWS. Join us and learn more about AWS’ solutions for SPICE-level verification\, tried-and-tested cloud configurations for Solido Design Environment\, and a Q&A session with Siemens and AWS experts to get started confidently and leverage AWS compute to maximize verification throughput and address peak demand on Solido Design Environment. \nTopic Include:\n– The need for cloud scalability for  semiconductor design\n– Solido Design Environment overview\n– Best practices and considerations\n– AWS capabilities for SPICE verification\, including example cloud configuration\n– Resources available for teams deploying to AWS cloud\n– Interactive Q&A \nFeatured Products:  Solido Design Environment\, AWS Cloud Platform \nSpeakers:\n\n\n\n\nWei-Lii Tan\nDirector of Product Management\, Siemens EDA\n\n\nWei-Lii Tan is Director of Product Management in Siemens DISW’s Custom IC Verification division for Solido’s AI-enabled verification & characterization\, and IP validation product lines. Wei-Lii has 15 years of experience in semiconductor and EDA\, having worked on both digital and analog methodologies. He has a master’s degree in electrical engineering from Mississippi State University\, and an M.B.A. from Santa Clara University. \n\nAzim Siddique\nSenior Solutions Architect\, Amazon Web Services\n\n\nAzim works with AWS Enterprise customers on their Cloud adoption journey. Azim has 20+ years of experience working at large global organizations in the manufacturing and industrials domain\, architecting and delivering innovative solutions at scale to generate business value. Azim is passionate about being part of transformational changes driven by technological innovation. \n\n\n\n\n\nShare this:\n				Share on LinkedIn (Opens in new window)\n				LinkedIn\n			\n				Share on X (Opens in new window)\n				X\n			\n				Share on Facebook (Opens in new window)\n				Facebook\n			Like this:Like Loading…
URL:https://marketingeda.com/event/deploying-solido-design-environment-ai-workflows-on-aws/
CATEGORIES:EDA,Webinar
ATTACH;FMTTYPE=image/jpeg:https://marketingeda.com/wp-content/uploads/Siemens-April-24-2024.jpg
END:VEVENT
BEGIN:VEVENT
DTSTART;TZID=Europe/London:20240423T120000
DTEND;TZID=Europe/London:20240423T130000
DTSTAMP:20240410T161505Z
CREATED:20240410T161505Z
LAST-MODIFIED:20240410T161505Z
UID:7823-1713873600-1713877200@marketingeda.com
SUMMARY:DVClub Europe - Formal Verification
DESCRIPTION:13 days to go the next DVClub Europe meeting takes place on Tuesday 23rd April with a theme of “Formal Verification“.\n\nFormal Verification can help you find bugs earlier in the design cycle and accelerate root cause analysis. But success with Formal requires the effective selection and implementation of the right formal technologies and methods. In this DVClub meeting our speakers will share their experiences adopting Formal Verification and then open the floor for discussion followed by the usual networking opportunities.\n\nAgenda (BST) \n12:00   Welcome and Introduction – Mike Bartley\, Tessolve\n12:00 Brajmohan Sharma\, Marvel Technology – Advanced Formal Verification and Robust Regression Strategies for Highly Parameterized Designs\n12:20 Easwaran Krishnan & Savita Suresh Lohar\, Tessolve Semiconductor\n12:40 Gayatri Padhy\, Object Automation – Formal Verification with AI/ML\n13:00 Cadence Design System\n13:15 Neena Chandawale \,Agnisys\n13:30 Close \nRegister now to become a part of this event. Free to attend online. \nTicket Tailor- DVClub Europe \nShare this:\n				Share on LinkedIn (Opens in new window)\n				LinkedIn\n			\n				Share on X (Opens in new window)\n				X\n			\n				Share on Facebook (Opens in new window)\n				Facebook\n			Like this:Like Loading…
URL:https://marketingeda.com/event/dvclub-europe-formal-verification/
CATEGORIES:EDA,Webinar
ATTACH;FMTTYPE=image/jpeg:https://marketingeda.com/wp-content/uploads/DVClub-Europe-23-April-2024.jpg
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