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DTSTART;TZID=America/New_York:20240523T080000
DTEND;TZID=America/New_York:20240523T170000
DTSTAMP:20240506T171106Z
CREATED:20240506T171106Z
LAST-MODIFIED:20240506T171106Z
UID:7946-1716451200-1716483600@marketingeda.com
SUMMARY:5 New Ways to Maximize Your Hardware Security Resilience
DESCRIPTION:Be sure to register for this high tech security webinar. You’ll learn how to identify threat scenarios quickly and why a model-based\, system-oriented solution is needed to protect your hardware. \n\n\n\n\nOverview\nConnected vehicles offer a range of benefits\, such as real-time data sharing\, app-to-car connectivity\, advanced driver assistance systems (ADAS)\, and critical safety features like location tracking\, remote parking\, and in-vehicle infotainment systems (IVIs). These advancements aim to enhance the overall driving and riding experience. However\, it is crucial to acknowledge that equipping vehicles with smart features also exposes them to potential cyberattacks. These attacks can result in customer data leakage or even compromise critical safety functionalities. \nIt’s expected to discover vulnerabilities after the product is released\, which could have been easily prevented. For instance\, as reported by Bloomberg\, a recent increase in car thefts was attributed to the absence of anti-theft computer chips in vehicle critical systems. Therefore\, it is imperative to proactively consider and address potential attack vectors right from the initial stages of development. \nThis cybersecurity vulnerability applies to many other industrial applications\, such as industrial IoT\, SmartCity\, and digital healthcare\, where every device or system is connected\, and every connection is a vulnerability. \nDesign for security is becoming mainstream and should be part of today’s standard design methodologies. \nWhat you will learn\n\nWhy a model-based and system-oriented solution is needed for automotive cybersecurity\nHow to quickly identify threat scenarios\nWhy a pre-silicon security verification flow is essential for secure ICs\nUsing AI to mitigate side-channel vulnerabilities\n\nWho should attend this presentation\nThis webinar is valuable to anyone who works with product design\, connectivity and security. \nSpeakers\nChief Technologist Christophe Bianchi
URL:https://marketingeda.com/event/5-new-ways-to-maximize-your-hardware-security-resilience/
CATEGORIES:EDA,Webinar
ATTACH;FMTTYPE=image/jpeg:https://marketingeda.com/wp-content/uploads/Ansys-May-23-2024.jpg
END:VEVENT
BEGIN:VEVENT
DTSTART;TZID=America/Los_Angeles:20240522T210000
DTEND;TZID=America/Los_Angeles:20240522T220000
DTSTAMP:20240521T182515Z
CREATED:20240521T182515Z
LAST-MODIFIED:20240521T182515Z
UID:8015-1716411600-1716415200@marketingeda.com
SUMMARY:RapidGPT: Meet Your New AI-Powered Design Assistant
DESCRIPTION:Join us for our upcoming webinar introducing RapidGPT\, a revolutionary tool developed by PrimisAI that is reshaping the field of AI-driven EDA. RapidGPT is changing the game in hardware engineering with its groundbreaking generative AI approach. Offering a natural language interface\, RapidGPT empowers designers to boost productivity and shorten time-to-market. During this session\, explore how RapidGPT simplifies the design journey for hardware engineers\, from initial concept to RTL\, transcending conventional automation and revolutionizing the hardware engineering process.
URL:https://marketingeda.com/event/rapidgpt-meet-your-new-ai-powered-design-assistant/
CATEGORIES:EDA,Webinar
ATTACH;FMTTYPE=image/jpeg:https://marketingeda.com/wp-content/uploads/PrimisAI-May-22-2024.jpg
END:VEVENT
BEGIN:VEVENT
DTSTART;TZID=America/Los_Angeles:20240522T100000
DTEND;TZID=America/Los_Angeles:20240522T110000
DTSTAMP:20240510T222103Z
CREATED:20240510T222103Z
LAST-MODIFIED:20240510T222103Z
UID:7985-1716372000-1716375600@marketingeda.com
SUMMARY:Debugging Features of UVM
DESCRIPTION:A UVM testbench is a large and complex piece of software. Like any other large and complex piece of software\, a verification environment written using UVM will require debugging at some stage. There are various debugging features built into UVM to help with this. \nIn this one-hour webinar\, Doulos Senior Member Technical Staff Doug Smith explores the various features in UVM to help you debug your UVM environment\, test cases\, and design under test. \nTopics include: \n\nDebugging the Testbench\nDebugging Stimulus\nDebugging the Design\n\nAt the end of the webinar\, we will also look at an example of the tool support features for debugging UVM using the Cadence Xcelium Logic Simulator.
URL:https://marketingeda.com/event/debugging-features-of-uvm-2/
CATEGORIES:EDA,Webinar
ATTACH;FMTTYPE=image/jpeg:https://marketingeda.com/wp-content/uploads/Cadence-May-22-2024-1.jpg
END:VEVENT
BEGIN:VEVENT
DTSTART;TZID=America/Los_Angeles:20240522T080000
DTEND;TZID=America/Los_Angeles:20240522T090000
DTSTAMP:20240508T181719Z
CREATED:20240508T181719Z
LAST-MODIFIED:20240508T181719Z
UID:7969-1716364800-1716368400@marketingeda.com
SUMMARY:Addressing the Challenges of PCB Design for Manufacturing
DESCRIPTION:Manufacturing issues can be a big reason why your project timelines get derailed and even result in costly failures. By understanding common errors that occur while designing or creating your fabrication and assembly documentation\, you can avoid making the same mistakes on future designs. With access to over 80 comprehensive Design for Test (DFT)\, Design for Assembly (DFA)\, and Design for Fabrication (DFF) checks\, automated documentation that is always synced to your layout data\, and single output manufacturing\, OrCAD X helps ensure that your designs are robust and functional from the start. \nWhether you’re a seasoned professional or new to PCB manufacturing\, this webinar will go into the power of OrCAD X and how it will streamline your manufacturing output process\, helping you eliminate late-stage PCB manufacturing problems. \n\nJoin us to learn about: \n\nCommon DFx issues seen by manufacturers/fabricators\nDFx design guidelines to follow\nIn-design DFM checking with DesignTrue DFM technology\nAutomating manufacturing documentation with Live DOC\nGenerating manufacturing outputs\n\n\nSPEAKERS: \nJohn Carney\, Product Engineering Architect\, Cadence \nKent Balius\, Director of Pre-Production Engineering. Summit Interconnect \nHOST: \nSupreeth Mannava\, Senior Principal Product Manager\, Cadence
URL:https://marketingeda.com/event/addressing-the-challenges-of-pcb-design-for-manufacturing/
CATEGORIES:EDA,Webinar
ATTACH;FMTTYPE=image/jpeg:https://marketingeda.com/wp-content/uploads/Cadence-May-22-2024.jpg
END:VEVENT
BEGIN:VEVENT
DTSTART;TZID=America/Los_Angeles:20240522T080000
DTEND;TZID=America/Los_Angeles:20240522T090000
DTSTAMP:20240502T173621Z
CREATED:20240502T173621Z
LAST-MODIFIED:20240502T173621Z
UID:7937-1716364800-1716368400@marketingeda.com
SUMMARY:Questa RDC Assist – Improving designer productivity and enabling faster RDC verification closure with machine learning
DESCRIPTION:In 2021 Siemens EDA released CDC Assist. CDC Assist is an ML powered feature that empowers users to configure\, debug\, and close CDC on designs more rapidly. Following the success of CDC Assist\, Siemens introduced RDC Assist in 2023.\n‌\nUsing the same ML technology in CDC Assist\, RDC Assist dramatically improves the time and effort required to configure\, debug\, and close reset domain crossing analysis.\n‌\nSince RDC violations often have a common cause\, RDC Assist helps users to identify the root cause for the RDC violations and errors through data mining and machine learning techniques.\n‌\nWe will discuss use models and best practices to utilize RDC Assist\, and walk through a demo showing its power.\nWhat you will learn: \n\n‌How RDC Assist helps users expedite their RDC Analysis\nHow to run RDC Assist\nHow to analyze RDC Assist results in the UI\nHow to use RDC Assist to focus on major hotspots first\nTechniques presented are applicable to both CDC and RDC analysis\n‌\n\nWho should attend: \nRTL designers\, anyone that runs CDC or RDC\, design team leads \nSpeaker:\n\n\n\n\n\n\nFarhad Ahmed\nPrincipal Product Engineer\, Siemens EDA\n\n\n\n\nFarhad Ahmed currently is a Principal Product Engineer at Siemens EDA Software.​ \nHe has been working in Chip Design and EDA companies for last 30+ years. He graduated with a B.Sc.(EE) degree from Bangladesh University of Engg. & Technology and a M.Sc.(EE) from Washington State University.​ \nHe started his career as an RTL Logic Designer for Sun Microsystems working on SPARC microprocessors.​ \nFarhad loves to read books on history\, an avid swimmer\, Squash player\, does hiking regularly and also loves kayaking.​
URL:https://marketingeda.com/event/questa-rdc-assist-improving-designer-productivity-and-enabling-faster-rdc-verification-closure-with-machine-learning/
CATEGORIES:EDA,Webinar
ATTACH;FMTTYPE=image/jpeg:https://marketingeda.com/wp-content/uploads/Siemens-May-22-2024.jpg
END:VEVENT
BEGIN:VEVENT
DTSTART;TZID=America/Los_Angeles:20240522T070000
DTEND;TZID=America/Los_Angeles:20240522T090000
DTSTAMP:20240424T164124Z
CREATED:20240424T164124Z
LAST-MODIFIED:20240424T164124Z
UID:7910-1716361200-1716368400@marketingeda.com
SUMMARY:Accelerating AI Applications Using Custom RISC-V based SIMD/VLIW DSPs
DESCRIPTION:The revolution in AI triggers an increased awareness for application-specific instruction-set processors (ASIPs). These processors implement a specialized instruction-set architecture (ISA) tailored to the AI application domain\, often starting from a baseline such as the RISC-V ISA.  ASIPs can replace traditional fixed-function hardware accelerators\, thereby introducing software-programmability in the AI acceleration domain\, and thus more flexibility and agility in both the design process and the eventual product.  By maintaining a RISC-V ISA baseline\, compatibility with and reuse of existing processor ecosystem elements is facilitated. \nSynopsys ASIP Designer is the industry-leading tool to design\, implement\, program and verify application-specific instruction-set processors. Starting from a single processor specification\, designers immediately obtain an optimizing C/C++ compiler\, cycle-accurate simulator and synthesizable hardware implementation of the ASIP.  Using a unique compiler-in-the-loop™ and synthesis-in-the-loop™ methodology\, the ISA and microarchitecture can be tuned quickly to the application domain. \nThis seminar introduces you to the ASIP Designer tool-suite. It features a tutorial and two case studies from AI application domains. The tutorial introduces the typical architectural features needed to accelerate AI algorithms\, such as specialization\, SIMD\, and VLIW\, and how ASIP Designer supports them. The first case study demonstrates a SIMD/VLIW architecture with a RISC-V baseline processor for accelerating activation functions. The second case study shows a RISC-V based ASIP for medium-throughput convolutional neural networks (CNN) with programming support for TensorFlowLite for Microcontrollers (TFLM). \n\n\n\nWho Should Attend? \nIf you are a design engineer\, algorithm developer\, software engineer\, system architect\, or design manager focusing on advanced SoCs requiring application-specific optimizations\, you won’t want to miss this event.
URL:https://marketingeda.com/event/accelerating-ai-applications-using-custom-risc-v-based-simd-vliw-dsps/
CATEGORIES:EDA,IP,Webinar
ATTACH;FMTTYPE=image/jpeg:https://marketingeda.com/wp-content/uploads/Synopsys-May-22-2024.jpg
END:VEVENT
BEGIN:VEVENT
DTSTART;TZID=America/Los_Angeles:20240521T100000
DTEND;TZID=America/Los_Angeles:20240521T110000
DTSTAMP:20240503T190402Z
CREATED:20240503T190402Z
LAST-MODIFIED:20240503T190402Z
UID:7943-1716285600-1716289200@marketingeda.com
SUMMARY:The Next Generation of 3DIC Interposer/InFO Design
DESCRIPTION:In recent years\, the semiconductor industry has experienced a breakthrough in the onset of 2.5D and 3D chiplet-based products. These products promise to extend the limits of Moore’s Law while demolishing limitations on speed and capacity for our highest tiers of compute. But for all the adulation we heap upon the 3DIC paradigm\, we seemingly pay very little attention to the humble interposer die that enables communication between these groundbreaking chiplets. \n  \nWhat Attendees Will Learn: \nSynopsys tools can now improve the construction and signoff process for all styles of interposers. AMD has tested these tools and will present a comprehensive update on what we see as a step forward in interposer design. This flow is driven primarily within the Synopsys 3DIC Compiler platform\, though other noteworthy tools and engines are employed at key stages to ensure a high standard of quality. The Synopsys webinar begins with a brief overview of the current interposer design flow\, including pros and cons to the current approach and opportunities for new development. We’ll then cover an end-to-end design flow that addresses these opportunities across the span of floorplanning\, construction\, extraction\, and signoff. Finally\, we’ll wrap up with conclusions and future work. \n\n\n\n\n\n\n\n\n\n\nSpeakers\n\n\nListed below are the industry leaders scheduled to speak. \n\n\n\n\n\n\n\n\n\n\n\n\n\n\n\n\n\n\n\n\n\n\n\n\n\n\nKenneth Larsen\n\n\nProduct Management\, Sr Director\nSynopsys \n\n\n\n\n\n\n\n\nKenneth Larsen is a director of product management in the EDA Group at Synopsys\, focusing on 3D Heterogeneous Integration and Advanced Packaging. He has 30 years of experience in IC design verification and validation. Before joining Synopsys\, Kenneth was worldwide senior technical director at Mentor. \n\n\n\n\n\n\n\n\n\n\n\n\n\n\n\n\n\n\n\n\n\n\n\n\n\n\n\n\n\n\n\nNitin Navale\n\n\nPrincipal Member of Technical Staff\nAMD \n\n\n\n\n\n\n\n\nNitin Navale has worked across AMD & Xilinx since 2008 and currently serves as Principal Member of Technical Staff in the CAD/Methodology team. His current role is Technical Lead for 3DIC Methodology\, though he has previously also worked on design automation that ranges across STA\, EM/IR\, Thermal\, ESD\, SOC Floorplanning & Construction\, IP Management\, Netlisting\, and Characterization. Nitin earned his BS and MS in Electrical Engineering from the University of Illinois\, Urbana-Champaign. Outside of work\, he is consumed by his devotion to board games and strategy. He’s also an avid musician who plays multiple instruments with an active interest in music theory. \n\n\n\n\n\n\n\n\n\n\n\n\n\n\n\n\n\n\n\n\n\n\n\n\n\n\n\n\n\n\nAkshata Sonnad\n\n\nMember of Technical Staff\nAMD \n\n\n\n\n\n\n\n\nAkshata Sonnad is a Member of Technical Staff at AMD\, working on developing methodologies and flows for floor planning\, signoff\, and interposer/ InFO routing for next-generation multi-die systems. She graduated from University of Southern California with a Master’s degree in Electrical Engineering and worked as a CAD engineer on the physical design and verification of block level IPs and SOCs\, before making a transition to 3DIC Design Methodology.
URL:https://marketingeda.com/event/the-next-generation-of-3dic-interposer-info-design/
CATEGORIES:EDA,Webinar
ATTACH;FMTTYPE=image/jpeg:https://marketingeda.com/wp-content/uploads/Synopsys-May-21-2024.jpg
END:VEVENT
BEGIN:VEVENT
DTSTART;TZID=America/Los_Angeles:20240516T100000
DTEND;TZID=America/Los_Angeles:20240516T110000
DTSTAMP:20240221T175436Z
CREATED:20240221T175436Z
LAST-MODIFIED:20240221T175436Z
UID:7667-1715853600-1715857200@marketingeda.com
SUMMARY:AI-Driven EM-IR Design Closure
DESCRIPTION:IR drop closure is becoming a major challenge for designers on advanced nodes. The number of violations at signoff has increased significantly\, leading to longer turnaround time (TAT) or violations being waived. To solve this challenge\, IR drop needs to be addressed early in the implementation phase with an automated IR prevention and fixing methodology. \nIn this webinar\, we will present an AI-driven EM-IR closure solution integrated into the implementation flow. This solution uses AI methods to automatically root cause the IR drop violations and selects the most efficient PPA- and DRC-aware methods to fix the IR drop issues. The solution also uses AI models to enable fast incremental IR inferencing to validate the benefit of the design improvements. \nCome learn about this breakthrough solution that will significantly improve your IR drop closure TAT.
URL:https://marketingeda.com/event/ai-driven-em-ir-design-closure/
CATEGORIES:EDA,Webinar
ATTACH;FMTTYPE=image/jpeg:https://marketingeda.com/wp-content/uploads/Cadence-May-16-2024.jpg
END:VEVENT
BEGIN:VEVENT
DTSTART;TZID=America/Los_Angeles:20240515T130000
DTEND;TZID=America/Los_Angeles:20240515T140000
DTSTAMP:20240508T233014Z
CREATED:20240508T233014Z
LAST-MODIFIED:20240508T233014Z
UID:7977-1715778000-1715781600@marketingeda.com
SUMMARY:Innovative Technologies\, Tools\, and Methodologies for Space Applications
DESCRIPTION:In the world of space applications\, reliability is paramount. As the space sector continues to experience rapid growth and evolution\, new challenges are emerging to meet the demands of various mission types and requirements\, such as robust functional safety protections\, high reliability\, and dependable operation. Join us for an exclusive panel discussion hosted by Lattice Semiconductor\, where we delve into the dynamic landscape of the space industry and the indispensable role of the groundbreaking technology solutions enabling the growing demands of mission-critical requirements and application development. \nSpeakers \nJim T.\, Business Development\, Lattice Semiconductor\nKhalid Khan\, Directory of Applications Engineer\, Synopsys\nMelanie Berg\, Founder and CEO\, Space R3
URL:https://marketingeda.com/event/innovative-technologies-tools-and-methodologies-for-space-applications/
CATEGORIES:EDA,IP,Webinar
ATTACH;FMTTYPE=image/jpeg:https://marketingeda.com/wp-content/uploads/Lattice-May-15-2024.jpg
END:VEVENT
BEGIN:VEVENT
DTSTART;TZID=Asia/Tokyo:20240509T150000
DTEND;TZID=Asia/Tokyo:20240509T160000
DTSTAMP:20240429T161300Z
CREATED:20240429T161300Z
LAST-MODIFIED:20240429T161300Z
UID:7922-1715266800-1715270400@marketingeda.com
SUMMARY:Innovative Approach to SoC Power Optimization
DESCRIPTION:Power is the biggest factor impacting semiconductors from custom silicon to CPU/GPU products. System-level Power modeling and simulation is needed to measure power accurately and efficiently. The scope of power studies has expanded to include the software\, thermal and generation to feed into the UVM/UPF methodology. At this Webinar we will highlight a new system-level power methodology that integrates micro-architecture power storage\, consumption\, management and thermal assessments. Case studies will be presented on Chiplet power\, mapping strategy of DNN on AI Engines and Tensor cores\, hardware-software partitioning\, and testing power management for mobile and low-power devices.
URL:https://marketingeda.com/event/innovative-approach-to-soc-power-optimization/
CATEGORIES:EDA,IP,Webinar
ATTACH;FMTTYPE=image/jpeg:https://marketingeda.com/wp-content/uploads/Mirabilis-May-9-2024.jpg
END:VEVENT
BEGIN:VEVENT
DTSTART;TZID=America/Los_Angeles:20240509T100000
DTEND;TZID=America/Los_Angeles:20240509T110000
DTSTAMP:20240429T161925Z
CREATED:20240429T161925Z
LAST-MODIFIED:20240429T161925Z
UID:7925-1715248800-1715252400@marketingeda.com
SUMMARY:Cracking the Power Code: Innovative Approach to SoC Power Optimization
DESCRIPTION:Power is the biggest factor impacting semiconductors from custom silicon to CPU/GPU products. System-level Power modeling and simulation is needed to measure power accurately and efficiently. The scope of power studies has expanded to include the software\, thermal and generation to feed into the UVM/UPF methodology. At this Webinar we will highlight a new system-level power methodology that integrates micro-architecture power storage\, consumption\, management and thermal assessments. Case studies will be presented on Chiplet power\, mapping strategy of DNN on AI Engines and Tensor cores\, hardware-software partitioning\, and testing power management for mobile and low-power devices.
URL:https://marketingeda.com/event/cracking-the-power-code-innovative-approach-to-soc-power-optimization/
CATEGORIES:EDA,Webinar
ATTACH;FMTTYPE=image/jpeg:https://marketingeda.com/wp-content/uploads/Mirabilis-May-9-2024-USA.jpg
END:VEVENT
BEGIN:VEVENT
DTSTART;TZID=America/Los_Angeles:20240509T100000
DTEND;TZID=America/Los_Angeles:20240509T110000
DTSTAMP:20240419T172547Z
CREATED:20240419T172547Z
LAST-MODIFIED:20240419T172547Z
UID:7883-1715248800-1715252400@marketingeda.com
SUMMARY:AI-Driven 3D System Analysis & Optimization for EM Antenna/RF Problems
DESCRIPTION:Antenna/RF design problems often involve the optimization of many variables\, requiring numerous evaluations (EM simulations) using traditional optimization methods. Design engineers need an intelligent\, accurate\, and easy-to-use simulation platform and analysis solution that reduces repetitive design cycles while increasing user productivity and efficiency. \nLeveraging an advanced AI-enabled methodology\, the Cadence Optimality Intelligent System Explorer delivers quality results leading to the optimal performance of electrical systems. Optimality Explorer utilizes a novel surrogate model-aware mechanism that significantly reduces the number of required EM simulations. In addition\, the seamless integration between different Cadence solver technologies (Clarity 3D Solver\, AWR Microwave Office\, and Optimality Explorer) enables full-cycle circuit-field co-simulation and optimization for RF/antenna design problems. \nWith the integration of Clarity 3D Solver and AWR Microwave Office\, RF/antenna designers will have ready access to high-capacity EM analysis for design verification and signoff of large\, complex RF mixed-signal systems beyond the capabilities offered by conventional solvers thanks to the Clarity distributed multiprocessing technology. \nThis webinar demonstrates the efficacy of the Optimality Explorer and Clarity 3D Solver engines for several complex high-dimensional antenna/RF problems. \nKey takeaways: \n\nOptimality Explorer leverages an advanced AI-enabled methodology to deliver quality results leading to the optimal performance of electrical systems\nThe seamless integration between Clarity 3D Solver\, AWR Microwave Office\, and Optimality Explorer enables full-cycle circuit-field co-simulation and optimization for RF/antenna design problems\nDemonstration of the efficacy of the Optimality Explorer and Clarity 3D Solver engines for several complex high-dimensional antenna/RF problems
URL:https://marketingeda.com/event/ai-driven-3d-system-analysis-optimization-for-em-antenna-rf-problems/
CATEGORIES:EDA,Webinar
ATTACH;FMTTYPE=image/jpeg:https://marketingeda.com/wp-content/uploads/Cadence-May-9-2024.jpg
END:VEVENT
BEGIN:VEVENT
DTSTART;TZID=America/Los_Angeles:20240502T090000
DTEND;TZID=America/Los_Angeles:20240502T100000
DTSTAMP:20240422T161648Z
CREATED:20240422T161648Z
LAST-MODIFIED:20240422T161648Z
UID:7886-1714640400-1714644000@marketingeda.com
SUMMARY:Smart methods for DFT chip architecture & validation
DESCRIPTION:Combining market-leading design-for-test (DFT) technologies with best-in-class netlist synthesis allows you to achieve DFT success more quickly. Many customers\, including those for emulation and IC test\, have challenges with scaling architectures. This webinar describes how Siemens emulation and silicon test solutions can work together to provide a smart DFT plug-and-play architecture for Veloce ICs. \nThe Veloce hardware-assisted verification system can efficiently handle large\, full-chip GLE designs. Tessent Streaming Scan Network (SSN)\, a once-in-a-decade technology\, packetizes test data to dramatically reduce DFT implementation effort and reduce manufacturing test cost. The Veloce DFT application enables SSN\, as well as other test functions such as TestKompress\, BIST pattern validation\, functional fault grading\, power profiling and estimation\, by accelerating multiple orders of magnitude faster than traditional software simulation. Combining Veloce Strato and Tessent SSN can accelerate your time to DFT success. \nTarget audience: \n\nDFT Engineers\nDFT Managers\nProduct and Test Engineers and Managers\n\nWhat you will learn: \n\nIntroduction to Veloce DFT App and how it helps validate Tessent DFT logic/patterns\nDFT Power Profiling and Fault grading using Veloce Power App\nApplying SSN to solve the Veloce chip design challenges\n\n\n\nSpeakers:\n\n\n\n\n\n\nRobert Serphillips\nProduct Manager\, Verification\, Siemens EDA\n\n\n\n\nRobert Serphillips has worked in the pre-silicon verification\, post-silicon validation\, and production design-for-test (DFT) fields. He has designed and debugged ATE test patterns on multiple stand alone and SoC devices spanning close to 20 years in the semiconductor industry. The products include a mix of consumer\, automotive\, industrial\, military\, networking and mixed signal. Robert is currently a product manager with the Siemens EDA hardware-assisted verification business unit. \n\n\n\n\n\n\n\nRon Press\nSr. Director of Technology Enablement\, Tessent\, Siemens EDA – Tessent\n\n\n\n\nRon Press\, a 30-year veteran of the test and DFT industry\, is a member of the International Test Conference (ITC) Steering Committee\, a Golden Core member of the IEEE Computer Society and a Senior Member of IEEE. Ron has patents on reduced-pin-count testing\, glitch-free clock switching and on 3D DFT. He started his work in the test industry at Raytheon Company working on test and consulting throughout the company on test and built-in test. He co-developed the Testability Design Rating System (TDRS) for the US Air Force and received the Raytheon inventor’s award for a built-in test analysis system. Ron led the development of a state-of-the-art RF/digital tester at Harris RF starting in 1995.
URL:https://marketingeda.com/event/smart-methods-for-dft-chip-architecture-validation/
CATEGORIES:EDA,Webinar
ATTACH;FMTTYPE=image/jpeg:https://marketingeda.com/wp-content/uploads/Siemens-May-2-2024.jpg
END:VEVENT
BEGIN:VEVENT
DTSTART;TZID=America/Los_Angeles:20240430T060000
DTEND;TZID=America/Los_Angeles:20240430T070000
DTSTAMP:20240416T003939Z
CREATED:20240416T003939Z
LAST-MODIFIED:20240416T003939Z
UID:7858-1714456800-1714460400@marketingeda.com
SUMMARY:DFT for chiplets & 3D ICs using Tessent Multi-die
DESCRIPTION:3D IC (2.5D/3D) designs are on the rise. Design for Test (DFT) for chiplets must be general purpose so they can be tested stand alone and easy to test after assembly into 2.5D or 3D devices. In this webinar you will learn how to use Tessent Multi-die and still adhere to standards like IEEE 1149.1\, IEEE 1500\, IEEE 1687\, and IEEE 1838. \nWho should attend:\n\nAnyone planning to implement chiplets\, 2.5D/3D designs and would like to learn about design for test.\nDFT Engineers\nDFT Managers\nDesign Engineers\nTest Engineers\nProject Managers for ASIC/design\n\nWhat you will learn:\n\nHow Tessent Multi-die will aid in 3D IC design for test\nIntro to what IEEE 1838 standard is and how Tessent solution can be used. Use of Tessent Streaming Scan Network (SSN) as flexible parallel port (FPP)\nHow in 2.5D device\, boundary scan-based interconnect test can be performed with Tessent Multi-die\n\n\n\nSpeaker:\n\n\n\n\n\n\nItamar Tsachi\nEurope DFT Manager\, Siemens EDA\n\n\n\n\nItamar Tsachi has more than 20 years of experience in the semiconductor industry and has collaborated with many local and international Siemens EDA customers on a wide range of solutions targeting DFT and RTL->GDSII flows. Before joining Mentor Graphics\, Itamar ramped up IBM’s Physical Design Group in Israel developing SoCs using IBM’s leading-edge technology. Itamar was also a Physical Implementation Consultant and Leader at multiple startups like Mysticom\, BrightCom technologies and Silicon Value\, where he began his chip design career in a variety of roles\, from Digital / Analog layout design to Place & Route and CAD development. Itamar holds one Patent” Placement Driving Routing (PDR) – “A method and apparatus for placement driven routing with a minimum number of changes in the placement.”
URL:https://marketingeda.com/event/dft-for-chiplets-3d-ics-using-tessent-multi-die/
CATEGORIES:EDA,Webinar
ATTACH;FMTTYPE=image/jpeg:https://marketingeda.com/wp-content/uploads/Siemens-April-30-2024.jpg
END:VEVENT
BEGIN:VEVENT
DTSTART;TZID=America/New_York:20240425T110000
DTEND;TZID=America/New_York:20240425T120000
DTSTAMP:20240401T181039Z
CREATED:20240401T181039Z
LAST-MODIFIED:20240401T181039Z
UID:7800-1714042800-1714046400@marketingeda.com
SUMMARY:Improving Semiconductor Wafer Fabrication Process Efficiencies Using Ansys Solutions
DESCRIPTION:Ansys Semiconductor Manufacturing Webinar Series: Part 1 of 3. \nJoin us on Thursday\, April 25th for an in-depth view of multi-physics simulation in the semiconductor fabrication process. \nOverview\nAccurate design and optimization of the semiconductor fabrication process/equipment for yield improvements and faster time-to-market require multiphysics simulation\, which can address various physical interactions and phenomena. By encompassing factors from contamination challenges to ensuring uniform product outcomes\, engineers can leverage such simulations to generate innovative ideas for optimized processes and cutting-edge solutions in semiconductor fabrication. \nThis webinar will demonstrate the practical application of Ansys tools in understanding the impact of various parameters on diverse wafer fabrication processes and fine-tuning them to improve yields and reduce wafer cycle time. \nWhat you will learn\n\nImportance of simulation in fabrication processes\nReduce wafer cycle time\nModel fabrication process with Ansys tools\nOptimize of fabrication processes\nSystem-level modeling of fabrication processes\n\nWho should attend\nEngineers and Engineering Managers/Directors\, Manufacturing teams\, Etch teams\, Deposition teams\, NPI teams and Aftermarket teams \nSpeaker\n\nNima Bohlooli\, Senior Application Engineer\, Ansys
URL:https://marketingeda.com/event/improving-semiconductor-wafer-fabrication-process-efficiencies-using-ansys-solutions/
CATEGORIES:EDA,Semiconductor,Webinar
ATTACH;FMTTYPE=image/jpeg:https://marketingeda.com/wp-content/uploads/April-25-2024-Ansys.jpg
END:VEVENT
BEGIN:VEVENT
DTSTART;TZID=America/New_York:20240425T090000
DTEND;TZID=America/New_York:20240425T100000
DTSTAMP:20240401T180250Z
CREATED:20240401T180042Z
LAST-MODIFIED:20240401T180250Z
UID:7797-1714035600-1714039200@marketingeda.com
SUMMARY:The Era of Software-Defined Everything: Chiplets and Bespoke Silicon
DESCRIPTION:From fintech to automotive\, defense to healthcare\, everyone wants bespoke computing platforms to build “software-defined solutions” that are differentiated in their respective markets. Sign up and save your spot for this special presentation. \nOverview\nWith the advent of 3D ICs and heterogeneous semiconductor integration\, mapping a system on a customized chip/hardware is accessible to “everyone.” \nThe semiconductor suppliers are gearing themselves for the change\, and\, as Jensen Huang (NVIDIA CEO) was recently quoted\, “2024 is the year where every industry is becoming a high-tech industry.” \nFrom fintech to automotive\, defense to healthcare\, everyone wants bespoke computing platforms to build “software-defined solutions” that are differentiated in their respective markets. \nBut this (r)evolution faces a multitude of challenges\, such as \n\nIs the workforce (engineering community at large) ready for this massive deployment of semiconductor technologies?\nAre the design methodologies\, both semiconductor and system\, ready and enabling?\nWhat is the level of over-engineering that drives this sequence?\n\nWhat you will learn\n\nHow to harness 3D-IC and chiplets to accelerate the transition to software-defined everything\nHow chiplets can give your business a competitive edge\nWhat is the best use of AI for the transition?\n\nWho should attend and why\nIf you are responsible for an engineering department or in charge of NPI and Product Development /Strategy\, sign up for this online webinar. \nSpeaker\n\nChief Technologist Christopher Bianchi
URL:https://marketingeda.com/event/the-era-of-software-defined-everything-chiplets-and-bespoke-silicon/
CATEGORIES:EDA,IP,Webinar
ATTACH;FMTTYPE=image/jpeg:https://marketingeda.com/wp-content/uploads/Ansys-April-25-2024.jpg
END:VEVENT
BEGIN:VEVENT
DTSTART;TZID=America/Los_Angeles:20240424T080000
DTEND;TZID=America/Los_Angeles:20240424T090000
DTSTAMP:20240416T183848Z
CREATED:20240416T183848Z
LAST-MODIFIED:20240416T183848Z
UID:7863-1713945600-1713949200@marketingeda.com
SUMMARY:Deploying Solido Design Environment AI Workflows on AWS
DESCRIPTION:Utilizing AWS cloud resources to accelerate variation-aware verification   \n\nAI-powered Solido Design Environment provides SPICE-accurate variation-aware verification for 3\, 4\, 5\, 6 and higher sigma targets\, orders of magnitude faster than traditional brute-force methods. With cloud computing made more accessible than before\, many teams are considering running design and verification workloads\, including Solido Design Environment\, on the cloud. \nSiemens and AWS’ strategic collaboration enables a Siemens EDA portfolio that is even more accessible\, scalable\, flexible\, and secure on AWS. Today\, Solido Design Environment users can leverage the power of AWS cloud computing to manage and deploy SPICE-level verification\, resulting in accelerated verification schedules and significantly higher capacity for peak workload demands. \nIn this Masterclass webinar\, co-presented by Siemens EDA and AWS\, we explore best practices and resources available for deploying Solido Design Environment on AWS. Join us and learn more about AWS’ solutions for SPICE-level verification\, tried-and-tested cloud configurations for Solido Design Environment\, and a Q&A session with Siemens and AWS experts to get started confidently and leverage AWS compute to maximize verification throughput and address peak demand on Solido Design Environment. \nTopic Include:\n– The need for cloud scalability for  semiconductor design\n– Solido Design Environment overview\n– Best practices and considerations\n– AWS capabilities for SPICE verification\, including example cloud configuration\n– Resources available for teams deploying to AWS cloud\n– Interactive Q&A \nFeatured Products:  Solido Design Environment\, AWS Cloud Platform \nSpeakers:\n\n\n\n\nWei-Lii Tan\nDirector of Product Management\, Siemens EDA\n\n\nWei-Lii Tan is Director of Product Management in Siemens DISW’s Custom IC Verification division for Solido’s AI-enabled verification & characterization\, and IP validation product lines. Wei-Lii has 15 years of experience in semiconductor and EDA\, having worked on both digital and analog methodologies. He has a master’s degree in electrical engineering from Mississippi State University\, and an M.B.A. from Santa Clara University. \n\nAzim Siddique\nSenior Solutions Architect\, Amazon Web Services\n\n\nAzim works with AWS Enterprise customers on their Cloud adoption journey. Azim has 20+ years of experience working at large global organizations in the manufacturing and industrials domain\, architecting and delivering innovative solutions at scale to generate business value. Azim is passionate about being part of transformational changes driven by technological innovation.
URL:https://marketingeda.com/event/deploying-solido-design-environment-ai-workflows-on-aws/
CATEGORIES:EDA,Webinar
ATTACH;FMTTYPE=image/jpeg:https://marketingeda.com/wp-content/uploads/Siemens-April-24-2024.jpg
END:VEVENT
BEGIN:VEVENT
DTSTART;TZID=Europe/London:20240423T120000
DTEND;TZID=Europe/London:20240423T130000
DTSTAMP:20240410T161505Z
CREATED:20240410T161505Z
LAST-MODIFIED:20240410T161505Z
UID:7823-1713873600-1713877200@marketingeda.com
SUMMARY:DVClub Europe - Formal Verification
DESCRIPTION:13 days to go the next DVClub Europe meeting takes place on Tuesday 23rd April with a theme of “Formal Verification“.\n\nFormal Verification can help you find bugs earlier in the design cycle and accelerate root cause analysis. But success with Formal requires the effective selection and implementation of the right formal technologies and methods. In this DVClub meeting our speakers will share their experiences adopting Formal Verification and then open the floor for discussion followed by the usual networking opportunities.\n\nAgenda (BST) \n12:00   Welcome and Introduction – Mike Bartley\, Tessolve\n12:00 Brajmohan Sharma\, Marvel Technology – Advanced Formal Verification and Robust Regression Strategies for Highly Parameterized Designs\n12:20 Easwaran Krishnan & Savita Suresh Lohar\, Tessolve Semiconductor\n12:40 Gayatri Padhy\, Object Automation – Formal Verification with AI/ML\n13:00 Cadence Design System\n13:15 Neena Chandawale \,Agnisys\n13:30 Close \nRegister now to become a part of this event. Free to attend online. \nTicket Tailor- DVClub Europe 
URL:https://marketingeda.com/event/dvclub-europe-formal-verification/
CATEGORIES:EDA,Webinar
ATTACH;FMTTYPE=image/jpeg:https://marketingeda.com/wp-content/uploads/DVClub-Europe-23-April-2024.jpg
END:VEVENT
BEGIN:VEVENT
DTSTART;TZID=Asia/Tokyo:20240418T150000
DTEND;TZID=Asia/Tokyo:20240418T160000
DTSTAMP:20240415T174855Z
CREATED:20240415T174855Z
LAST-MODIFIED:20240415T174855Z
UID:7844-1713452400-1713456000@marketingeda.com
SUMMARY:Optimizing Chiplet architectures of RISC-V clusters\, GPU and DNN using System-Level IP
DESCRIPTION:Multi-die SoC containing multiple RISC-V clusters\, GPU\, NPU\, accelerators and DNN have considerable benefits for applications in automotive\, space and industrial. Architecture exploration of the chiplet-based SoC requires multiple interconnect protocol models\, and multiple coherent and non-coherent compute resources. This Webinar will demonstrate a methodology for rapid modeling and architecture trade-off using UCIe in modeling and simulating a multi-die SoC in a matter of weeks. These models can be used for UCIe setup\, task partitioning\, distribution of compute resources across dies\, sharing coherency between RISC-V clusters\, GPU and AI Engines. We will show how workloads and application task graphs can be used to optimize the settings to meet the requirements\, identify system bottlenecks and optimize for PPA. Results from actual hardware designs with different configurations and allocations will be discussed during the session.
URL:https://marketingeda.com/event/optimizing-chiplet-architectures-of-risc-v-clusters-gpu-and-dnn-using-system-level-ip/
CATEGORIES:EDA,IP,Webinar
ATTACH;FMTTYPE=image/jpeg:https://marketingeda.com/wp-content/uploads/Mirabilis-18-April-2024.jpg
END:VEVENT
BEGIN:VEVENT
DTSTART;TZID=America/Los_Angeles:20240418T100000
DTEND;TZID=America/Los_Angeles:20240418T110000
DTSTAMP:20240415T175505Z
CREATED:20240415T175505Z
LAST-MODIFIED:20240415T175505Z
UID:7847-1713434400-1713438000@marketingeda.com
SUMMARY:Optimizing Chiplet architectures of RISC-V clusters\, GPU and DNN using System-Level IP
DESCRIPTION:Multi-die SoC containing multiple RISC-V clusters\, GPU\, NPU\, accelerators and DNN have considerable benefits for applications in automotive\, space and industrial. Architecture exploration of the chiplet-based SoC requires multiple interconnect protocol models\, and multiple coherent and non-coherent compute resources. This Webinar will demonstrate a methodology for rapid modeling and architecture trade-off using UCIe in modeling and simulating a multi-die SoC in a matter of weeks. These models can be used for UCIe setup\, task partitioning\, distribution of compute resources across dies\, sharing coherency between RISC-V clusters\, GPU and AI Engines. We will show how workloads and application task graphs can be used to optimize the settings to meet the requirements\, identify system bottlenecks and optimize for PPA. Results from actual hardware designs with different configurations and allocations will be discussed during the session.
URL:https://marketingeda.com/event/optimizing-chiplet-architectures-of-risc-v-clusters-gpu-and-dnn-using-system-level-ip-2/
CATEGORIES:EDA,IP,Webinar
ATTACH;FMTTYPE=image/jpeg:https://marketingeda.com/wp-content/uploads/Mirabilis-April-18-2024.jpg
END:VEVENT
BEGIN:VEVENT
DTSTART;TZID=America/Los_Angeles:20240417T090000
DTEND;TZID=America/Los_Angeles:20240417T103000
DTSTAMP:20240415T184123Z
CREATED:20240415T184123Z
LAST-MODIFIED:20240415T184123Z
UID:7855-1713344400-1713349800@marketingeda.com
SUMMARY:Introduction to ParagonX
DESCRIPTION:Are you ready to supercharge your design process? Introducing our Diakopto Training Program – your gateway to a faster\, easier\, and more intuitive approach to design analysis and optimization! \nIn this course\, you’ll learn how to:\n Analyze and visualize layout parasitics with precision using R/C/delay/I maps.\n Perform net matching for accurate and refined designs.\n Identify the root cause of bottlenecks in post-layout simulation results with ease.\n Iterate over layout improvements efficiently before running post-layout simulations using the powerful Diakopto – ParagonX tool. \nCourse Details:-\nDate: Wednesday\, April 17th \, 2024\nTime: 9:00 am to 10:30 am Pacific Time (PDT)\nInstructor: Maxim Ershov\, Senior Director R&D\, USA \nRegister here:- https://ansys.me/3x6p95i\nDon’t miss this opportunity to revolutionize your design workflow and unlock new levels of efficiency and precision. Sign up for the Diakopto ParagonX Training today!
URL:https://marketingeda.com/event/introduction-to-paragonx/
CATEGORIES:EDA,Webinar
ATTACH;FMTTYPE=image/jpeg:https://marketingeda.com/wp-content/uploads/Ansys-April-17-2024.jpg
END:VEVENT
BEGIN:VEVENT
DTSTART;TZID=America/Los_Angeles:20240417T080000
DTEND;TZID=America/Los_Angeles:20240417T090000
DTSTAMP:20240327T173831Z
CREATED:20240327T173831Z
LAST-MODIFIED:20240327T173831Z
UID:7774-1713340800-1713344400@marketingeda.com
SUMMARY:Exploring the Advancement of Chiplet Technology and the Ecosystem
DESCRIPTION:Semiconductor companies are making transistors smaller and cramming more into chips to meet the demands of today’s high-tech industries and applications. In fact\, in a recent article from the Financial Times\, technology industry consultants McKinsey forecast that semiconductors will become a trillion-dollar industry by the end of this decade. Even with this massive growth\, manufacturers recognize the need to balance costs with chip performance and are working to solve this challenge by shifting toward chiplet manufacturing – creating smaller\, modular chiplets\, designed for a specific function\, that can be connected to build a larger system. Chiplets enable design flexibility for end-users seeking to match chip designs based on requirements. \n​ \nUCIe™ (Universal Chiplet Interconnect Express™) provides an industry standard for interface and is driving the adoption of chiplet technology. The open specification defines the interconnect between chiplets within a package\, enabling an open chiplet ecosystem and ubiquitous interconnect at the package level. \nThis webinar aims to explore the industry trends that prompted the development of chiplet technology and how an interoperable solution meets industry demand. Our panelists will also discuss how UCIe fosters collaboration in the industry toward the future of chiplet innovation in markets such as AI\, ML\, aerospace\, and automotive.
URL:https://marketingeda.com/event/exploring-the-advancement-of-chiplet-technology-and-the-ecosystem/
CATEGORIES:IP,Webinar
ATTACH;FMTTYPE=image/jpeg:https://marketingeda.com/wp-content/uploads/UCIe-April-17-2024.jpeg
END:VEVENT
BEGIN:VEVENT
DTSTART;TZID=America/Los_Angeles:20240416T100000
DTEND;TZID=America/Los_Angeles:20240416T110000
DTSTAMP:20240411T185913Z
CREATED:20240411T185913Z
LAST-MODIFIED:20240411T185913Z
UID:7841-1713261600-1713265200@marketingeda.com
SUMMARY:Streamline MMIC Design  Efficiency with Intelligent  Design Data Management
DESCRIPTION:In the fast-evolving world of monolithic microwave integrated circuit (MMIC) design\, meeting higher-frequency requirements is just the beginning. Are you seeking insights on achieving dimensional accuracy for both analog and RF components? Wondering about the automatic synchronization of schematics and layouts across various electronic design automation (EDA) tools? \nTrusted by hundreds of IC design organizations worldwide\, Keysight Design Data Management (SOS) transforms design data chaos into intelligence. Attend to experience a live demonstration showcasing the synergy of Cadence Virtuoso Studio\, Keysight ADS\, and Keysight SOS in action. \nJoin our upcoming webinar for practical insights from Keysight design experts Karim Khalfan and Nupur Bhonge. Learn how to: \n\nSecure and simplify data transfer and design collaboration across the enterprise.\nReduce network storage with smart caching.\nFacilitate efficient co-simulation across Cadence Virtuoso Studio and Keysight ADS with real-time analytics.\nEliminate versioning issues with comprehensive virtualization.\n\n  \nRegister now to streamline your design data management and expedite your MMIC design cycles.  \n\nHandouts\nRequest a personalized demo View/Download\nApply for a free trial View/Download\nBrochure – Keysight Design Data Management SOS View/Download\neBook – Essential IP-Based Design Strategies for Chiplet Success View/Download\n\n\nPresenters\n\nKarim Khalfan\nDirector Solutions Engineering\, Data and IP Management\, at Keysight Technologies.\nKarim leads solutions engineering for data and IP management for Keysight EDA. Before joining Keysight in May 2023 through the acquisition of Cliosoft Inc.\, Karim was Vice President of Applications Engineering managing the Application Engineering group and the office of customer advocacy for the previous 18 years. He has led various efforts to ensure the broad deployment of Keysight design data and IP management across the semiconductor industry. Karim has received his Bachelor of Science degree in Computer Science from the University of Texas. He has authored several articles and white papers on the importance and need of SoC design management solutions. He also has a patent on defining a universal data management adapter to be used for integration with any EDA tool.\n\n\n\nNupur Bhonge\nSenior Solutions Engineer at Keysight Technologies\nNupur works with IC design teams on Keysight Design Data Management (SOS) and IP design (HUB) management platforms. She specializes in deploying EDA workloads to the cloud and new product integrations with SOS and HUB. With a Master’s Degree in Computer Engineering from Syracuse University\, she brings in-depth knowledge and experience with EDA tools and workflows to her work.
URL:https://marketingeda.com/event/streamline-mmic-design-efficiency-with-intelligent-design-data-management/
CATEGORIES:EDA,Webinar
ATTACH;FMTTYPE=image/jpeg:https://marketingeda.com/wp-content/uploads/Keysight-April-16-2024.jpg
END:VEVENT
BEGIN:VEVENT
DTSTART;TZID=America/Los_Angeles:20240416T080000
DTEND;TZID=America/Los_Angeles:20240416T090000
DTSTAMP:20240326T180707Z
CREATED:20240326T180707Z
LAST-MODIFIED:20240326T180707Z
UID:7763-1713254400-1713258000@marketingeda.com
SUMMARY:Win The Tick to Trade Race by Root Causing Bugs Faster with the Latest Innovations In QuestaSim
DESCRIPTION:Root causing RTL design or simulation testbench bugs can be tedious process\, especially if just relying on traditional waveform viewing and debug. Also\, it can be costly if more sophisticated debug ties up precious simulation resources during the debug process.\n‌\nLearn how the latest innovations in QuestaSim address these challenges by enabling full off-line debugging freeing up simulation licenses for more simulations runs per day. Also\, learn how unique debugging features like driver tracing\, biometric search\, temporal causality trace back\, and much more will enable you root cause bugs more straight forward and faster. All the while delivering industry-leading performance and capacity through aggressive\, global compile and simulation optimization algorithms for SystemVerilog\, VHDL\, and SystemC. \nWhat you will learn: \nIn this Web Seminar\, we will highlight the key innovations in QuestaSim that enable full debug visibility with significant reduction in simulation performance overhead and waveform database size. For existing QuestaSim users\, we will show the simple change to scripts to see a 2X performance boost and 3X reduction in waveform database.\n‌\nWe will highlight the debug features in our Visualizer debugger now included as part of every QuestaSim license\, such as:\n‌ \n\nDriver/receiver tracing from wave and source code\n‘x’ tracing through sequential logic and time\nFSM debug & cross probing\nSchematics exploration with smart hierarchical flattening and pruning.\nWaveforms with cross probing & biometric search\nDesign search by type\n\n‌\nWe will step through some design and testbench examples showing how these features can speed up root causing bugs and tackle complex logic that may be impossible for humans to figure out.\n‌ \nWho should attend: \nUltra Low Latency FPGA Designers in the High Frequency Trade industry \n\n\nWhat/Which Products are Covered:   \n\nQuestaSim with Visualizer Debugger\n\n\n\nSpeaker:\n\n\n\n\n\n\nRich Edelman\nProduct Engineer\, Siemens EDA\n\n\n\n\nRich Edelman is a Product Engineer at Siemens EDA and is responsible for the Visualizer Debug Environment. He holds a Bachelor of Science Degree in Electrical Engineering\, a Bachelor of Science Degree in Computer Science\, and a Master of Science Degree in Computer Science from Washington University in St. Louis. Prior to Siemens EDA\, Rich worked for a C Synthesis company\, a compute farm company\, Design Acceleration\, and a couple of ASIC houses. Rich’s best days are in Yosemite backpacking – or at least dreaming about it.
URL:https://marketingeda.com/event/win-the-tick-to-trade-race-by-root-causing-bugs-faster-with-the-latest-innovations-in-questasim/
CATEGORIES:EDA,Webinar
ATTACH;FMTTYPE=image/jpeg:https://marketingeda.com/wp-content/uploads/Siemens-April-16-2024.jpg
END:VEVENT
BEGIN:VEVENT
DTSTART;TZID=America/Los_Angeles:20240411T110000
DTEND;TZID=America/Los_Angeles:20240411T120000
DTSTAMP:20240408T161908Z
CREATED:20240408T161857Z
LAST-MODIFIED:20240408T161908Z
UID:7813-1712833200-1712836800@marketingeda.com
SUMMARY:Making a Structured VHDL Testbench – A Demo for Beginners
DESCRIPTION:Abstract: \nThis demonstrated tutorial is intended for designers and verification engineers who want to learn to make better and more structured testbenches. \nThis session will show you what is needed for any good testbench\, irrespective of its complexity.\nWe will make a testbench from scratch for a simple VHDL module and do the following:\n\nAdd a balanced and controllable clock generator\nAdd logging of progress in a simple way\nCheck default values and reset\nAccess module via an interface – using BFMs (Bus Functional models)\nCheck output signals with and without a positive acknowledge\nWait for flag or interrupt or a given value – with a timeout\nCheck that signals have been stable – without pulses or spikes for a given time\nReport an alert summary\n… and more\n\n…all  using well-documented VHDL procedures and functions from UVVM\, the open source fastest growing VHDL verification methodology.\nThe presented solution will use UVVM Utility Library and BFMs\, but the principles and mechanisms are 100% general verification methodology; i.e.\, independent of library and available functionality.\nAlthough this testbench is applied on a very simple design under test (DUT)\, the same principles also apply to advanced testbenches for complex DUTs. (But the advanced testbenches need more on top.)\nAgenda\n\nQuality and Efficiency Enablers\nThe simple DUT and simple TB architecture\nUVVM: Concepts\, Download and Compile\nMaking the testbench – prior to test cases\nAdding clock generator and starting logging and checking\nBFMs: Explained\, Usage\, Making simple overloads\nAlert handling\, Verbosity control and Timeouts\nConclusion\nQ&A\n\nWebinar Duration\n\n45 min presentation/live demo\n15 min Q&A\n\nPresenter \n \nBio: \nEspen is also the author and architect of UVVM and founder of previous Bitvis. He has a strong interest for methodology cultivation and pragmatic efficiency and quality improvement\, and he has given many presentations on various international conferences with great feedback. He has also given courses on FPGA Design and Verification world-wide.
URL:https://marketingeda.com/event/making-a-structured-vhdl-testbench-a-demo-for-beginners/
CATEGORIES:EDA,Webinar
ATTACH;FMTTYPE=image/jpeg:https://marketingeda.com/wp-content/uploads/Aldec-April-11-2024.jpg
END:VEVENT
BEGIN:VEVENT
DTSTART;TZID=America/Los_Angeles:20240411T100000
DTEND;TZID=America/Los_Angeles:20240411T110000
DTSTAMP:20240314T180820Z
CREATED:20240314T180820Z
LAST-MODIFIED:20240314T180820Z
UID:7736-1712829600-1712833200@marketingeda.com
SUMMARY:Cadence Managed Cloud for Cost Efficient and Productive Chip Design
DESCRIPTION:Join us for an informative webinar\, as we unveil the capabilities of our cloud solutions designed to revolutionize EDA workloads. Whether you require completely hosted environments or need peak/burst capacity\, our cloud solutions offer unparalleled flexibility and efficiency. \nWe will discuss how Cadence Managed Cloud can optimize cost-efficiency and productivity for your chip design projects. Learn how to harness the full potential of cloud technology to streamline your EDA workflows and achieve remarkable results. \nDon’t miss our live demonstration of Cadence Managed Cloud\, where we’ll showcase its robust productivity and security features. Plus\, discover how you can kickstart your journey with a 30-day free trial. \nWho should attend:\nChip designers\, Cloud IT Architects\, CAD Platform team\, and business decision makers. \nPresenters: \nKushal Koolwal\, Business Development Director\, Cadence \nMike Stranton\, IT Group Director\, Cadence
URL:https://marketingeda.com/event/cadence-managed-cloud-for-cost-efficient-and-productive-chip-design/
CATEGORIES:EDA,Webinar
ATTACH;FMTTYPE=image/jpeg:https://marketingeda.com/wp-content/uploads/Cadence-April-11-2024.jpg
END:VEVENT
BEGIN:VEVENT
DTSTART;TZID=America/Los_Angeles:20240410T100000
DTEND;TZID=America/Los_Angeles:20240410T110000
DTSTAMP:20240221T221535Z
CREATED:20240221T221535Z
LAST-MODIFIED:20240221T221535Z
UID:7677-1712743200-1712746800@marketingeda.com
SUMMARY:Virtuoso - Finding Hidden Treasures to Accelerate Routing Your Layout
DESCRIPTION:Every layout designer frets over routing all the interconnects DRC clean and correct as per the circuit designer’s expectations. On the one hand\, you want a magic wand that just hooks up all the connections with perfect smartness. On the other hand\, you need to guide the connections carefully while weaving your own creative magic – too tough to tell the auto-router the exact constraints. With the assisted routing features in your familiar layout editor in Virtuoso Studio\, you have the Swiss army knife to finish your routing tasks more than 10X faster. Finish more work in the same amount of time or regain your work-life balance with the assisted routing functionality. \nThis webinar takes you on a treasure hunt to find the hidden gems – some you already had but didn’t know\, and some that are part of Virtuoso Studio. Strap your seat belts and learn about: \n\nHow simulation-driven routing goes a step ahead than the create-verify-fix paradigm\nReplicate complicated yet similar bus structures with more than just a simple shape copy\n Fast interactive routing with auto twigs feature\nOptimal routing widths in advanced node with WSP compliance\, wire stranding and wire stacking\nAuto Via Assistant\n\nWebinar #1: March 12\nAccelerate Layout Creation with Automated Place and Route in Virtuoso Studio \nWebinar #2: March 19\nSaving on Signoff Effort with iPegasus Verification System for Virtuoso Studio – In-Design DRC and Fill \nWebinar #3: April 4\nMaximizing the Benefits of Virtuoso Layout Suite XL \nWebinar #4: April 10\nFinding Hidden Treasures to Accelerate Routing Your Layout
URL:https://marketingeda.com/event/virtuoso-finding-hidden-treasures-to-accelerate-routing-your-layout/
CATEGORIES:EDA,Webinar
ATTACH;FMTTYPE=image/jpeg:https://marketingeda.com/wp-content/uploads/Cadence-March-2024.jpg
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BEGIN:VEVENT
DTSTART;TZID=America/Los_Angeles:20240409T080000
DTEND;TZID=America/Los_Angeles:20240409T170000
DTSTAMP:20240401T175124Z
CREATED:20240401T175124Z
LAST-MODIFIED:20240401T175124Z
UID:7794-1712649600-1712682000@marketingeda.com
SUMMARY:Ansys 2024 R1: High Frequency Electronics What’s New
DESCRIPTION:Learn about the latest improvements and new features to the high frequency electronics simulation tools. There are many enhancements for engineers involved in RF\, automotive\, A&D\, and consumer electronics designs that our subject matter experts will discuss. \n\n\nOverview\nThis Ansys 2024 R1 webinar will review the high-frequency electronics tool updates\, enhancements\, and new features – HFSS\, Q3D\, SIwave\, and NuHertz. Engineers developing PCBs\, antennas\, and other RF capabilities for telecommunications\, HPC\, automotive\, A&D\, and IoT applications will find many new capabilities and improvements in this update. \nWhat you will learn\n\nEncrypted technology file support in HFSS 3D Layout IC Mode\nEnhanced support for FlexPCB in HFSS 3D\nHFSS Finite Array metadata export and mask automation\nIcepak Thermal Mesh Fusion\nSolver enhancements for SIwave and Q3D\nImprovements to HPC/Distributed Computing support for all products\n\nWho should attend and why\nEngineers involved in new product development for any electronics market \nSpeaker\n\nJuliano Mologni\n\n\n\n\n\nJuliano Mologni is a Lead Product Manager in the Electronics Business Unit at Ansys\, responsible for all HF electronics products. He has over 20 years of experience in computational electromagnetics and is the author of multiple patents and more than 60 journal and conference papers. Juliano is involved in many RF and EMC projects with top automotive\, A&D\, appliances\, and high tech companies. He holds a BSc degree in telecommunication engineering and an MSc in microelectronics and has authored a PhD thesis on automotive EMC and signal integrity.
URL:https://marketingeda.com/event/ansys-2024-r1-high-frequency-electronics-whats-new/
CATEGORIES:EDA,Webinar
ATTACH;FMTTYPE=image/jpeg:https://marketingeda.com/wp-content/uploads/Ansys-April-9-2024.jpg
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BEGIN:VEVENT
DTSTART;TZID=America/Los_Angeles:20240409T080000
DTEND;TZID=America/Los_Angeles:20240409T090000
DTSTAMP:20240402T170530Z
CREATED:20240402T170530Z
LAST-MODIFIED:20240402T170530Z
UID:7803-1712649600-1712653200@marketingeda.com
SUMMARY:Guiding your aerospace electrical journey
DESCRIPTION:Aerospace electrical/electronic (EE) design requires a delicate balance between innovative technology and uncompromising reliability. Meanwhile\, the pressure to get products to market faster is growing exponentially. Finding ways to design electrical systems quickly\, cost-effectively and efficiently has become a central focus of manufacturers. \nSiemens has the solutions and partnerships to guide the development of best-in-class solutions to these problems. This session will highlight how Capital plays a part in these solutions. \nMeet the speaker\n\n\n\n\n\n\nSIEMENS IES\nChad Holley\nTechnical Product Manager \n\nChad Holley is a Technical Product Manager in IES supporting our Connectivity offerings. He has been working for Siemens for over 8 years and has supported many customers in their Capital deployments. Prior to Siemens\, Chad has held varying positions in wiring and systems design in both the automotive and aerospace and defense industries. Chad is a veteran of the United States Navy as an electrician and holds a bachelor’s degree in Electrical Engineering from Michigan State University.
URL:https://marketingeda.com/event/guiding-your-aerospace-electrical-journey/
CATEGORIES:EDA,Webinar
ATTACH;FMTTYPE=image/jpeg:https://marketingeda.com/wp-content/uploads/Siemens-April-9-2024.jpg
END:VEVENT
BEGIN:VEVENT
DTSTART;TZID=America/Los_Angeles:20240404T110000
DTEND;TZID=America/Los_Angeles:20240404T120000
DTSTAMP:20240311T212213Z
CREATED:20240311T212000Z
LAST-MODIFIED:20240311T212213Z
UID:7730-1712228400-1712232000@marketingeda.com
SUMMARY:High-Performance RTL Simulation Workflow with Libero and Active-HDL
DESCRIPTION:Based on recent industry research\, the FPGA market was valued at approximately USD 7.5 Billion in 2023\, with an expected compound annual growth rate (CAGR) of around 10% by 2032. More and more engineers will be adopting FPGAs due to their versatility\, acceleration capability\, power efficiency and lower non-recurring engineering (NRE) costs (compared to ASICs). Major FPGA vendors like AMD\, Altera and Microchip are continuously innovating their technologies\, architectures\, and IPs – and consequently enhancing their respective design capabilities and workflows. For example\, Vivado\, Quartus and Libero all provide useful design and RTL simulation features. Aldec collaborates closely with the FPGA vendors as partners to ensure seamless simulation of all their IPs and libraries using Aldec’s simulation tool\, Active-HDL. \nIn terms of verification\, FPGA designs undergo testing directly in the lab or through simulations\, depending on factors such as design size\, complexity\, and project objectives. While some FPGA designs may find adequate simulation support from the FPGA vendor tools\, many require higher simulation performance and a more comprehensive language support\, particularly those with larger designs with complex logic and deep hierarchies. \nSimulation stands as the primary verification method for FPGA designs\, essential for minimizing non-trivial bugs escaping into production. The ability to run more simulation enables the verification of a wider range of test scenarios\, thus elevating verification quality. Aldec’s Active-HDL offers a faster compilation/simulation engine\, robust debugging features and comprehensive language support for the latest versions of VHDL\, SystemVerilog\, and SystemC. \nIn this three-part webinar series\, we will show how to turbocharge FPGA simulation workflows by using Active-HDL as the default simulator within AMD® Vivado\, Altera® Quartus and Microchip® Libero SoC. \n  \nAbstract: \nIn the concluding part of this three-part webinar series\, we will show how to simulate a Microchip design example. We will generate a design example from Libero SoC and simulate it using Active-HDL as the default simulator. We will discuss various tips that you can use to optimize compilation and simulation run times. The tips will be categorized from zero-cost effort to high-cost effort and\, depending on your budget/resource constraints\, you will have a path to speed up your simulation by a huge factor. We will turn on Profiler so that you can determine the bottlenecks in your design/testbench and we will perform debugging using Breakpoints\, Xtrace\, Drivers/Readers and Advanced Dataflow. \nAgenda\n\nWorkflow with Libero SoC and Active-HDL\nTips on how to optimize simulation performance\nPerformance bottleneck analysis with Design Profiler\nBreakpoints\, Xtrace and Advanced Dataflow\, Drivers and Readers\nLive Demo\nQ&A\n\nWebinar Duration\n\n45 min presentation/live demo\n15 min Q&A\n\nPresenter Bio: \n \nLouie De Luna\, Director of Marketing at Aldec \nLouie De Luna is Aldec’s Director of Marketing with 20+ years’ experience in FPGA/SoC design verification and EDA tools. He currently directs the overall product and technical marketing of Aldec’s design verification solutions. He earned his B.S. in Computer Engineering from University of Nevada\, Las Vegas\, in 2001.  His practical engineering experience includes simulation-based verification\, linting\, CDC analysis\, and hardware-assisted verification.
URL:https://marketingeda.com/event/high-performance-rtl-simulation-workflow-with-libero-and-active-hdl/
CATEGORIES:EDA,Webinar
ATTACH;FMTTYPE=image/jpeg:https://marketingeda.com/wp-content/uploads/Aldec-April-4-2024.jpg
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END:VCALENDAR