BEGIN:VCALENDAR
VERSION:2.0
PRODID:-//Marketing EDA - ECPv6.17.5//NONSGML v1.0//EN
CALSCALE:GREGORIAN
METHOD:PUBLISH
X-ORIGINAL-URL:https://marketingeda.com
X-WR-CALDESC:Events for Marketing EDA
REFRESH-INTERVAL;VALUE=DURATION:PT1H
X-Robots-Tag:noindex
X-PUBLISHED-TTL:PT1H
BEGIN:VTIMEZONE
TZID:America/Los_Angeles
BEGIN:DAYLIGHT
TZOFFSETFROM:-0800
TZOFFSETTO:-0700
TZNAME:PDT
DTSTART:20230312T100000
END:DAYLIGHT
BEGIN:STANDARD
TZOFFSETFROM:-0700
TZOFFSETTO:-0800
TZNAME:PST
DTSTART:20231105T090000
END:STANDARD
BEGIN:DAYLIGHT
TZOFFSETFROM:-0800
TZOFFSETTO:-0700
TZNAME:PDT
DTSTART:20240310T100000
END:DAYLIGHT
BEGIN:STANDARD
TZOFFSETFROM:-0700
TZOFFSETTO:-0800
TZNAME:PST
DTSTART:20241103T090000
END:STANDARD
BEGIN:DAYLIGHT
TZOFFSETFROM:-0800
TZOFFSETTO:-0700
TZNAME:PDT
DTSTART:20250309T100000
END:DAYLIGHT
BEGIN:STANDARD
TZOFFSETFROM:-0700
TZOFFSETTO:-0800
TZNAME:PST
DTSTART:20251102T090000
END:STANDARD
END:VTIMEZONE
BEGIN:VTIMEZONE
TZID:America/New_York
BEGIN:DAYLIGHT
TZOFFSETFROM:-0500
TZOFFSETTO:-0400
TZNAME:EDT
DTSTART:20230312T070000
END:DAYLIGHT
BEGIN:STANDARD
TZOFFSETFROM:-0400
TZOFFSETTO:-0500
TZNAME:EST
DTSTART:20231105T060000
END:STANDARD
BEGIN:DAYLIGHT
TZOFFSETFROM:-0500
TZOFFSETTO:-0400
TZNAME:EDT
DTSTART:20240310T070000
END:DAYLIGHT
BEGIN:STANDARD
TZOFFSETFROM:-0400
TZOFFSETTO:-0500
TZNAME:EST
DTSTART:20241103T060000
END:STANDARD
BEGIN:DAYLIGHT
TZOFFSETFROM:-0500
TZOFFSETTO:-0400
TZNAME:EDT
DTSTART:20250309T070000
END:DAYLIGHT
BEGIN:STANDARD
TZOFFSETFROM:-0400
TZOFFSETTO:-0500
TZNAME:EST
DTSTART:20251102T060000
END:STANDARD
END:VTIMEZONE
BEGIN:VTIMEZONE
TZID:Europe/London
BEGIN:DAYLIGHT
TZOFFSETFROM:+0000
TZOFFSETTO:+0100
TZNAME:BST
DTSTART:20230326T010000
END:DAYLIGHT
BEGIN:STANDARD
TZOFFSETFROM:+0100
TZOFFSETTO:+0000
TZNAME:GMT
DTSTART:20231029T010000
END:STANDARD
BEGIN:DAYLIGHT
TZOFFSETFROM:+0000
TZOFFSETTO:+0100
TZNAME:BST
DTSTART:20240331T010000
END:DAYLIGHT
BEGIN:STANDARD
TZOFFSETFROM:+0100
TZOFFSETTO:+0000
TZNAME:GMT
DTSTART:20241027T010000
END:STANDARD
BEGIN:DAYLIGHT
TZOFFSETFROM:+0000
TZOFFSETTO:+0100
TZNAME:BST
DTSTART:20250330T010000
END:DAYLIGHT
BEGIN:STANDARD
TZOFFSETFROM:+0100
TZOFFSETTO:+0000
TZNAME:GMT
DTSTART:20251026T010000
END:STANDARD
END:VTIMEZONE
BEGIN:VTIMEZONE
TZID:Asia/Tokyo
BEGIN:STANDARD
TZOFFSETFROM:+0900
TZOFFSETTO:+0900
TZNAME:JST
DTSTART:20230101T000000
END:STANDARD
END:VTIMEZONE
BEGIN:VEVENT
DTSTART;TZID=America/Los_Angeles:20240502T090000
DTEND;TZID=America/Los_Angeles:20240502T100000
DTSTAMP:20240422T161648Z
CREATED:20240422T161648Z
LAST-MODIFIED:20240422T161648Z
UID:7886-1714640400-1714644000@marketingeda.com
SUMMARY:Smart methods for DFT chip architecture & validation
DESCRIPTION:Combining market-leading design-for-test (DFT) technologies with best-in-class netlist synthesis allows you to achieve DFT success more quickly. Many customers\, including those for emulation and IC test\, have challenges with scaling architectures. This webinar describes how Siemens emulation and silicon test solutions can work together to provide a smart DFT plug-and-play architecture for Veloce ICs. \nThe Veloce hardware-assisted verification system can efficiently handle large\, full-chip GLE designs. Tessent Streaming Scan Network (SSN)\, a once-in-a-decade technology\, packetizes test data to dramatically reduce DFT implementation effort and reduce manufacturing test cost. The Veloce DFT application enables SSN\, as well as other test functions such as TestKompress\, BIST pattern validation\, functional fault grading\, power profiling and estimation\, by accelerating multiple orders of magnitude faster than traditional software simulation. Combining Veloce Strato and Tessent SSN can accelerate your time to DFT success. \nTarget audience: \n\nDFT Engineers\nDFT Managers\nProduct and Test Engineers and Managers\n\nWhat you will learn: \n\nIntroduction to Veloce DFT App and how it helps validate Tessent DFT logic/patterns\nDFT Power Profiling and Fault grading using Veloce Power App\nApplying SSN to solve the Veloce chip design challenges\n\n\n\nSpeakers:\n\n\n\n\n\n\nRobert Serphillips\nProduct Manager\, Verification\, Siemens EDA\n\n\n\n\nRobert Serphillips has worked in the pre-silicon verification\, post-silicon validation\, and production design-for-test (DFT) fields. He has designed and debugged ATE test patterns on multiple stand alone and SoC devices spanning close to 20 years in the semiconductor industry. The products include a mix of consumer\, automotive\, industrial\, military\, networking and mixed signal. Robert is currently a product manager with the Siemens EDA hardware-assisted verification business unit. \n\n\n\n\n\n\n\nRon Press\nSr. Director of Technology Enablement\, Tessent\, Siemens EDA – Tessent\n\n\n\n\nRon Press\, a 30-year veteran of the test and DFT industry\, is a member of the International Test Conference (ITC) Steering Committee\, a Golden Core member of the IEEE Computer Society and a Senior Member of IEEE. Ron has patents on reduced-pin-count testing\, glitch-free clock switching and on 3D DFT. He started his work in the test industry at Raytheon Company working on test and consulting throughout the company on test and built-in test. He co-developed the Testability Design Rating System (TDRS) for the US Air Force and received the Raytheon inventor’s award for a built-in test analysis system. Ron led the development of a state-of-the-art RF/digital tester at Harris RF starting in 1995.
URL:https://marketingeda.com/event/smart-methods-for-dft-chip-architecture-validation/
CATEGORIES:EDA,Webinar
ATTACH;FMTTYPE=image/jpeg:https://marketingeda.com/wp-content/uploads/Siemens-May-2-2024.jpg
END:VEVENT
BEGIN:VEVENT
DTSTART;TZID=America/Los_Angeles:20240430T060000
DTEND;TZID=America/Los_Angeles:20240430T070000
DTSTAMP:20240416T003939Z
CREATED:20240416T003939Z
LAST-MODIFIED:20240416T003939Z
UID:7858-1714456800-1714460400@marketingeda.com
SUMMARY:DFT for chiplets & 3D ICs using Tessent Multi-die
DESCRIPTION:3D IC (2.5D/3D) designs are on the rise. Design for Test (DFT) for chiplets must be general purpose so they can be tested stand alone and easy to test after assembly into 2.5D or 3D devices. In this webinar you will learn how to use Tessent Multi-die and still adhere to standards like IEEE 1149.1\, IEEE 1500\, IEEE 1687\, and IEEE 1838. \nWho should attend:\n\nAnyone planning to implement chiplets\, 2.5D/3D designs and would like to learn about design for test.\nDFT Engineers\nDFT Managers\nDesign Engineers\nTest Engineers\nProject Managers for ASIC/design\n\nWhat you will learn:\n\nHow Tessent Multi-die will aid in 3D IC design for test\nIntro to what IEEE 1838 standard is and how Tessent solution can be used. Use of Tessent Streaming Scan Network (SSN) as flexible parallel port (FPP)\nHow in 2.5D device\, boundary scan-based interconnect test can be performed with Tessent Multi-die\n\n\n\nSpeaker:\n\n\n\n\n\n\nItamar Tsachi\nEurope DFT Manager\, Siemens EDA\n\n\n\n\nItamar Tsachi has more than 20 years of experience in the semiconductor industry and has collaborated with many local and international Siemens EDA customers on a wide range of solutions targeting DFT and RTL->GDSII flows. Before joining Mentor Graphics\, Itamar ramped up IBM’s Physical Design Group in Israel developing SoCs using IBM’s leading-edge technology. Itamar was also a Physical Implementation Consultant and Leader at multiple startups like Mysticom\, BrightCom technologies and Silicon Value\, where he began his chip design career in a variety of roles\, from Digital / Analog layout design to Place & Route and CAD development. Itamar holds one Patent” Placement Driving Routing (PDR) – “A method and apparatus for placement driven routing with a minimum number of changes in the placement.”
URL:https://marketingeda.com/event/dft-for-chiplets-3d-ics-using-tessent-multi-die/
CATEGORIES:EDA,Webinar
ATTACH;FMTTYPE=image/jpeg:https://marketingeda.com/wp-content/uploads/Siemens-April-30-2024.jpg
END:VEVENT
BEGIN:VEVENT
DTSTART;TZID=America/New_York:20240425T110000
DTEND;TZID=America/New_York:20240425T120000
DTSTAMP:20240401T181039Z
CREATED:20240401T181039Z
LAST-MODIFIED:20240401T181039Z
UID:7800-1714042800-1714046400@marketingeda.com
SUMMARY:Improving Semiconductor Wafer Fabrication Process Efficiencies Using Ansys Solutions
DESCRIPTION:Ansys Semiconductor Manufacturing Webinar Series: Part 1 of 3. \nJoin us on Thursday\, April 25th for an in-depth view of multi-physics simulation in the semiconductor fabrication process. \nOverview\nAccurate design and optimization of the semiconductor fabrication process/equipment for yield improvements and faster time-to-market require multiphysics simulation\, which can address various physical interactions and phenomena. By encompassing factors from contamination challenges to ensuring uniform product outcomes\, engineers can leverage such simulations to generate innovative ideas for optimized processes and cutting-edge solutions in semiconductor fabrication. \nThis webinar will demonstrate the practical application of Ansys tools in understanding the impact of various parameters on diverse wafer fabrication processes and fine-tuning them to improve yields and reduce wafer cycle time. \nWhat you will learn\n\nImportance of simulation in fabrication processes\nReduce wafer cycle time\nModel fabrication process with Ansys tools\nOptimize of fabrication processes\nSystem-level modeling of fabrication processes\n\nWho should attend\nEngineers and Engineering Managers/Directors\, Manufacturing teams\, Etch teams\, Deposition teams\, NPI teams and Aftermarket teams \nSpeaker\n\nNima Bohlooli\, Senior Application Engineer\, Ansys
URL:https://marketingeda.com/event/improving-semiconductor-wafer-fabrication-process-efficiencies-using-ansys-solutions/
CATEGORIES:EDA,Semiconductor,Webinar
ATTACH;FMTTYPE=image/jpeg:https://marketingeda.com/wp-content/uploads/April-25-2024-Ansys.jpg
END:VEVENT
BEGIN:VEVENT
DTSTART;TZID=America/New_York:20240425T090000
DTEND;TZID=America/New_York:20240425T100000
DTSTAMP:20240401T180250Z
CREATED:20240401T180042Z
LAST-MODIFIED:20240401T180250Z
UID:7797-1714035600-1714039200@marketingeda.com
SUMMARY:The Era of Software-Defined Everything: Chiplets and Bespoke Silicon
DESCRIPTION:From fintech to automotive\, defense to healthcare\, everyone wants bespoke computing platforms to build “software-defined solutions” that are differentiated in their respective markets. Sign up and save your spot for this special presentation. \nOverview\nWith the advent of 3D ICs and heterogeneous semiconductor integration\, mapping a system on a customized chip/hardware is accessible to “everyone.” \nThe semiconductor suppliers are gearing themselves for the change\, and\, as Jensen Huang (NVIDIA CEO) was recently quoted\, “2024 is the year where every industry is becoming a high-tech industry.” \nFrom fintech to automotive\, defense to healthcare\, everyone wants bespoke computing platforms to build “software-defined solutions” that are differentiated in their respective markets. \nBut this (r)evolution faces a multitude of challenges\, such as \n\nIs the workforce (engineering community at large) ready for this massive deployment of semiconductor technologies?\nAre the design methodologies\, both semiconductor and system\, ready and enabling?\nWhat is the level of over-engineering that drives this sequence?\n\nWhat you will learn\n\nHow to harness 3D-IC and chiplets to accelerate the transition to software-defined everything\nHow chiplets can give your business a competitive edge\nWhat is the best use of AI for the transition?\n\nWho should attend and why\nIf you are responsible for an engineering department or in charge of NPI and Product Development /Strategy\, sign up for this online webinar. \nSpeaker\n\nChief Technologist Christopher Bianchi
URL:https://marketingeda.com/event/the-era-of-software-defined-everything-chiplets-and-bespoke-silicon/
CATEGORIES:EDA,IP,Webinar
ATTACH;FMTTYPE=image/jpeg:https://marketingeda.com/wp-content/uploads/Ansys-April-25-2024.jpg
END:VEVENT
BEGIN:VEVENT
DTSTART;TZID=America/Los_Angeles:20240424T080000
DTEND;TZID=America/Los_Angeles:20240424T090000
DTSTAMP:20240416T183848Z
CREATED:20240416T183848Z
LAST-MODIFIED:20240416T183848Z
UID:7863-1713945600-1713949200@marketingeda.com
SUMMARY:Deploying Solido Design Environment AI Workflows on AWS
DESCRIPTION:Utilizing AWS cloud resources to accelerate variation-aware verification   \n\nAI-powered Solido Design Environment provides SPICE-accurate variation-aware verification for 3\, 4\, 5\, 6 and higher sigma targets\, orders of magnitude faster than traditional brute-force methods. With cloud computing made more accessible than before\, many teams are considering running design and verification workloads\, including Solido Design Environment\, on the cloud. \nSiemens and AWS’ strategic collaboration enables a Siemens EDA portfolio that is even more accessible\, scalable\, flexible\, and secure on AWS. Today\, Solido Design Environment users can leverage the power of AWS cloud computing to manage and deploy SPICE-level verification\, resulting in accelerated verification schedules and significantly higher capacity for peak workload demands. \nIn this Masterclass webinar\, co-presented by Siemens EDA and AWS\, we explore best practices and resources available for deploying Solido Design Environment on AWS. Join us and learn more about AWS’ solutions for SPICE-level verification\, tried-and-tested cloud configurations for Solido Design Environment\, and a Q&A session with Siemens and AWS experts to get started confidently and leverage AWS compute to maximize verification throughput and address peak demand on Solido Design Environment. \nTopic Include:\n– The need for cloud scalability for  semiconductor design\n– Solido Design Environment overview\n– Best practices and considerations\n– AWS capabilities for SPICE verification\, including example cloud configuration\n– Resources available for teams deploying to AWS cloud\n– Interactive Q&A \nFeatured Products:  Solido Design Environment\, AWS Cloud Platform \nSpeakers:\n\n\n\n\nWei-Lii Tan\nDirector of Product Management\, Siemens EDA\n\n\nWei-Lii Tan is Director of Product Management in Siemens DISW’s Custom IC Verification division for Solido’s AI-enabled verification & characterization\, and IP validation product lines. Wei-Lii has 15 years of experience in semiconductor and EDA\, having worked on both digital and analog methodologies. He has a master’s degree in electrical engineering from Mississippi State University\, and an M.B.A. from Santa Clara University. \n\nAzim Siddique\nSenior Solutions Architect\, Amazon Web Services\n\n\nAzim works with AWS Enterprise customers on their Cloud adoption journey. Azim has 20+ years of experience working at large global organizations in the manufacturing and industrials domain\, architecting and delivering innovative solutions at scale to generate business value. Azim is passionate about being part of transformational changes driven by technological innovation.
URL:https://marketingeda.com/event/deploying-solido-design-environment-ai-workflows-on-aws/
CATEGORIES:EDA,Webinar
ATTACH;FMTTYPE=image/jpeg:https://marketingeda.com/wp-content/uploads/Siemens-April-24-2024.jpg
END:VEVENT
BEGIN:VEVENT
DTSTART;TZID=Europe/London:20240423T120000
DTEND;TZID=Europe/London:20240423T130000
DTSTAMP:20240410T161505Z
CREATED:20240410T161505Z
LAST-MODIFIED:20240410T161505Z
UID:7823-1713873600-1713877200@marketingeda.com
SUMMARY:DVClub Europe - Formal Verification
DESCRIPTION:13 days to go the next DVClub Europe meeting takes place on Tuesday 23rd April with a theme of “Formal Verification“.\n\nFormal Verification can help you find bugs earlier in the design cycle and accelerate root cause analysis. But success with Formal requires the effective selection and implementation of the right formal technologies and methods. In this DVClub meeting our speakers will share their experiences adopting Formal Verification and then open the floor for discussion followed by the usual networking opportunities.\n\nAgenda (BST) \n12:00   Welcome and Introduction – Mike Bartley\, Tessolve\n12:00 Brajmohan Sharma\, Marvel Technology – Advanced Formal Verification and Robust Regression Strategies for Highly Parameterized Designs\n12:20 Easwaran Krishnan & Savita Suresh Lohar\, Tessolve Semiconductor\n12:40 Gayatri Padhy\, Object Automation – Formal Verification with AI/ML\n13:00 Cadence Design System\n13:15 Neena Chandawale \,Agnisys\n13:30 Close \nRegister now to become a part of this event. Free to attend online. \nTicket Tailor- DVClub Europe 
URL:https://marketingeda.com/event/dvclub-europe-formal-verification/
CATEGORIES:EDA,Webinar
ATTACH;FMTTYPE=image/jpeg:https://marketingeda.com/wp-content/uploads/DVClub-Europe-23-April-2024.jpg
END:VEVENT
BEGIN:VEVENT
DTSTART;TZID=Asia/Tokyo:20240418T150000
DTEND;TZID=Asia/Tokyo:20240418T160000
DTSTAMP:20240415T174855Z
CREATED:20240415T174855Z
LAST-MODIFIED:20240415T174855Z
UID:7844-1713452400-1713456000@marketingeda.com
SUMMARY:Optimizing Chiplet architectures of RISC-V clusters\, GPU and DNN using System-Level IP
DESCRIPTION:Multi-die SoC containing multiple RISC-V clusters\, GPU\, NPU\, accelerators and DNN have considerable benefits for applications in automotive\, space and industrial. Architecture exploration of the chiplet-based SoC requires multiple interconnect protocol models\, and multiple coherent and non-coherent compute resources. This Webinar will demonstrate a methodology for rapid modeling and architecture trade-off using UCIe in modeling and simulating a multi-die SoC in a matter of weeks. These models can be used for UCIe setup\, task partitioning\, distribution of compute resources across dies\, sharing coherency between RISC-V clusters\, GPU and AI Engines. We will show how workloads and application task graphs can be used to optimize the settings to meet the requirements\, identify system bottlenecks and optimize for PPA. Results from actual hardware designs with different configurations and allocations will be discussed during the session.
URL:https://marketingeda.com/event/optimizing-chiplet-architectures-of-risc-v-clusters-gpu-and-dnn-using-system-level-ip/
CATEGORIES:EDA,IP,Webinar
ATTACH;FMTTYPE=image/jpeg:https://marketingeda.com/wp-content/uploads/Mirabilis-18-April-2024.jpg
END:VEVENT
BEGIN:VEVENT
DTSTART;TZID=America/Los_Angeles:20240418T100000
DTEND;TZID=America/Los_Angeles:20240418T110000
DTSTAMP:20240415T175505Z
CREATED:20240415T175505Z
LAST-MODIFIED:20240415T175505Z
UID:7847-1713434400-1713438000@marketingeda.com
SUMMARY:Optimizing Chiplet architectures of RISC-V clusters\, GPU and DNN using System-Level IP
DESCRIPTION:Multi-die SoC containing multiple RISC-V clusters\, GPU\, NPU\, accelerators and DNN have considerable benefits for applications in automotive\, space and industrial. Architecture exploration of the chiplet-based SoC requires multiple interconnect protocol models\, and multiple coherent and non-coherent compute resources. This Webinar will demonstrate a methodology for rapid modeling and architecture trade-off using UCIe in modeling and simulating a multi-die SoC in a matter of weeks. These models can be used for UCIe setup\, task partitioning\, distribution of compute resources across dies\, sharing coherency between RISC-V clusters\, GPU and AI Engines. We will show how workloads and application task graphs can be used to optimize the settings to meet the requirements\, identify system bottlenecks and optimize for PPA. Results from actual hardware designs with different configurations and allocations will be discussed during the session.
URL:https://marketingeda.com/event/optimizing-chiplet-architectures-of-risc-v-clusters-gpu-and-dnn-using-system-level-ip-2/
CATEGORIES:EDA,IP,Webinar
ATTACH;FMTTYPE=image/jpeg:https://marketingeda.com/wp-content/uploads/Mirabilis-April-18-2024.jpg
END:VEVENT
BEGIN:VEVENT
DTSTART;TZID=America/Los_Angeles:20240417T090000
DTEND;TZID=America/Los_Angeles:20240417T103000
DTSTAMP:20240415T184123Z
CREATED:20240415T184123Z
LAST-MODIFIED:20240415T184123Z
UID:7855-1713344400-1713349800@marketingeda.com
SUMMARY:Introduction to ParagonX
DESCRIPTION:Are you ready to supercharge your design process? Introducing our Diakopto Training Program – your gateway to a faster\, easier\, and more intuitive approach to design analysis and optimization! \nIn this course\, you’ll learn how to:\n Analyze and visualize layout parasitics with precision using R/C/delay/I maps.\n Perform net matching for accurate and refined designs.\n Identify the root cause of bottlenecks in post-layout simulation results with ease.\n Iterate over layout improvements efficiently before running post-layout simulations using the powerful Diakopto – ParagonX tool. \nCourse Details:-\nDate: Wednesday\, April 17th \, 2024\nTime: 9:00 am to 10:30 am Pacific Time (PDT)\nInstructor: Maxim Ershov\, Senior Director R&D\, USA \nRegister here:- https://ansys.me/3x6p95i\nDon’t miss this opportunity to revolutionize your design workflow and unlock new levels of efficiency and precision. Sign up for the Diakopto ParagonX Training today!
URL:https://marketingeda.com/event/introduction-to-paragonx/
CATEGORIES:EDA,Webinar
ATTACH;FMTTYPE=image/jpeg:https://marketingeda.com/wp-content/uploads/Ansys-April-17-2024.jpg
END:VEVENT
BEGIN:VEVENT
DTSTART;TZID=America/Los_Angeles:20240417T080000
DTEND;TZID=America/Los_Angeles:20240417T090000
DTSTAMP:20240327T173831Z
CREATED:20240327T173831Z
LAST-MODIFIED:20240327T173831Z
UID:7774-1713340800-1713344400@marketingeda.com
SUMMARY:Exploring the Advancement of Chiplet Technology and the Ecosystem
DESCRIPTION:Semiconductor companies are making transistors smaller and cramming more into chips to meet the demands of today’s high-tech industries and applications. In fact\, in a recent article from the Financial Times\, technology industry consultants McKinsey forecast that semiconductors will become a trillion-dollar industry by the end of this decade. Even with this massive growth\, manufacturers recognize the need to balance costs with chip performance and are working to solve this challenge by shifting toward chiplet manufacturing – creating smaller\, modular chiplets\, designed for a specific function\, that can be connected to build a larger system. Chiplets enable design flexibility for end-users seeking to match chip designs based on requirements. \n​ \nUCIe™ (Universal Chiplet Interconnect Express™) provides an industry standard for interface and is driving the adoption of chiplet technology. The open specification defines the interconnect between chiplets within a package\, enabling an open chiplet ecosystem and ubiquitous interconnect at the package level. \nThis webinar aims to explore the industry trends that prompted the development of chiplet technology and how an interoperable solution meets industry demand. Our panelists will also discuss how UCIe fosters collaboration in the industry toward the future of chiplet innovation in markets such as AI\, ML\, aerospace\, and automotive.
URL:https://marketingeda.com/event/exploring-the-advancement-of-chiplet-technology-and-the-ecosystem/
CATEGORIES:IP,Webinar
ATTACH;FMTTYPE=image/jpeg:https://marketingeda.com/wp-content/uploads/UCIe-April-17-2024.jpeg
END:VEVENT
BEGIN:VEVENT
DTSTART;TZID=America/Los_Angeles:20240416T100000
DTEND;TZID=America/Los_Angeles:20240416T110000
DTSTAMP:20240411T185913Z
CREATED:20240411T185913Z
LAST-MODIFIED:20240411T185913Z
UID:7841-1713261600-1713265200@marketingeda.com
SUMMARY:Streamline MMIC Design  Efficiency with Intelligent  Design Data Management
DESCRIPTION:In the fast-evolving world of monolithic microwave integrated circuit (MMIC) design\, meeting higher-frequency requirements is just the beginning. Are you seeking insights on achieving dimensional accuracy for both analog and RF components? Wondering about the automatic synchronization of schematics and layouts across various electronic design automation (EDA) tools? \nTrusted by hundreds of IC design organizations worldwide\, Keysight Design Data Management (SOS) transforms design data chaos into intelligence. Attend to experience a live demonstration showcasing the synergy of Cadence Virtuoso Studio\, Keysight ADS\, and Keysight SOS in action. \nJoin our upcoming webinar for practical insights from Keysight design experts Karim Khalfan and Nupur Bhonge. Learn how to: \n\nSecure and simplify data transfer and design collaboration across the enterprise.\nReduce network storage with smart caching.\nFacilitate efficient co-simulation across Cadence Virtuoso Studio and Keysight ADS with real-time analytics.\nEliminate versioning issues with comprehensive virtualization.\n\n  \nRegister now to streamline your design data management and expedite your MMIC design cycles.  \n\nHandouts\nRequest a personalized demo View/Download\nApply for a free trial View/Download\nBrochure – Keysight Design Data Management SOS View/Download\neBook – Essential IP-Based Design Strategies for Chiplet Success View/Download\n\n\nPresenters\n\nKarim Khalfan\nDirector Solutions Engineering\, Data and IP Management\, at Keysight Technologies.\nKarim leads solutions engineering for data and IP management for Keysight EDA. Before joining Keysight in May 2023 through the acquisition of Cliosoft Inc.\, Karim was Vice President of Applications Engineering managing the Application Engineering group and the office of customer advocacy for the previous 18 years. He has led various efforts to ensure the broad deployment of Keysight design data and IP management across the semiconductor industry. Karim has received his Bachelor of Science degree in Computer Science from the University of Texas. He has authored several articles and white papers on the importance and need of SoC design management solutions. He also has a patent on defining a universal data management adapter to be used for integration with any EDA tool.\n\n\n\nNupur Bhonge\nSenior Solutions Engineer at Keysight Technologies\nNupur works with IC design teams on Keysight Design Data Management (SOS) and IP design (HUB) management platforms. She specializes in deploying EDA workloads to the cloud and new product integrations with SOS and HUB. With a Master’s Degree in Computer Engineering from Syracuse University\, she brings in-depth knowledge and experience with EDA tools and workflows to her work.
URL:https://marketingeda.com/event/streamline-mmic-design-efficiency-with-intelligent-design-data-management/
CATEGORIES:EDA,Webinar
ATTACH;FMTTYPE=image/jpeg:https://marketingeda.com/wp-content/uploads/Keysight-April-16-2024.jpg
END:VEVENT
BEGIN:VEVENT
DTSTART;TZID=America/Los_Angeles:20240416T080000
DTEND;TZID=America/Los_Angeles:20240416T090000
DTSTAMP:20240326T180707Z
CREATED:20240326T180707Z
LAST-MODIFIED:20240326T180707Z
UID:7763-1713254400-1713258000@marketingeda.com
SUMMARY:Win The Tick to Trade Race by Root Causing Bugs Faster with the Latest Innovations In QuestaSim
DESCRIPTION:Root causing RTL design or simulation testbench bugs can be tedious process\, especially if just relying on traditional waveform viewing and debug. Also\, it can be costly if more sophisticated debug ties up precious simulation resources during the debug process.\n‌\nLearn how the latest innovations in QuestaSim address these challenges by enabling full off-line debugging freeing up simulation licenses for more simulations runs per day. Also\, learn how unique debugging features like driver tracing\, biometric search\, temporal causality trace back\, and much more will enable you root cause bugs more straight forward and faster. All the while delivering industry-leading performance and capacity through aggressive\, global compile and simulation optimization algorithms for SystemVerilog\, VHDL\, and SystemC. \nWhat you will learn: \nIn this Web Seminar\, we will highlight the key innovations in QuestaSim that enable full debug visibility with significant reduction in simulation performance overhead and waveform database size. For existing QuestaSim users\, we will show the simple change to scripts to see a 2X performance boost and 3X reduction in waveform database.\n‌\nWe will highlight the debug features in our Visualizer debugger now included as part of every QuestaSim license\, such as:\n‌ \n\nDriver/receiver tracing from wave and source code\n‘x’ tracing through sequential logic and time\nFSM debug & cross probing\nSchematics exploration with smart hierarchical flattening and pruning.\nWaveforms with cross probing & biometric search\nDesign search by type\n\n‌\nWe will step through some design and testbench examples showing how these features can speed up root causing bugs and tackle complex logic that may be impossible for humans to figure out.\n‌ \nWho should attend: \nUltra Low Latency FPGA Designers in the High Frequency Trade industry \n\n\nWhat/Which Products are Covered:   \n\nQuestaSim with Visualizer Debugger\n\n\n\nSpeaker:\n\n\n\n\n\n\nRich Edelman\nProduct Engineer\, Siemens EDA\n\n\n\n\nRich Edelman is a Product Engineer at Siemens EDA and is responsible for the Visualizer Debug Environment. He holds a Bachelor of Science Degree in Electrical Engineering\, a Bachelor of Science Degree in Computer Science\, and a Master of Science Degree in Computer Science from Washington University in St. Louis. Prior to Siemens EDA\, Rich worked for a C Synthesis company\, a compute farm company\, Design Acceleration\, and a couple of ASIC houses. Rich’s best days are in Yosemite backpacking – or at least dreaming about it.
URL:https://marketingeda.com/event/win-the-tick-to-trade-race-by-root-causing-bugs-faster-with-the-latest-innovations-in-questasim/
CATEGORIES:EDA,Webinar
ATTACH;FMTTYPE=image/jpeg:https://marketingeda.com/wp-content/uploads/Siemens-April-16-2024.jpg
END:VEVENT
BEGIN:VEVENT
DTSTART;TZID=America/Los_Angeles:20240411T110000
DTEND;TZID=America/Los_Angeles:20240411T120000
DTSTAMP:20240408T161908Z
CREATED:20240408T161857Z
LAST-MODIFIED:20240408T161908Z
UID:7813-1712833200-1712836800@marketingeda.com
SUMMARY:Making a Structured VHDL Testbench – A Demo for Beginners
DESCRIPTION:Abstract: \nThis demonstrated tutorial is intended for designers and verification engineers who want to learn to make better and more structured testbenches. \nThis session will show you what is needed for any good testbench\, irrespective of its complexity.\nWe will make a testbench from scratch for a simple VHDL module and do the following:\n\nAdd a balanced and controllable clock generator\nAdd logging of progress in a simple way\nCheck default values and reset\nAccess module via an interface – using BFMs (Bus Functional models)\nCheck output signals with and without a positive acknowledge\nWait for flag or interrupt or a given value – with a timeout\nCheck that signals have been stable – without pulses or spikes for a given time\nReport an alert summary\n… and more\n\n…all  using well-documented VHDL procedures and functions from UVVM\, the open source fastest growing VHDL verification methodology.\nThe presented solution will use UVVM Utility Library and BFMs\, but the principles and mechanisms are 100% general verification methodology; i.e.\, independent of library and available functionality.\nAlthough this testbench is applied on a very simple design under test (DUT)\, the same principles also apply to advanced testbenches for complex DUTs. (But the advanced testbenches need more on top.)\nAgenda\n\nQuality and Efficiency Enablers\nThe simple DUT and simple TB architecture\nUVVM: Concepts\, Download and Compile\nMaking the testbench – prior to test cases\nAdding clock generator and starting logging and checking\nBFMs: Explained\, Usage\, Making simple overloads\nAlert handling\, Verbosity control and Timeouts\nConclusion\nQ&A\n\nWebinar Duration\n\n45 min presentation/live demo\n15 min Q&A\n\nPresenter \n \nBio: \nEspen is also the author and architect of UVVM and founder of previous Bitvis. He has a strong interest for methodology cultivation and pragmatic efficiency and quality improvement\, and he has given many presentations on various international conferences with great feedback. He has also given courses on FPGA Design and Verification world-wide.
URL:https://marketingeda.com/event/making-a-structured-vhdl-testbench-a-demo-for-beginners/
CATEGORIES:EDA,Webinar
ATTACH;FMTTYPE=image/jpeg:https://marketingeda.com/wp-content/uploads/Aldec-April-11-2024.jpg
END:VEVENT
BEGIN:VEVENT
DTSTART;TZID=America/Los_Angeles:20240411T100000
DTEND;TZID=America/Los_Angeles:20240411T110000
DTSTAMP:20240314T180820Z
CREATED:20240314T180820Z
LAST-MODIFIED:20240314T180820Z
UID:7736-1712829600-1712833200@marketingeda.com
SUMMARY:Cadence Managed Cloud for Cost Efficient and Productive Chip Design
DESCRIPTION:Join us for an informative webinar\, as we unveil the capabilities of our cloud solutions designed to revolutionize EDA workloads. Whether you require completely hosted environments or need peak/burst capacity\, our cloud solutions offer unparalleled flexibility and efficiency. \nWe will discuss how Cadence Managed Cloud can optimize cost-efficiency and productivity for your chip design projects. Learn how to harness the full potential of cloud technology to streamline your EDA workflows and achieve remarkable results. \nDon’t miss our live demonstration of Cadence Managed Cloud\, where we’ll showcase its robust productivity and security features. Plus\, discover how you can kickstart your journey with a 30-day free trial. \nWho should attend:\nChip designers\, Cloud IT Architects\, CAD Platform team\, and business decision makers. \nPresenters: \nKushal Koolwal\, Business Development Director\, Cadence \nMike Stranton\, IT Group Director\, Cadence
URL:https://marketingeda.com/event/cadence-managed-cloud-for-cost-efficient-and-productive-chip-design/
CATEGORIES:EDA,Webinar
ATTACH;FMTTYPE=image/jpeg:https://marketingeda.com/wp-content/uploads/Cadence-April-11-2024.jpg
END:VEVENT
BEGIN:VEVENT
DTSTART;TZID=America/Los_Angeles:20240410T100000
DTEND;TZID=America/Los_Angeles:20240410T110000
DTSTAMP:20240221T221535Z
CREATED:20240221T221535Z
LAST-MODIFIED:20240221T221535Z
UID:7677-1712743200-1712746800@marketingeda.com
SUMMARY:Virtuoso - Finding Hidden Treasures to Accelerate Routing Your Layout
DESCRIPTION:Every layout designer frets over routing all the interconnects DRC clean and correct as per the circuit designer’s expectations. On the one hand\, you want a magic wand that just hooks up all the connections with perfect smartness. On the other hand\, you need to guide the connections carefully while weaving your own creative magic – too tough to tell the auto-router the exact constraints. With the assisted routing features in your familiar layout editor in Virtuoso Studio\, you have the Swiss army knife to finish your routing tasks more than 10X faster. Finish more work in the same amount of time or regain your work-life balance with the assisted routing functionality. \nThis webinar takes you on a treasure hunt to find the hidden gems – some you already had but didn’t know\, and some that are part of Virtuoso Studio. Strap your seat belts and learn about: \n\nHow simulation-driven routing goes a step ahead than the create-verify-fix paradigm\nReplicate complicated yet similar bus structures with more than just a simple shape copy\n Fast interactive routing with auto twigs feature\nOptimal routing widths in advanced node with WSP compliance\, wire stranding and wire stacking\nAuto Via Assistant\n\nWebinar #1: March 12\nAccelerate Layout Creation with Automated Place and Route in Virtuoso Studio \nWebinar #2: March 19\nSaving on Signoff Effort with iPegasus Verification System for Virtuoso Studio – In-Design DRC and Fill \nWebinar #3: April 4\nMaximizing the Benefits of Virtuoso Layout Suite XL \nWebinar #4: April 10\nFinding Hidden Treasures to Accelerate Routing Your Layout
URL:https://marketingeda.com/event/virtuoso-finding-hidden-treasures-to-accelerate-routing-your-layout/
CATEGORIES:EDA,Webinar
ATTACH;FMTTYPE=image/jpeg:https://marketingeda.com/wp-content/uploads/Cadence-March-2024.jpg
END:VEVENT
BEGIN:VEVENT
DTSTART;TZID=America/Los_Angeles:20240409T080000
DTEND;TZID=America/Los_Angeles:20240409T170000
DTSTAMP:20240401T175124Z
CREATED:20240401T175124Z
LAST-MODIFIED:20240401T175124Z
UID:7794-1712649600-1712682000@marketingeda.com
SUMMARY:Ansys 2024 R1: High Frequency Electronics What’s New
DESCRIPTION:Learn about the latest improvements and new features to the high frequency electronics simulation tools. There are many enhancements for engineers involved in RF\, automotive\, A&D\, and consumer electronics designs that our subject matter experts will discuss. \n\n\nOverview\nThis Ansys 2024 R1 webinar will review the high-frequency electronics tool updates\, enhancements\, and new features – HFSS\, Q3D\, SIwave\, and NuHertz. Engineers developing PCBs\, antennas\, and other RF capabilities for telecommunications\, HPC\, automotive\, A&D\, and IoT applications will find many new capabilities and improvements in this update. \nWhat you will learn\n\nEncrypted technology file support in HFSS 3D Layout IC Mode\nEnhanced support for FlexPCB in HFSS 3D\nHFSS Finite Array metadata export and mask automation\nIcepak Thermal Mesh Fusion\nSolver enhancements for SIwave and Q3D\nImprovements to HPC/Distributed Computing support for all products\n\nWho should attend and why\nEngineers involved in new product development for any electronics market \nSpeaker\n\nJuliano Mologni\n\n\n\n\n\nJuliano Mologni is a Lead Product Manager in the Electronics Business Unit at Ansys\, responsible for all HF electronics products. He has over 20 years of experience in computational electromagnetics and is the author of multiple patents and more than 60 journal and conference papers. Juliano is involved in many RF and EMC projects with top automotive\, A&D\, appliances\, and high tech companies. He holds a BSc degree in telecommunication engineering and an MSc in microelectronics and has authored a PhD thesis on automotive EMC and signal integrity.
URL:https://marketingeda.com/event/ansys-2024-r1-high-frequency-electronics-whats-new/
CATEGORIES:EDA,Webinar
ATTACH;FMTTYPE=image/jpeg:https://marketingeda.com/wp-content/uploads/Ansys-April-9-2024.jpg
END:VEVENT
BEGIN:VEVENT
DTSTART;TZID=America/Los_Angeles:20240409T080000
DTEND;TZID=America/Los_Angeles:20240409T090000
DTSTAMP:20240402T170530Z
CREATED:20240402T170530Z
LAST-MODIFIED:20240402T170530Z
UID:7803-1712649600-1712653200@marketingeda.com
SUMMARY:Guiding your aerospace electrical journey
DESCRIPTION:Aerospace electrical/electronic (EE) design requires a delicate balance between innovative technology and uncompromising reliability. Meanwhile\, the pressure to get products to market faster is growing exponentially. Finding ways to design electrical systems quickly\, cost-effectively and efficiently has become a central focus of manufacturers. \nSiemens has the solutions and partnerships to guide the development of best-in-class solutions to these problems. This session will highlight how Capital plays a part in these solutions. \nMeet the speaker\n\n\n\n\n\n\nSIEMENS IES\nChad Holley\nTechnical Product Manager \n\nChad Holley is a Technical Product Manager in IES supporting our Connectivity offerings. He has been working for Siemens for over 8 years and has supported many customers in their Capital deployments. Prior to Siemens\, Chad has held varying positions in wiring and systems design in both the automotive and aerospace and defense industries. Chad is a veteran of the United States Navy as an electrician and holds a bachelor’s degree in Electrical Engineering from Michigan State University.
URL:https://marketingeda.com/event/guiding-your-aerospace-electrical-journey/
CATEGORIES:EDA,Webinar
ATTACH;FMTTYPE=image/jpeg:https://marketingeda.com/wp-content/uploads/Siemens-April-9-2024.jpg
END:VEVENT
BEGIN:VEVENT
DTSTART;TZID=America/Los_Angeles:20240404T110000
DTEND;TZID=America/Los_Angeles:20240404T120000
DTSTAMP:20240311T212213Z
CREATED:20240311T212000Z
LAST-MODIFIED:20240311T212213Z
UID:7730-1712228400-1712232000@marketingeda.com
SUMMARY:High-Performance RTL Simulation Workflow with Libero and Active-HDL
DESCRIPTION:Based on recent industry research\, the FPGA market was valued at approximately USD 7.5 Billion in 2023\, with an expected compound annual growth rate (CAGR) of around 10% by 2032. More and more engineers will be adopting FPGAs due to their versatility\, acceleration capability\, power efficiency and lower non-recurring engineering (NRE) costs (compared to ASICs). Major FPGA vendors like AMD\, Altera and Microchip are continuously innovating their technologies\, architectures\, and IPs – and consequently enhancing their respective design capabilities and workflows. For example\, Vivado\, Quartus and Libero all provide useful design and RTL simulation features. Aldec collaborates closely with the FPGA vendors as partners to ensure seamless simulation of all their IPs and libraries using Aldec’s simulation tool\, Active-HDL. \nIn terms of verification\, FPGA designs undergo testing directly in the lab or through simulations\, depending on factors such as design size\, complexity\, and project objectives. While some FPGA designs may find adequate simulation support from the FPGA vendor tools\, many require higher simulation performance and a more comprehensive language support\, particularly those with larger designs with complex logic and deep hierarchies. \nSimulation stands as the primary verification method for FPGA designs\, essential for minimizing non-trivial bugs escaping into production. The ability to run more simulation enables the verification of a wider range of test scenarios\, thus elevating verification quality. Aldec’s Active-HDL offers a faster compilation/simulation engine\, robust debugging features and comprehensive language support for the latest versions of VHDL\, SystemVerilog\, and SystemC. \nIn this three-part webinar series\, we will show how to turbocharge FPGA simulation workflows by using Active-HDL as the default simulator within AMD® Vivado\, Altera® Quartus and Microchip® Libero SoC. \n  \nAbstract: \nIn the concluding part of this three-part webinar series\, we will show how to simulate a Microchip design example. We will generate a design example from Libero SoC and simulate it using Active-HDL as the default simulator. We will discuss various tips that you can use to optimize compilation and simulation run times. The tips will be categorized from zero-cost effort to high-cost effort and\, depending on your budget/resource constraints\, you will have a path to speed up your simulation by a huge factor. We will turn on Profiler so that you can determine the bottlenecks in your design/testbench and we will perform debugging using Breakpoints\, Xtrace\, Drivers/Readers and Advanced Dataflow. \nAgenda\n\nWorkflow with Libero SoC and Active-HDL\nTips on how to optimize simulation performance\nPerformance bottleneck analysis with Design Profiler\nBreakpoints\, Xtrace and Advanced Dataflow\, Drivers and Readers\nLive Demo\nQ&A\n\nWebinar Duration\n\n45 min presentation/live demo\n15 min Q&A\n\nPresenter Bio: \n \nLouie De Luna\, Director of Marketing at Aldec \nLouie De Luna is Aldec’s Director of Marketing with 20+ years’ experience in FPGA/SoC design verification and EDA tools. He currently directs the overall product and technical marketing of Aldec’s design verification solutions. He earned his B.S. in Computer Engineering from University of Nevada\, Las Vegas\, in 2001.  His practical engineering experience includes simulation-based verification\, linting\, CDC analysis\, and hardware-assisted verification.
URL:https://marketingeda.com/event/high-performance-rtl-simulation-workflow-with-libero-and-active-hdl/
CATEGORIES:EDA,Webinar
ATTACH;FMTTYPE=image/jpeg:https://marketingeda.com/wp-content/uploads/Aldec-April-4-2024.jpg
END:VEVENT
BEGIN:VEVENT
DTSTART;TZID=America/Los_Angeles:20240404T100000
DTEND;TZID=America/Los_Angeles:20240404T110000
DTSTAMP:20240318T163105Z
CREATED:20240318T163105Z
LAST-MODIFIED:20240318T163105Z
UID:7740-1712224800-1712228400@marketingeda.com
SUMMARY:Hierarchical Analysis of EM Crosstalk with EMX Planar 3D Solver
DESCRIPTION:Identifying sources of electromagnetic (EM) coupling and safeguarding today’s complex electronic designs from EM crosstalk are daunting tasks. For designs with multiple levels of hierarchy\, identification\, and detailed analysis of the “EM-sensitive” content is a challenge. The manual creation of wrapper cells or new layout views to enable this quickly becomes a time-consuming and error-prone task. \nLearn how the Cadence EMX Planar 3D Solver black-box flow lets you specify hierarchical layout cells to be excluded from the EM analysis\, saving design time and eliminating errors. Automate the flow and integrate with Virtuoso ADE Suite and Spectre Simulation platforms for more control during circuit analysis. \nLearn through real-life circuit examples how to achieve: \n\nFaster design cycles: Streamline your analysis process and free up time for innovation.\nReduced errors and rework: Eliminate manual tasks and minimize the risk of mistakes.\nEnhanced confidence in your designs: Gain superior control over signal integrity for optimal performance.
URL:https://marketingeda.com/event/hierarchical-analysis-of-em-crosstalk-with-emx-planar-3d-solver/
CATEGORIES:EDA,Webinar
ATTACH;FMTTYPE=image/jpeg:https://marketingeda.com/wp-content/uploads/Cadence-April-4-2024.jpg
END:VEVENT
BEGIN:VEVENT
DTSTART;TZID=America/Los_Angeles:20240404T100000
DTEND;TZID=America/Los_Angeles:20240404T110000
DTSTAMP:20240221T221413Z
CREATED:20240221T221413Z
LAST-MODIFIED:20240221T221413Z
UID:7675-1712224800-1712228400@marketingeda.com
SUMMARY:Maximizing the Benefits of Virtuoso Layout Suite XL
DESCRIPTION:Find out how the Virtuoso Layout Suite XL you’ve known for many years is setting new standards in custom layout authoring. The connectivity-driven paradigm keeps the layout in synch with the circuit design and ensures that the design intents are always honored. Learn how we strengthened the layout editor in Virtuoso Studio\, launched in 2023\, with new features that empower you to achieve tasks much faster. In this webinar\, you will learn about: \n\nNew features such as Schematic Assistant\, Incremental Check Against Source\nWhether Group Array can solve your historical problem of mosaics conflicting with Virtuoso Layout Suite XL\nStreamlining the daunting task of managing the sanctity of review process using the design review feature in Virtuoso Studio\nPerformance improvements you will gain if you switch to Virtuoso Studio\n\nWebinar #1: March 12\nAccelerate Layout Creation with Automated Place and Route in Virtuoso Studio \nWebinar #2: March 19\nSaving on Signoff Effort with iPegasus Verification System for Virtuoso Studio – In-Design DRC and Fill \nWebinar #3: April 4\nMaximizing the Benefits of Virtuoso Layout Suite XL \nWebinar #4: April 10\nFinding Hidden Treasures to Accelerate Routing Your Layout
URL:https://marketingeda.com/event/maximizing-the-benefits-of-virtuoso-layout-suite-xl/
CATEGORIES:EDA,Webinar
ATTACH;FMTTYPE=image/jpeg:https://marketingeda.com/wp-content/uploads/Cadence-March-2024.jpg
END:VEVENT
BEGIN:VEVENT
DTSTART;TZID=America/Los_Angeles:20240402T100000
DTEND;TZID=America/Los_Angeles:20240402T110000
DTSTAMP:20240327T160224Z
CREATED:20240327T160224Z
LAST-MODIFIED:20240327T160224Z
UID:7768-1712052000-1712055600@marketingeda.com
SUMMARY:RISC-V Instruction Set Architecture: Enhancing Computing Power
DESCRIPTION:*Work email required for registration*  \nDon’t miss out on this exclusive opportunity to stay ahead in the rapidly evolving landscape of chip design. Join us for an engaging discussion that promises to inspire and inform: \n– Gain insights into the latest trends shaping chip design. \n– Learn from industry leaders about the strategies behind successful SoC design. \n– Discover how RISC-V and software-defined products are shaping the future of chip architecture. \n– Network with professionals and experts in the field. \nSoftware Defined Products: Meeting the Challenges of Change \nAndes Technology Corp.  \nPresenter: Bing Yu\, Computer and AI Architect\, Andes Technology USA Corp. The adoption of the RISC-V instruction set architecture has revolutionized chip design. For the first time\, designers can extend the instruction set architecture to achieve significant improvements in performance or reductions in power consumption. Bing Yu will delve into how this trend has propelled Andes Technology Corp. to success. \nMenta SAS  \nPresenter: Gareth Baron\, Applications Engineering Director\, Menta SAS North America. As the industry moves towards software-defined products\, there’s an increasing demand for flexibility in chip design\, including the flexibility to update some portions of the logic post-fab. Gareth Baron will explore this trend\, drawing from examples like Software Defined vehicles. Learn how Menta SAS has navigated the challenges of designing for change in silicon. \n*This webinar is in partnership with SemiWiki\, Andes\, and Menta SaS*
URL:https://marketingeda.com/event/risc-v-instruction-set-architecture-enhancing-computing-power/
CATEGORIES:EDA,IP,Webinar
ATTACH;FMTTYPE=image/jpeg:https://marketingeda.com/wp-content/uploads/Amdes-Menta-April-2-2024.jpg
END:VEVENT
BEGIN:VEVENT
DTSTART;TZID=America/Los_Angeles:20240328T110000
DTEND;TZID=America/Los_Angeles:20240328T120000
DTSTAMP:20240311T211521Z
CREATED:20240311T211521Z
LAST-MODIFIED:20240311T211521Z
UID:7727-1711623600-1711627200@marketingeda.com
SUMMARY:High-Performance RTL Simulation Workflow with Quartus and Active-HDL
DESCRIPTION:Based on recent industry research\, the FPGA market was valued at approximately USD 7.5 Billion in 2023\, with an expected compound annual growth rate (CAGR) of around 10% by 2032. More and more engineers will be adopting FPGAs due to their versatility\, acceleration capability\, power efficiency and lower non-recurring engineering (NRE) costs (compared to ASICs). Major FPGA vendors like AMD\, Altera and Microchip are continuously innovating their technologies\, architectures\, and IPs – and consequently enhancing their respective design capabilities and workflows. For example\, Vivado\, Quartus and Libero all provide useful design and RTL simulation features. Aldec collaborates closely with the FPGA vendors as partners to ensure seamless simulation of all their IPs and libraries using Aldec’s simulation tool\, Active-HDL. \nIn terms of verification\, FPGA designs undergo testing directly in the lab or through simulations\, depending on factors such as design size\, complexity\, and project objectives. While some FPGA designs may find adequate simulation support from the FPGA vendor tools\, many require higher simulation performance and a more comprehensive language support\, particularly those with larger designs with complex logic and deep hierarchies. \nSimulation stands as the primary verification method for FPGA designs\, essential for minimizing non-trivial bugs escaping into production. The ability to run more simulation enables the verification of a wider range of test scenarios\, thus elevating verification quality. Aldec’s Active-HDL offers a faster compilation/simulation engine\, robust debugging features and comprehensive language support for the latest versions of VHDL\, SystemVerilog\, and SystemC. \nIn this three-part webinar series\, we will show how to turbocharge FPGA simulation workflows by using Active-HDL as the default simulator within AMD® Vivado\, Altera® Quartus and Microchip® Libero SoC. \nAbstract: \nIn part two of this three-part webinar series\, we will show how to simulate an Altera design example. We will generate a design example from Quartus and simulate it using Active-HDL as the default simulator. We will discuss various tips that you can use to optimize compilation and simulation run times. The tips will be categorized from zero-cost effort to high-cost effort and\, depending on your budget/resource constraints\, you will have a path to speed up your simulation by a huge factor. We will turn on Profiler so that you can determine the bottlenecks in your design/testbench\, and we will show how you to do a post-simulation debug using Waveform Viewer\, Hierarchy\, Object and Watch windows. \n\nAgenda\n\nWorkflow with Quartus and Active-HDL\nTips on how to optimize simulation performance\nPerformance bottleneck analysis with Profiler\nPost-simulation debugging with Waveform Viewer\, Hierarchy and Watch window\nLive demo\nQ&A\n\nWebinar Duration\n\n45 min presentation/live demo\n15 min Q&A\n\nPresenter Bio: \n \nLouie De Luna\, Director of Marketing at Aldec \nLouie De Luna is Aldec’s Director of Marketing with 20+ years’ experience in FPGA/SoC design verification and EDA tools. He currently directs the overall product and technical marketing of Aldec’s design verification solutions. He earned his B.S. in Computer Engineering from University of Nevada\, Las Vegas\, in 2001.  His practical engineering experience includes simulation-based verification\, linting\, CDC analysis\, and hardware-assisted verification.
URL:https://marketingeda.com/event/high-performance-rtl-simulation-workflow-with-quartus-and-active-hdl/
CATEGORIES:EDA,Webinar
ATTACH;FMTTYPE=image/jpeg:https://marketingeda.com/wp-content/uploads/Akdec-March-28-2024.jpg
END:VEVENT
BEGIN:VEVENT
DTSTART;TZID=America/Los_Angeles:20240328T100000
DTEND;TZID=America/Los_Angeles:20240328T110000
DTSTAMP:20240322T224737Z
CREATED:20240322T224737Z
LAST-MODIFIED:20240322T224737Z
UID:7753-1711620000-1711623600@marketingeda.com
SUMMARY:Analyze the Impact of Surface Defect Dot on Short Circuit Phenomena in SiC Devices
DESCRIPTION:Learn How STMicroelectronics Silicon Carbide (SiC) Research Team uses Silvaco TCAD to Analyze the Impact of Surface Defect Dot on Short Circuit Phenomena in SiC Devices\nDuring SiC device switching operations\, it is possible that devices could be reaching abnormal overload conditions\, which is why some applications require “robustness” specifications (e.g.\, Short Circuit and UIS tests). Such overload phenomena can be simulated by mixed-mode circuits and an accurate tuning of simulation parameters\, thanks to simulation/experiment information exchange. This allows us to predict electrothermal behavior during a dynamic phase. As an example\, we report here a study of short circuit phenomenon. The impact of a short circuit of a defect localized in active area has been investigated by means of TCAD simulations performed with Silvaco software. Different cases have been studied in which the defect dot was localized at flat interface body/drain\, at SiC/oxide interface in the channel region\, and at curved interface body/drain. A sensitivity with position has also been performed. \nWhat You Will Learn\n\nWide bandgap (WBG) technologies and key features of SiC\nSiC MOSFET switching operation and ruggedness\nTCAD simulations and device reliability\nShort circuit: Impact of surface defect dot\n\n\n\n\n\n\nPresenter\n\n\n\n\nSalvatore Cascino\, SiC R&D Engineer\, ST Microelectronics \nSalvatore Cascino was born in Palermo (Italy) in 1970. He obtained a Degree in Physics from the University of Palermo. He was involved at ENEA (Frascati – Rome) with Nuclear Fusion Department (FTU project) and with the Fusion Research group in Padua (RFX project). He is currently at STMicroelectronics (Catania) with the R&D Group and his current research interest is aimed to technology development for Silicon Carbide devices. In the past he worked on development of devices for sensing applications and radiofrequency\, too. \n\n\n\n\n\nWHO SHOULD ATTEND:\n\n\n\n\nSemiconductor Device and Process engineers\, product managers\, and engineering management.
URL:https://marketingeda.com/event/analyze-the-impact-of-surface-defect-dot-on-short-circuit-phenomena-in-sic-devices/
CATEGORIES:EDA,Webinar
ATTACH;FMTTYPE=image/jpeg:https://marketingeda.com/wp-content/uploads/Silvaco-March-28-2024.jpg
END:VEVENT
BEGIN:VEVENT
DTSTART;TZID=America/Los_Angeles:20240327T100000
DTEND;TZID=America/Los_Angeles:20240327T110000
DTSTAMP:20240306T173441Z
CREATED:20240306T173441Z
LAST-MODIFIED:20240306T173441Z
UID:7713-1711533600-1711537200@marketingeda.com
SUMMARY:Reduce Gate-level Simulation Bring-up Time with Semi-formal X Verification
DESCRIPTION:Gate-level simulations (GLS) are a crucial step in the verification of an ASIC/FPGA. GLS is used for verifying power-up\, reset operation\, timing\, multi-cycle paths\, and power estimation. However\, GLS can be a bottleneck in the project cycle due to its complexity. The nature of a GLS can cause simulations to run much longer than the equivalent RTL simulations. Additionally\, GLS bring-up and debug is slow and manual. In GLS\, engineers spend time cleaning up sources of unknowns (Xs).  Xs can be caused by uninitialized inputs\, registers\, and simulation artifacts such as X-pessimism. Ad-hoc methods to handle Xs in GLS could mask problems. \nThis webinar will describe a reliable formal-based method to manage Xs in GLS.  It centers on the use of Siemens Avery SimXACT solution alongside your preferred simulator. \nWhat You Will Learn:  \n\nX mitigation techniques to use in RTL\nHow to eliminate X-pessimism in GLS for a streamlined bring-up\nGenerate fixes for unknowns in a fraction of time compared to manual debug\nThe SimXACT workflow\n\nWho Should Attend:  \n\nDesigners and Design Verification engineers\nDesign Managers and Directors responsible for project tapeout schedule\n\nWhat/Which Products are Covered:   \n\nSiemens Avery SimXACT\nQuesta simulation\n\n\n\nSpeakers:\n\n\n\n\n\n\nRick Koster\nLow Power Specialist\, Siemens EDA\n\n\n\n\nRick Koster is the North America Low Power Specialist for verification tools at Siemens EDA.  Rick started his career at Texas Instruments and has held engineering positions at the US Army\, Bytex Corporation.  For more than 25 years\, Rick has worked in verification at Siemens EDA through Mentor Graphics and Ikos Systems. \n\n\n\n\n\n\n\nKai-hui Chang\nSiemens EDA\n\n\n\n\nKai-hui Chang is the architect of the SimXACT tool. He has been with Avery Design Systems for 20 years and recently joined Siemens through the Avery acquisition. His work focuses on simulation technologies and formal verification. He has a Ph. D. in computer science and engineering from the University of Michigan\, Ann Arbor.
URL:https://marketingeda.com/event/reduce-gate-level-simulation-bring-up-time-with-semi-formal-x-verification/
CATEGORIES:EDA,Webinar
ATTACH;FMTTYPE=image/jpeg:https://marketingeda.com/wp-content/uploads/Siemens-March-27-202.jpg
END:VEVENT
BEGIN:VEVENT
DTSTART;TZID=America/Los_Angeles:20240321T110000
DTEND;TZID=America/Los_Angeles:20240321T120000
DTSTAMP:20240311T211030Z
CREATED:20240311T211030Z
LAST-MODIFIED:20240311T211030Z
UID:7724-1711018800-1711022400@marketingeda.com
SUMMARY:High-Performance RTL Simulation Workflow with Vivado and Active-HDL
DESCRIPTION:Based on recent industry research\, the FPGA market was valued at approximately USD 7.5 Billion in 2023\, with an expected compound annual growth rate (CAGR) of around 10% by 2032. More and more engineers will be adopting FPGAs due to their versatility\, acceleration capability\, power efficiency and lower non-recurring engineering (NRE) costs (compared to ASICs). Major FPGA vendors like AMD\, Altera and Microchip are continuously innovating their technologies\, architectures\, and IPs – and consequently enhancing their respective design capabilities and workflows. For example\, Vivado\, Quartus and Libero all provide useful design and RTL simulation features. Aldec collaborates closely with the FPGA vendors as partners to ensure seamless simulation of all their IPs and libraries using Aldec’s simulation tool\, Active-HDL. \nIn terms of verification\, FPGA designs undergo testing directly in the lab or through simulations\, depending on factors such as design size\, complexity\, and project objectives. While some FPGA designs may find adequate simulation support from the FPGA vendor tools\, many require higher simulation performance and a more comprehensive language support\, particularly those with larger designs with complex logic and deep hierarchies. \nSimulation stands as the primary verification method for FPGA designs\, essential for minimizing non-trivial bugs escaping into production. The ability to run more simulation enables the verification of a wider range of test scenarios\, thus elevating verification quality. Aldec’s Active-HDL offers a faster compilation/simulation engine\, robust debugging features and comprehensive language support for the latest versions of VHDL\, SystemVerilog\, and SystemC. \nIn this three-part webinar series\, we will show how to turbocharge FPGA simulation workflows by using Active-HDL as the default simulator within AMD® Vivado\, Altera® Quartus and Microchip® Libero SoC. \nAbstract: \nIn part one of this three-part webinar series\, we will show you how to simulate an AMD example design. We will generate a design example from Vivado and simulate it using Active-HDL as the default simulator. We will discuss various tips that you can use to optimize compilation and simulation run times. The tips will be categorized from zero-cost effort to high-cost effort and\, depending on your budget/resource constraints\, you will have a path to speed up your simulation by a huge factor. We will turn on Profiler so that you can determine the bottlenecks in your design/testbench\, and we will show you advanced debugging capabilities using our advanced waveform viewer. We will also turn on code coverage and analyze the results in html format. \n\nAgenda\n\nWorkflow with Vivado and Active-HDL\nTips on how to optimize simulation performance\nPerformance bottleneck analysis with Profiler\nAdvanced Debugging with Waveform Viewer\nCode Coverage\nLive Demo\nQ&A\n\nWebinar Duration\n\n45 min presentation/live demo\n15 min Q&A\n\nPresenter Bio: \n \nLouie De Luna\, Director of Marketing at Aldec \nLouie De Luna is Aldec’s Director of Marketing with 20+ years’ experience in FPGA/SoC design verification and EDA tools. He currently directs the overall product and technical marketing of Aldec’s design verification solutions. He earned his B.S. in Computer Engineering from University of Nevada\, Las Vegas\, in 2001.  His practical engineering experience includes simulation-based verification\, linting\, CDC analysis\, and hardware-assisted verification.
URL:https://marketingeda.com/event/high-performance-rtl-simulation-workflow-with-vivado-and-active-hdl/
CATEGORIES:EDA,Webinar
ATTACH;FMTTYPE=image/jpeg:https://marketingeda.com/wp-content/uploads/Aldec-March-21-2024.jpg
END:VEVENT
BEGIN:VEVENT
DTSTART;TZID=America/Los_Angeles:20240321T100000
DTEND;TZID=America/Los_Angeles:20240321T110000
DTSTAMP:20240229T180535Z
CREATED:20240229T180535Z
LAST-MODIFIED:20240229T180535Z
UID:7696-1711015200-1711018800@marketingeda.com
SUMMARY:Shift-Left Thermal Analysis with AI-Enabled Celsius Studio Platform
DESCRIPTION:With the growing complexities of 3D-ICs\, chiplets\, advanced packaging\, and high-performance boards\, engineers need a unified solution that provides early insight and analysis to detect and correct design problems before it is too late. This solution must also offer the ability to simulate the entire design efficiently\, providing confidence in system signoff. \nJoin our webinar as we present the new Cadence Celsius Studio the industry’s first complete thermal platform for electronic systems developed specifically to address thermal analysis\, thermal stress\, and electronics cooling design issues. This solution provides accurate system-level thermal analysis by combining finite element method (FEM) with computational fluid dynamics (CFD) technologies for full-system thermal analysis from chip to packaging to board through to the end-system product. \nAttendees will learn: \n\nHow Celsius Studio provides AI-enabled thermal analysis for electro-mechanical systems design\nHow the convergence of FEM and CFD engines addresses thermal challenges spanning from the chip to the packaging and out to the board and end system
URL:https://marketingeda.com/event/shift-left-thermal-analysis-with-ai-enabled-celsius-studio-platform/
CATEGORIES:EDA,Webinar
ATTACH;FMTTYPE=image/jpeg:https://marketingeda.com/wp-content/uploads/Cadence-March-21-2024-1.jpg
END:VEVENT
BEGIN:VEVENT
DTSTART;TZID=Europe/London:20240319T130000
DTEND;TZID=Europe/London:20240319T140000
DTSTAMP:20240410T161048Z
CREATED:20240216T190810Z
LAST-MODIFIED:20240410T161048Z
UID:7624-1710853200-1710856800@marketingeda.com
SUMMARY:DVClub Europe: Latest VHDL Verification Techniques
DESCRIPTION:This DVClub focuses on the latest verification techniques in VHDL including UVVM and OSVVM \nAgenda (GMT) \n13:00   Welcome and Introduction – Mike Bartley\, Tessolve \n13:00   Epsen Tallaksen\, EmLogic – Get the right FPGA quality through efficient Specification Coverage (aka Requirement Coverage) \n13:30   Jim Lewis\, SynthWorks – OSVVM in a NutShell\, VHDL’s #1 Verification Methodology \n14:00    Close \nAdditional Information\nFor additional information please visit the Tessolve DVClub Europe webpage for this event. \nSponsors\nDVClub Europe is made possible through the generous support of our sponsors: Agnisys\, Cadence\, Breker Verification System\, Synopsys
URL:https://marketingeda.com/event/dvclub-europe-latest-vhdl-verification-techniques/
CATEGORIES:EDA,Webinar
ATTACH;FMTTYPE=image/jpeg:https://marketingeda.com/wp-content/uploads/DVClub-Europe-19-March-2024.jpg
END:VEVENT
BEGIN:VEVENT
DTSTART;TZID=America/Los_Angeles:20240319T100000
DTEND;TZID=America/Los_Angeles:20240319T110000
DTSTAMP:20240221T221244Z
CREATED:20240221T221244Z
LAST-MODIFIED:20240221T221244Z
UID:7673-1710842400-1710846000@marketingeda.com
SUMMARY:Virtuoso - Save on Signoff Effort with In-Design DRC and Fill
DESCRIPTION:Virtuoso Layout Suite has pioneered in-design DRC checking and fixing in the layout editor. However\, many of you have realized that the lack of completeness of rules in the techfile has caused many violations to fall through the cracks and are discovered later during signoff. An in-design DRC checking with signoff rule decks often comes at a cost – time and money. Not anymore. With iPegasus Verification System for Virtuoso Studio\, you can get signoff-quality physical verification within the Virtuoso Layout Suite. This webinar will teach you how: \n\nyou can avoid late surprises during signoff and save your efforts using iPegasus system for Virtuoso Studio\nthe new unified toolbar and settings simplifies your design checks with signoff quality\nthe enhanced Annotation Browser gives you an integrated solution for reviewing and fixing errors\nflexible run scope helps you in DRC fixing without losing focus\n\nMetal fill is an important step in the layout creation process that has gained significance in recent times. Crucial analog portions of the IP need careful handling with symmetry and non-minimum spacing to ensure that metal fills do not degrade circuit performance. iPegasus fill for Virtuoso Studio elevates the user experience by bringing metal fill using signoff rule decks closer to the layout. Natively integrated into Virtuoso Studio\, iPegasus fill provides control\, accuracy\, and performance benefits over running a standalone loosely tied-up flow. \nWebinar #1: March 12\nAccelerate Layout Creation with Automated Place and Route in Virtuoso Studio \nWebinar #2: March 19\nSaving on Signoff Effort with iPegasus Verification System for Virtuoso Studio – In-Design DRC and Fill \nWebinar #3: April 4\nMaximizing the Benefits of Virtuoso Layout Suite XL \nWebinar #4: April 10\nFinding Hidden Treasures to Accelerate Routing Your Layout
URL:https://marketingeda.com/event/virtuoso-save-on-signoff-effort-with-in-design-drc-and-fill/
CATEGORIES:EDA,Webinar
ATTACH;FMTTYPE=image/jpeg:https://marketingeda.com/wp-content/uploads/Cadence-March-2024.jpg
END:VEVENT
BEGIN:VEVENT
DTSTART;TZID=America/Los_Angeles:20240314T080000
DTEND;TZID=America/Los_Angeles:20240314T090000
DTSTAMP:20240222T181810Z
CREATED:20240222T181810Z
LAST-MODIFIED:20240222T181810Z
UID:7683-1710403200-1710406800@marketingeda.com
SUMMARY:New Advanced Techniques for Reset Domain Crossing (RDC) Analysis
DESCRIPTION:Designers increasingly use complex reset signaling architectures to meet high-performance\, low-latency\, and low-power requirements. Specifically\, independent reset domains are created by complex reset sequences\, reset circuitry\, and the intermixing of IPs with different reset schemas\, power-management domains\, and security domains or functionality. This increase in reset signaling complexity is creating new RDC verification challenges that are straining “gen one” RDC solutions.\n‌\nIn this webinar we will show new\, advanced RDC techniques\, methodology\, and automation for:\n‌ \n\nHow to hierarchically characterize and structure reset (and clock) domain models for rapid analysis and re-use of IP-level RDC information as the design grows\nAI/ML-based automation that pinpoints where to place synchronizers\, and in parallel to aggressively minimize false positives (e.g. automatically minimizing “noise”)\nCreating custom synchronizers for proprietary synchronization styles\nWaiver management flows to efficiently address violations and waiver tracking throughout the project\nConsiderations for low power designs with UPF\n\n‌\nWhat you will learn: \nA short review of the basics of Clock and Reset Domain Crossing issues that may cause meta-stability\, glitch or data coherency.\nWhat’s the right methodology for a comprehensive RDC analysis?\nQuesta RDC solutions \nWho should attend: \nDesign Engineers\, CAD Engineers\, Project Leads who are using/supporting static verification flows.\nWorking knowledge of Verilog\, SystemVerilog\, or VHDL will presumed. \nSpeaker:\n\n\n\n\n\n\nAtul Sharma\nLead Product Engineer\, Siemens EDA\n\n\n\n\nAtul Sharma is Lead Product Engineer for Questa Static and Formal Solutions in Design Verification Technology Division of Siemens Electronic Design Automation (EDA) and is primarily responsible for CDC\, RDC\, SignOff CDC and Lint products. Atul has 16 years of experience in design and verification\, design methodologies\, technical marketing and applications engineering. Prior to Siemens EDA\, Atul has held design verification role for a design company\, and Product expert role in an EDA company\, for multiple products covering different aspects of static and functional verification. \nWith 16 years of total experience\, he has spent over a decade in customer facing role to solve Static Verification issues (CDC\, RDC\, Lint\, DFT\, Power Estimation/Reduction & Power Verification) and to create customer methodologies\, use models for multiple EDA products.
URL:https://marketingeda.com/event/new-advanced-techniques-for-reset-domain-crossing-rdc-analysis/
CATEGORIES:EDA,Webinar
ATTACH;FMTTYPE=image/jpeg:https://marketingeda.com/wp-content/uploads/Siemens-March-14-2024.jpg
END:VEVENT
BEGIN:VEVENT
DTSTART;TZID=America/Los_Angeles:20240312T100000
DTEND;TZID=America/Los_Angeles:20240312T110000
DTSTAMP:20240221T220803Z
CREATED:20240221T220803Z
LAST-MODIFIED:20240221T220803Z
UID:7670-1710237600-1710241200@marketingeda.com
SUMMARY:What’s New About Virtuoso Layout Suite?
DESCRIPTION:Accelerate Layout Creation with Automated Place and Route in Virtuoso Studio\n\n\n\nHow can you cut down custom layout implementation from days to minutes? Custom device-level automated place and route (APR) for advanced nodes has very different requirements than mature node chip assembly routing. With our new unified APR flow-based user interface integrating the various automation engines in Virtuoso Studio\, device-level layout\, standard cells and blocks\, chip assembly\, and memory can automatically be designed from the same interface using the right tool underneath for the right job. \nBy including an intuitive spreadsheet-style constraint management interface\, pre-routing checkers\, and support for custom routing constraints\, all layout users will find APR technology easy to use\, not just the expert ones. In this webinar\, we will showcase the following flows: \n\nCustom device-level APR for advanced node\nStandard cell APR for custom digital designs leveraging seamless integration of Innovus Implementation System’s GigaPlace placement engine and NanoRoute routing engine\nChip assembly and specialty routing for mature nodes\n\nAutomating the placement and routing of custom and analog designs with thousands of nets lets you finish the layout in minutes! \nWebinar #1: March 12\nAccelerate Layout Creation with Automated Place and Route in Virtuoso Studio \nWebinar #2: March 19\nSaving on Signoff Effort with iPegasus Verification System for Virtuoso Studio – In-Design DRC and Fill \nWebinar #3: April 4\nMaximizing the Benefits of Virtuoso Layout Suite XL \nWebinar #4: April 10\nFinding Hidden Treasures to Accelerate Routing Your Layout
URL:https://marketingeda.com/event/whats-new-about-virtuoso-layout-suite/
CATEGORIES:EDA,Webinar
ATTACH;FMTTYPE=image/jpeg:https://marketingeda.com/wp-content/uploads/Cadence-March-2024.jpg
END:VEVENT
END:VCALENDAR