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DTSTART;TZID=America/Los_Angeles:20240411T110000
DTEND;TZID=America/Los_Angeles:20240411T120000
DTSTAMP:20240408T161908Z
CREATED:20240408T161857Z
LAST-MODIFIED:20240408T161908Z
UID:7813-1712833200-1712836800@marketingeda.com
SUMMARY:Making a Structured VHDL Testbench – A Demo for Beginners
DESCRIPTION:Abstract: \nThis demonstrated tutorial is intended for designers and verification engineers who want to learn to make better and more structured testbenches. \nThis session will show you what is needed for any good testbench\, irrespective of its complexity.\nWe will make a testbench from scratch for a simple VHDL module and do the following:\n\nAdd a balanced and controllable clock generator\nAdd logging of progress in a simple way\nCheck default values and reset\nAccess module via an interface – using BFMs (Bus Functional models)\nCheck output signals with and without a positive acknowledge\nWait for flag or interrupt or a given value – with a timeout\nCheck that signals have been stable – without pulses or spikes for a given time\nReport an alert summary\n… and more\n\n…all  using well-documented VHDL procedures and functions from UVVM\, the open source fastest growing VHDL verification methodology.\nThe presented solution will use UVVM Utility Library and BFMs\, but the principles and mechanisms are 100% general verification methodology; i.e.\, independent of library and available functionality.\nAlthough this testbench is applied on a very simple design under test (DUT)\, the same principles also apply to advanced testbenches for complex DUTs. (But the advanced testbenches need more on top.)\nAgenda\n\nQuality and Efficiency Enablers\nThe simple DUT and simple TB architecture\nUVVM: Concepts\, Download and Compile\nMaking the testbench – prior to test cases\nAdding clock generator and starting logging and checking\nBFMs: Explained\, Usage\, Making simple overloads\nAlert handling\, Verbosity control and Timeouts\nConclusion\nQ&A\n\nWebinar Duration\n\n45 min presentation/live demo\n15 min Q&A\n\nPresenter \n \nBio: \nEspen is also the author and architect of UVVM and founder of previous Bitvis. He has a strong interest for methodology cultivation and pragmatic efficiency and quality improvement\, and he has given many presentations on various international conferences with great feedback. He has also given courses on FPGA Design and Verification world-wide.
URL:https://marketingeda.com/event/making-a-structured-vhdl-testbench-a-demo-for-beginners/
CATEGORIES:EDA,Webinar
ATTACH;FMTTYPE=image/jpeg:https://marketingeda.com/wp-content/uploads/Aldec-April-11-2024.jpg
END:VEVENT
BEGIN:VEVENT
DTSTART;TZID=America/Los_Angeles:20240411T100000
DTEND;TZID=America/Los_Angeles:20240411T110000
DTSTAMP:20240314T180820Z
CREATED:20240314T180820Z
LAST-MODIFIED:20240314T180820Z
UID:7736-1712829600-1712833200@marketingeda.com
SUMMARY:Cadence Managed Cloud for Cost Efficient and Productive Chip Design
DESCRIPTION:Join us for an informative webinar\, as we unveil the capabilities of our cloud solutions designed to revolutionize EDA workloads. Whether you require completely hosted environments or need peak/burst capacity\, our cloud solutions offer unparalleled flexibility and efficiency. \nWe will discuss how Cadence Managed Cloud can optimize cost-efficiency and productivity for your chip design projects. Learn how to harness the full potential of cloud technology to streamline your EDA workflows and achieve remarkable results. \nDon’t miss our live demonstration of Cadence Managed Cloud\, where we’ll showcase its robust productivity and security features. Plus\, discover how you can kickstart your journey with a 30-day free trial. \nWho should attend:\nChip designers\, Cloud IT Architects\, CAD Platform team\, and business decision makers. \nPresenters: \nKushal Koolwal\, Business Development Director\, Cadence \nMike Stranton\, IT Group Director\, Cadence
URL:https://marketingeda.com/event/cadence-managed-cloud-for-cost-efficient-and-productive-chip-design/
CATEGORIES:EDA,Webinar
ATTACH;FMTTYPE=image/jpeg:https://marketingeda.com/wp-content/uploads/Cadence-April-11-2024.jpg
END:VEVENT
BEGIN:VEVENT
DTSTART;TZID=America/Los_Angeles:20240410T100000
DTEND;TZID=America/Los_Angeles:20240410T110000
DTSTAMP:20240221T221535Z
CREATED:20240221T221535Z
LAST-MODIFIED:20240221T221535Z
UID:7677-1712743200-1712746800@marketingeda.com
SUMMARY:Virtuoso - Finding Hidden Treasures to Accelerate Routing Your Layout
DESCRIPTION:Every layout designer frets over routing all the interconnects DRC clean and correct as per the circuit designer’s expectations. On the one hand\, you want a magic wand that just hooks up all the connections with perfect smartness. On the other hand\, you need to guide the connections carefully while weaving your own creative magic – too tough to tell the auto-router the exact constraints. With the assisted routing features in your familiar layout editor in Virtuoso Studio\, you have the Swiss army knife to finish your routing tasks more than 10X faster. Finish more work in the same amount of time or regain your work-life balance with the assisted routing functionality. \nThis webinar takes you on a treasure hunt to find the hidden gems – some you already had but didn’t know\, and some that are part of Virtuoso Studio. Strap your seat belts and learn about: \n\nHow simulation-driven routing goes a step ahead than the create-verify-fix paradigm\nReplicate complicated yet similar bus structures with more than just a simple shape copy\n Fast interactive routing with auto twigs feature\nOptimal routing widths in advanced node with WSP compliance\, wire stranding and wire stacking\nAuto Via Assistant\n\nWebinar #1: March 12\nAccelerate Layout Creation with Automated Place and Route in Virtuoso Studio \nWebinar #2: March 19\nSaving on Signoff Effort with iPegasus Verification System for Virtuoso Studio – In-Design DRC and Fill \nWebinar #3: April 4\nMaximizing the Benefits of Virtuoso Layout Suite XL \nWebinar #4: April 10\nFinding Hidden Treasures to Accelerate Routing Your Layout
URL:https://marketingeda.com/event/virtuoso-finding-hidden-treasures-to-accelerate-routing-your-layout/
CATEGORIES:EDA,Webinar
ATTACH;FMTTYPE=image/jpeg:https://marketingeda.com/wp-content/uploads/Cadence-March-2024.jpg
END:VEVENT
BEGIN:VEVENT
DTSTART;TZID=America/Los_Angeles:20240409T080000
DTEND;TZID=America/Los_Angeles:20240409T170000
DTSTAMP:20240401T175124Z
CREATED:20240401T175124Z
LAST-MODIFIED:20240401T175124Z
UID:7794-1712649600-1712682000@marketingeda.com
SUMMARY:Ansys 2024 R1: High Frequency Electronics What’s New
DESCRIPTION:Learn about the latest improvements and new features to the high frequency electronics simulation tools. There are many enhancements for engineers involved in RF\, automotive\, A&D\, and consumer electronics designs that our subject matter experts will discuss. \n\n\nOverview\nThis Ansys 2024 R1 webinar will review the high-frequency electronics tool updates\, enhancements\, and new features – HFSS\, Q3D\, SIwave\, and NuHertz. Engineers developing PCBs\, antennas\, and other RF capabilities for telecommunications\, HPC\, automotive\, A&D\, and IoT applications will find many new capabilities and improvements in this update. \nWhat you will learn\n\nEncrypted technology file support in HFSS 3D Layout IC Mode\nEnhanced support for FlexPCB in HFSS 3D\nHFSS Finite Array metadata export and mask automation\nIcepak Thermal Mesh Fusion\nSolver enhancements for SIwave and Q3D\nImprovements to HPC/Distributed Computing support for all products\n\nWho should attend and why\nEngineers involved in new product development for any electronics market \nSpeaker\n\nJuliano Mologni\n\n\n\n\n\nJuliano Mologni is a Lead Product Manager in the Electronics Business Unit at Ansys\, responsible for all HF electronics products. He has over 20 years of experience in computational electromagnetics and is the author of multiple patents and more than 60 journal and conference papers. Juliano is involved in many RF and EMC projects with top automotive\, A&D\, appliances\, and high tech companies. He holds a BSc degree in telecommunication engineering and an MSc in microelectronics and has authored a PhD thesis on automotive EMC and signal integrity.
URL:https://marketingeda.com/event/ansys-2024-r1-high-frequency-electronics-whats-new/
CATEGORIES:EDA,Webinar
ATTACH;FMTTYPE=image/jpeg:https://marketingeda.com/wp-content/uploads/Ansys-April-9-2024.jpg
END:VEVENT
BEGIN:VEVENT
DTSTART;TZID=America/Los_Angeles:20240409T080000
DTEND;TZID=America/Los_Angeles:20240409T090000
DTSTAMP:20240402T170530Z
CREATED:20240402T170530Z
LAST-MODIFIED:20240402T170530Z
UID:7803-1712649600-1712653200@marketingeda.com
SUMMARY:Guiding your aerospace electrical journey
DESCRIPTION:Aerospace electrical/electronic (EE) design requires a delicate balance between innovative technology and uncompromising reliability. Meanwhile\, the pressure to get products to market faster is growing exponentially. Finding ways to design electrical systems quickly\, cost-effectively and efficiently has become a central focus of manufacturers. \nSiemens has the solutions and partnerships to guide the development of best-in-class solutions to these problems. This session will highlight how Capital plays a part in these solutions. \nMeet the speaker\n\n\n\n\n\n\nSIEMENS IES\nChad Holley\nTechnical Product Manager \n\nChad Holley is a Technical Product Manager in IES supporting our Connectivity offerings. He has been working for Siemens for over 8 years and has supported many customers in their Capital deployments. Prior to Siemens\, Chad has held varying positions in wiring and systems design in both the automotive and aerospace and defense industries. Chad is a veteran of the United States Navy as an electrician and holds a bachelor’s degree in Electrical Engineering from Michigan State University.
URL:https://marketingeda.com/event/guiding-your-aerospace-electrical-journey/
CATEGORIES:EDA,Webinar
ATTACH;FMTTYPE=image/jpeg:https://marketingeda.com/wp-content/uploads/Siemens-April-9-2024.jpg
END:VEVENT
BEGIN:VEVENT
DTSTART;TZID=America/Los_Angeles:20240404T110000
DTEND;TZID=America/Los_Angeles:20240404T120000
DTSTAMP:20240311T212213Z
CREATED:20240311T212000Z
LAST-MODIFIED:20240311T212213Z
UID:7730-1712228400-1712232000@marketingeda.com
SUMMARY:High-Performance RTL Simulation Workflow with Libero and Active-HDL
DESCRIPTION:Based on recent industry research\, the FPGA market was valued at approximately USD 7.5 Billion in 2023\, with an expected compound annual growth rate (CAGR) of around 10% by 2032. More and more engineers will be adopting FPGAs due to their versatility\, acceleration capability\, power efficiency and lower non-recurring engineering (NRE) costs (compared to ASICs). Major FPGA vendors like AMD\, Altera and Microchip are continuously innovating their technologies\, architectures\, and IPs – and consequently enhancing their respective design capabilities and workflows. For example\, Vivado\, Quartus and Libero all provide useful design and RTL simulation features. Aldec collaborates closely with the FPGA vendors as partners to ensure seamless simulation of all their IPs and libraries using Aldec’s simulation tool\, Active-HDL. \nIn terms of verification\, FPGA designs undergo testing directly in the lab or through simulations\, depending on factors such as design size\, complexity\, and project objectives. While some FPGA designs may find adequate simulation support from the FPGA vendor tools\, many require higher simulation performance and a more comprehensive language support\, particularly those with larger designs with complex logic and deep hierarchies. \nSimulation stands as the primary verification method for FPGA designs\, essential for minimizing non-trivial bugs escaping into production. The ability to run more simulation enables the verification of a wider range of test scenarios\, thus elevating verification quality. Aldec’s Active-HDL offers a faster compilation/simulation engine\, robust debugging features and comprehensive language support for the latest versions of VHDL\, SystemVerilog\, and SystemC. \nIn this three-part webinar series\, we will show how to turbocharge FPGA simulation workflows by using Active-HDL as the default simulator within AMD® Vivado\, Altera® Quartus and Microchip® Libero SoC. \n  \nAbstract: \nIn the concluding part of this three-part webinar series\, we will show how to simulate a Microchip design example. We will generate a design example from Libero SoC and simulate it using Active-HDL as the default simulator. We will discuss various tips that you can use to optimize compilation and simulation run times. The tips will be categorized from zero-cost effort to high-cost effort and\, depending on your budget/resource constraints\, you will have a path to speed up your simulation by a huge factor. We will turn on Profiler so that you can determine the bottlenecks in your design/testbench and we will perform debugging using Breakpoints\, Xtrace\, Drivers/Readers and Advanced Dataflow. \nAgenda\n\nWorkflow with Libero SoC and Active-HDL\nTips on how to optimize simulation performance\nPerformance bottleneck analysis with Design Profiler\nBreakpoints\, Xtrace and Advanced Dataflow\, Drivers and Readers\nLive Demo\nQ&A\n\nWebinar Duration\n\n45 min presentation/live demo\n15 min Q&A\n\nPresenter Bio: \n \nLouie De Luna\, Director of Marketing at Aldec \nLouie De Luna is Aldec’s Director of Marketing with 20+ years’ experience in FPGA/SoC design verification and EDA tools. He currently directs the overall product and technical marketing of Aldec’s design verification solutions. He earned his B.S. in Computer Engineering from University of Nevada\, Las Vegas\, in 2001.  His practical engineering experience includes simulation-based verification\, linting\, CDC analysis\, and hardware-assisted verification.
URL:https://marketingeda.com/event/high-performance-rtl-simulation-workflow-with-libero-and-active-hdl/
CATEGORIES:EDA,Webinar
ATTACH;FMTTYPE=image/jpeg:https://marketingeda.com/wp-content/uploads/Aldec-April-4-2024.jpg
END:VEVENT
BEGIN:VEVENT
DTSTART;TZID=America/Los_Angeles:20240404T100000
DTEND;TZID=America/Los_Angeles:20240404T110000
DTSTAMP:20240318T163105Z
CREATED:20240318T163105Z
LAST-MODIFIED:20240318T163105Z
UID:7740-1712224800-1712228400@marketingeda.com
SUMMARY:Hierarchical Analysis of EM Crosstalk with EMX Planar 3D Solver
DESCRIPTION:Identifying sources of electromagnetic (EM) coupling and safeguarding today’s complex electronic designs from EM crosstalk are daunting tasks. For designs with multiple levels of hierarchy\, identification\, and detailed analysis of the “EM-sensitive” content is a challenge. The manual creation of wrapper cells or new layout views to enable this quickly becomes a time-consuming and error-prone task. \nLearn how the Cadence EMX Planar 3D Solver black-box flow lets you specify hierarchical layout cells to be excluded from the EM analysis\, saving design time and eliminating errors. Automate the flow and integrate with Virtuoso ADE Suite and Spectre Simulation platforms for more control during circuit analysis. \nLearn through real-life circuit examples how to achieve: \n\nFaster design cycles: Streamline your analysis process and free up time for innovation.\nReduced errors and rework: Eliminate manual tasks and minimize the risk of mistakes.\nEnhanced confidence in your designs: Gain superior control over signal integrity for optimal performance.
URL:https://marketingeda.com/event/hierarchical-analysis-of-em-crosstalk-with-emx-planar-3d-solver/
CATEGORIES:EDA,Webinar
ATTACH;FMTTYPE=image/jpeg:https://marketingeda.com/wp-content/uploads/Cadence-April-4-2024.jpg
END:VEVENT
BEGIN:VEVENT
DTSTART;TZID=America/Los_Angeles:20240404T100000
DTEND;TZID=America/Los_Angeles:20240404T110000
DTSTAMP:20240221T221413Z
CREATED:20240221T221413Z
LAST-MODIFIED:20240221T221413Z
UID:7675-1712224800-1712228400@marketingeda.com
SUMMARY:Maximizing the Benefits of Virtuoso Layout Suite XL
DESCRIPTION:Find out how the Virtuoso Layout Suite XL you’ve known for many years is setting new standards in custom layout authoring. The connectivity-driven paradigm keeps the layout in synch with the circuit design and ensures that the design intents are always honored. Learn how we strengthened the layout editor in Virtuoso Studio\, launched in 2023\, with new features that empower you to achieve tasks much faster. In this webinar\, you will learn about: \n\nNew features such as Schematic Assistant\, Incremental Check Against Source\nWhether Group Array can solve your historical problem of mosaics conflicting with Virtuoso Layout Suite XL\nStreamlining the daunting task of managing the sanctity of review process using the design review feature in Virtuoso Studio\nPerformance improvements you will gain if you switch to Virtuoso Studio\n\nWebinar #1: March 12\nAccelerate Layout Creation with Automated Place and Route in Virtuoso Studio \nWebinar #2: March 19\nSaving on Signoff Effort with iPegasus Verification System for Virtuoso Studio – In-Design DRC and Fill \nWebinar #3: April 4\nMaximizing the Benefits of Virtuoso Layout Suite XL \nWebinar #4: April 10\nFinding Hidden Treasures to Accelerate Routing Your Layout
URL:https://marketingeda.com/event/maximizing-the-benefits-of-virtuoso-layout-suite-xl/
CATEGORIES:EDA,Webinar
ATTACH;FMTTYPE=image/jpeg:https://marketingeda.com/wp-content/uploads/Cadence-March-2024.jpg
END:VEVENT
BEGIN:VEVENT
DTSTART;TZID=America/Los_Angeles:20240402T100000
DTEND;TZID=America/Los_Angeles:20240402T110000
DTSTAMP:20240327T160224Z
CREATED:20240327T160224Z
LAST-MODIFIED:20240327T160224Z
UID:7768-1712052000-1712055600@marketingeda.com
SUMMARY:RISC-V Instruction Set Architecture: Enhancing Computing Power
DESCRIPTION:*Work email required for registration*  \nDon’t miss out on this exclusive opportunity to stay ahead in the rapidly evolving landscape of chip design. Join us for an engaging discussion that promises to inspire and inform: \n– Gain insights into the latest trends shaping chip design. \n– Learn from industry leaders about the strategies behind successful SoC design. \n– Discover how RISC-V and software-defined products are shaping the future of chip architecture. \n– Network with professionals and experts in the field. \nSoftware Defined Products: Meeting the Challenges of Change \nAndes Technology Corp.  \nPresenter: Bing Yu\, Computer and AI Architect\, Andes Technology USA Corp. The adoption of the RISC-V instruction set architecture has revolutionized chip design. For the first time\, designers can extend the instruction set architecture to achieve significant improvements in performance or reductions in power consumption. Bing Yu will delve into how this trend has propelled Andes Technology Corp. to success. \nMenta SAS  \nPresenter: Gareth Baron\, Applications Engineering Director\, Menta SAS North America. As the industry moves towards software-defined products\, there’s an increasing demand for flexibility in chip design\, including the flexibility to update some portions of the logic post-fab. Gareth Baron will explore this trend\, drawing from examples like Software Defined vehicles. Learn how Menta SAS has navigated the challenges of designing for change in silicon. \n*This webinar is in partnership with SemiWiki\, Andes\, and Menta SaS*
URL:https://marketingeda.com/event/risc-v-instruction-set-architecture-enhancing-computing-power/
CATEGORIES:EDA,IP,Webinar
ATTACH;FMTTYPE=image/jpeg:https://marketingeda.com/wp-content/uploads/Amdes-Menta-April-2-2024.jpg
END:VEVENT
BEGIN:VEVENT
DTSTART;TZID=America/Los_Angeles:20240328T110000
DTEND;TZID=America/Los_Angeles:20240328T120000
DTSTAMP:20240311T211521Z
CREATED:20240311T211521Z
LAST-MODIFIED:20240311T211521Z
UID:7727-1711623600-1711627200@marketingeda.com
SUMMARY:High-Performance RTL Simulation Workflow with Quartus and Active-HDL
DESCRIPTION:Based on recent industry research\, the FPGA market was valued at approximately USD 7.5 Billion in 2023\, with an expected compound annual growth rate (CAGR) of around 10% by 2032. More and more engineers will be adopting FPGAs due to their versatility\, acceleration capability\, power efficiency and lower non-recurring engineering (NRE) costs (compared to ASICs). Major FPGA vendors like AMD\, Altera and Microchip are continuously innovating their technologies\, architectures\, and IPs – and consequently enhancing their respective design capabilities and workflows. For example\, Vivado\, Quartus and Libero all provide useful design and RTL simulation features. Aldec collaborates closely with the FPGA vendors as partners to ensure seamless simulation of all their IPs and libraries using Aldec’s simulation tool\, Active-HDL. \nIn terms of verification\, FPGA designs undergo testing directly in the lab or through simulations\, depending on factors such as design size\, complexity\, and project objectives. While some FPGA designs may find adequate simulation support from the FPGA vendor tools\, many require higher simulation performance and a more comprehensive language support\, particularly those with larger designs with complex logic and deep hierarchies. \nSimulation stands as the primary verification method for FPGA designs\, essential for minimizing non-trivial bugs escaping into production. The ability to run more simulation enables the verification of a wider range of test scenarios\, thus elevating verification quality. Aldec’s Active-HDL offers a faster compilation/simulation engine\, robust debugging features and comprehensive language support for the latest versions of VHDL\, SystemVerilog\, and SystemC. \nIn this three-part webinar series\, we will show how to turbocharge FPGA simulation workflows by using Active-HDL as the default simulator within AMD® Vivado\, Altera® Quartus and Microchip® Libero SoC. \nAbstract: \nIn part two of this three-part webinar series\, we will show how to simulate an Altera design example. We will generate a design example from Quartus and simulate it using Active-HDL as the default simulator. We will discuss various tips that you can use to optimize compilation and simulation run times. The tips will be categorized from zero-cost effort to high-cost effort and\, depending on your budget/resource constraints\, you will have a path to speed up your simulation by a huge factor. We will turn on Profiler so that you can determine the bottlenecks in your design/testbench\, and we will show how you to do a post-simulation debug using Waveform Viewer\, Hierarchy\, Object and Watch windows. \n\nAgenda\n\nWorkflow with Quartus and Active-HDL\nTips on how to optimize simulation performance\nPerformance bottleneck analysis with Profiler\nPost-simulation debugging with Waveform Viewer\, Hierarchy and Watch window\nLive demo\nQ&A\n\nWebinar Duration\n\n45 min presentation/live demo\n15 min Q&A\n\nPresenter Bio: \n \nLouie De Luna\, Director of Marketing at Aldec \nLouie De Luna is Aldec’s Director of Marketing with 20+ years’ experience in FPGA/SoC design verification and EDA tools. He currently directs the overall product and technical marketing of Aldec’s design verification solutions. He earned his B.S. in Computer Engineering from University of Nevada\, Las Vegas\, in 2001.  His practical engineering experience includes simulation-based verification\, linting\, CDC analysis\, and hardware-assisted verification.
URL:https://marketingeda.com/event/high-performance-rtl-simulation-workflow-with-quartus-and-active-hdl/
CATEGORIES:EDA,Webinar
ATTACH;FMTTYPE=image/jpeg:https://marketingeda.com/wp-content/uploads/Akdec-March-28-2024.jpg
END:VEVENT
BEGIN:VEVENT
DTSTART;TZID=America/Los_Angeles:20240328T100000
DTEND;TZID=America/Los_Angeles:20240328T110000
DTSTAMP:20240322T224737Z
CREATED:20240322T224737Z
LAST-MODIFIED:20240322T224737Z
UID:7753-1711620000-1711623600@marketingeda.com
SUMMARY:Analyze the Impact of Surface Defect Dot on Short Circuit Phenomena in SiC Devices
DESCRIPTION:Learn How STMicroelectronics Silicon Carbide (SiC) Research Team uses Silvaco TCAD to Analyze the Impact of Surface Defect Dot on Short Circuit Phenomena in SiC Devices\nDuring SiC device switching operations\, it is possible that devices could be reaching abnormal overload conditions\, which is why some applications require “robustness” specifications (e.g.\, Short Circuit and UIS tests). Such overload phenomena can be simulated by mixed-mode circuits and an accurate tuning of simulation parameters\, thanks to simulation/experiment information exchange. This allows us to predict electrothermal behavior during a dynamic phase. As an example\, we report here a study of short circuit phenomenon. The impact of a short circuit of a defect localized in active area has been investigated by means of TCAD simulations performed with Silvaco software. Different cases have been studied in which the defect dot was localized at flat interface body/drain\, at SiC/oxide interface in the channel region\, and at curved interface body/drain. A sensitivity with position has also been performed. \nWhat You Will Learn\n\nWide bandgap (WBG) technologies and key features of SiC\nSiC MOSFET switching operation and ruggedness\nTCAD simulations and device reliability\nShort circuit: Impact of surface defect dot\n\n\n\n\n\n\nPresenter\n\n\n\n\nSalvatore Cascino\, SiC R&D Engineer\, ST Microelectronics \nSalvatore Cascino was born in Palermo (Italy) in 1970. He obtained a Degree in Physics from the University of Palermo. He was involved at ENEA (Frascati – Rome) with Nuclear Fusion Department (FTU project) and with the Fusion Research group in Padua (RFX project). He is currently at STMicroelectronics (Catania) with the R&D Group and his current research interest is aimed to technology development for Silicon Carbide devices. In the past he worked on development of devices for sensing applications and radiofrequency\, too. \n\n\n\n\n\nWHO SHOULD ATTEND:\n\n\n\n\nSemiconductor Device and Process engineers\, product managers\, and engineering management.
URL:https://marketingeda.com/event/analyze-the-impact-of-surface-defect-dot-on-short-circuit-phenomena-in-sic-devices/
CATEGORIES:EDA,Webinar
ATTACH;FMTTYPE=image/jpeg:https://marketingeda.com/wp-content/uploads/Silvaco-March-28-2024.jpg
END:VEVENT
BEGIN:VEVENT
DTSTART;TZID=America/Los_Angeles:20240327T100000
DTEND;TZID=America/Los_Angeles:20240327T110000
DTSTAMP:20240306T173441Z
CREATED:20240306T173441Z
LAST-MODIFIED:20240306T173441Z
UID:7713-1711533600-1711537200@marketingeda.com
SUMMARY:Reduce Gate-level Simulation Bring-up Time with Semi-formal X Verification
DESCRIPTION:Gate-level simulations (GLS) are a crucial step in the verification of an ASIC/FPGA. GLS is used for verifying power-up\, reset operation\, timing\, multi-cycle paths\, and power estimation. However\, GLS can be a bottleneck in the project cycle due to its complexity. The nature of a GLS can cause simulations to run much longer than the equivalent RTL simulations. Additionally\, GLS bring-up and debug is slow and manual. In GLS\, engineers spend time cleaning up sources of unknowns (Xs).  Xs can be caused by uninitialized inputs\, registers\, and simulation artifacts such as X-pessimism. Ad-hoc methods to handle Xs in GLS could mask problems. \nThis webinar will describe a reliable formal-based method to manage Xs in GLS.  It centers on the use of Siemens Avery SimXACT solution alongside your preferred simulator. \nWhat You Will Learn:  \n\nX mitigation techniques to use in RTL\nHow to eliminate X-pessimism in GLS for a streamlined bring-up\nGenerate fixes for unknowns in a fraction of time compared to manual debug\nThe SimXACT workflow\n\nWho Should Attend:  \n\nDesigners and Design Verification engineers\nDesign Managers and Directors responsible for project tapeout schedule\n\nWhat/Which Products are Covered:   \n\nSiemens Avery SimXACT\nQuesta simulation\n\n\n\nSpeakers:\n\n\n\n\n\n\nRick Koster\nLow Power Specialist\, Siemens EDA\n\n\n\n\nRick Koster is the North America Low Power Specialist for verification tools at Siemens EDA.  Rick started his career at Texas Instruments and has held engineering positions at the US Army\, Bytex Corporation.  For more than 25 years\, Rick has worked in verification at Siemens EDA through Mentor Graphics and Ikos Systems. \n\n\n\n\n\n\n\nKai-hui Chang\nSiemens EDA\n\n\n\n\nKai-hui Chang is the architect of the SimXACT tool. He has been with Avery Design Systems for 20 years and recently joined Siemens through the Avery acquisition. His work focuses on simulation technologies and formal verification. He has a Ph. D. in computer science and engineering from the University of Michigan\, Ann Arbor.
URL:https://marketingeda.com/event/reduce-gate-level-simulation-bring-up-time-with-semi-formal-x-verification/
CATEGORIES:EDA,Webinar
ATTACH;FMTTYPE=image/jpeg:https://marketingeda.com/wp-content/uploads/Siemens-March-27-202.jpg
END:VEVENT
BEGIN:VEVENT
DTSTART;TZID=America/Los_Angeles:20240321T110000
DTEND;TZID=America/Los_Angeles:20240321T120000
DTSTAMP:20240311T211030Z
CREATED:20240311T211030Z
LAST-MODIFIED:20240311T211030Z
UID:7724-1711018800-1711022400@marketingeda.com
SUMMARY:High-Performance RTL Simulation Workflow with Vivado and Active-HDL
DESCRIPTION:Based on recent industry research\, the FPGA market was valued at approximately USD 7.5 Billion in 2023\, with an expected compound annual growth rate (CAGR) of around 10% by 2032. More and more engineers will be adopting FPGAs due to their versatility\, acceleration capability\, power efficiency and lower non-recurring engineering (NRE) costs (compared to ASICs). Major FPGA vendors like AMD\, Altera and Microchip are continuously innovating their technologies\, architectures\, and IPs – and consequently enhancing their respective design capabilities and workflows. For example\, Vivado\, Quartus and Libero all provide useful design and RTL simulation features. Aldec collaborates closely with the FPGA vendors as partners to ensure seamless simulation of all their IPs and libraries using Aldec’s simulation tool\, Active-HDL. \nIn terms of verification\, FPGA designs undergo testing directly in the lab or through simulations\, depending on factors such as design size\, complexity\, and project objectives. While some FPGA designs may find adequate simulation support from the FPGA vendor tools\, many require higher simulation performance and a more comprehensive language support\, particularly those with larger designs with complex logic and deep hierarchies. \nSimulation stands as the primary verification method for FPGA designs\, essential for minimizing non-trivial bugs escaping into production. The ability to run more simulation enables the verification of a wider range of test scenarios\, thus elevating verification quality. Aldec’s Active-HDL offers a faster compilation/simulation engine\, robust debugging features and comprehensive language support for the latest versions of VHDL\, SystemVerilog\, and SystemC. \nIn this three-part webinar series\, we will show how to turbocharge FPGA simulation workflows by using Active-HDL as the default simulator within AMD® Vivado\, Altera® Quartus and Microchip® Libero SoC. \nAbstract: \nIn part one of this three-part webinar series\, we will show you how to simulate an AMD example design. We will generate a design example from Vivado and simulate it using Active-HDL as the default simulator. We will discuss various tips that you can use to optimize compilation and simulation run times. The tips will be categorized from zero-cost effort to high-cost effort and\, depending on your budget/resource constraints\, you will have a path to speed up your simulation by a huge factor. We will turn on Profiler so that you can determine the bottlenecks in your design/testbench\, and we will show you advanced debugging capabilities using our advanced waveform viewer. We will also turn on code coverage and analyze the results in html format. \n\nAgenda\n\nWorkflow with Vivado and Active-HDL\nTips on how to optimize simulation performance\nPerformance bottleneck analysis with Profiler\nAdvanced Debugging with Waveform Viewer\nCode Coverage\nLive Demo\nQ&A\n\nWebinar Duration\n\n45 min presentation/live demo\n15 min Q&A\n\nPresenter Bio: \n \nLouie De Luna\, Director of Marketing at Aldec \nLouie De Luna is Aldec’s Director of Marketing with 20+ years’ experience in FPGA/SoC design verification and EDA tools. He currently directs the overall product and technical marketing of Aldec’s design verification solutions. He earned his B.S. in Computer Engineering from University of Nevada\, Las Vegas\, in 2001.  His practical engineering experience includes simulation-based verification\, linting\, CDC analysis\, and hardware-assisted verification.
URL:https://marketingeda.com/event/high-performance-rtl-simulation-workflow-with-vivado-and-active-hdl/
CATEGORIES:EDA,Webinar
ATTACH;FMTTYPE=image/jpeg:https://marketingeda.com/wp-content/uploads/Aldec-March-21-2024.jpg
END:VEVENT
BEGIN:VEVENT
DTSTART;TZID=America/Los_Angeles:20240321T100000
DTEND;TZID=America/Los_Angeles:20240321T110000
DTSTAMP:20240229T180535Z
CREATED:20240229T180535Z
LAST-MODIFIED:20240229T180535Z
UID:7696-1711015200-1711018800@marketingeda.com
SUMMARY:Shift-Left Thermal Analysis with AI-Enabled Celsius Studio Platform
DESCRIPTION:With the growing complexities of 3D-ICs\, chiplets\, advanced packaging\, and high-performance boards\, engineers need a unified solution that provides early insight and analysis to detect and correct design problems before it is too late. This solution must also offer the ability to simulate the entire design efficiently\, providing confidence in system signoff. \nJoin our webinar as we present the new Cadence Celsius Studio the industry’s first complete thermal platform for electronic systems developed specifically to address thermal analysis\, thermal stress\, and electronics cooling design issues. This solution provides accurate system-level thermal analysis by combining finite element method (FEM) with computational fluid dynamics (CFD) technologies for full-system thermal analysis from chip to packaging to board through to the end-system product. \nAttendees will learn: \n\nHow Celsius Studio provides AI-enabled thermal analysis for electro-mechanical systems design\nHow the convergence of FEM and CFD engines addresses thermal challenges spanning from the chip to the packaging and out to the board and end system
URL:https://marketingeda.com/event/shift-left-thermal-analysis-with-ai-enabled-celsius-studio-platform/
CATEGORIES:EDA,Webinar
ATTACH;FMTTYPE=image/jpeg:https://marketingeda.com/wp-content/uploads/Cadence-March-21-2024-1.jpg
END:VEVENT
BEGIN:VEVENT
DTSTART;TZID=Europe/London:20240319T130000
DTEND;TZID=Europe/London:20240319T140000
DTSTAMP:20240410T161048Z
CREATED:20240216T190810Z
LAST-MODIFIED:20240410T161048Z
UID:7624-1710853200-1710856800@marketingeda.com
SUMMARY:DVClub Europe: Latest VHDL Verification Techniques
DESCRIPTION:This DVClub focuses on the latest verification techniques in VHDL including UVVM and OSVVM \nAgenda (GMT) \n13:00   Welcome and Introduction – Mike Bartley\, Tessolve \n13:00   Epsen Tallaksen\, EmLogic – Get the right FPGA quality through efficient Specification Coverage (aka Requirement Coverage) \n13:30   Jim Lewis\, SynthWorks – OSVVM in a NutShell\, VHDL’s #1 Verification Methodology \n14:00    Close \nAdditional Information\nFor additional information please visit the Tessolve DVClub Europe webpage for this event. \nSponsors\nDVClub Europe is made possible through the generous support of our sponsors: Agnisys\, Cadence\, Breker Verification System\, Synopsys
URL:https://marketingeda.com/event/dvclub-europe-latest-vhdl-verification-techniques/
CATEGORIES:EDA,Webinar
ATTACH;FMTTYPE=image/jpeg:https://marketingeda.com/wp-content/uploads/DVClub-Europe-19-March-2024.jpg
END:VEVENT
BEGIN:VEVENT
DTSTART;TZID=America/Los_Angeles:20240319T100000
DTEND;TZID=America/Los_Angeles:20240319T110000
DTSTAMP:20240221T221244Z
CREATED:20240221T221244Z
LAST-MODIFIED:20240221T221244Z
UID:7673-1710842400-1710846000@marketingeda.com
SUMMARY:Virtuoso - Save on Signoff Effort with In-Design DRC and Fill
DESCRIPTION:Virtuoso Layout Suite has pioneered in-design DRC checking and fixing in the layout editor. However\, many of you have realized that the lack of completeness of rules in the techfile has caused many violations to fall through the cracks and are discovered later during signoff. An in-design DRC checking with signoff rule decks often comes at a cost – time and money. Not anymore. With iPegasus Verification System for Virtuoso Studio\, you can get signoff-quality physical verification within the Virtuoso Layout Suite. This webinar will teach you how: \n\nyou can avoid late surprises during signoff and save your efforts using iPegasus system for Virtuoso Studio\nthe new unified toolbar and settings simplifies your design checks with signoff quality\nthe enhanced Annotation Browser gives you an integrated solution for reviewing and fixing errors\nflexible run scope helps you in DRC fixing without losing focus\n\nMetal fill is an important step in the layout creation process that has gained significance in recent times. Crucial analog portions of the IP need careful handling with symmetry and non-minimum spacing to ensure that metal fills do not degrade circuit performance. iPegasus fill for Virtuoso Studio elevates the user experience by bringing metal fill using signoff rule decks closer to the layout. Natively integrated into Virtuoso Studio\, iPegasus fill provides control\, accuracy\, and performance benefits over running a standalone loosely tied-up flow. \nWebinar #1: March 12\nAccelerate Layout Creation with Automated Place and Route in Virtuoso Studio \nWebinar #2: March 19\nSaving on Signoff Effort with iPegasus Verification System for Virtuoso Studio – In-Design DRC and Fill \nWebinar #3: April 4\nMaximizing the Benefits of Virtuoso Layout Suite XL \nWebinar #4: April 10\nFinding Hidden Treasures to Accelerate Routing Your Layout
URL:https://marketingeda.com/event/virtuoso-save-on-signoff-effort-with-in-design-drc-and-fill/
CATEGORIES:EDA,Webinar
ATTACH;FMTTYPE=image/jpeg:https://marketingeda.com/wp-content/uploads/Cadence-March-2024.jpg
END:VEVENT
BEGIN:VEVENT
DTSTART;TZID=America/Los_Angeles:20240314T080000
DTEND;TZID=America/Los_Angeles:20240314T090000
DTSTAMP:20240222T181810Z
CREATED:20240222T181810Z
LAST-MODIFIED:20240222T181810Z
UID:7683-1710403200-1710406800@marketingeda.com
SUMMARY:New Advanced Techniques for Reset Domain Crossing (RDC) Analysis
DESCRIPTION:Designers increasingly use complex reset signaling architectures to meet high-performance\, low-latency\, and low-power requirements. Specifically\, independent reset domains are created by complex reset sequences\, reset circuitry\, and the intermixing of IPs with different reset schemas\, power-management domains\, and security domains or functionality. This increase in reset signaling complexity is creating new RDC verification challenges that are straining “gen one” RDC solutions.\n‌\nIn this webinar we will show new\, advanced RDC techniques\, methodology\, and automation for:\n‌ \n\nHow to hierarchically characterize and structure reset (and clock) domain models for rapid analysis and re-use of IP-level RDC information as the design grows\nAI/ML-based automation that pinpoints where to place synchronizers\, and in parallel to aggressively minimize false positives (e.g. automatically minimizing “noise”)\nCreating custom synchronizers for proprietary synchronization styles\nWaiver management flows to efficiently address violations and waiver tracking throughout the project\nConsiderations for low power designs with UPF\n\n‌\nWhat you will learn: \nA short review of the basics of Clock and Reset Domain Crossing issues that may cause meta-stability\, glitch or data coherency.\nWhat’s the right methodology for a comprehensive RDC analysis?\nQuesta RDC solutions \nWho should attend: \nDesign Engineers\, CAD Engineers\, Project Leads who are using/supporting static verification flows.\nWorking knowledge of Verilog\, SystemVerilog\, or VHDL will presumed. \nSpeaker:\n\n\n\n\n\n\nAtul Sharma\nLead Product Engineer\, Siemens EDA\n\n\n\n\nAtul Sharma is Lead Product Engineer for Questa Static and Formal Solutions in Design Verification Technology Division of Siemens Electronic Design Automation (EDA) and is primarily responsible for CDC\, RDC\, SignOff CDC and Lint products. Atul has 16 years of experience in design and verification\, design methodologies\, technical marketing and applications engineering. Prior to Siemens EDA\, Atul has held design verification role for a design company\, and Product expert role in an EDA company\, for multiple products covering different aspects of static and functional verification. \nWith 16 years of total experience\, he has spent over a decade in customer facing role to solve Static Verification issues (CDC\, RDC\, Lint\, DFT\, Power Estimation/Reduction & Power Verification) and to create customer methodologies\, use models for multiple EDA products.
URL:https://marketingeda.com/event/new-advanced-techniques-for-reset-domain-crossing-rdc-analysis/
CATEGORIES:EDA,Webinar
ATTACH;FMTTYPE=image/jpeg:https://marketingeda.com/wp-content/uploads/Siemens-March-14-2024.jpg
END:VEVENT
BEGIN:VEVENT
DTSTART;TZID=America/Los_Angeles:20240312T100000
DTEND;TZID=America/Los_Angeles:20240312T110000
DTSTAMP:20240221T220803Z
CREATED:20240221T220803Z
LAST-MODIFIED:20240221T220803Z
UID:7670-1710237600-1710241200@marketingeda.com
SUMMARY:What’s New About Virtuoso Layout Suite?
DESCRIPTION:Accelerate Layout Creation with Automated Place and Route in Virtuoso Studio\n\n\n\nHow can you cut down custom layout implementation from days to minutes? Custom device-level automated place and route (APR) for advanced nodes has very different requirements than mature node chip assembly routing. With our new unified APR flow-based user interface integrating the various automation engines in Virtuoso Studio\, device-level layout\, standard cells and blocks\, chip assembly\, and memory can automatically be designed from the same interface using the right tool underneath for the right job. \nBy including an intuitive spreadsheet-style constraint management interface\, pre-routing checkers\, and support for custom routing constraints\, all layout users will find APR technology easy to use\, not just the expert ones. In this webinar\, we will showcase the following flows: \n\nCustom device-level APR for advanced node\nStandard cell APR for custom digital designs leveraging seamless integration of Innovus Implementation System’s GigaPlace placement engine and NanoRoute routing engine\nChip assembly and specialty routing for mature nodes\n\nAutomating the placement and routing of custom and analog designs with thousands of nets lets you finish the layout in minutes! \nWebinar #1: March 12\nAccelerate Layout Creation with Automated Place and Route in Virtuoso Studio \nWebinar #2: March 19\nSaving on Signoff Effort with iPegasus Verification System for Virtuoso Studio – In-Design DRC and Fill \nWebinar #3: April 4\nMaximizing the Benefits of Virtuoso Layout Suite XL \nWebinar #4: April 10\nFinding Hidden Treasures to Accelerate Routing Your Layout
URL:https://marketingeda.com/event/whats-new-about-virtuoso-layout-suite/
CATEGORIES:EDA,Webinar
ATTACH;FMTTYPE=image/jpeg:https://marketingeda.com/wp-content/uploads/Cadence-March-2024.jpg
END:VEVENT
BEGIN:VEVENT
DTSTART;TZID=America/Los_Angeles:20240307T100000
DTEND;TZID=America/Los_Angeles:20240307T110000
DTSTAMP:20240216T204434Z
CREATED:20240216T204434Z
LAST-MODIFIED:20240216T204434Z
UID:7634-1709805600-1709809200@marketingeda.com
SUMMARY:Efficient Design Methodology for 112G Interface Compliance
DESCRIPTION:As 112G+ data transfer becomes the new normal\, companies risk schedule delays unless they improve the efficiency of their multi-board design methodology. An efficient design methodology looks at signal and power integrity early and often as the design progresses. In addition\, with the precision required to meet 112G compliance\, companies can take extra steps to avoid design re-spins. \n\nThis webinar will: \n\nHighlight the workflow required to overcome the new challenges associated with 112G\nHow Cadence integrated design and analysis technology provides a unique and powerful solution
URL:https://marketingeda.com/event/efficient-design-methodology-for-112g-interface-compliance/
CATEGORIES:EDA,Webinar
ATTACH;FMTTYPE=image/jpeg:https://marketingeda.com/wp-content/uploads/Cadence-March-7-2024.jpg
END:VEVENT
BEGIN:VEVENT
DTSTART;TZID=America/Los_Angeles:20240307T090000
DTEND;TZID=America/Los_Angeles:20240307T100000
DTSTAMP:20240226T233450Z
CREATED:20240226T233450Z
LAST-MODIFIED:20240226T233450Z
UID:7690-1709802000-1709805600@marketingeda.com
SUMMARY:Navigating the Power Challenges of Datacenter Infrastructure
DESCRIPTION:The surge in applications such as AI\, HPC\, and GPU-intensive workloads requires unparalleled performance\, placing cloud vendors and enterprise datacenters under immense pressure to simultaneously maximize power efficiency\, reduce costs\, and adhere to stringent environmental standards.\nJoin us for a 1-hour panel discussion featuring unique perspectives from industry experts at Intel\, Microsoft\, Arm and proteanTecs. We will explore the intricate dynamics between datacenter operations\, power management\, advanced technologies\, and emerging designs.\n\nTopics covered: \n\n\nPower reduction strategies for today and for the next wave of growth\nEmerging trends and technologies to reduce hardware power\nHow the industry is collaborating to address power challenges and achieve sustainable and efficient datacenter infrastructure\nThe impact of AI and best practices to scale\n\n\nThis panel will be moderated by Mark Potter\, a highly respected business executive in the datacenter market. He spent the majority of his career with Hewlett Packard Enterprise\, in his last role as Global CTO\, while also leading Hewlett Packard Labs and the company’s Silicon Design Group. Along with serving on the proteanTecs Advisory Board\, he has served on the Board of Directors or Board of Advisors for multiple organizations including Pensando\, H3C\, Solarflare Communications\, the Greater Houston Partnership\, Texas A&M Engineering Experiment Station (TEES)\, the University of Houston.\n\n\n\nMeet Our Panelists\n\n\nShesha Krishnapura is a Fellow and CTO in the IT organization at Intel Corporation. He is responsible for advancing Intel data centers for energy and rack space efficiency\, disaggregated server innovation and hardware designs\, HPC for EDA\, and optimized platforms for enterprise computing. Shesha has led the introduction and optimization of Intel architecture compute platforms in the EDA industry since 2001. A three-time recipient of the Intel Achievement Award\, he has been granted several patents and has published more than 75 technical articles.\n\nArtour Levin is an industry veteran with over 30 years of semiconductor experience\, owning a deep expertise in chip design and product engineering. Currently\, he is leading in-house AI silicon engineering team in Microsoft that is working on leading-edge AI acceleration technologies. Prior to joining Microsoft\, Artour had a long career at Intel Corporation where he held wide range of leadership positions in developing Products and IPs across various markets including Client\, Data Center\, Graphics and Accelerating Computing.\n\nEddie Ramirez leads the Go-to-Market and ecosystem enablement functions for Arm’s Infrastructure business. He is responsible for helping partners innovate and grow through the adoption of Arm-based solutions into the cloud\, networking and edge markets. Eddie’s global team is helping Arm establish a rich and vibrant ecosystem of hardware and software partners.  He has over 20 years of experience at technology companies including successful campaigns at AMD\, Marvell\, LSI and Western Digital.\n\nEvelyn Landman is the Co-Founder and CTO at proteanTecs. She is an industry veteran and entrepreneur with over 30 years of semiconductor experience. Prior to founding proteanTecs\, Evelyn co-founded Mellanox (NASDAQ: MLNX)\, a global leader of end-to-end InfiniBand and Ethernet interconnect solutions for servers and storage\, where she served as VP of Backend and Product Engineering. From 1988-1999\, Evelyn worked at Intel Corporation\, where she was a senior staff member in the Processors department.
URL:https://marketingeda.com/event/navigating-the-power-challenges-of-datacenter-infrastructure/
CATEGORIES:EDA,IP,Webinar
ATTACH;FMTTYPE=image/jpeg:https://marketingeda.com/wp-content/uploads/proteanTecs-March-7-2024.jpg
END:VEVENT
BEGIN:VEVENT
DTSTART;TZID=America/Chicago:20240229T100000
DTEND;TZID=America/Chicago:20240229T110000
DTSTAMP:20240208T174710Z
CREATED:20240208T174710Z
LAST-MODIFIED:20240208T174710Z
UID:7596-1709200800-1709204400@marketingeda.com
SUMMARY:Manufacturing driven design - DFM within an Xpedition Flow
DESCRIPTION:We often think of Design for Manufacturing (DFM) as the sole responsibility of the fabricator. Over the years\, many OEMs have implemented DFM as a final check in their release process\, but that approach does not prevent issues within a design from piling up and being left for a DFM engineer to identify and communicate back to the designer for resolution. \n‌ \nJoin PCB Design experts for a live discussion and demonstration of the recommended PCB design best practice of identifying and resolving DFM issues at the earliest possible stage in the PCB design process. They will showcase how Xpedition DFM\, an integrated solution that operates right within the Xpedition environment\, provides designers with specific DFM analysis that can be performed at the appropriate design stage. This ensures your design is optimized for manufacturing before proceeding to the next stage of design. This greatly reduces the bottlenecks common with post-layout DFM. \n‌ \nTo learn more\, attend the upcoming LinkedIn Live on February 29th\, 2024. 
URL:https://marketingeda.com/event/manufacturing-driven-design-dfm-within-an-xpedition-flow/
CATEGORIES:EDA,Webinar
ATTACH;FMTTYPE=image/jpeg:https://marketingeda.com/wp-content/uploads/Siemens-February-29-2024.jpg
END:VEVENT
BEGIN:VEVENT
DTSTART;TZID=America/New_York:20240227T090000
DTEND;TZID=America/New_York:20240227T100000
DTSTAMP:20240216T202136Z
CREATED:20240216T202136Z
LAST-MODIFIED:20240216T202136Z
UID:7631-1709024400-1709028000@marketingeda.com
SUMMARY:From code to solution: tools and tactics for aerospace fault code troubleshooting
DESCRIPTION:Join us in this insightful webinar as we delve into the world of aerospace and defense electrical fault code troubleshooting\, unveiling the power of Capital™ Service Explorer. \nDiscover innovative strategies to diagnose issues swiftly\, minimizing downtime and optimizing product performance. Explore real-world examples showcasing how Capital Service Explorer facilitates the identification of commonalities among multiple fault codes\, empowering technicians to expedite resolutions. \nWe will also demonstrate its ability to seamlessly integrate 3D visualization data\, providing a comprehensive solution for efficient and intelligent troubleshooting in the aerospace and defense industry. \nMeet the speakers\nOjaswa Sharma\nSenior Product Manager\, IES \n\nHe is a Senior Product Manager with 15 years of experience in the Automotive Industry. With expertise in the design and development of Electrical Distribution Systems\, he has successfully led teams across various Original Equipment Manufacturers (OEMs) to deliver exceptional EE content for a wide range of vehicle platforms. \nDavid Gamba\nProduct Owner\, IES \n\nAs a Product Owner for Documentation & Diagnostics within the Integrated Electrical Systems\, he has spent the past 10 years deploying Capital tools in both the aerospace and automotive sectors. His expertise lies in usability\, customer deployments\, and proposing growth-driving solutions. Through collaboration with customers\, engineers\, and users\, he has contributed to the development of intuitive products that have transformed the industry.
URL:https://marketingeda.com/event/from-code-to-solution-tools-and-tactics-for-aerospace-fault-code-troubleshooting/
CATEGORIES:EDA,Webinar
ATTACH;FMTTYPE=image/jpeg:https://marketingeda.com/wp-content/uploads/Siemens-Februay-27-2024.jpg
END:VEVENT
BEGIN:VEVENT
DTSTART;TZID=America/Los_Angeles:20240221T090000
DTEND;TZID=America/Los_Angeles:20240221T100000
DTSTAMP:20240212T201810Z
CREATED:20240212T201810Z
LAST-MODIFIED:20240212T201810Z
UID:7604-1708506000-1708509600@marketingeda.com
SUMMARY:Comprehensive CXL 3.0 Verification Solution for High-Bandwidth and Low-Latency Connectivity
DESCRIPTION:Join us for a deep dive into the most comprehensive CXL Verification IP solution available in the market that targets 1.1\, 2.0 and 3.0\, Siemens Avery CXL Verification IP. \nCompute Express Link (CXL) is an open industry-standard interconnect offering coherency and memory semantics using high- bandwidth\, low-latency connectivity between host processor and devices such as accelerators\, memory buffers\, and smart I/O devices. CXL 3.0 provides a range of advanced features and benefits including doubling bandwidth with the same latency. \nTo rapidly meet the growing needs for the CXL datacenter ecosystem\, developers of server processors\, managed DRAM and storage class memory (SCM) buffers\, switch/retimer\, and IP companies need a comprehensive CXL verification solution that enables rapid and thorough system interoperability\, validation and performance benchmarking of systems targeting the full range of versions of the standard\, including 1.1\, 2.0 and 3.0. \nWhat You Will Learn:\n\nConsiderations for exhaustive verification of the CXL interconnect\nUnique features in Siemens Avery CXL Verification IP\, including\, capabilities for scalability and resource utilization\, realistic traffic arbitration and unified user application data class for PCIe and CXL traffic\nHow Siemens Avery CXL Validation Suite enables hardware and software development teams to start system integration and validation extremely early\n\nWho Should Attend? \n\nDesign and verification engineers\nFirmware engineers and architects working on CXL projects\n\nThe session will include a demonstration of the CXL Validation Suite\, followed by Q&A with the presenters. \n\n\nSpeakers:\n\n\n\nChris Browy\nSenior Director\, VIP\, Siemens EDA\n\n\nChris Browy is Senior Director of Siemens VIP Product Line. He came to Siemens recently through the acquisition of Avery Design Systems where he was co-founder and served as VP Sales/Marketing for close to 25 years. From 1989 to 1998\, Chris held various positions at Cadence Design Systems including Director of ASIC Design Services\, Director of Top-down IC Design Practice\, and product marketing manager for synthesis\, timing analysis\, and test products. Prior to Cadence\, Chris held numerous other positions in EDA applications engineering and ASIC design involving large-scale ATM switching systems\, Non-linear digital video editing systems\, and massively parallel multiprocessors and super minicomputers. Chris received a B.S.E.E. from Rensselaer Polytechnic Institute in 1984 and resides in New Hampshire. \n\nTzi Yang Shao\nLead Developer\, VICS\, Siemens EDA\n\n\nTzi Yang Shao is the lead developer at Siemens in the VICS Product Line. His association with Siemens commenced with the acquisition of Avery Design Systems\, and he has dedicated six years to the company. Tzi Yang actively contributes to CXLCV development\, demonstrating his proficiency in QEMU and various protocols. In 2017\, he earned an MPhil in Technology Leadership and Entrepreneurship from the Hong Kong University of Science and Technology\, complementing his background in Electronic Engineering.
URL:https://marketingeda.com/event/comprehensive-cxl-3-0-verification-solution-for-high-bandwidth-and-low-latency-connectivity/
CATEGORIES:EDA,IP,Webinar
ATTACH;FMTTYPE=image/jpeg:https://marketingeda.com/wp-content/uploads/Siemens-February-21-2024.jpg
END:VEVENT
BEGIN:VEVENT
DTSTART;TZID=America/Los_Angeles:20240220T080000
DTEND;TZID=America/Los_Angeles:20240220T090000
DTSTAMP:20240216T185704Z
CREATED:20240216T185704Z
LAST-MODIFIED:20240216T185704Z
UID:7621-1708416000-1708419600@marketingeda.com
SUMMARY:SPICE-accurate variation-aware verification best practices with Solido AI-powered technologies
DESCRIPTION:The demand for Custom ICs is on the rise globally along with high proliferation of semiconductor content. Higher requirements on power\, performance\, area\, and yield\, as well as other factors such as advanced process nodes and mission-critical applications have increased the need for accurate verification across process\, voltage\, and temperature corners\, as well as local variation. \nWhere traditional brute-force Monte Carlo solutions are insufficient to scale to meet these escalating design requirements\, an effective SPICE-level verification methodology can provide a robust solution to meet these growing demands in shorter design and verification cycles. \nI invite you to join me in this webinar\, where we’ll delve into the evolving challenges of variation-aware verification in IC design\, uncover the most effective best practices\, and explore how a methodology leveraging Solido Design Environment’s AI technologies can enhance SPICE-level variation-aware verification\, accelerating verification runtime while enhancing coverage and accuracy. \nWhat you will learn:\nIn this masterclass you’ll gain a comprehensive understanding of design variations and effective techniques to manage them. Explore Solido Design Environment’s AI-powered tools\, and discover how they streamline design verification\, ensuring improved speed and accuracy. \nFeatured Products: Solido Design Environment \nSpeaker:\n\nMohamed Atoua\nProduct Manager\, Siemens EDA \nMohamed Atoua is a Product Manager for Solido Design Environment at Siemens EDA with more than 7 years of experience in the EDA industry. With a track record of blending technical solutions with business acumen\, his current mission is to help circuit designers address the challenges of meeting higher design complexity faster with less effort through Siemens’ Solido Design Environment software. \nHis journey began at Cairo University\, where he earned a bachelor’s degree in electrical engineering\, specializing in electronics with a minor in computer engineering. Atoua is currently pursuing his master’s degree in business administration at the University of Illinois Urbana-Champaign\, he thrives at the intersection of technology and management.
URL:https://marketingeda.com/event/spice-accurate-variation-aware-verification-best-practices-with-solido-ai-powered-technologies/
CATEGORIES:EDA,Webinar
ATTACH;FMTTYPE=image/jpeg:https://marketingeda.com/wp-content/uploads/Siemens-February-20-2024.jpg
END:VEVENT
BEGIN:VEVENT
DTSTART;TZID=America/Los_Angeles:20240215T110000
DTEND;TZID=America/Los_Angeles:20240215T120000
DTSTAMP:20240202T185233Z
CREATED:20240202T185233Z
LAST-MODIFIED:20240202T185233Z
UID:7574-1707994800-1707998400@marketingeda.com
SUMMARY:Essential Steps to Simplify VHDL Testbenches Using OSVVM
DESCRIPTION:This “Getting Started” webinar focuses on the first\, essential steps you need to take when looking to improve your VHDL testbench approach. In this webinar we examine transaction-based testing\, self-checking tests\, messaging\, reports\, and Open Source VHDL Verification Methodology (OSVVM) helper utilities. \n  \nThe “transaction” in transaction-based testing is just a fancy word for an abstraction that represents a single action on an interface – such as a Send or Get on a streaming interface. We will look at alternatives in implementing transactions – including using OSVVM’s Model Independent Transaction library. Using transactions is important because they accelerate test case development\, increase reuse\, and reduce maintenance costs. \n  \nSelf-checking is essential in test cases as checking waveform output manually is time consuming\, error prone\, and soul-crushingly boring. Self-checking involves counting errors and using the count to create a pass/fail report when the test is completed. If we use signals (and there may be a collection\, some of which might be in a different entity) we will need to sum them up and generate an error report. However\, it is easy to forget one and give a false pass condition. OSVVM simplifies error counting and makes it reliable by creating a data structure in a package and using it to track the multitude of error sources. The pass/fail report is created by looking at the entire data structure for errors – so nothing is missed. We can even track and report separate sources of errors – such as different interfaces. \n  \nMessaging (a.k.a. verbosity control) is about creating detailed informational messages when we are debugging and just pass/fail messages when running regressions. Since the messages may be generated by different entities\, we need controls that have a wide scope. Furthermore\, we may want to control different sources of messages independently. OSVVM simplifies the control of log messages (enable/disable) using the same data structure we use for tracking errors. \n  \nTest reports are about quickly finding which tests in a suite of tests failed and why. OSVVM creates two levels of test reports. The OSVVM build summary report gives a summary of the pass/fail status of each separate test case that was run\, and the OSVVM test case report provides details on the self-checking\, functional coverage\, and scoreboard/FIFO usage for each test case. When running sets of tests (such as during regression testing)\, these reports help us quickly find which test cases failed and why. \n  \nThe OSVVM helper utilities target simplifying testbench development with capabilities that include clock generation\, reset generation and test case development with synchronization utilities such as WaitForClock and WaitForBarrier. \n  \nAbout OSVVM \nOSVVM is a suite of libraries that allows any VHDL engineer to write VHDL testbenches and test cases for both simple unit/RTL level tests and complex\, randomized full chip or system level tests. OSVVM is developed by VHDL experts who actively contribute to VHDL standards development to provide VHDL with verification capabilities that rival SystemVerilog + UVM.\nGetting your entire team united in using OSVVM will simplify deploying VHDL engineers to projects. Why VHDL for verification? According to the 2022 Wilson Research Group Functional Verification Study\, in the FPGA market\, 66% use VHDL for design\, 58% use VHDL for verification\, and 28% use OSVVM. Hence\, VHDL is #1 for FPGA development and OSVVM is #1 for VHDL verification. \n  \nWebinar Duration: \n\n45 min presentation/live demo\n10 min Q&A\n\n  \nPresenter BIO \nJim Lewis is an innovator and leader in the VHDL community. He has 30 plus years of design and teaching experience. He is the Chair of the IEEE 1076 VHDL Standards Working Group. He is a co-founder of the Open Source VHDL Verification Methodology (OSVVM) and the chief architect of the packages and methodology. He is an expert VHDL trainer for SynthWorks Design Inc. In his design practice\, he has created designs for print servers\, IMA E1/T1 networking\, fighter jets\, video phones\, and spacecraft.\nWhether teaching\, developing OSVVM\, consulting on VHDL design and verification projects\, or working on the IEEE VHDL standard\, Jim brings a deep understanding of VHDL to architect solutions that solve difficult problems in simple ways.
URL:https://marketingeda.com/event/essential-steps-to-simplify-vhdl-testbenches-using-osvvm/
CATEGORIES:EDA,Webinar
ATTACH;FMTTYPE=image/jpeg:https://marketingeda.com/wp-content/uploads/Aldec-February-15-2024.jpg
END:VEVENT
BEGIN:VEVENT
DTSTART;TZID=America/New_York:20240213T110000
DTEND;TZID=America/New_York:20240213T120000
DTSTAMP:20240206T191819Z
CREATED:20240206T191819Z
LAST-MODIFIED:20240206T191819Z
UID:7581-1707822000-1707825600@marketingeda.com
SUMMARY:Introducing Ansys AI: A New Chapter in Engineering Simulation
DESCRIPTION:Join us to learn more about the AI and Simulation Revolution in this upcoming webinar. We’re revolutionizing engineering simulation with the power of Artificial Intelligence with SimAI\, AnsysGPT\, and Ansys AI+. \nOverview\nAt Ansys\, we are revolutionizing engineering simulation with the power of Artificial Intelligence. Our AI-augmented simulation technology is a game-changer\, bringing unprecedented speed\, innovation\, and accessibility to the engineering world. With Ansys AI\, we enable product engineers to leverage their previous simulation and measurement data to reliably assess the performance of new designs in minutes instead of hours. We are not just accelerating simulations but transforming how engineers work\, making simulation simple\, natural\, and accessible. \nWhat you will learn\n\nFirst\, we’ll introduce Ansys SimAI\, a machine learning platform for engineers who must rapidly explore and predict the performance of new concepts across design phases. SimAI provides reliable and fast results\, accessible through user-friendly cloud-native application\, targeting a broad engineering audience that includes all simulation engineers and designers.\nSecond\, we’ll showcase the AnsysGPT chatbot\, which re-imagines the user and support experience through simple\, natural language interaction.\nFinally\, we’ll demonstrate how Ansys AI+ add-ons augment the product capabilities across the Ansys collection\, starting with optiSLang AI+ and Granta MI AI+.\n\nWho should attend\nCAE/CAD Engineers / Designers / Simulation Analyst / Engineers\, Computation Engineers \nSpeaker\nIlya Tolchinsky
URL:https://marketingeda.com/event/introducing-ansys-ai-a-new-chapter-in-engineering-simulation/
CATEGORIES:EDA,Webinar
ATTACH;FMTTYPE=image/jpeg:https://marketingeda.com/wp-content/uploads/Ansys-February-13-2024-1.jpg
END:VEVENT
BEGIN:VEVENT
DTSTART;TZID=Europe/Paris:20240213T100000
DTEND;TZID=Europe/Paris:20240213T110000
DTSTAMP:20240205T215030Z
CREATED:20240205T215030Z
LAST-MODIFIED:20240205T215030Z
UID:7578-1707818400-1707822000@marketingeda.com
SUMMARY:Power Innovations in Consumer Electronics Using LF EM Solutions
DESCRIPTION:This webinar will cover how the Ansys simulation tools are now widely used in many low-frequency (LF) EM applications\, such as wireless charging\, power supplies\, transformers\, magnetic latches and actuators\, PCB/ECAD\, and more. Discover how Ansys Maxwell enables rapid and accurate simulation of EM fields in electronic and consumer devices to reduce design iterations\, component footprint\, size\, and time to market. \n\n\n\n\nWhat You Will Learn\n\nComponent design considerations for consumer electronics devices (i.e.\,smartphones\, tablets\, watches\, earbuds\, and digital cameras)\nAnsys Maxwell solution for EM component design\nNew Maxwell capabilities for PCB and ECAD\nMultiphysics workflows for coupling EM with structural/kinematic\, NVH\, and thermal for comprehensive product design\n\nWho should attend?\nPCB Designers\, Consumer Electronics Engineers\, Systems Engineers\, Power Solutions Engineers\, SI/PI Engineers\, Product Design Engineers\, Power Module Engineers \nSpeakers\nIrene Woyna
URL:https://marketingeda.com/event/power-innovations-in-consumer-electronics-using-lf-em-solutions/
CATEGORIES:EDA,Webinar
ATTACH;FMTTYPE=image/jpeg:https://marketingeda.com/wp-content/uploads/Ansys-February-13-2024.jpg
END:VEVENT
BEGIN:VEVENT
DTSTART;TZID=America/Los_Angeles:20240208T100000
DTEND;TZID=America/Los_Angeles:20240208T110000
DTSTAMP:20240122T184006Z
CREATED:20240122T183940Z
LAST-MODIFIED:20240122T184006Z
UID:7546-1707386400-1707390000@marketingeda.com
SUMMARY:Seamless SI/PI Signoff of Allegro PCB Designs Driven by In-Design Analysis
DESCRIPTION:Signal and power integrity (SI/PI) are top priorities for engineers designing today’s high-speed\, high-density PCBs. Easy-to-use in-design analysis directly integrated into the Allegro PCB design environment uncovers SI/PI issues early in the design process\, leading to faster signoff of designs. With analysis shifting left in the design cycle\, design teams can achieve efficient signoff of high-speed PCB designs that include complex power delivery networks\, gigabit-speed serializer/deserializer (SerDes)\, and the latest double-data rate (DDR) memory interfaces. \nLearn about three key issues that engineers must overcome to sign off on high-speed PCB designs: serial link compliance (SerDes)\, power analysis\, and DDR memory interface compliance. We will demonstrate how Cadence’s PCB design methodology\, including Sigrity Aurora\, Sigrity SystemSI\, and Allegro technologies\, empowers EEs to create successful products on time and on budget.\nAttendees will learn to address: \n\nSerDes compliance\nPower analysis\nDDR memory interface compliance
URL:https://marketingeda.com/event/seamless-si-pi-signoff-of-allegro-pcb-designs-driven-by-in-design-analysis/
CATEGORIES:EDA,Webinar
ATTACH;FMTTYPE=image/jpeg:https://marketingeda.com/wp-content/uploads/Cadence-February-8-2024.jpg
END:VEVENT
BEGIN:VEVENT
DTSTART;TZID=America/Los_Angeles:20240208T100000
DTEND;TZID=America/Los_Angeles:20240208T103000
DTSTAMP:20240118T213134Z
CREATED:20240118T213134Z
LAST-MODIFIED:20240118T213134Z
UID:7526-1707386400-1707388200@marketingeda.com
SUMMARY:Power Devices SPICE Modeling for Si\, GaN and SiC Technologies
DESCRIPTION:We start by examining the different technologies used in the manufacturing of power devices\, including Si\, GaN\, and SiC\, considering their respective particularities and advantages.\nWe will then analyze various approaches to the SPICE modeling of power devices\, including compact models and macromodels.\nA significant portion of our presentation will be dedicated to the topic of power FET modeling. In particular we will illustrate how to properly address its specific bias-dependent capacitances and how to deal with model tuning based on dynamic characteristics.\nFinally\, we will share some of our expertise in dealing with the unique challenges of power devices\, including parasitic elements and model accuracy. \nWhat You Will Learn\n\nSPICE models for GaN and SiC FET\nModeling power FET-specific capacitances\nGeneral power FET model extraction methodology\nAdvantages of TCAD-based SPICE modeling\nSPICE modeling examples of Si\, GaN\, and SiC devices\n\n\n\n\n\n\nPresenter\n\n\n\n\nBogdan Tudor\, Senior Manager\, Device Characterization \nBogdan Tudor is Head of Device Characterization for Silvaco\, leading the Utmost and Modeling Service teams. He has over 20 years of experience in model development and characterization software. \n\n\n\n\n\nWHO SHOULD ATTEND:\n\n\n\n\nSemiconductor Device and Process engineers\, product managers\, and engineering management.
URL:https://marketingeda.com/event/power-devices-spice-modeling-for-si-gan-and-sic-technologies/
CATEGORIES:EDA,Webinar
ATTACH;FMTTYPE=image/jpeg:https://marketingeda.com/wp-content/uploads/Silvaco-February-8-2024.jpg
END:VEVENT
BEGIN:VEVENT
DTSTART;TZID=America/New_York:20240207T090000
DTEND;TZID=America/New_York:20240207T100000
DTSTAMP:20240202T014858Z
CREATED:20240202T014858Z
LAST-MODIFIED:20240202T014858Z
UID:7571-1707296400-1707300000@marketingeda.com
SUMMARY:Design Exploration of RF GaN Amplifier\, 3D Packaging\, and Thermal Analysis
DESCRIPTION:Join us for this webinar on RF GaN amplifier design using electromagnetic/thermal 3D solvers. We will discuss the step-by-step process of building a GaN amplifier\, beginning with the transistor model in the circuit simulator. The webinar will outline the steps required to convert this to a physical layout for electromagnetic simulation and verification while integrating packaging and thermal effects co-simulation to analyze a complete packaged system. Discover how this comprehensive approach yields innovative solutions\, important design insights\, and their potential impact on packaged performance. \nTime:\nFebruary 7\, 2024\n9 AM EST / 3 PM CET / 7:30 PM IST \nVenue:\nDigital
URL:https://marketingeda.com/event/design-exploration-of-rf-gan-amplifier-3d-packaging-and-thermal-analysis/
CATEGORIES:EDA,Webinar
ATTACH;FMTTYPE=image/jpeg:https://marketingeda.com/wp-content/uploads/Ansys-Feb-7-2024.jpg
END:VEVENT
END:VCALENDAR