-
ISPLED 2023
TU Wien Gußhausstraße 27-29/384, Vienna, AustriaThe International Symposium on Low Power Electronics and Design (ISLPED) is the premier forum for presentation of innovative research in all aspects of low power electronics and design, ranging from process technologies and analog/digital circuits, simulation and synthesis tools, system-level design and optimization, to system software and applications.
-
Synopsys Static Verification SIG 2023
Synopsys 675 Almanor Ave, Sunnyvale, CA, United StatesJoin us in-person on August 8th for the Synopsys Static Verification Special Interest Group (SIG) event. This event provides an opportunity for users, managers, and enthusiasts to stay connected with the latest innovations, techniques and methodologies. Attendees will hear about groundbreaking and successful applications and deployments of Synopsys VC SpyGlass RTL static signoff solution. Full agenda coming soon!
-
Flash Memory Summit
Santa Clara Convention Center 5001 Great America Parkway, Santa Clara, CA, United StatesWhy Attend Flash Memory Summit? Flash Memory Summit (FMS) is an all-inclusive international memory and storage showcase. It is the event for the memory and storage industry. It is the one-stop place to catch up on the latest technologies, see the hottest products, and learn about what's happening and where the latest trends are heading.… Flash Memory Summit
-
Deliver Next-gen Smartphones
Stefan Rosinger, Senior Director, Product Management – Arm About this talk Join us for a look at how the latest Arm Cortex compute cluster launched as part of Arm's Total Compute Solution 2023 can help OEMs deliver next-level immersion, AI intelligence and security while promoting greater efficiency in their mobiles, laptops, home, and wearable devices.… Deliver Next-gen Smartphones
-
Synopsys Formal Verification SIG 2023
Synopsys 675 Almanor Ave, Sunnyvale, CA, United StatesJoin us in-person on August 9th for the Synopsys Formal Verification SIG 2023 event. This event provides an opportunity for users, managers, and enthusiasts to stay connected with the latest innovations, techniques and methodologies. Attendees will hear about groundbreaking and successful applications and deployments of Synopsys VC Formal. Full agenda coming soon!
-
CadenceLIVE India
Radisson Blu Outer King Road, Bengaluru, IndiaCadenceLIVE India 2023 will be held on August 9-10 at the Radisson Blu Bengaluru Outer Ring Road. It features peer presentations that offer solutions for today’s design challenges that will impact tomorrow’s products. CadenceLIVE brings together users, developers, and industry experts to connect, share ideas, and inspire design creativity. Attendees have the opportunity to attend… CadenceLIVE India
-
Step-by-Step Guide for Your UCIe Design Verification
As traditional Moore’s law scaling approaches its physical limits, the industry is moving towards multi-die solutions for higher electronics system densities. Multi-die designs present one way for engineers to pack more functionality into silicon chips and improve yield without affecting fabrication feasibility or project budgets. The Universal Chiplet Interconnect Express (UCIe) standard was introduced in… Step-by-Step Guide for Your UCIe Design Verification
-
Dealing with Inconclusive Formal Proofs
Webinar Overview: Formal proofs of end-to-end properties can be a very valuable contribution to RTL sign-off and yet are often the most difficult to achieve. In this webinar Doulos Senior Member Technical Staff, Doug Smith will explore some practical ways of dealing with inconclusive formal proofs when using Jasper by Cadence . This includes the… Dealing with Inconclusive Formal Proofs
-
UCIe: On-Package Chiplet Innovation Opportunities
High-performance workloads demand on-package integration of heterogeneous processing units, on-package memory, and communication infrastructure to meet the demands of today’s data centers, autonomous vehicles, etc. On-package interconnects are a critical component to deliver the power-efficient performance for this evolving landscape. Universal Chiplet Interconnect Express (UCIe), is an open industry standard with a fully specified stack… UCIe: On-Package Chiplet Innovation Opportunities
-
Using Generative AI for ASIC Design
Tools like ChatGPT can be used for a variety of purposes, including writing Verilog. Unfortunately, these models are not (yet) perfect, and the quality of the output varies heavily depending on how you use them. Just as models may "hallucinate" facts they are not certain about, they can also "hallucinate" buggy and non-functional Verilog. In… Using Generative AI for ASIC Design
-
Advanced Analog Design Using S-parameters
This webinar highlights the importance of S-parameters to IC design and how Semtech Corporation, a high-performance semiconductor, IoT systems and Cloud connectivity service provider, utilizes Siemens AFS XT simulation technology to accelerate Semtech’s design process without compromising on accuracy to develop differentiated analog solutions for wired and wireless applications. Two case studies of analog circuits… Advanced Analog Design Using S-parameters
-
MIPI A-PHY & MASS – Revolutionizing Automotive Connectivity
1) Intro - MASS introduction 2) Usage - Full chip automotive systems from peripheral to processor and vice versa. E.g.Used in Radar, LiDAR, ADAS , etc. 3) APHY - PHY& Link layer for MASS 4) PAL - Protocol adaption layer for MASS 5) App - Application Layer For MASS like CSI2,DSI2, I2C, GPIO ,Includes FUSA protocols like CSE, DSE… MIPI A-PHY & MASS – Revolutionizing Automotive Connectivity
12 events found.