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Addressing 3D-IC Power Integrity Design Challenges
Power network design and analysis of 3D-ICs is a major challenge because of the complex nature and large size of the power network. In addition, designers must deal with the complexity of routing power through the interposer, multiple dies, through-silicon vias (TSVs), and through-dielectric vias (TDVs). In this webinar, you will learn how the Cadence… Addressing 3D-IC Power Integrity Design Challenges
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Leveraging Verisium Debug to Debug Digital-Mixed Signal Designs
Many of today’s designs that are primarily digital also contain analog components. We refer to such designs as “Digital-Mixed-Signal” or DMS designs. In this webinar, we will demonstrate using the Verisium Debug App to debug such DMS designs. What You Will Learn How Verisium Debug supports debugging Xcelium (Real Number Modeling) RNM and mixed Xcelium… Leveraging Verisium Debug to Debug Digital-Mixed Signal Designs
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Unleash Performance, Save Power: Mastering Processor Customization with the Tensilica Instruction Extension (TIE) Language
Join us for an engaging webinar where we show you how to turbocharge performance and minimize power consumption by harnessing the power of custom instructions using the TIE language. Don't miss this opportunity to optimize your processors like never before! TIE enables you to compute and move data many times faster than conventional processors, resulting… Unleash Performance, Save Power: Mastering Processor Customization with the Tensilica Instruction Extension (TIE) Language
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ORConf 2024
Gothenburg Gothenburg, SwedenOur 10th ORConf! The FOSSi Foundation is proud to announce the 10th installment of ORConf, a conference dedicated to free and open source silicon to be held over the weekend of Friday September 13 to Sunday September 15 in Gothenburg, Sweden. ORConf is a weekend of presentations and networking for the open source silicon community.… ORConf 2024
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46th Annual EOS/ESD Symposium & Exhibits
Peppermill Resort and Casino 2707 South Virginia Street, Reno, NV, United StatesThe EOS/ESD Symposium is dedicated to the understanding of issues related to electrostatic discharge and electrical transients/overstress, and the application of this knowledge to the solution of problems in consumer, industrial, and automotive applications, including electronic components, as well as in systems, subsystems, and equipment.
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IP-SoC Japan 24
Tokyo Convention Hall 3 Chome-1-1 Kyobashi, Toyo, JapanA worldwide connected Event !! D&R IP-SoC Japan 2024 Day is the unique worldwide Spring event fully dedicated to IP (Silicon Intellectual Property) and IP based Electronic Systems. IP-SoC providers, the seed of innovation in Electronic Industry, are invited to highlight their latest products and services and share their vision about the next innovation steps… IP-SoC Japan 24
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Managing Constraints Like a Pro in OrCAD X
Join us in this constraint-focused webinar to learn all the best practices for managing constraints in your design with OrCAD X Presto PCB Editor. We’ll cover everything from the basics of setting up spacing and physical constraints to advanced electrical constraints, which are critical for HDI designs. The webinar will feature a brief presentation, a… Managing Constraints Like a Pro in OrCAD X
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DVCon India 2024
Hotel Radission Blu, Marathalli ORR 90/4 Outer Ring Road, Bengaluru, IndiaOn behalf of the DVCon India 2024 steering committee, it is my pleasure to welcome you all to the 9th edition of the Design and Verification Conference in India planned from 18- 19th September 2024 in Bangalore, India. The theme of this year’s conference is “Architecture to Analytics – A2A“. We want to carry forward… DVCon India 2024
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Redefining Mobile Experiences with AI
The Arm platform is providing the foundation for the next wave of AI smartphones and laptops. As AI models rapidly evolve, we’re seeing that software begins to outpace hardware, requiring additional innovation at all levels of the compute stack. To meet these growing demands, the Arm platform offers a new compute solution for maximum performance… Redefining Mobile Experiences with AI
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A Beginner’s Guide to RTL-to-GDSII Front-End Flow
In this Training Webinar, explore the concepts of RTL design, design verification, and coverage analysis while unveiling the exciting world of front-end design flow. Walk through the essential steps in creating integrated circuits, the building blocks of modern electronics. This webinar provides practical knowledge, making it your gateway to understanding the magic behind RTL-to-GDSII front-end… A Beginner’s Guide to RTL-to-GDSII Front-End Flow
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FPGA Front Runner: FPGA Verification Strategies
Rolls Royce Control Systems 5000 Solihull Parkway, Birmingham, United KingdomTime Speaker Details 09.30 Arrival and Registration 10.00 Dave Sanders, Rolls-Royce Overview of Rolls Royce @ Solihull Presentation Title - Rolls-Royce… the past, the present and the future Abstract - Rolls-Royce has come a long way since its inception as a car manufacturer at the start of the twentieth century, for starters it doesn’t make cars anymore!… FPGA Front Runner: FPGA Verification Strategies
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TSMC North America OIP Ecosystem Forum 2024
Santa Clara Convention Center 5001 Great America Parkway, Santa Clara, CA, United StatesLearn About: Emerging advanced node design challenges and corresponding design flows and methodologies for A16, N2 and N3 processes Latest updates on TSMC 3DFabric™ chip stacking and advanced packaging processes, InFO, CoWoS®, and SoIC, 3DFabric Alliance, and 3Dblox™ standard, plus innovative 3Dblox-based design enablement technologies and solutions, targeting HPC, AI/ML, and mobile applications Comprehensive design… TSMC North America OIP Ecosystem Forum 2024
12 events found.