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BEGIN:VEVENT
DTSTART;TZID=Europe/London:20240903T120000
DTEND;TZID=Europe/London:20240903T130000
DTSTAMP:20240731T161732Z
CREATED:20240731T161715Z
LAST-MODIFIED:20240731T161732Z
UID:8191-1725364800-1725368400@marketingeda.com
SUMMARY:DVClub Europe - September 2024
DESCRIPTION:This DVClub event will have talks on verification of low power features of VLSI designs\, discussing strategies for accurately measuring power consumption and ensuring that power-saving mechanisms are effective. Additionally\, speakers will share insights on how to simulate and analyze different power scenarios to identify potential issues and optimize power management techniques. Attendees will have the opportunity to learn best practices for low power verification and gain valuable knowledge on how to successfully implement energy-efficient designs in their projects. Overall\, this event promises to provide valuable insights and practical strategies for ensuring the success of low power verification in VLSI designs. \nAgenda (BST)\n12:00 Welcome and Introduction – Mike Bartley\, Tessolve\n12:00 Satinder Paul\n12:20 Synopsys\n12:40 TBD\n13:00 Close
URL:https://marketingeda.com/event/dvclub-europe-september-2024/
LOCATION:CA
CATEGORIES:EDA,Webinar
ATTACH;FMTTYPE=image/jpeg:https://marketingeda.com/wp-content/uploads/DVClub-Europe-2024.jpg
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BEGIN:VEVENT
DTSTART;TZID=America/Los_Angeles:20240829T100000
DTEND;TZID=America/Los_Angeles:20240829T110000
DTSTAMP:20240808T172706Z
CREATED:20240808T172706Z
LAST-MODIFIED:20240808T172706Z
UID:8222-1724925600-1724929200@marketingeda.com
SUMMARY:Micron Utilizes Silvaco’s Fab Technology Co-Optimization for Development and Manufacturing of Memory Technologies
DESCRIPTION:Memory products from Micron Technology\, such as DRAM components and 3D NAND\, are propelling the advancement of process technologies. Innovative modeling methods are required to tackle the complexities in fabricating structures and to evaluate process variation effects on electrical performance. \nThis webinar highlights how Micron Technology utilizes Silvaco’s Fab Technology Co-Optimization (FTCOTM) platform for the development and manufacturing of advanced memory technologies. Use cases demonstrate the application of virtual process models\, sensitivity analysis\, and stress modeling to optimize semiconductor processes. The collaborative effort between Silvaco and Micron shows how to build a digital twin of a fabrication process\, enabling a transformative solution for scaling memory technologies. \n\n\n\n\nPresenter\n\n\n\n\nSumeet Pandey\, Distinguished Member of Technical Staff\, Micron Technology \n\n\n\n\nWHO SHOULD ATTEND:\n\n\n\n\nTCAD engineers\, fab engineers\, process engineers\, product managers\, and engineering management.
URL:https://marketingeda.com/event/micron-utilizes-silvacos-fab-technology-co-optimization-for-development-and-manufacturing-of-memory-technologies/
LOCATION:CA
CATEGORIES:EDA,Webinar
ATTACH;FMTTYPE=image/jpeg:https://marketingeda.com/wp-content/uploads/Silvaco-August-29-2024.jpg
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BEGIN:VEVENT
DTSTART;TZID=Asia/Tokyo:20240829T080000
DTEND;TZID=Asia/Tokyo:20240829T170000
DTSTAMP:20240805T220150Z
CREATED:20240805T220150Z
LAST-MODIFIED:20240805T220150Z
UID:8198-1724918400-1724950800@marketingeda.com
SUMMARY:DVCon Japan 2024
DESCRIPTION:The Design & Verification Conference & Exhibition is the premier conference on the application of languages\, tools\, methodologies and standards for the design and verification of electronic systems and integrated circuits. The focus of this highly technical conference is on the practical aspects of these technologies and their use in leading-edge projects to encourage attendees to adopt similar techniques to improve their own design and verification flows. \n\n\n\nDVCon Japan 2024 will be held on August 29\, 2024 in Shinagawa\, Tokyo. \nDVCon (Design and Verification Conference) is a conference mainly sponsored by Accellera Systems Initiative. DVCon focuses on solving problems in a wide range of areas such as logic design\, architecture study\, functional verification\, HW/SW co-verification\, analog simulation\, functional safety compliance\, security verification\, and application of AI to development flow in semiconductors and systems\, DVCon is the premier conference for learning and discussing best practices in the application of IEEE and Accellera standard languages\, formats\, and methodologies. \nDVCon has been held in the U.S. for more than 30 years and has been held in Japan since 2022\, with online and on-demand delivery in 2022 and in-person in 2023. We were able to offer a diverse and in-depth program with a variety of paper presentations\, tutorial sessions\, and exhibits from sponsors and exhibitors. We would like to thank all the audiences\, presenters\, sponsors\, and all those involved. \nDVCon Japan 2024 will be held at a venue that is only a 3-minute walk from the Takanawa Exit of Shinagawa Station. The morning sessions will consist of general sessions and panel discussions\, and the afternoon will be technical sessions including many paper presentations and tutorials. DVCon is a forum for sharing and discussing the latest information in a wide variety of areas including functional verification strategies\, SystemVerilog\, UVM\, UPF\, SystemC\, PSS\, formal verification methodologies\, HLS\, AMS\, IP-XACT\, and more\, and discussion in a wide variety of fields. It is also a great opportunity to meet and mingle with other attendees\, presenters and attendees\, sponsors\, and Accellera representatives. I \nWe encourage designers\, engineers\, and managers to attend. We look forward to seeing you there. Finally\, I would like to take this opportunity to thank our Gold and Silver Sponsors and Supporters for their support of the event\, as well as the Information Processing Society of Japan and IEEE CEDA AJJC for their sponsorship. \nDVCon Japan 2023 General Chair : Genichi Tanaka
URL:https://marketingeda.com/event/dvcon-japan-2024/
LOCATION:TKP Garde CIty Premium – Shinagawa Takanawa\, Tokyo\, TKP Garden City Premium\, Tokyo\, Japan
CATEGORIES:Conference,EDA
ATTACH;FMTTYPE=image/jpeg:https://marketingeda.com/wp-content/uploads/DVCon-Japan-2024.jpg
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BEGIN:VEVENT
DTSTART;TZID=America/Los_Angeles:20240829T080000
DTEND;TZID=America/Los_Angeles:20240829T170000
DTSTAMP:20240729T162620Z
CREATED:20240729T162620Z
LAST-MODIFIED:20240729T162620Z
UID:8188-1724918400-1724950800@marketingeda.com
SUMMARY:GlobalFoundries Technology Summit 2024 - North America
DESCRIPTION:The annual GTS conference brings GF executives and technologists together with customers and partners to discuss the latest breakthroughs and innovations in the semiconductor industry.
URL:https://marketingeda.com/event/globalfoundries-technology-summit-2024-north-america/
LOCATION:Santa Clara Convention Center\, 5001 Great America Parkway\, Santa Clara\, CA\, 95054\, United States
CATEGORIES:Foundry,IP
ATTACH;FMTTYPE=image/jpeg:https://marketingeda.com/wp-content/uploads/GlobalFoundries-2024.jpg
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BEGIN:VEVENT
DTSTART;TZID=America/Los_Angeles:20240828T080000
DTEND;TZID=America/Los_Angeles:20240828T090000
DTSTAMP:20240809T162606Z
CREATED:20240809T162606Z
LAST-MODIFIED:20240809T162606Z
UID:8225-1724832000-1724835600@marketingeda.com
SUMMARY:Design\, Integrate\, Analyze and Manage with Allegro X
DESCRIPTION:Designing PCBs in today’s world means using multiple tools to get the job done. The Allegro X Design Platform allows you to access all these tools in one unified design environment. \nJoin us to discuss how you can reduce your cycle time\, ensure product reliability and get first-time-right designs with Allegro X. \n\nTopics we’ll cover during the webinar: \n\nHierarchical and multi-board design\nReliability analysis covering electrical overstress (EOS) and mean time between failure (MTBF)\nFloor planning and in-design analysis with integrated Cadence Celsius Solver\nConstraint-driven design to ensure functionality and manufacturability\nAnd how to utilize DesignTrue DFM to reduce costly manufacturing failures\n\n\nSpeakers: \nSaankhya Parekh\, Lead Product Engineer\, Cadence \nPablo Barraza\, Lead Application Engineer\, Cadence \nHost: \nSupreeth Mannava\, Sr. Principal Product Manager\, Cadence
URL:https://marketingeda.com/event/design-integrate-analyze-and-manage-with-allegro-x/
LOCATION:CA
CATEGORIES:EDA,Webinar
ATTACH;FMTTYPE=image/jpeg:https://marketingeda.com/wp-content/uploads/Cadence-August-28-2024.jpg
END:VEVENT
BEGIN:VEVENT
DTSTART;TZID=America/Los_Angeles:20240827T090000
DTEND;TZID=America/Los_Angeles:20240827T180000
DTSTAMP:20240814T180313Z
CREATED:20240814T175832Z
LAST-MODIFIED:20240814T180313Z
UID:8240-1724749200-1724781600@marketingeda.com
SUMMARY:Siemens EDA Custom IC Verification Forum - Austin\, TX
DESCRIPTION:Join us and learn how Siemens’ intelligent Custom IC Verification platform is transforming the custom IC verification landscape with AI-powered methods and the latest in circuit simulation technology! Our expert speakers will provide insight on IC verification topics such as circuit simulation\, mixed signal verification\, nominal to high-sigma variation analysis\, library characterization\, and IP QA. With customer testimonials presented in each session\, this event offers a great opportunity to learn how others within the electronic design community are using our solutions to solve their most complex real-world challenges. \n9:00 am – 9:30 am\nRegistration & Continental Breakfast \n9:30 am – 10:00 am\nIndustry Keynote \n10:00 am – 10:45 am\nIntroducing AI-accelerated Solido Simulation Suite for intelligent IC design and verification \n10:45 am – 11:30 am\nAccelerating SPICE accurate verification with Solido SPICE and Solido LibSPICE for analog\, mixed-signal\, RF\, 3D-IC and library IP applications \n11:30 am – 12:00 pm\nAccelerating memory and analog functional verification with Solido FastSPICE \n12:00 pm – 1:00 pm\nLunch \n12:30 pm – 1:00 pm\nKeynote – AI in EDA \n1:00 pm – 1:30 pm\nIndustry’s fastest mixed-signal simulation with Symphony for complex IC designs \n1:30 pm – 2:15 pm\nUtilizing AI-powered Solido Design Environment to accelerate production-accurate SPICE verification from nominal to high-sigma \n2:15 pm – 2:30 pm\nAfternoon Break \n2:30 pm – 3:15 pm\nAccelerating characterization and STA workflows with AI-powered Solido Characterization Suite \n3:15 pm – 4:00 pm\nTrust but verify your IP: Comprehensive IP QA with Solido IP Validation Suite \n4:00 pm – 6:00 pm\nReception and Golf Event
URL:https://marketingeda.com/event/siemens-eda-custom-ic-verification-forum-austin-tx/
LOCATION:Topgolf Austin\, 2700 Esperanza Crossing\, Austin\, TX\, 78758\, United States
CATEGORIES:EDA
ATTACH;FMTTYPE=image/jpeg:https://marketingeda.com/wp-content/uploads/topgolf.jpg
END:VEVENT
BEGIN:VEVENT
DTSTART;TZID=America/Los_Angeles:20240827T090000
DTEND;TZID=America/Los_Angeles:20240827T170000
DTSTAMP:20240827T162200Z
CREATED:20240827T162200Z
LAST-MODIFIED:20240827T162200Z
UID:8279-1724749200-1724778000@marketingeda.com
SUMMARY:Q3 Memory Fabric Forum
DESCRIPTION:Memory fabrics unlock the power to pool\, tier\, and share memory in a data center fabric. The results will be vastly more memory capacity and lower cost due to higher utilization—the things needed to support memory-hungry generative AI apps. \n  \nAttend this webinar for a comprehensive update on CXL® market adoption\, technology\, products\, and use cases. \n\nRegister to attend and/or watch on YouTube after the event. \n  \nPart 1 – Industry Landscape. Highlighted by the presentation at 9:10 PT by Samsung of a “Moonshot” project to leapfrog from 10\,000 AI cluster nodes to 1\,000\,000 nodes. \nPart 2 – Technologies and products for the Enterprise. Highlighted by an overview from NVIDIA at 12:09 PT of their portfolio of high-bandwidth\, low-latency networking products for AI. \nPart 3 – Technologies and products for developers. Highlighted by new CXL forecast data presented by Montage at 1:26 PT. \n  \nBest\, Frank Berry\, VP of Marketing at MemVerge.\n\n\n \n\n\n\n\n\n \n\n\nQ3 Memory Fabric Forum Agenda \nRegister to attend\n\n\n \n\n\n\n\n\n\nIndustry Landscape\n\n\n1\n9:00 PT\nFrank Berry\nMemVerge\nThe AI Big Bang\n\n\n2\n9:10 PT\nSiamak Tavallaei\nSamsung\nAt-scale Systems: Interconnecting Massively Parallel xPUs\n\n\n3\n9:41 PT\nKurtis Bowman\nCXL Consortium\nCXL® Advancing Coherent Connectivity\n\n\n4\n9:53 PT\nJim Handy\nObjective Analysis\nCXL Is Exciting\, But Where is It Headed?\n\n\n5\n10:16 PT\nMark Nossokoff\nHyperion Research\nHPC/AI Market Update and Industry Composability Snapshot\n\n\n6\n10:32 PT\nJack Gidding\nSTAC Research\nSTAC Overview\n\n\n7\n10:46 PT\nSeth Friedman\nLiquid Markets\nLiquid-Markets-Solutions: Introduction to UberNIC\n\n\nTechnology and Products for the Enterprise\n\n\n8\n11:10 PT\nAnil Godbole\nIntel\nIntel Compute Express Link™ Enablement\n\n\n9\n11:25 PT\nMichael Abraham\nMicron\nCXL-Compatible Memory Modules\n\n\n10\n11:45 PT\nTorry Steed\nSMART Modular\nCXL Memory Expansion Advantages\n\n\n11\n12:09 PT\nReggie Reynolds\nNVIDIA\nNVIDIA Networking for HPC\, AI\, and Accelerated IO\n\n\n12\n12:41 PT\nSteve Scargall\nMemVerge\nMemory Machine™ for CXL\n\n\n13\n1:00 PT\nPhilip Maher\nMSI\nS2301 CXL Memory Expansion Server\n\n\nTechnology and Products for the Enterprise\n\n\n14\n1:08 PT\nMichael Ocampo\nAstera Labs\nAccelerating AI & ML with CXL-Attached Memory\n\n\n15\n1:26 PT\nGeof Findley\nMontage\nCXL 2.0 Use Case: Using Both DDR4 & DDR5 on the Same Server\n\n\n16\n1:43 PT\nJP Jiang\nXConn\nCXL Switch for Scalable & Composable Memory Pooling/Sharing\n\n\n17\n2:05 PT\nGary Ruggles\nSynopsys\nEnabling New Memory Applications Using CXL IP\n\n\n18\n2:37 PT\nNilesh Shah\nZeroPoint\nHyperscale Composable Memory Systems with Dynamically Adjusting Compressed Tier\n\n\n19\n3:00 PT\nGrant Mackey\nJackrabbit Labs\nYou Don’t Know Jack: CXL Fabric Orchestration and Management\n\n\n20\n3:19 PT\nBill Gervasi\nWolley\nNVMe Over CXL: How CXL Lets Us Do Controller Memory Buffers the Right Way\n\n\n21\n3:39 PT\nBill Gervasi\nWolley\nFleX: Bringing CXL to the Motherboard\n\n\n22\n3:59 PT\nBill Gervasi\nWolley\nCXL Native Memory: Do We Really Need DDR?\n\n\n23\n4:20 PT\nArvind Jagannath\nVMware\nVMware Memory Tiering: Customer-Ready Today
URL:https://marketingeda.com/event/q3-memory-fabric-forum/
LOCATION:CA
CATEGORIES:Forum,IP
ATTACH;FMTTYPE=image/jpeg:https://marketingeda.com/wp-content/uploads/Q3-Memory-Fabric-Forum.jpg
END:VEVENT
BEGIN:VEVENT
DTSTART;TZID=America/Los_Angeles:20240825T080000
DTEND;TZID=America/Los_Angeles:20240827T170000
DTSTAMP:20240712T004207Z
CREATED:20240712T004207Z
LAST-MODIFIED:20240712T004207Z
UID:8141-1724572800-1724778000@marketingeda.com
SUMMARY:Hot Chips 2024
DESCRIPTION:Hot Chips 2024 will be held as a hybrid conference with in-person attendance at Memorial Auditorium\, Stanford University from August 25 to 27\, 2024. \nConference Format\nHot Chips 2024 is a hybrid conference. You may register to attend Virtually or In-Person. The In-Person conference is held at Memorial Auditorium\, Stanford University. \n\nTutorials: Sunday\, August 25\nConference: Monday-Tuesday\, August 26-27\n\nVirtual Conference: Includes full access to conference videos\, presentation PDFs\, and Slack channels for BOTH tutorial and conference days. All talks are transmitted in real time and are also recorded so they may be viewed later. Details are here. \nIn-Person Conference: Includes all on-line access described above for the Virtual Conference. In addition\, In-Person registration includes breakfast\, lunch\, break snacks and receptions on Sunday and Monday evenings. \nIn-Person registrations options: \n\nConference Days only (includes Sunday evening reception)\nBoth Conference and Tutorial Days\n\nThere is no registration option for the Tutorial Day only nor for single session attendance. \nRegistration Deadlines\nEarly Registration Deadline: 11:59 PM (PDT) Friday\, August 02\, 2024. \nPlease Read: General Registration Policies.
URL:https://marketingeda.com/event/hot-chips-2024/
LOCATION:Memorial Auditorium\, 551 Jane Stanford Way\, Stanford\, CA\, 94305\, United States
CATEGORIES:Conference,IP
ATTACH;FMTTYPE=image/png:https://marketingeda.com/wp-content/uploads/1681617277049-HC-Logo-Trasparent.png
END:VEVENT
BEGIN:VEVENT
DTSTART;TZID=America/Los_Angeles:20240822T110000
DTEND;TZID=America/Los_Angeles:20240822T120000
DTSTAMP:20240819T162836Z
CREATED:20240819T162836Z
LAST-MODIFIED:20240819T162836Z
UID:8248-1724324400-1724328000@marketingeda.com
SUMMARY:Using OSVVM’s AXI4 Verification Components:  Pt 1 Creating the AXI4 Testbench / Test Harness
DESCRIPTION:European Session \nAbstract: \nThis “Getting Started” presentation is for engineers who need to use the OSVVM AXI4 verification components (VCs) in their testbenches. Part 1 of this presentation provides a detailed walkthrough of creating a testbench environment that uses AXI4 VCs. \nAXI4 VCs are probably the most complex VCs in the OSVVM library. This complexity is due to the AXI4 interface having five independent interfaces: Write Address\, Write Data\, Write Response\, Read Address\, and Read Data. Going further\, the interface supports user configurable optional aspects of the interface – such as the ID and User fields. \nIn this presentation we examine the details of the test harness including the required context references\, configuring the transaction interface\, configuring the AXI interface\, creating clock and reset\, connecting the DUT to the OSVVM AXI interface record\, and connecting to the AXI VCs. \nWe continue by examining how to size the AXI4 interface by sizing the unconstrained record elements of the AXI4 interface and OSVVM transaction interface records. \nWe wrap up by looking at how to use AXI4 VCs inside a DUT – such as with Zynq. In this situation\, the DUT does not have a port for the transaction interface(s). To address this use model\, OSVVM provides another set of AXI4 VCs that use OSVVM’s virtual transaction interface (VTI). These VCs all have Vti in their name\, such as Axi4ManagerVti.vhd. \nThe Zynq subordinate interfaces (such as Axi4Memory) can share the same memory space. As a result\, we look at how OSVVM configures multiple instances of the Axi4Memory to share their internal address space. \n\nAbout OSVVM \nOSVVM is a suite of libraries designed to streamline your VHDL entire verification process\, boosting productivity and reducing development time. Each library provides independent capabilities\, allowing selective adoption and a learn-as-you-go approach. Whether using directed or random testing\, OSVVM facilitates writing concise and readable test cases for both unit/RTL tests and complex FPGA and ASIC tests. \nOSVVM provides VHDL with verification capabilities that rival SystemVerilog + UVM. These include transaction-level modeling\, verification components\, co-simulation with software\, randomized test generation\, self-checking test support\, verification data structures\, comprehensive test reporting in HTML and text\, and synchronization primitives.\n\nWith OSVVM and a good team lead\, any VHDL engineer can do verification – and have fun doing it. As a result\, having your entire team united in using OSVVM will simplify deploying VHDL engineers to projects.\n\nSynthWorks has been using OSVVM for 25+ years in our training classes and consulting work. During that time\, we have innovated new capabilities and evolved our existing ones to increase re-use and reduce effort and time spent.\n\nWhy VHDL for verification? According to the 2022 Wilson Research Group Functional Verification Study\, in the FPGA market\, 66% use VHDL for design\, 58% use VHDL for verification\, and 28% use OSVVM. Hence\, VHDL is #1 for FPGA development and OSVVM is #1 for VHDL verification.\n  \n\nAgenda\n\n50 min presentation/live demo\n10 min Q&A\n\nPresenter Bio: \n \nJim Lewis\, VHDL Design and Verification Expert\, Trainer\, OSVVM developer\, and IEEE VHDL Chair \nJim Lewis is an innovator and leader in the VHDL community. He has 30 plus years of design and teaching experience. He is the Chair of the IEEE 1076 VHDL Standards Working Group. He is a co-founder of the Open Source VHDL Verification Methodology (OSVVM) and the chief architect of the packages and methodology. He is an expert VHDL trainer for SynthWorks Design Inc. In his design practice\, he has created designs for print servers\, IMA E1/T1 networking\, fighter jets\, video phones\, and space craft. \nWhether teaching\, developing OSVVM\, consulting on VHDL design and verification projects\, or working on the IEEE VHDL standard\, Mr. Lewis brings a deep understanding of VHDL to architect solutions that solve difficult problems in simple ways.
URL:https://marketingeda.com/event/using-osvvms-axi4-verification-components-pt-1-creating-the-axi4-testbench-test-harness/
LOCATION:CA
CATEGORIES:EDA,Webinar
ATTACH;FMTTYPE=image/jpeg:https://marketingeda.com/wp-content/uploads/Aldec-August-22-2024.jpg
END:VEVENT
BEGIN:VEVENT
DTSTART;TZID=Asia/Taipei:20240822T080000
DTEND;TZID=Asia/Taipei:20240822T170000
DTSTAMP:20240821T171827Z
CREATED:20240821T171827Z
LAST-MODIFIED:20240821T171827Z
UID:8262-1724313600-1724346000@marketingeda.com
SUMMARY:CadenceCONNECT Taiwan 2024
DESCRIPTION:CadenceCONNECT Taiwan event will introduce you to optimized design methodologies for electronics system applications. The event brings together Cadence technology users\, developers\, and industry experts for networking\, sharing best practices on critical design and verification issues and discovering new techniques for designing advanced silicon\, SoCs\, and systems. Don’t miss this opportunity to learn from industry experts and connect with peers in the electronics community. Registration is now open\, and seats are limited. \n\n\n\n\nWe introduce a new CadenceCONNECT Taiwan conference that encompasses a range of technology and vertical topics. \nCadenceCONNECT Taiwan 2024 will be held on August 22 at the Sheraton Hsinchu Hotel. CadenceCONNECT Taiwan provides a forum to share best practices on critical design implementation and verification issues\, and to discover inspiring new techniques for realizing advanced silicon\, system-on-chip (SoC ) designs\, and systems in different vertical markets. This event is organized to inspire and network with emerging technical experts to continue creating revolutionary possibilities with semiconductors. \nIn the face of today’s fierce international competition\, increasingly complex process development and application challenges\, design can not only realize creativity\, but also shape future innovation. Cadence has been based in Taiwan for more than 35 years and has always been the best assistant to local customers and partners. It will continue to work hard for electronic design innovation. This year\, the CadenceCONNECT Taiwan conference will be grandly presented at the Sheraton Hsinchu Hotel on August 22 (Thursday)\, providing an interactive platform to invite Cadence customers\, partners and industry elites to gather\, propose the best policies and case sharing for today’s electronic design\, and deeply discuss and exchange ideas for the future of Taiwan’s semiconductors\, and help and prosper together! \nThank you for your eagerness to register. Registration is now full! \nEvent Info\nEvent Date/Time: August 22\, 2024 (Thursday) 09:00-17:30PM \nVenue: 3F\, Sheraton Hsinchu Hotel \n\n\n\n\n\n\n\n\n\n\nKeynotes\nBe inspired by visionary keynotes as they discuss the latest trends and breakthrough technologies shaping the AI ​​era. \nChin-Chi Teng\nSenior Vice President and General Manager\nDigital & Signoff Group\, Cadence\n\n\n\nKS Pua\nFounder and CEO\nPhison Electronics\n\n\n\nAlbert Kuo\nHead of Automotive Business Unit\nRealtek\n\n\n\n\nCY Chang\nHardware and Operations Vice President\nMetanoia\n\n\n\nBen Gu\nCorporate Vice President\, Multi-Physics System Analysis Group\nCadence\n\n\nEunice Chiu\nVice President and General Manager Taiwan\nNVIDIA
URL:https://marketingeda.com/event/cadenceconnect-taiwan-2024/
LOCATION:Sheraton Hsinchu Hotel\, No. 265號\, E Section 1\, Guangming 6th Rd\, Zhubei City\, Taiwan
CATEGORIES:EDA,IP,User Group
ATTACH;FMTTYPE=image/jpeg:https://marketingeda.com/wp-content/uploads/Cadence-August-22-2024.jpg
END:VEVENT
BEGIN:VEVENT
DTSTART;TZID=America/Los_Angeles:20240820T110000
DTEND;TZID=America/Los_Angeles:20240820T130000
DTSTAMP:20240725T163046Z
CREATED:20240725T163046Z
LAST-MODIFIED:20240725T163046Z
UID:8180-1724151600-1724158800@marketingeda.com
SUMMARY:Mastering EMC Simulations for Electronic Designs
DESCRIPTION:Overview\nElectromagnetic Compatibility (EMC) simulation is critical for ensuring that electronic devices comply with regulatory standards and perform optimally in their intended environments. As the complexity of electronic systems increases\, the importance of EMC simulation grows\, allowing engineers to predict and mitigate potential electromagnetic interference (EMI) issues before physical prototypes are built. \nFor EMC and product design engineers\, it can be challenging to understand how to effectively use simulation tools. This hands-on session with experts in full-device simulation offers a unique opportunity for engineers to dive into the world of EMC simulation. This session will provide practical experience\, demystifying the simulation process and empowering engineers with the knowledge to implement simulations early in the design phase. Experts will offer insights into best practices\, common pitfalls to avoid\, and strategies for interpreting simulation results. \nBy participating in such a session\, engineers can gain a deeper understanding of the nuances of EMC simulation. They learn to set up simulations that model their products’ real-world behavior\, identify potential EMI issues\, and explore design modifications to enhance EMC performance. This proactive approach ensures compliance with regulatory standards and contributes to the final product’s overall reliability and quality. \nEMC simulation is more than just a compliance checkbox; it’s a strategic tool that\, when used effectively\, can significantly improve product design. Join this hands-on session guided by experts created for engineers looking to master EMC simulation and integrate it into their design process. It’s an investment in knowledge that will pay dividends throughout the product’s lifecycle. \n  \nWhat attendees will learn\n\nCAD File Preparation: Master importing mechanical CAD designs\, assigning materials\, and preparing for simulations.\n\n\nPCB and Package Setup: Discover the steps to import electronic design files for PCBs and packages\, including automation of the setup process.\n\n\nCable Specification: Gain hands-on experience in defining cables through co-simulation with multi-conductor transmission line solvers.\n\n\nComponent Modeling: Understand how to represent components using ideal or SPICE circuit models for co-simulation with 3D geometries.\n\n\nPerformance Evaluation: Learn to transform simulation results into formats that facilitate comparison with standard measurements for device performance assessment.\n\n  \nWho should attend\n\nFor Electromagnetic Compatibility Engineers: If your expertise lies in heuristic design guidelines and physical testing for compliance\, are you considering enhancing your capabilities with engineering simulation?\n\n\nFor Mechanical Design Engineers: Engaged in creating products with EMC requirements? Explore user-friendly simulation tools that can guide you toward compliance.\n\n\nFor RF Engineers: Charged with safeguarding your RF designs from the inadvertent interference of surrounding electronics? Discover methods to assess and mitigate RF desensitization risks earlier in the design process.\n\n\nFor Electrical Engineers Involved in designing PCBs and integrating components that must adhere to EMC regulations: Assess the need to account for the influence of enclosures and cables on EMC and signal and power integrity.
URL:https://marketingeda.com/event/mastering-emc-simulations-for-electronic-designs/
LOCATION:CA
CATEGORIES:EDA,Webinar
ATTACH;FMTTYPE=image/jpeg:https://marketingeda.com/wp-content/uploads/Ansys-august-20-2024.jpg
END:VEVENT
BEGIN:VEVENT
DTSTART;TZID=America/Los_Angeles:20240820T100000
DTEND;TZID=America/Los_Angeles:20240820T150000
DTSTAMP:20240723T174531Z
CREATED:20240723T174531Z
LAST-MODIFIED:20240723T174531Z
UID:8171-1724148000-1724166000@marketingeda.com
SUMMARY:Cloud Tech Day
DESCRIPTION:Join your fellow engineers and the Cadence Cloud team for an educational and networking event focused on developing a secure and scalable electronic design flow in the cloud. \nDate: August 20\, 2024\nTime: 10:00am – 3:00pm PDT\nLocation: Cadence HQ | 2655 Seely Avenue San Jose\, CA\, 95134 | Building 5 \n  \nWhat You Will Learn \n\nExciting new features and a roadmap view of Cadence Cloud\nStrategies and solutions for all-cloud or hybrid-cloud environment for your next design\nHands-on workshop: Experience running a design flow in Cadence Cloud\nMeet the R&D team behind the Cadence Cloud portfolio\n\nWho Should Attend \n\nThis free event is a terrific opportunity for design/CAD engineers\, CAD managers\, IT managers and business leaders seeking to optimize their design flow and technology infrastructure.\n\nLimited seating available\, register now to reserve your spot!
URL:https://marketingeda.com/event/cloud-tech-day/
LOCATION:Cadence Design Systems\, Building 5\, 2655 Seely Avenue\, San Jose\, CA\, 95131\, United States
CATEGORIES:EDA,Forum
ATTACH;FMTTYPE=image/jpeg:https://marketingeda.com/wp-content/uploads/Cadence-August-20-2024.jpg
END:VEVENT
BEGIN:VEVENT
DTSTART;TZID=America/Los_Angeles:20240815T110000
DTEND;TZID=America/Los_Angeles:20240815T120000
DTSTAMP:20240809T165235Z
CREATED:20240809T165235Z
LAST-MODIFIED:20240809T165235Z
UID:8228-1723719600-1723723200@marketingeda.com
SUMMARY:Why Should Our Team be Using VHDL + OSVVM for Verification?
DESCRIPTION:Abstract: \nThis is a high-level presentation that identifies the key aspects of a modern verification methodology and shows how to achieve them with OSVVM. This is a great presentation to share with your management about why OSVVM (and OSVVM training) is important for your team. \nDescription: \nDeveloping and deploying a verification methodology can be costly and time consuming. Going without one will be even more costly due to bugs escaping into production hardware systems.\n\nOpen Source VHDL Verification Methodology (OSVVM) provides the VHDL community with an already developed\, open-source solution. OSVVM implements all of the capabilities of a modern verification methodology: transaction-based testing\, a verification framework\, verification components\, self-checking tests\, messaging handling\, error tracking\, requirements tracking\, constrained random testing\, scoreboards\, functional coverage\, co simulation with software\, test automation\, and a comprehensive set of test reports.\n\nThis presentation examines how these capabilities will benefit your projects.\n\nSystemVerilog+UVM also provides a similar set of capabilities. Unfortunately\, SV+UVM ended up absurdly complex to use – instead of using a module (entity/architecture in VHDL) with its built-in concurrency\, SV+UVM uses OO\, sequential code\, and fork and join (to get concurrency). As a result\, SV has failed to unify the design and verification communities.\n\nVHDL+OSVVM on the other hand uses entity/architectures to create verification components and libraries of subprograms (procedures and functions) to extend VHDL into a complete verification language. In doing this\, OSVVM creates verification capabilities that rival SystemVerilog+UVM while at the same time it uses VHDL language elements that are familiar to VHDL design engineers.\n\nAs a result\, with VHDL+OSVVM and a good verification lead\, any VHDL engineer can do verification as well as RTL design.\n\n\nAbout OSVVM \nOSVVM is a suite of libraries designed to streamline your VHDL entire verification process\, boosting productivity and reducing development time. Each library provides independent capabilities\, allowing selective adoption and a learn-as-you-go approach. Whether using directed or random testing\, OSVVM facilitates writing concise and readable test cases for both unit/RTL tests and complex FPGA and ASIC tests. \nOSVVM provides VHDL with verification capabilities that rival SystemVerilog + UVM. These include transaction-level modeling\, verification components\, co-simulation with software\, randomized test generation\, self-checking test support\, verification data structures\, comprehensive test reporting in HTML and text\, and synchronization primitives.\n\nWith OSVVM and a good team lead\, any VHDL engineer can do verification – and have fun doing it. As a result\, having your entire team united in using OSVVM will simplify deploying VHDL engineers to projects.\n\nSynthWorks has been using OSVVM for 25+ years in our training classes and consulting work. During that time\, we have innovated new capabilities and evolved our existing ones to increase re-use and reduce effort and time spent.\n\nWhy VHDL for verification? According to the 2022 Wilson Research Group Functional Verification Study\, in the FPGA market\, 66% use VHDL for design\, 58% use VHDL for verification\, and 28% use OSVVM. Hence\, VHDL is #1 for FPGA development and OSVVM is #1 for VHDL verification.\n  \n\nAgenda\n\n50 min presentation/live demo\n10 min Q&A\n\n  \n\n\n\n\n\n\n\n\n\n\n\n\n\n\n\n\n\n\n\n\n\n\n\n\n\n\n\n\n\n\n\n\n\nPresenter Bio: \n \nJim Lewis\, VHDL Design and Verification Expert\, Trainer\, OSVVM developer\, and IEEE VHDL Chair \nJim Lewis is an innovator and leader in the VHDL community. He has 30 plus years of design and teaching experience. He is the Chair of the IEEE 1076 VHDL Standards Working Group. He is a co-founder of the Open Source VHDL Verification Methodology (OSVVM) and the chief architect of the packages and methodology. He is an expert VHDL trainer for SynthWorks Design Inc. In his design practice\, he has created designs for print servers\, IMA E1/T1 networking\, fighter jets\, video phones\, and space craft.\nWhether teaching\, developing OSVVM\, consulting on VHDL design and verification projects\, or working on the IEEE VHDL standard\, Mr. Lewis brings a deep understanding of VHDL to architect solutions that solve difficult problems in simple ways.
URL:https://marketingeda.com/event/why-should-our-team-be-using-vhdl-osvvm-for-verification/
LOCATION:CA
CATEGORIES:EDA,Webinar
ATTACH;FMTTYPE=image/jpeg:https://marketingeda.com/wp-content/uploads/Aldec-AUgust-15-2024.jpg
END:VEVENT
BEGIN:VEVENT
DTSTART;TZID=America/Los_Angeles:20240812T150000
DTEND;TZID=America/Los_Angeles:20240812T160000
DTSTAMP:20240731T170816Z
CREATED:20240731T170816Z
LAST-MODIFIED:20240731T170816Z
UID:8194-1723474800-1723478400@marketingeda.com
SUMMARY:Modeling and Simulation of Silicon Photonics Systems in SystemVerilog
DESCRIPTION:Silicon photonics systems integrate photonic components such as optical waveguides\, couplers\, resonators\, photodetectors\, etc. along with electronic components on the same silicon chip to realize high-bandwidth\, high-density\, and low-power communication via wavelength-division multiplexing (WDM). This talk will address the challenges of modeling and simulating silicon photonics WDM transceivers in SystemVerilog\, which contain photonic devices for WDM signaling\, analog interface circuits for pulse-amplitude modulation (PAM)\, and digital controllers for temperature calibration. It will show that the XMODEL’s way of expressing analog signals in the Laplace domain and computing them in an event-driven fashion can be extended to simulating optical waves\, even when they are treated as ~200 THz frequency signals. The talk will be given from a circuit designer’s perspective\, and those without prior background in silicon photonics are all welcome to join.
URL:https://marketingeda.com/event/modeling-and-simulation-of-silicon-photonics-systems-in-systemverilog/
LOCATION:CA
CATEGORIES:EDA,Webinar
ATTACH;FMTTYPE=image/jpeg:https://marketingeda.com/wp-content/uploads/Scientific-Analog-August-12-2024.jpg
END:VEVENT
BEGIN:VEVENT
DTSTART;TZID=America/Los_Angeles:20240806T100000
DTEND;TZID=America/Los_Angeles:20240806T110000
DTSTAMP:20240528T173110Z
CREATED:20240528T173009Z
LAST-MODIFIED:20240528T173110Z
UID:8063-1722938400-1722942000@marketingeda.com
SUMMARY:Fab.da: Comprehensive AI-Driven Process Analytics for Faster Ramp and Efficient High-Volume Manufacturing
DESCRIPTION:The challenges before semiconductor fabs are expansive and evolving. As the size of chips shrinks from nanometers to eventually angstroms\, the complexity of the manufacturing process increases in response. To combat the complexity and sheer intricacy of semiconductor manufacturing\, innovative software solutions are required. Synopsys Fab.da is a comprehensive process control solution that utilizes artificial intelligence (AI) and machine learning (ML) to allow for faster production ramp and efficient high-volume manufacturing. Fab.da is a part of the Synopsys.da Data Analytics solutions\, which brings together data analytics and insights from the entire chip lifecycle. It can analyze many petabytes of data originating from thousands of equipment in semiconductor fabs with zero downtime. Join the webcast to learn more about the Synopsys Fab.da. \n\n\n\n\n\n\n\n\n\n\nSpeakers\n\n\nListed below are the industry leaders scheduled to speak. \n\n\n\n\n\n\n\n\n\n\n\n\n\n\n\n\n\n\n\n\n\n\n\n\n\n\nVivek Jain\n\n\nProduct Management\, Principal\nSynopsys \n\n\n\n\n\n\n\n\n\n\n\nVivek Jain is an accomplished product management professional at Synopsys with a career distinguished by strong leadership and a proven record of contribution to lithography\, metrology\, and inspection products. He holds four issued patents in technologies that improve semiconductor fab efficiency and has a number of papers in publications. Vivek graduated from the Indian Institute of Technologies with a major in chemical engineering and\, since 2019\, has been a member of the technical committee of SEMI Advanced Semiconductor Manufacturing Conference (ASMC).
URL:https://marketingeda.com/event/fab-da-comprehensive-ai-driven-process-analytics-for-faster-ramp-and-efficient-high-volume-manufacturing/
LOCATION:CA
CATEGORIES:EDA,Webinar
ATTACH;FMTTYPE=image/jpeg:https://marketingeda.com/wp-content/uploads/Synopsys-August-6-2024.jpeg
END:VEVENT
BEGIN:VEVENT
DTSTART;TZID=America/Los_Angeles:20240806T080000
DTEND;TZID=America/Los_Angeles:20240808T170000
DTSTAMP:20240729T183004Z
CREATED:20240723T173747Z
LAST-MODIFIED:20240729T183004Z
UID:8167-1722931200-1723136400@marketingeda.com
SUMMARY:Future of Memory and Storage - 2024
DESCRIPTION:FMS: the Future of Memory and Storage is an all-inclusive international memory and storage showcase. It is the event for the memory and storage industry. It is the one-stop place to catch up on the latest technologies\, see the hottest products\, and learn about what’s happening and where the latest trends are heading. FMS is now the largest memory and storage industry show with the most high-level keynoters from leading companies\, the largest exhibits\, and the most sessions covering everything from applications and architectures through enterprise storage\, controllers\, and new technologies. \nOur industry continues to thrive and grow with new technology and more applications than ever. FMS has expanded to an all- inclusive memory and storage summit welcoming all emerging memory and storage solutions. The scope of FMS will include DRAM\, DNA data storage\, UCIe chiplet interconnects\, Compute Express Link (CXL)\, wearables\, automotive\, AI/ML\, data centers\, and entertainment applications\, along with 3D flash\, NVMe\, ZNS\, and important industry announcements. As one past attendee put it\, “Flash is a big society and FMS is the right show.”
URL:https://marketingeda.com/event/future-of-memory-and-storage-2024/
LOCATION:Santa Clara Convention Center\, 5001 Great America Parkway\, Santa Clara\, CA\, 95054\, United States
CATEGORIES:Conference,IP,Semiconductor
ATTACH;FMTTYPE=image/jpeg:https://marketingeda.com/wp-content/uploads/FMS-2024.jpg
END:VEVENT
BEGIN:VEVENT
DTSTART;TZID=America/Los_Angeles:20240725T100000
DTEND;TZID=America/Los_Angeles:20240725T110000
DTSTAMP:20240710T173759Z
CREATED:20240710T173759Z
LAST-MODIFIED:20240710T173759Z
UID:8128-1721901600-1721905200@marketingeda.com
SUMMARY:Applying Artificial Intelligence in Fab Technology Co-Optimization​​
DESCRIPTION:The common approach to optimize a fabrication process involves process and fab engineers creating and setting up Design of Experiments (DoEs) using a trial-and-error approach. This approach often leads to costly iterations since wafer fabrication is both expensive and time-consuming. Typically\, it can take weeks to months of experimentation\, depending on what process parameters are not meeting their targets. \nThe new approach described in this webinar\, already in production use today\, leverages artificial intelligence (AI) and machine learning (ML) to generate an accurate model of a fabrication step. The approach involves using TCAD digital models of a fab process (digital twin) that consider the actual physics and chemistry involved. This digital twin model is used to test and analyze using the same DoE methodology\, but without the need to fabricate multiple wafers\, thus saving the cycle times and costs associated with the fabrication. \nThis webinar will showcase this FTCO flow with examples to give you more insight into this flow and how you can apply it for you and your team’s needs. \nWhat You Will Learn \n\nIntroduction to FTCO\n\nDigital Twin\nMachine learning\nFab Technology Co-Optimization (FTCO)\nOverview of Silvaco’s tools enabling FTCO\n\n\nFTCO for Process Margin Analysis\n\nUse case example: STI trench modeling and optimization\n\n\nRTSM: A Real-Time 2D Structure Modeling Tool\nOther FTCO examples\n\nBio\nDr. Christian Caillat\, Senior Staff CAE\, Silvaco Inc. \nDr. Christian Caillat is a Senior Staff CAE at Silvaco\, based in Boise\, ID. Prior to joining Silvaco in June 2023\, he was with Micron Technology for 13 years\, where he contributed to various projects including emerging memory program collaboration with imec\, 3D NAND Cell team lead\, and advanced memory modeling. \nDr. Caillat holds an engineering degree in Electronics and a PhD in Microelectronics from the National Polytechnical Institute of Grenoble\, France.
URL:https://marketingeda.com/event/applying-artificial-intelligence-in-fab-technology-co-optimization/
LOCATION:CA
CATEGORIES:EDA,Webinar
ATTACH;FMTTYPE=image/jpeg:https://marketingeda.com/wp-content/uploads/Silvaco-July-25-2024.jpg
END:VEVENT
BEGIN:VEVENT
DTSTART;TZID=America/Los_Angeles:20240724T080000
DTEND;TZID=America/Los_Angeles:20240725T170000
DTSTAMP:20240711T164050Z
CREATED:20240711T160540Z
LAST-MODIFIED:20240711T164050Z
UID:8135-1721808000-1721926800@marketingeda.com
SUMMARY:Chiplets: Building the Future of SoCs
DESCRIPTION:Chiplets\, also known as heterogeneous multi-die systems\, are increasingly seen as the future of System on Chips (SoCs). They offer a solution to meet the growing demands of high-performance computing in various industries\, particularly fueled by the widespread adoption of AI technology. However\, while the concept of using chiplets to construct larger chips to overcome the limitations associated with building monolithic chips using advanced process technologies is promising in theory\, the practical implementation poses challenges. \nThe “Chiplets: Building the Future of SoCs” virtual event will delve into the complex considerations surrounding chiplet-based systems. Discussions will encompass the entire value chain and ecosystem\, spanning from initial concept and design exploration to packaging and testing. Moreover\, the event will examine the emergence of initiatives aiming to establish a chiplet marketplace\, exploring relevant standards and the actual feasibility of such endeavors. \nKey questions to be addressed include how to effectively integrate multiple dies from various foundries\, the methods for pre-validating these chips\, ensuring they meet specified standards\, and managing the integration of components and software. Additionally\, attention will be given to the development of a system integrator community\, strategies for enabling traceability and security within the chiplet supply chain\, and the potential economic viability of chiplet-based systems. \nCrucially\, the event will assess the industry’s readiness to foster the collaborative ecosystems necessary to support a chiplet economy. Will there be a proliferation of competing standards\, or will the industry converge around a unified standard like UCIe? Moreover\, the feasibility of economically designing chiplet-based systems will be scrutinized\, considering factors such as production costs and market demand. \n  \n\nWhat to expect?\nWith a conference space and resource center\, this event will function similarly to a live exhibition and conference. The conference includes keynotes\, panel discussions\, and technical presentations on a variety of subject matters\, including significant technical trends\, market demand and application areas. \nAttendees can expect an immersive exploration of the dynamic landscape of the chiplet and multi-die systems market. \nJuly 24: We’ll look at chiplet definitions\, standards\, and technologies. \nJuly 25: We’ll explore some real-world implementations of chiplet technologies\, and also the chiplet ecosystem. \n  \n\nWho should attend?\nBuilding future SoCs using chiplets involves a diverse range of disciplines\, making this event relevant to anyone involved in the value chain of constructing 2.5D\, 3D stacked heterogeneous systems that incorporate chiplet-style architectures. Whether you specialize in design\, validation\, packaging\, testing\, or provide services related to building these systems\, there will be valuable insights for you at this event. \nFrom automotive industry system developers to those working in data centers and beyond\, we’ll look to explore the technologies\, challenges\, opportunities\, and solutions. \nThis event caters to engineers\, researchers\, developers\, technical marketing professionals\, and industry professionals keen on understanding the potential opportunities and realities of working with and building chiplet-based systems. \n  \n\n\n\n\n\n\n\n  \n\n\n\n\n\n\n\n\n\n\nAgenda\n\n  \n\n\n\n\n\n\n\nAll Dates\n\n\n\n\n\n\n\n\n\nJuly 24 \n8:00 am – 8:10 am PDT \n\n\n\nOpening and start of the conference track “Chiplet Concepts – Principles and Promise”\n\nWelcome and Opening Nitin Dahad\, Editor-in-Chief\, Embedded.com \n\n\n\n\n\n\n\n\n\n\nJuly 24 \n8:10 am – 8:45 am PDT \n\n\n\n(CC1) Multi-Die Design in the Pervasive Intelligence Era\n\nThis Keynote is presented by Shankar Krishnamoorthy\, General Manager\, EDA Group\, Synopsys \nArtificial intelligence and silicon proliferation are shaping a new era of pervasive intelligence. At the forefront is the shift to multi-die\, driving the advancements of trillion-transistor systems and the march to angstroms. With its promise to enable significant compute performance\, heterogenous integration is a critical requirement in today’s AI-driven world. Join Shankar Krishnamoorthy\, the General Manager of Synopsys’ EDA Group\, as he explores the opportunities presented by multi-die design. \n\nRead More \n\n\n\n\n\n\n\n\n\nJuly 24 \n8:50 am – 9:25 am PDT \n\n\n\n(CC2) Universal Memory Interface (UMI): The solution to break the memory wall for AI ASICs\n\nThis Keynote is presented by Ramin Farjadrad is the founding CEO of Eliyan. \nCompute performance demand has been growing exponentially in recent years\, and with the advent of Generative AI\, this demand is growing even faster. Moore’s law coming to an end as well as the Memory Wall (memory bandwidth & capacity) and IO Wall are the main performance bottlenecks. The chiplet system-in-package (SiP) is the industry’s solution to these bottlenecks. Silicon interposers are industry’s main technology to connect chiplets in SiPs\, but they introduce several new bottlenecks. The largest interposer going to production is 2700mm2\, which is ~1/4 the largest standard package substrate. Thus\, a SiP with silicon interposer has limited compute & memory chiplets\, thus limited performance. This presentation introduces Universal Memory Interface (UMI)\, a high bandwidth efficient D2D connectivity technology between XPU-Memory & XPU-XPU\, which enables innovative architectures that help remove Memory & IO walls for next generation AI\, specifically Gen AI\, systems. \n\nRead More \n\n\n\n\n\n\n\n\n\nJuly 24 \n9:25 am – 9:35 am PDT \n\n\n\nTechnical Resources Time\n\nVisit the Resource Center which includes microsites from leading Chiplet companies with lots of technical information like White Papers\, Webinars\, Datasheets\, etc. \n\n\n\n\n\n\n\n\n\nJuly 24 \n9:35 am – 10:35 am PDT \n\n\n\n(CC3) The A to Z of Multi-Die Design\n\nThis Tutorial is presented by Tim Kogel\, Sr. Director for Technical Product Management\, Synopsys \nThis tutorial explains the intricacies of multi-die design\, covering topics from functional architecture and IP integration to implementation and signoff. It uses case studies to highlight the steps\, considerations\, and new innovations in multi-die designs. \n\n\n\n\n\n\n\n\n\n\nJuly 24 \n10:40 am – 11:25 am PDT \n\n\n\n(CC4) Panel Discussion: Taming Complexity – Building a Successful Open Chiplet Ecosystem\n\nThis Panel Discussion with industry experts is moderated by Nitin Dahad\, Editor-in-Chief\, Embedded.com. \nWhat is the current state of the commercial chiplet ecosystem\, and is a multi-company open ecosystem needed for chiplets to achieve their full potential? As we move from single company effort to a complex\, multi-supplier ecosystem\, we’ll discuss the biggest challenges we face\, including the need to manage and reduce supply chain complexity\, and doing so at reasonable cost. We’ll also talk about some of the practicalities. Do we have sufficient standards in place to enable the chiplet economy\, and is there appetite for industry and vendors to collaborate on these standards? Who takes ownership of the process when chiplets come from multiple suppliers\, and who is responsible for overall yield? And how do we ensure that all parts of the supply chain make money\, including smaller companies and startups? \nPanelists:\n– Ramin Farjadrad \, founding CEO\, Eliyan\n– Mohit Gupta\, Senior Vice President\, Alphawave Semi\n– Nick Ilyadis\, Vice President of Product Planning\, Achronix\n– Kenneth Larsen\, Product Management Director\, EDA Group\, Synopsys \n\nRead More \n\n\n\n\n\n\n\n\n\nJuly 24 \n11:25 am – 11:30 am PDT \n\n\n\nTechnical Resources Time\n\nVisit the Resource Center which includes microsites from leading Automotive companies with lots of technical information like White Papers\, Webinars\, Datasheets\, etc. \n\n\n\n\n\n\n\n\n\nJuly 24 \n11:30 am – 11:50 am PDT \n\n\n\n(CC5) Optimizing Next-Gen I/O Chiplet: Pioneering UCIe D2D Interconnects from 1.6 Terabits to 224 Gigabits\n\nPresented by Letizia Giuliano\, Vice President\, Alphawave Semi \nIn this presentation\, we will explore the benefits of adopting UCIe-enabled chiplet IP subsystems\, featuring state-of-the-art Multi-Standard SerDes I/O connectivity for advanced AI solutions. As the need for more powerful compute capability continues to grow\, the landscape and role of chiplets has become increasingly crucial for providing essential avenues for scalability\, efficiency\, and innovation in the infrastructure of next-generation AI data networks. We will review the obstacles associated with developing an interoperable 112G Multi-Lane and Multi-Standard I/O chiplet\, and share detailed implementation insights and outcomes from Alphawave Semi’s Chiplet portfolio. Furthermore\, we will demonstrate how AI connectivity use cases can be rapidly enhanced through the deployment of I/O Chiplets\, which are vital for today’s multi-Terabit I/O systems. The presentation will conclude with a discussion on the challenges facing the industry and propose solutions for advancing scale-up and scale-out connectivity options to meet the networking bandwidth demands of future AI systems. \n\nRead More \n\n\n\n\n\n\n\n\n\nJuly 24 \n11:50 am – 12:10 pm PDT \n\n\n\n(CC6) Chiplets for Everyone – Modular Re-usable Solution Powered by Patented Technology\n\nPresented by Kash Johal\, CEO and Founder\, YorChip \nToday\, Chiplets are primarily being deployed by MegaCap companies due to economics\, long lead-times\, and the complexity of development. QuickLogic and YorChip present a solution to deploy re-usable off-the-shelf Chiplets for everyone. Our solution empowers engineers at companies of any size to leverage chiplets:\n– Modular Chiplets: Ease connectivity and enable reuse across diverse customer designs.\n– Patented PHY: Supports both advanced and standard packaging\, lowering development cost and production deployment.\n– Legacy-Node PHY: Extends chiplet benefits to mix older process nodes (up to 90nm) with advanced nodes.\n– Routing Link Layer: Reduces Latency and helps eliminate signal integrity challenges.\n– AI Friendly: Chiplets specifically optimized for running Generative AI models at the edge. \nThe QuickLogic and YorChip collaboration empowers engineers at any size company to deploy chiplets for any application quickly and at low cost. \n\nRead More \n\n\n\n\n\n\n\n\n\nJuly 24 \n12:10 pm – 12:30 pm PDT \n\n\n\n(CC7) The Role of EDA as Chips Transform Into 3D Systems\n\nPresented by John Park\, Product Director\, Cadence \nWhat challenges will you face when pivoting from monolithic IC design to 3D heterogenous package design? How can electronic design automation (EDA) address these challenges? As we go from Moore’s Law to More-than-Moore\, technologies begin to converge across IC and systems design. This shift requires new advanced design flows combining EDA tools. These system-level design flows must enable seamless cross-domain co-design and analysis. The days of IC and package designers “throwing data over the wall” are over. Heterogeneous integration presents a new era of electronic product design with collaboration at its core – one that depends on the seamless interaction between analog/digital IC teams and package design teams. The use of advanced packaging technologies to combine smaller\, discrete chiplets into one SiP not only pushes the need for more advanced multi-die packaging\, but also makes packaging part of the process. This significantly reduces dependence on Moore’s Law at a time when building advanced monolithic SoCs is no longer the best option from a cost and technology perspective. \n\nRead More \n\n\n\n\n\n\n\n\n\nJuly 24 \n12:30 pm – 12:50 pm PDT \n\n\n\n(CC8) Taking 3DIC Heterogeneous Integration Mainstream\n\nPresented by Tony Mastroianni\, Advanced Packaging Solutions Director\, Siemens EDA \nHeterogeneous integration itself isn’t new\, but new design and manufacturing technologies\, combined with new product demands from system integrators\, means that heterogeneous integration and 3DIC are now becoming a necessity in mainstream design. This shift however is not without its challenges as 3D IC is not a simple extension of existing packaging solutions but creates a whole new set of Multiphysics integration considerations. The interaction of thermal\, mechanical\, reliability\, test\, and core semiconductor design increases complexity and requires disparate domains to seemly collaborate.In this presentation we will explore the challenges introduced by 3D IC\, the current state of the industry to address those challenges\, the ecosystem needed to support 3DIC\, and how users today can successfully adopt 3D IC leveraging new solutions\, workflows\, and 3D IC Design Kits (3D K) from Siemens EDA that are designed specifically with 3D IC in mind. \n  \n\nRead More \n\n\n\n\n\n\n\n\n\nJuly 24 \n12:50 pm – 1:10 pm PDT \n\n\n\n(CC9) UCIe Standard Versus UCIe Advanced – What Designers Need to Know\n\nPresented by Manuel Mota\, Principal Product Manager\, Synopsys \nThis technical presentation delves into the requirements and considerations for UCIe in standard and advanced packaging\, including density\, testing\, and the power and performance impact on the die-to-die implementation. The presentation will use real examples of UCIe silicon proofs to showcase the two variants of UCIe interfaces. \n\n\n\n\n\n\n\n\n\n\nJuly 24 \n1:10 pm – 1:20 pm PDT \n\n\n\nTechnical Resources Time\n\nVisit the Resource Center which includes microsites from leading Chiplet companies with lots of technical information like White Papers\, Webinars\, Datasheets\, etc. \n\n\n\n\n\n\n\n\n\nJuly 24 \n1:20 pm – 1:40 pm PDT \n\n\n\n(CC10) Celestial AI Photonic Fabric based 14.4Tbps Optical Chiplets for AI XPU Connectivity\n\nPresented by Dave Lazovsky\, CEO\, Celestial AI \nWith the growth in GenAI\, AI infrastructure is not just about the System on Chip but about the System of Chips. The bottleneck is no longer compute performance of a single XPU but scale-up interconnect bandwidth\, memory bandwidth and capacity. Photonic Fabric is the next generation optical interconnect technology offering >10X more performance than any competitive technology. Chiplets based on the Photonic Fabric and incorporating D2D interfaces like UCIe\, MAX3 etc are built in TSMC 5nm process and are fully compatible with standard 2.5D packaging flows for easy integration with XPUs. This enables XPUs to have optical interconnects for compute-to-compute and compute-to-memory fabrics that deliver Tbps bandwidth with nano-second latencies. XPUs can also seamlessly integrate with Photonic Fabric based memory solutions offering TBs of memory capacity at full HBM3 bandwidth. This innovation empowers hyperscalers to optimize the number of XPUs needed for training & inference\, improving the efficiency and economics of AI processing with significantly lower TCO2 impact. \n\nRead More \n\n\n\n\n\n\n\n\n\nJuly 24 \n1:40 pm – 2:00 pm PDT \n\n\n\n(CC11) Traceability and security for chiplet supply chain\n\nPresented by Jun Kawaguchi\, Marketing Executive\, Winbond \nThis presentation describes the issues relating to authenticity of individual chiplet and how to ensure the supply chain security is assured. A secure supply chain is becoming increasingly critical topic to counter cybersecurity concerns and the operation of critical systems such as infrastructure systems and autonomous vehicle application. There are trusted certification organizations that will audit and assure the supply chain to be intact\, however this becomes complex as multiple chiplets enter the supply chain. We will discuss these issues in the context of certified\, secure memory product that Winbond provides. \n\nRead More \n\n\n\n\n\n\n\n\n\nJuly 24 \n2:00 pm – 2:20 pm PDT \n\n\n\n(CC12) Innovations in AI Chip Packaging: Advanced Processes & Equipment Technologies\n\nPresented by Aaron Fellis\, Corporate Vice President\, Lam Research \nAs artificial intelligence (AI) continues to permeate diverse sectors\, from autonomous vehicles to healthcare\, there is increasing demand for more powerful and efficient AI chips. This has led to a paradigm shift\, with a focus not only on the performance of AI chips but also on their packaging. As the demand for higher processing power and energy efficiency grows\, advanced packaging becomes more essential to support these requirements\, driving sophisticated processes and equipment technologies that can handle the complexity of packaging AI chips. The presentation will shed light on equipment innovations and packaging methodologies that are shaping the future of AI chip technology. \n\nRead More \n\n\n\n\n\n\n\n\n\nJuly 24 \n2:20 pm – 2:55 pm PDT \n\n\n\n(CC13) Packaging matters: extending Moore’s law with “re-aggregation”\n\nThis Keynote is presented by Lalitha Immaneni\, VP of Semiconductor R&D\, Intel \nWith the arrival of ChatGPT\, Large Language Models (LLMs) have transformed AI into an interactive and accessible technology that recursively builds on its prior accomplishments\, fueling a new gold rush era of applications. AI models have exploded in complexity and size\, exerting demand pressure on both compute and memory. Over time\, Moore’s law has yielded a roughly 2x increase in compute every 2 years\, compared to the enormous 750x per year growth demand from the LLMs. Memory is an even trickier problem as it needs to address capacity\, speed and cost of data transport. Packaging plays a pivotal role in this era\, architecting bespoke solutions for a highly differentiated set of applications. We take a look at the role of disaggregation\, chiplets and interconnects in enabling the future of AI and HPC and illustrate this with solutions that can help create unique functionality\, performance\, and cost while enabling reuse and modularity. \n\nRead More \n\n\n\n\n\n\n\n\n\nJuly 24 \n2:55 pm – 3:15 pm PDT \n\n\n\n(CC14) Emerging Chiplet Ecosystems Enable Innovative Multi-Vendor Designs\n\nPresented by Elad Alon\, CEO and Co-Founder\, Blue Cheetah Analog Design \nChiplets reduce the rising costs of innovation. Heterogeneous compute\, especially AI applications\, stands to gain the most from chiplet-based designs. System architects are discovering that the keys to successful chiplet integration are an application-appropriate ecosystem and a customizable die-to-die (D2D) interconnect tailored for their end applications. \n\n\n\n\n\n\n\n\n\n\nJuly 25 \n8:00 am – 8:10 am PDT \n\n\n\nOpening and start of the conference track “Chiplet Technologies – Practicalities and Performance”\n\nWelcome and Opening by Sally Ward-Foxton\, Senior Reporter\, EE Times \n\n\n\n\n\n\n\n\n\n\nJuly 25 \n8:10 am – 8:45 am PDT \n\n\n\n(CP1) Jumpstart Your Chiplets Journey with End-to-End System Silicon Solutions\n\nThis Keynote is presented by David Glasco\, Vice President\, Compute Solutions Group\, Cadence. \nExplore the chiplet journey and gain insights into the reasons behind the increasing adoption of chiplets and the vital role that partners play in helping engineers succeed in their chiplet journey.  Learn how the right IP portfolio and IP teams can deliver on this journey with multiple engineering engagement models and strong industry partnerships.  See how design automation flows can help accelerate product time-to-market and reduce engineering costs. Understand how the design process can be automated and how virtual platforms and package design flows can significantly improve the engineering efficiency of chiplets. Join this keynote to discover the advantages and future potential of chiplets and how partners can help you succeed. \n\nRead More \n\n\n\n\n\n\n\n\n\nJuly 25 \n8:50 am – 9:25 am PDT \n\n\n\n(CP2) Chipletonomics : Economic foundation of future AI and HPC supercomputing.\n\nThis Keynote is presented by Sambit Sahu\, Senior Vice President at Krutrim\, an Ola company. \nThere is a huge surge in AI and HPC supercomputing currently and this will continue to accelerate. Generative AI explosion and associated multi-trillion dollar impact to revenue is triggering huge innovations in the AI space. HPC computing is on a rapid growth path with multiple supercomputers (multiple chips interconnected with high bandwidth and highly reliable network fabric and infrastructure) being built worldwide. Chiplets\, which are small pieces of silicon dies targeting a particular functionality\, are evolving rapidly as a concept and implementation style. In this presentation\, we will talk about how chiplets are going to address some of the key challenges of building next generation AI and HPC supercomputers. We will also demonstrate the significant economic advantages of chiplets architecture over conventional monolithic architectures. We will also demonstrate methodologies and approaches on how to use chiplets for your cost advantage. We will walk through how we are capitalizing on the chiplet strategy for economic advantage in building our high end AI server\, scaling upto a supercomputer. We will walk through strategies in optimizing NRE costs\, optimizing TCO\, optimizing on scaleout costs\, and optimizing on time to market\, and extending the benefits to additional products. \n\nRead More \n\n\n\n\n\n\n\n\n\nJuly 25 \n9:25 am – 9:35 am PDT \n\n\n\nTechnical Resources Time\n\nVisit the Resource Center which includes microsites from leading Chiplet companies with lots of technical information like White Papers\, Webinars\, Datasheets\, etc. \n\n\n\n\n\n\n\n\n\nJuly 25 \n9:35 am – 10:35 am PDT \n\n\n\n(CP3) Semiconductor design: Linking design to manufacturing for a sustainable semiconductor future\n\nTechnical Talk with Michael Munsey\, Vice President\, Siemens EDA and Sally Ward-Foxton\, Senior Reporter\, EE Times \nSemiconductor sustainability starts with design and the decisions made during the design process affect sustainability. This is amplified as we transition to the heterogeneous integration of chiplets using advanced substrate platforms such as 2.5/3D in order to continue silicon scaling. By linking the digital twins for semiconductor design to the digital twin of a semiconductor fab\, design details can be fed forward to optimize fabs for sustainability and manufacturing data can be fed back to optimize design libraries and decisions. In this talk\, we will talk about the evolution of the digital twin\, how new solutions aid design and manufacturability\, and the start of a new semiconductor era. \n\nRead More \n\n\n\n\n\n\n\n\n\nJuly 25 \n10:40 am – 11:25 am PDT \n\n\n\n(CP4) Panel Discussion: Lowering Barriers – Making Chiplets Work Together\n\nThis Panel Discussion with industry experts is moderated by Sally Ward-Foxton\, Senior Reporter\, EE Times. \nChiplets are attracting a lot of attention\, but which industries or verticals will benefit most from chiplets in the short term\, and why? We’ll start by talking about applications for chiplets and how they will evolve as the technology matures.We’ll discuss the biggest challenges to designing successful multi-die systems today. How do we ensure dies from different processes work together\, and what about dies designed by different companies? Are standards ready for this challenge\, and how are design tool vendors\, silicon vendors and IP providers taking it on? We’ll cover topics like multi-die system simulation\, emulation and verification\, and whether the complexity of these processes is limiting the size and scope of multi-die designs today. \nPanelists:\n– David Glasco\, Vice President\, Compute Solutions Group\, Cadence\n– Andreas Olofsson\, CEO\, Zero ASIC\n– Sambit Sahu\, Senior Vice President\, Krutrim\, an Ola company\n– John Sotir\, Senior Director\, Altera\, an Intel Company \n\nRead More \n\n\n\n\n\n\n\n\n\nJuly 25 \n11:25 am – 11:35 am PDT \n\n\n\nTechnical Resources Time\n\nVisit the Resource Center which includes microsites from leading Chiplet companies with lots of technical information like White Papers\, Webinars\, Datasheets\, etc. \n\n\n\n\n\n\n\n\n\nJuly 25 \n11:35 am – 12:10 pm PDT \n\n\n\n(CP5) Using composable chiplets to reduce ASIC design costs\n\nThis Keynote is presented by Andreas Olofsson\, CEO and founder of Zero ASIC. \nThe compounding effect of monolithic miniaturization on electronics has been nothing short of miraculous. Fifty plus years of Moore’s Law has resulted in a million fold improvement in computing cost and efficiency. Now that physical device scaling is approaching hard atomic limits\, the question is: Where will the next million fold computing efficiency improvement come from? Extreme domain specific circuit specialization can provide the next 1\,000 bost\, but the path is blocked by the prohibitive cost and complexity of ASIC design. Chiplets offer a compelling solution to reducing the cost and time of ASIC design\, but challenges remain. In this talk\, I will present my experience with chiplets over the last decade\, review the current obstacles\, and propose some potential paths for the future. \n\nRead More \n\n\n\n\n\n\n\n\n\nJuly 25 \n12:15 pm – 1:15 pm PDT \n\n\n\n(CP6) Unleashing AI Potential Through Advanced Chiplet Architecture\n\nThis Tutorial is presented by Dr. Tony Chan Carusone\, Chief Technology Officer\, Alphawave Semi \nIn this tutorial\, Tony Chan Carusone\, CTO of Alphawave Semi\, explores the crucial advancements required to propel the next generation of computing\, with a particular emphasis on AI as a transformative force reshaping our daily lives and data management systems. He highlights how pervasive connectivity\, from extensive optical fiber networks to intricate chiplet wirings\, is critical for AI functionalities. The discussion traces AI’s evolution over the last two decades. These developments are pivotal in meeting the computational demands\, from teraflops to petaflops\, while focusing on sustainability through chiplet-based designs. Additionally\, he will delve deeper into the chiplet architecture\, discussing how it revolutionizes cost and power efficiencies in AI applications. Tony will detail Alphawave Semi’s leadership in providing connectivity solutions specifically designed for chiplet architectures\, including the groundbreaking UCIe interface that offers a path up to 10 Tbps/mm bandwidth density. The session will further examine how AI is transforming data infrastructure connectivity\, highlighting the necessity for robust inter-chip links within datacenters and the reengineering of optical networks that cater to AI’s specific needs. The session wraps up by addressing the trend toward disaggregated computing and distributed data centers\, facilitated by low-latency connectivity. \n\nRead More \n\n\n\n\n\n\n\n\n\nJuly 25 \n1:15 pm – 1:25 pm PDT \n\n\n\nTechnical Resources Time\n\nVisit the Resource Center which includes microsites from leading Chiplet companies with lots of technical information like White Papers\, Webinars\, Datasheets\, etc. \n\n\n\n\n\n\n\n\n\nJuly 25 \n1:25 pm – 1:45 pm PDT \n\n\n\n(CP7) MIPS Accelerating the Chiplet Revolution: Powering the Future of GenAI\n\nPresented by Durgesh Srivastava\, Chief Technology Officer\, MIPS \nCompute requirements have outpaced supply by 10x. Historically\, HW advancements consistently outpaced SW. However\, the advent of GenAI has reversed this trend\, with SW developments now outstripping HW. Advanced algorithms\, especially those involving deep learning and large-scale data processing\, require vast processing power\, memory\, and efficient data handling. The computational demands of training and running GenAI models have pushed traditional silicon-based processors to their limits\, necessitating new hardware designs. Concurrently\, the slowdown of Moore’s Law has worsened these challenges. The chiplet architecture has emerged as a promising solution. This presentation will discuss how MIPS’ data-centric approach\, with the integration of the RISC-V ISA\, is driving the chiplet revolution\, optimizing data flow and processing efficiency to bridge the HW-SW gap and ensure ongoing computational advancements. \n\nRead More \n\n\n\n\n\n\n\n\n\nJuly 25 \n1:45 pm – 2:05 pm PDT \n\n\n\n(CP8) Multi-Die Health Management\n\nPresented by Dr. Yervant Zorian\, Chief Architect and Fellow\, Synopsys \nThis technical presentation discusses four multi-die health management solutions for different chiplet-to-chiplet configurations: Using IEEE 1838 for testing interconnects and dies (or chiplets) in a GPIO-based configuration\, using Synopsys SLM SMS EXT-RAM for test and repair of interconnects and DRAMs in an HBM-based logic-to-memory chiplet configuration\, using MTR for monitoring\, test\, and repair of interconnects in a UCIe-based chiplet-to-chiplet configuration\, using lane test and repair (LTR) for monitoring\, test\, and repair of light I/O in a TSV-based hybrid bonding configuration. \n\nRead More \n\n\n\n\n\n\n\n\n\nJuly 25 \n2:05 pm – 2:25 pm PDT \n\n\n\n(CP9) The Rise of Chiplets in Advanced AI/ML/High Performance Compute SoCs\n\nPresented by Jeff Twombly\, VP Business Development\, Credo \nThis presentation will cover critical SerDes IP development\, chiplet productization\, testing considerations to enable volume at scale\, and how Credo’s experience and infrastructure will enable more chiplet variants required for emerging I/O standards such as UCIe. Credo is a proven industry leader in providing high-performance\, low power chiplet solutions. Credo has two 3.2Tbps chiplets shipping in production. Credo developed all the necessary IP inhouse and combined our purpose built SerDes blocks to create the chiplet products. The 3.2Tbps Nutcracker device utilizes 32-lanes of 112G XSR SerDes to connect to the ASIC/SoC die and 32-lanes of 112G MR SerDes for the off-package\, line-side connectivity. The XSR interface can connect up to 50mm trace lengths on standard organic packaging substrates. The 3.2Tbps BlueJay device was developed to enable multi-chip module solutions using TSMCs CoWoS\, InFO\, and/or SoIC 3DFabric configuration technology. Credo developed a BoW (bunch of wires) interface to connect to the ASIC/SoC die and enables the off-package\, line-side connectivity with 64-lanes of 56Gbps LR SerDes. \n\nRead More \n\n\n\n\n\n\n\n\n\nJuly 25 \n2:25 pm – 2:45 pm PDT \n\n\n\n(CP10) Architecture challenges in meeting power\, thermal and performance needs in partitioning Chiplets for rapid deployment\n\nPresented by Deepak Shankar\, Founder and Chief Visionary\, Mirabilis Design \nDesign of chiplet architectures must transition from silicon-centric to system-centric. Early application-specific architecture exploration provides power\, latency\, throughput and thermal impact statistics to measure quality and efficiency. The exploration covers partitioning of heterogeneous compute resources onto chiplets\, task assignment\, maximize throughput and minimize latency\, manage power and thermal below the threshold for corner cases\, and scalability across workloads and tasks. System modeling using IP blocks enables this using multi-abstraction methodology with rapid modeling\, extensive exploration with constraints and optimization of the specification. During the session\, we will explain the exploration of real-life examples using system modeling. How to determine the best assignment of caches and memory at the host processor vs chiplet hub vs accelerator? How do you ensure chiplets are of the same dimension and thermal is equally distributed? How do you decide between UCIe standard vs advanced\, number of UCIe interfaces\, memory request distribution and coherency on performance? \n\nRead More \n\n\n\n\n\n\n\n\n\nJuly 25 \n2:45 pm – 2:55 pm PDT \n\n\n\nWrap-Up Session
URL:https://marketingeda.com/event/chiplets-building-the-future-of-socs/
LOCATION:CA
CATEGORIES:EDA,IP,Webinar
ATTACH;FMTTYPE=image/jpeg:https://marketingeda.com/wp-content/uploads/EE-Times-July-24-25-2024.jpg
END:VEVENT
BEGIN:VEVENT
DTSTART;TZID=America/Los_Angeles:20240724T080000
DTEND;TZID=America/Los_Angeles:20240724T090000
DTSTAMP:20240710T164355Z
CREATED:20240710T164355Z
LAST-MODIFIED:20240710T164355Z
UID:8118-1721808000-1721811600@marketingeda.com
SUMMARY:Simulating AMD's next-gen Versal Adaptive SoC devices using Questasim
DESCRIPTION:Versal Adaptive SoC\, a revolutionary adaptable platform developed by AMD\, integrates several key components such as the AI Engine (AIE)\, Processing System (PS)\, Programmable Logic (PL)\, Network on Chip (NoC)\, and a diverse array of specialized IPs. This innovative platform facilitates the efficient execution of intricate algorithms spanning from machine learning to high-performance computing tasks. In our upcoming webinar\, we aim to provide an in-depth guide on running simulation flows for a Versal Adaptive SoC. Additionally\, we’ll delve into QEMU\, the open-source system emulator\, and its co-simulation interface with Questa. Demonstrating how to conduct a system simulation of a Versal example design will be a focal point\, showcasing Questa’s support for system simulation of Versal designs based on the Vitis™ hardware emulation flow. This comprehensive setup\, including hardware emulation and system integration\, is seamlessly achieved within the Vitis environment. It incorporates the AIE simulator for graph applications\, Questasim for PL kernels\, and QEMU for PS host applications. \nWhat you will learn: \n‌\nHow to use Questa to simulate AMD’s Versal Adaptive SoC designs\n‌ \nWho should attend: \nUsers Looking into the latest AMD Versal devices and wanting to simulate the designs using a commercial simulator \nWhat/Which Products are Covered:   \n\nQuestasim\n\nSpeaker:\n\n\n\n\n\n\nFan Zhang\nProduct Engineer\, Siemens EDA\n\n\n\n\nFan Zhang is currently a Product Engineer at Siemens EDA Software. He has been working in Design and Verification\, and EDA companies for the last 16 years. He graduated with a MS in Computer Engineering from Texas A&M University. \nHe previously worked at AMD as a Design Engineer\, Nvidia and Cadence as a Verification Engineer before joining Siemens as a Product Engineer. \nFan likes to go hiking and camping in his spare time and loves to swim.
URL:https://marketingeda.com/event/simulating-amds-next-gen-versal-adaptive-soc-devices-using-questasim/
LOCATION:CA
CATEGORIES:EDA,Webinar
ATTACH;FMTTYPE=image/jpeg:https://marketingeda.com/wp-content/uploads/Siemens-July-24-2024.jpg
END:VEVENT
BEGIN:VEVENT
DTSTART;TZID=America/Los_Angeles:20240723T080000
DTEND;TZID=America/Los_Angeles:20240723T090000
DTSTAMP:20240717T173729Z
CREATED:20240717T173729Z
LAST-MODIFIED:20240717T173729Z
UID:8153-1721721600-1721725200@marketingeda.com
SUMMARY:30th Siemens Xcelerator Technology Innovation Awards
DESCRIPTION:Join us as we name the winners of the most prestigious design contest in PCB — the 30th Siemens Xcelerator Technology Innovation Awards! \nDuring this live event\, we will announce winners in multiple categories representing a wide variety of design types. Hear from leading industry experts as they discuss features that make these printed circuit boards exceptional accomplishments. \nStarted in 1988\, and formerly known as Mentor’s Technology Leadership Awards\, this program is the longest-running competition of its kind in the EDA industry. It recognizes engineers and designers who use Siemens’ innovative technology to address today’s complex electronics systems design challenges and produce industry-leading products. \nFind out more about the competition and meet the judges here: https://lnkd.in/g2FjQugA
URL:https://marketingeda.com/event/30th-siemens-xcelerator-technology-innovation-awards/
LOCATION:CA
CATEGORIES:Award,EDA
ATTACH;FMTTYPE=image/jpeg:https://marketingeda.com/wp-content/uploads/Siemens-July-23-2024.jpg
END:VEVENT
BEGIN:VEVENT
DTSTART;TZID=Asia/Kolkata:20240721T080000
DTEND;TZID=Asia/Kolkata:20240723T170000
DTSTAMP:20240717T213106Z
CREATED:20240717T213106Z
LAST-MODIFIED:20240717T213106Z
UID:8156-1721548800-1721754000@marketingeda.com
SUMMARY:ITC India 2024
DESCRIPTION:International Test Conference is the world’s premier venue dedicated to the electronic test of devices\, boards and systems-covering the complete cycle from design verification\, design-for-test\, design-for-manufacturing\, silicon debug\, manufacturing test\, system test\, diagnosis\, reliability and failure analysis\, and back to process and design improvement. \n\n\n\n\nAt ITC India\, design\, test\, and yield professionals can confront challenges faced by the industry\, and learn how these challenges are being addressed by the combined efforts of academia\, design tool and equipment suppliers\, designers\, and test engineers. \n\n\n\n\nThe 2024 ITC India conference is happening at The Radisson Blu Hotel\, Outer Ring Road\, Bengaluru on 21 to 23 July\, 2024.
URL:https://marketingeda.com/event/itc-india-2024/
LOCATION:Radisson Blu\, Outer King Road\, Bengaluru\, India
CATEGORIES:Conference,EDA
ATTACH;FMTTYPE=image/jpeg:https://marketingeda.com/wp-content/uploads/ITC-India-2024.jpg
END:VEVENT
BEGIN:VEVENT
DTSTART;TZID=Asia/Kolkata:20240718T080000
DTEND;TZID=Asia/Kolkata:20240718T170000
DTSTAMP:20240712T024146Z
CREATED:20240712T024146Z
LAST-MODIFIED:20240712T024146Z
UID:8145-1721289600-1721322000@marketingeda.com
SUMMARY:SNUG India 2024
DESCRIPTION:Since 1991\, the Synopsys Users Group (SNUG) has represented a global design community focused on innovating from Silicon to Software. Today\, as the electronics industry’s largest user conference\, SNUG brings together over 12\,000 Synopsys tool and technology users across North America\, Europe\, Asia\, and Japan. In addition to peer-reviewed technical presentations and insightful keynotes from industry leaders\, SNUG provides a unique opportunity to connect with Synopsys executives\, design ecosystem partners\, and members of your design community. \nJoin your fellow engineers at SNUG to hear practical information you can use on your current projects and the inspiration to create in the Era of Pervasive Intelligence. \nSNUG is restricted to Synopsys customers only\, and offered at no charge. \n\n\n\n\n\n\n\n\n\nWhy Attend? \n\n\n\n\n\n\n\n\n\n\n\n\n\n\n\n\n\n\nAttend tutorials for the latest advancements in Synopsys technology \n\n\n\n\n\n\n\n\n\n\n\n\nGain practical knowledge you can apply today \n\n\n\n\n\n\n\n\n\n\n\n\n\n\nChoose from among 7 Technical Tracks and see other users showcase best practices for design & verification challenges: Analog/Mixed-Signal Design and Simulation\, Digital Design Implementation\, IC Verification Software\, Signoff\, Silicon Test and Lifecycle Management\, Systems & IP\, and Verification Hardware \n\n\n\n\n\n\n\n\n\n\n\n\nHear users showcase best practices for design  & verification challenges
URL:https://marketingeda.com/event/snug-india-2024/
LOCATION:Sheraton Grand Bengaluru Whitefield\, Bengaluru\, India
CATEGORIES:EDA,IP,User Group
ATTACH;FMTTYPE=image/jpeg:https://marketingeda.com/wp-content/uploads/SNUG-India-2024.jpg
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BEGIN:VEVENT
DTSTART;TZID=America/Los_Angeles:20240717T100000
DTEND;TZID=America/Los_Angeles:20240717T110000
DTSTAMP:20240715T161354Z
CREATED:20240715T161354Z
LAST-MODIFIED:20240715T161354Z
UID:8149-1721210400-1721214000@marketingeda.com
SUMMARY:Enhancing Manufacturing Test Flows with Synopsys VC Z01X
DESCRIPTION:Leveraging functional patterns is crucial for achieving high defect coverage and reducing defective parts per million (DPPM) levels. Synopsys VC Z01X fault simulator offers enhanced fault coverage in manufacturing test flows\, complementing ATPG tools like Synopsys TestMAX ATPG. In this presentation we will delve into unique coverage scenarios\, such as resets and clocks blocked during ATPG mode. We’ll also highlight the benefits of VC Z01X robust support of the SystemVerilog language. Finally\, a practical flow discussion will equip viewers with best practices to get started. \n\n\n\n\n\n\n\n\n\n\nSpeakers\n\n\nListed below are the industry leaders scheduled to speak. \n\n\n\n\n\n\n\n\n\n\n\n\n\n\n\n\n\n\n\n\n\n\n\n\n\n\nRobert Ruiz\n\n\nProduct Management Director\nSynopsys \n\n\n\n\n\n\n\n\n\n\n\nRobert Ruiz is a product management director responsible for strategy and business growth of several verification products at Synopsys. Robert has held various marketing and technical positions for leading functional verification and test automation products at various companies including Synopsys\, Novas Software\, and Viewlogic Systems. He has more than 30 years of experience in advanced EDA technologies and methodologies and spent several years designing application-specific integrated circuits (ASICs). Robert has a BSEE degree from Stanford University. \n\n\n\n\n\n\n\n\n\n\n\n\n\n\n\n\n\n\n\n\n\n\n\n\n\n\n\n\n\n\n\nKirankumar Karanam\n\n\nApplications Engineer\, Manager\nSynopsys \n\n\n\n\n\n\n\n\n\n\n\nKirankumar Karanam is Staff Application Engineer at Synopsys. He currently oversees various customer deployments of Synopsys FuSa verification solutions worldwide. He also works with Synopsys functional verification offerings such as VCS\, Verdi\, and more. He holds M.S in Software Systems from BITS\, Pilani.
URL:https://marketingeda.com/event/enhancing-manufacturing-test-flows-with-synopsys-vc-z01x/
LOCATION:CA
CATEGORIES:EDA,Webinar
ATTACH;FMTTYPE=image/jpeg:https://marketingeda.com/wp-content/uploads/Synopsys-July-17-2024.jpg
END:VEVENT
BEGIN:VEVENT
DTSTART;TZID=America/Los_Angeles:20240717T100000
DTEND;TZID=America/Los_Angeles:20240717T110000
DTSTAMP:20240628T030757Z
CREATED:20240628T030757Z
LAST-MODIFIED:20240628T030757Z
UID:8107-1721210400-1721214000@marketingeda.com
SUMMARY:Efficient Way to UVM Constraint Randomization Debug
DESCRIPTION:Become skilled at the art of UVM randomization debugging! \n\n\n\n\n\n\n\n\n\n\n\n\nDate: Wednesday\, July 17\, 2024 \nTime: 10:00am PDT | 1:00pm EDT \nThis webinar equips you with effective strategies to tackle randomization-related errors within your UVM verification environment. We’ll explore the power of Cadence’s Verisium Debug\, a tool designed to simplify the debugging process. \n\n\n\n\n\n\n\n\n\n\n\n\nWhat You Will Learn \n\n\n\n\n\n\n\n\n\n\n\n\n\nPractical techniques for isolating and resolving randomization-related errors\nOptimize your UVM verification environment for robust functionality\nGain valuable insights into best practices for UVM randomization debugging\n\n\n\n\n\n\n\n\n\n\n\n\n\nWho Should Attend \n\n\n\n\n\n\n\n\n\n\n\n\nThis webinar is designed for verification engineers of all levels who want to become skilled in the art of UVM randomization debugging. \n\n\n\n\n\n\n\n\n\n\n\n\nSpeakers \n\n\n\n\n\n\n\n\n\n\n\n\n\nNadav Chazen\, Product Engineering Architect\, Cadence\nRich Chang\, Product Marketing Director\, Cadence
URL:https://marketingeda.com/event/efficient-way-to-uvm-constraint-randomization-debug/
LOCATION:CA
CATEGORIES:EDA,Webinar
ATTACH;FMTTYPE=image/jpeg:https://marketingeda.com/wp-content/uploads/Cadence-July-17-2024.jpg
END:VEVENT
BEGIN:VEVENT
DTSTART;TZID=America/Los_Angeles:20240716T100000
DTEND;TZID=America/Los_Angeles:20240716T110000
DTSTAMP:20240528T172552Z
CREATED:20240528T172552Z
LAST-MODIFIED:20240528T172552Z
UID:8060-1721124000-1721127600@marketingeda.com
SUMMARY:Maximize Productivity with Deep Insights into PPA Trajectories
DESCRIPTION:The digital chip design flow carries with it an enormous wealth of untapped information regarding the health and status of your SoC design. The ability to efficiently mine this data provides chip designers with comprehensive visibility and actionable insights to uncover PPA opportunities. This webinar will introduce you to Synopsys Design.da\, the industry’s first comprehensive data-visibility and analytic-driven design optimization and signoff closure solution. We’ll show you how to leverage vast datasets to bring unmatched productivity and a better\, faster\, and smarter way to design. We’ll highlight how to siphon metrics data while curating associate analysis data efficiently and automatically to pinpoint areas of focus in real-time. We’ll show you how the Synopsys Design.da solution performs analysis to identify PPA bottlenecks and the root-cause. The solution automatically classifies design trends\, identifies limitations\, and provides prescriptive guided root-cause analysis across the entire design flow. \n\n\n\n\n\n\n\n\n\n\nSpeakers\n\n\nListed below are the industry leaders scheduled to speak. \n\n\n\n\n\n\n\n\n\n\n\n\n\n\n\n\n\n\n\n\n\n\n\n\n\n\nJim Schultz\n\n\nProduct Mgmt Mgr\, Sr Staff\nSynopsys \n\n\n\n\n\n\n\n\n\n\n\nJim Schultz is a senior staff product manager for the Synopsys EDA Group. He holds a B.S. in electrical engineering from the University of California\, Davis with an emphasis in electromagnetics. His design engineering experience includes physical verification\, design planning and design implementation on CPUs\, networking and security chips. As a product engineer\, he has supported design implementation\, design planning and package design at various EDA companies.
URL:https://marketingeda.com/event/maximize-productivity-with-deep-insights-into-ppa-trajectories/
LOCATION:CA
CATEGORIES:EDA,Webinar
ATTACH;FMTTYPE=image/jpeg:https://marketingeda.com/wp-content/uploads/Synopsys-July-16-2024.jpeg
END:VEVENT
BEGIN:VEVENT
DTSTART;TZID=America/Los_Angeles:20240715T080000
DTEND;TZID=America/Los_Angeles:20240719T170000
DTSTAMP:20240710T171300Z
CREATED:20240710T170314Z
LAST-MODIFIED:20240710T171300Z
UID:8125-1721030400-1721408400@marketingeda.com
SUMMARY:IEEE SMC-IT/SCC 2024
DESCRIPTION:The International Conference on Space Mission Challenges for Information Technology (SMC-IT) and the Space Computing Conference (SCC) gather system designers\, engineers\, computer architects\, scientists\, practitioners\, and space explorers with the objective of advancing information technology\, and the computational capability and reliability of space missions. The forums will provide an excellent opportunity for fostering technical interchange on all hardware and software aspects of space missions. The joint conferences will focus on current systems practice and challenges as well as emerging hardware and software technologies with applicability for future space missions. \nSystems in all aspects of the space mission will be explored\, including flight systems\, ground systems\, science data processing\, engineering and development tools\, operations\, telecommunications\, radiation-tolerant computing devices\, reliable electronics\, space-qualifiable packaging technologies. The entire information systems lifecycle of the mission development will also be covered\, such as conceptual design\, engineering tools development\, integration and test\, operations\, science analysis\, quality control. \n 
URL:https://marketingeda.com/event/ieee-smc-it-scc-2024/
LOCATION:Computer History Museum\, 1401 N. Shoreline Blvd\, Mountain View\, CA\, 94043\, United States
CATEGORIES:Conference,EDA,IP,Semiconductor
ATTACH;FMTTYPE=image/jpeg:https://marketingeda.com/wp-content/uploads/IEEE-SMC-ITSCC-2024.jpg
END:VEVENT
BEGIN:VEVENT
DTSTART;TZID=America/Los_Angeles:20240711T091500
DTEND;TZID=America/Los_Angeles:20240711T120000
DTSTAMP:20240710T195826Z
CREATED:20240710T195715Z
LAST-MODIFIED:20240710T195826Z
UID:8131-1720689300-1720699200@marketingeda.com
SUMMARY:Synopsys Virtual Prototyping Day 2024
DESCRIPTION:Join us at Virtual Prototyping Day 2024 to hear about the latest deployed virtual prototyping innovations. This event highlights applications from around the world using the latest virtual prototyping technology\, covering applications from automotive\, AI\, and data center domains.​ \n​Industry leaders will share their experiences with the latest techniques and methodologies using virtual prototypes for early software development and architecture exploration. Presentations will highlight how virtual prototypes help to address the increased architectural challenges of highly complex SoC and multi-die architecture designs\, as well as enabling early embedded software development\, debug\, and testing. \nWelcome\n9:15 AM-9:30 AM\nGeneral Session\nJoin Marc Serughetti as he welcomes you to Virtual Prototyping Day. \nM S\nMarc Serughetti\nVP Product Management\nSynopsys \nLeveraging Virtual Platforms to Shift-left HW/SW Verification\nJuly 11\, 2024 \n9:30 AM-9:55 AMPT\nSoftware Development & Test\nAs SoC(System-On-Chip) complexity continues to increase due to the hardware-dependent software functionality\, hardware/software co-verification should be done in the early design stage. This presentation shows how the virtual platform technology enables early software development as well as the concurrent hardware/software co-verification for SSD(Solid State Drive) development as an industrial case study \nKyungsu Kang\nSamsung \nPre-Design Verification and Optimization for On-chip Interconnects\nJuly 11\, 2024 \n9:30 AM-10:00 AMPT\nSystem Architecture Design & Exploration\nData movement plays a big role in overall SoC performance. It is essential to qualify the on-chip interconnect architecture as early as possible – to verify algorithms applied on the on-chip interconnect\, determine the best performance tuning settings in the design\, and assist in power and performance projections – all before RTL is available. \nThis presentation discusses the collaboration between Microsoft and Synopsys on the on-chip interconnect model development and exploration using Platform Architect\, the many learnings that were made along the way\, and the achievements made by the team. \nCharlie Zhou\nMicrosoft \nMonica Tang\nMicrosoft \nApplication-level Hybrid Emulation for Software-Defined-Systems\nJuly 11\, 2024 \n9:55 AM-10:25 AMPT\nSoftware Development & Test\nOver the last 10 years\, Hybrid Emulation has been widely deployed for Early SW bring-up and HW/SW validation. Combining a fast virtual prototype of the CPU sub-system with the RTL of the remaining SoC running on an emulator typically produces a 10x speed-up over full emulation setups and saves precious emulator resources. ​ \nRecent advances in both virtual prototyping and emulation now yield another leap in hybrid performance\, which enables pre-silicon execution of full Software stacks\, including end-user applications. In an emerging world of Software-defined Systems\, this provides invaluable insight for the validation and optimization of HW resources and their deployment by Software applications under realistic use-case scenarios\, like AI-enabled functions\, autonomous drive stacks\, end-to-end networking applications\, etc.​ \nIn this tutorial\, we will first review the latest state-of-the-art of hybrid emulation technologies and use-cases. We will then illustrate the application of hybrid emulation for the pre-silicon validation and optimization of Software-defined Systems. \nTim Kogel\nSr. Director for Technical Product Management\nSynopsys \nNetwork-on-Chip Design for Automotive Processor and Platform Integration for Front-end Benchmarking\nJuly 11\, 2024 \n10:00 AM-10:30 AMPT\nSystem Architecture Design & Exploration\nIn this presentation we would like to address our flow of architectural exploration of StellarApp SoC using Synopsys Platform Architect tool and Designware LPDDR5 model. Validation of automotive SoCs using valid benchmark is must to guarantee all performance and design parameters are met and this could not be possible without usage of Synopsys Platform Architect tool: 1) to assemble models with different level of abstraction and from 3rd parities (ARM and Arteris )\, 2) easy configuration and sweeping their parameters in different round of fast simulation\, 3) effective analysis from both HW and SW point of view and 4) finally accurate model of Synopsys DW_LPDDR5 which helped us extremely fast and effective to validate our SoC with different benchmark. \nFilippo Colaninno\nST \nVirtual Prototypes Drive RISC-V Software Development\, Optimization and Test\nJuly 11\, 2024 \n10:25 AM-10:55 PMPT\nSoftware Development & Test\nAs RISC-V processors gain momentum in the semiconductor market\, attention is shifting from a complete focus on the processor design to a shared focus on processor and software. Just as with other processor architectures\, software development is most often the critical path to SoC projects. Challenges for software development include how to shift left software development\, how to optimize architecture\, effective debug\, software optimization\, and continuous integration and DevOps flow integration. \nVirtual prototypes provide a productive answer to these challenges. Virtual prototypes\, with ImperasFPM RISC-V fast processor models and the Virtualizer tools\, enable pre-silicon software development. The virtual prototypes also enable architecture optimization (RISC-V custom instructions) and software optimization with Virtualizer analysis tools. Virtualizer also supports hardware-software debug\, and is used every day in DevOps flows. \nWith the ImperasFPMs supporting RISC-V processor IP from both vendors and custom processors\, users have full flexibility to design in a RISC-V domain-specific processor\, and build the software to execute on their SoC platform. \nLarry Lapides\nExec. Director\, Business Development\nSynopsys \nEarly Performance Exploration of Kalray ManyCore IC Using App Dataflows w/Arm Performance Models\nJuly 11\, 2024 \n10:30 AM-11:00 AMPT\nSystem Architecture Design & Exploration\nEarly validation of system architecture decisions is crucial to avoid delays and meet product requirements. Kalray’s ManyCore chips\, designed for storage\, compute and AI applications\, need high compute efficiency and optimized dataflows between the chip’s interfaces\, main memory\, and local memory. The efficiency of these dataflows depends on various hardware and software parameters\, such as workload patterns\, the number of concurrent workloads\, DRAM transaction distribution\, DRAM scheduling policies\, and interconnect configurations. \nUsing Synopsys Platform Architect\, with generic IP and Arm performance models\, we created a performance SystemC simulation platform that helps validate architectural assumptions early on\, guiding data-driven decisions during chip design. Our simulation platform\, which can be quickly developed without needing RTL availability\, supports continuous integration to detect potential architecture regressions. We plan to enhance the model’s accuracy by integrating IP models as the design progresses. \nPierre-Yves Taloud\nKalray \nEnflame Virtual Prototyping for AI Chip Early SW Development\nJuly 11\, 2024 \n10:55 AM-11:25 AMPT\nSoftware Development & Test\nEnflame is an AI chip start-up company. It also develops runtime/framework SW to run AI models on its chip. Synopsys Virtualizer helps to shift-left SW development by 6 months. On virtual prototyping of the whole AI chip\, HW designer got early feedback for new architecture; Performance optimization started before chip tap-out; Hybrid virtual prototyping even help to verify RTL design. HW and its SW’s time-to-market was reduced. This session will present: \nWhy Virtual Prototyping\nVirtual Prototyping Development\nUsage Model\nAchievements and Next Steps \nGang Jia\nEnflame \nUse of Platform Architect for Architecting the Next Generation AURIX Microcontroller\nJuly 11\, 2024 \n11:00 AM-11:30 PMPT\nSystem Architecture Design & Exploration\nVirtual prototyping is key for early design space exploration and proper architecture definition for any given SoC platform. This talk focuses on how the Synopsys Platform Architect tool is used to help architect the next generation AURIX microcontroller:​ \nPrimarily\, the tool is used to execute system performance simulations for different architectural domains such as compute\, interconnect and memory. ​\nOur simulation platform comprises of several components with different modelling abstraction levels\, such as Synopsys library models\, custom developed models and even RTL models.​\nSimulations are executed using both standard code benchmarks and synthetic traffic as stimuli.​\nThe simulation results are analysed using standard metrics such as latency\, bandwidth\, etc.\, with deeper analysis using automated custom post-processing scripts​ \nSandeep Vangipuram\nInfineon Technologies \nOrchestrating SoC Design Space Exploration to Optimize Performance for Multi-Agent Core-IO Workloads\nJuly 11\, 2024 \n11:30 AM-12:00 PMPT\nSystem Architecture Design & Exploration\nOptimizing the performance of System-on-Chip (SoC) designs requires a comprehensive understanding of the workload characteristics and complex interactions between fabric interconnects\, system caches\, and DRAM controllers. In this presentation we will share a robust methodology to model different workloads and orchestrate design space exploration (DSE) for performance optimization of these critical SoC components using Synopsys Platform Architect.​ \nOur approach utilizes the advanced capabilities of Synopsys Platform Architect to create detailed and accurate workload models and use performance models of the fabric\, system cache\, and DRAM controller. By integrating these models with heuristic optimization techniques\, we conduct an efficient and exhaustive exploration of the design space\, identifying configurations that offer the best trade-offs between performance\, power\, and area (PPA). We specifically address the challenges posed by multi-agent Core-IO traffic\, focusing on the intricate interactions between compute and memory subsystems.​ \nThe results demonstrate marked improvements in design efficiency\, with optimized configurations achieving orders of improvement in Performance compared to baseline designs. This methodology equips industry practitioners with a powerful toolset for early-stage SoC DSE\, enabling more informed design decisions and enhancing the overall performance of computing systems. \nMelwyn Scudder\nIntel NEX
URL:https://marketingeda.com/event/synopsys-virtual-prototyping-2024/
LOCATION:CA
CATEGORIES:EDA,Forum,IP
ATTACH;FMTTYPE=image/jpeg:https://marketingeda.com/wp-content/uploads/Synopsys-July-11-2024.jpg
END:VEVENT
BEGIN:VEVENT
DTSTART;TZID=Asia/Kolkata:20240709T120000
DTEND;TZID=Asia/Kolkata:20240709T160000
DTSTAMP:20240621T162414Z
CREATED:20240621T162353Z
LAST-MODIFIED:20240621T162414Z
UID:8103-1720526400-1720540800@marketingeda.com
SUMMARY:Ensuring my Design Verification is ISO26262 Compliant
DESCRIPTION:With the widespread of the modern automobiles\, run and regulated by automotive ECUs\, the need for advanced safety features has also become inevitable. And this is why today modern vehicles are required to adhere to the safety standards listed within the Automotive Safety Integrity Level (ASIL).In this DVClub meeting our speakers will share best practices in Verification of automotive designs that need to be ISO26262 compliant. \nAgenda (IST)\n12:00    Welcome and Introduction – Tessolve\n12:00    External Speaker\n12:30    External Speaker\n13:00    Lunch & Networking\n14:00    Sundararajan Ananthakrishnan\, Cadence Design System – Ensuring my Design Verification is ISO26262 Compliant\n15:00  Dr. Mike Bartley & Marmik Soni\, Tessolve Semiconductor Pvt Ltd – Refining ISO 26262 practices by adopting GenAI\n16:00     Refreshments & Networking \nRegister now to become a part of this event. Free to attend in-person & online. \n\nTicket Tailor- DVClub India \nDVClub India is made possible through the generous support of our sponsors: Cadence & Tessolve
URL:https://marketingeda.com/event/ensuring-my-design-verification-is-iso26262-compliant/
LOCATION:Cadence\, Bengaluru\, Sarjapur Outer Ring Road\, Bengaluru\, 560103\, India
CATEGORIES:EDA,Symposium,Webinar
ATTACH;FMTTYPE=image/jpeg:https://marketingeda.com/wp-content/uploads/DVClub-India-2024.jpg
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BEGIN:VEVENT
DTSTART;TZID=America/Los_Angeles:20240709T090000
DTEND;TZID=America/Los_Angeles:20240709T100000
DTSTAMP:20240618T194728Z
CREATED:20240618T194728Z
LAST-MODIFIED:20240618T194728Z
UID:8098-1720515600-1720519200@marketingeda.com
SUMMARY:How to Reduce Thousands of False Errors in 15 Minutes
DESCRIPTION:Analyzing electrical errors across an IP or a SoC at top level\, can be a painful and long process\, often requiring extensive setup time and hundred of hours to distinguish real issues from false positives. \nTo address this challenge\, Aniah developed OneCheck\, a formal analysis tool capable of detecting 100% of electrical errors at the transistor level. With intelligent features\, it reduces false positives and groups replicated errors by root cause. \nJoin our webinar for an in-depth look at Aniah OneCheck and its SmartClustering technology\, presented by CEO Vincent Bligny. Through a live demo on a 20 million transistor SoC design\, you’ll witness OneCheck’s powerful formal analysis and SmartClustering capabilities in action\, streamlining setup\, processing\, and analysis. \nDiscover in this insightful session for technical experts how modern Electrical Rules Checking solution\, with SmartClustering intelligence can transform your verification workflows. \nSpeaker Bio :\nVincent Bligny is a renowned expert in mixed-signal verification\, particularly with transistor-level formal techniques. He spent 15 years in this industry\, mainly within STMicroelectronics’ design and verification teams\, allowing him to understand the challenges and opportunities of the EDA field. In 2019\, Vincent co-founded Aniah with the vision of delivering an ERC tool that empowers 100% of designers to find 100% of errors efficiently. Driven by a designer-centric approach\, Aniah’s tool for ERC aims to improve the verification process and bring products to market more effectively\, while simplifying the lives of designers! \n*This webinar is in partnership with SemiWiki and Aniah
URL:https://marketingeda.com/event/how-to-reduce-thousands-of-false-errors-in-15-minutes/
LOCATION:CA
CATEGORIES:EDA,Webinar
ATTACH;FMTTYPE=image/png:https://marketingeda.com/wp-content/uploads/Aniah-July-9-2024.png
END:VEVENT
BEGIN:VEVENT
DTSTART;TZID=America/Los_Angeles:20240709T080000
DTEND;TZID=America/Los_Angeles:20240711T170000
DTSTAMP:20240327T191153Z
CREATED:20240327T191111Z
LAST-MODIFIED:20240327T191153Z
UID:7778-1720512000-1720717200@marketingeda.com
SUMMARY:Semicon West 2024
DESCRIPTION:SEMICON West 2024 is North America’s premier conference and exhibition that gathers the incredibly diverse global electronics supply chain together to address the semiconductor ecosystem’s greatest opportunities and changes. Join industry leaders\, experts\, and visionaries at the Moscone Center\, San Francisco\, CA from July 9–11. \nJoin us to explore groundbreaking technologies transforming the microelectronics sector and enabling smart applications. This is the perfect opportunity for top minds and manufacturers to connect\, collaborate\, innovate\, and STRONGER TOGETHER we’ll unite in our journey towards the $1T milestone! \nPrograms + Events\n\n– CEO Summit/Keynotes\n– Market Trends & Data\n– Sustainability\n– TechTALKS\n– SEMI U—Workshops\n– Test Vision Symposium\n– Smart Manufacturing\, MedTech + Mobility\n– WFD—Workforce Development\n– FLEX Conference & Exhibition\nAnd much more! \nNetworking + Activations\n\n– Lively Receptions\n– Networking Lounges\n– Beer & Wine Garden\n– Award Ceremonies\n– SEMI Booth + SEMI U\n– Private Meeting Rooms\n– Taste of San Francisco\n– Food Truck Fare\n– Media Hub\nAnd much more!
URL:https://marketingeda.com/event/semicon-west-2024/
LOCATION:Moscone Center\, 747 Howard Street\, San Francisco\, CA\, 94103\, United States
CATEGORIES:Conference,Semiconductor
ATTACH;FMTTYPE=image/jpeg:https://marketingeda.com/wp-content/uploads/Semicon-West-2024.jpg
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