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BEGIN:VEVENT
DTSTART;TZID=America/Los_Angeles:20240716T100000
DTEND;TZID=America/Los_Angeles:20240716T110000
DTSTAMP:20240528T172552Z
CREATED:20240528T172552Z
LAST-MODIFIED:20240528T172552Z
UID:8060-1721124000-1721127600@marketingeda.com
SUMMARY:Maximize Productivity with Deep Insights into PPA Trajectories
DESCRIPTION:The digital chip design flow carries with it an enormous wealth of untapped information regarding the health and status of your SoC design. The ability to efficiently mine this data provides chip designers with comprehensive visibility and actionable insights to uncover PPA opportunities. This webinar will introduce you to Synopsys Design.da\, the industry’s first comprehensive data-visibility and analytic-driven design optimization and signoff closure solution. We’ll show you how to leverage vast datasets to bring unmatched productivity and a better\, faster\, and smarter way to design. We’ll highlight how to siphon metrics data while curating associate analysis data efficiently and automatically to pinpoint areas of focus in real-time. We’ll show you how the Synopsys Design.da solution performs analysis to identify PPA bottlenecks and the root-cause. The solution automatically classifies design trends\, identifies limitations\, and provides prescriptive guided root-cause analysis across the entire design flow. \n\n\n\n\n\n\n\n\n\n\nSpeakers\n\n\nListed below are the industry leaders scheduled to speak. \n\n\n\n\n\n\n\n\n\n\n\n\n\n\n\n\n\n\n\n\n\n\n\n\n\n\nJim Schultz\n\n\nProduct Mgmt Mgr\, Sr Staff\nSynopsys \n\n\n\n\n\n\n\n\n\n\n\nJim Schultz is a senior staff product manager for the Synopsys EDA Group. He holds a B.S. in electrical engineering from the University of California\, Davis with an emphasis in electromagnetics. His design engineering experience includes physical verification\, design planning and design implementation on CPUs\, networking and security chips. As a product engineer\, he has supported design implementation\, design planning and package design at various EDA companies.
URL:https://marketingeda.com/event/maximize-productivity-with-deep-insights-into-ppa-trajectories/
CATEGORIES:EDA,Webinar
ATTACH;FMTTYPE=image/jpeg:https://marketingeda.com/wp-content/uploads/Synopsys-July-16-2024.jpeg
END:VEVENT
BEGIN:VEVENT
DTSTART;TZID=America/Los_Angeles:20240715T080000
DTEND;TZID=America/Los_Angeles:20240719T170000
DTSTAMP:20240710T171300Z
CREATED:20240710T170314Z
LAST-MODIFIED:20240710T171300Z
UID:8125-1721030400-1721408400@marketingeda.com
SUMMARY:IEEE SMC-IT/SCC 2024
DESCRIPTION:The International Conference on Space Mission Challenges for Information Technology (SMC-IT) and the Space Computing Conference (SCC) gather system designers\, engineers\, computer architects\, scientists\, practitioners\, and space explorers with the objective of advancing information technology\, and the computational capability and reliability of space missions. The forums will provide an excellent opportunity for fostering technical interchange on all hardware and software aspects of space missions. The joint conferences will focus on current systems practice and challenges as well as emerging hardware and software technologies with applicability for future space missions. \nSystems in all aspects of the space mission will be explored\, including flight systems\, ground systems\, science data processing\, engineering and development tools\, operations\, telecommunications\, radiation-tolerant computing devices\, reliable electronics\, space-qualifiable packaging technologies. The entire information systems lifecycle of the mission development will also be covered\, such as conceptual design\, engineering tools development\, integration and test\, operations\, science analysis\, quality control. \n 
URL:https://marketingeda.com/event/ieee-smc-it-scc-2024/
LOCATION:Computer History Museum\, 1401 N. Shoreline Blvd\, Mountain View\, CA\, 94043\, United States
CATEGORIES:Conference,EDA,IP,Semiconductor
ATTACH;FMTTYPE=image/jpeg:https://marketingeda.com/wp-content/uploads/IEEE-SMC-ITSCC-2024.jpg
END:VEVENT
BEGIN:VEVENT
DTSTART;TZID=America/Los_Angeles:20240711T091500
DTEND;TZID=America/Los_Angeles:20240711T120000
DTSTAMP:20240710T195826Z
CREATED:20240710T195715Z
LAST-MODIFIED:20240710T195826Z
UID:8131-1720689300-1720699200@marketingeda.com
SUMMARY:Synopsys Virtual Prototyping Day 2024
DESCRIPTION:Join us at Virtual Prototyping Day 2024 to hear about the latest deployed virtual prototyping innovations. This event highlights applications from around the world using the latest virtual prototyping technology\, covering applications from automotive\, AI\, and data center domains.​ \n​Industry leaders will share their experiences with the latest techniques and methodologies using virtual prototypes for early software development and architecture exploration. Presentations will highlight how virtual prototypes help to address the increased architectural challenges of highly complex SoC and multi-die architecture designs\, as well as enabling early embedded software development\, debug\, and testing. \nWelcome\n9:15 AM-9:30 AM\nGeneral Session\nJoin Marc Serughetti as he welcomes you to Virtual Prototyping Day. \nM S\nMarc Serughetti\nVP Product Management\nSynopsys \nLeveraging Virtual Platforms to Shift-left HW/SW Verification\nJuly 11\, 2024 \n9:30 AM-9:55 AMPT\nSoftware Development & Test\nAs SoC(System-On-Chip) complexity continues to increase due to the hardware-dependent software functionality\, hardware/software co-verification should be done in the early design stage. This presentation shows how the virtual platform technology enables early software development as well as the concurrent hardware/software co-verification for SSD(Solid State Drive) development as an industrial case study \nKyungsu Kang\nSamsung \nPre-Design Verification and Optimization for On-chip Interconnects\nJuly 11\, 2024 \n9:30 AM-10:00 AMPT\nSystem Architecture Design & Exploration\nData movement plays a big role in overall SoC performance. It is essential to qualify the on-chip interconnect architecture as early as possible – to verify algorithms applied on the on-chip interconnect\, determine the best performance tuning settings in the design\, and assist in power and performance projections – all before RTL is available. \nThis presentation discusses the collaboration between Microsoft and Synopsys on the on-chip interconnect model development and exploration using Platform Architect\, the many learnings that were made along the way\, and the achievements made by the team. \nCharlie Zhou\nMicrosoft \nMonica Tang\nMicrosoft \nApplication-level Hybrid Emulation for Software-Defined-Systems\nJuly 11\, 2024 \n9:55 AM-10:25 AMPT\nSoftware Development & Test\nOver the last 10 years\, Hybrid Emulation has been widely deployed for Early SW bring-up and HW/SW validation. Combining a fast virtual prototype of the CPU sub-system with the RTL of the remaining SoC running on an emulator typically produces a 10x speed-up over full emulation setups and saves precious emulator resources. ​ \nRecent advances in both virtual prototyping and emulation now yield another leap in hybrid performance\, which enables pre-silicon execution of full Software stacks\, including end-user applications. In an emerging world of Software-defined Systems\, this provides invaluable insight for the validation and optimization of HW resources and their deployment by Software applications under realistic use-case scenarios\, like AI-enabled functions\, autonomous drive stacks\, end-to-end networking applications\, etc.​ \nIn this tutorial\, we will first review the latest state-of-the-art of hybrid emulation technologies and use-cases. We will then illustrate the application of hybrid emulation for the pre-silicon validation and optimization of Software-defined Systems. \nTim Kogel\nSr. Director for Technical Product Management\nSynopsys \nNetwork-on-Chip Design for Automotive Processor and Platform Integration for Front-end Benchmarking\nJuly 11\, 2024 \n10:00 AM-10:30 AMPT\nSystem Architecture Design & Exploration\nIn this presentation we would like to address our flow of architectural exploration of StellarApp SoC using Synopsys Platform Architect tool and Designware LPDDR5 model. Validation of automotive SoCs using valid benchmark is must to guarantee all performance and design parameters are met and this could not be possible without usage of Synopsys Platform Architect tool: 1) to assemble models with different level of abstraction and from 3rd parities (ARM and Arteris )\, 2) easy configuration and sweeping their parameters in different round of fast simulation\, 3) effective analysis from both HW and SW point of view and 4) finally accurate model of Synopsys DW_LPDDR5 which helped us extremely fast and effective to validate our SoC with different benchmark. \nFilippo Colaninno\nST \nVirtual Prototypes Drive RISC-V Software Development\, Optimization and Test\nJuly 11\, 2024 \n10:25 AM-10:55 PMPT\nSoftware Development & Test\nAs RISC-V processors gain momentum in the semiconductor market\, attention is shifting from a complete focus on the processor design to a shared focus on processor and software. Just as with other processor architectures\, software development is most often the critical path to SoC projects. Challenges for software development include how to shift left software development\, how to optimize architecture\, effective debug\, software optimization\, and continuous integration and DevOps flow integration. \nVirtual prototypes provide a productive answer to these challenges. Virtual prototypes\, with ImperasFPM RISC-V fast processor models and the Virtualizer tools\, enable pre-silicon software development. The virtual prototypes also enable architecture optimization (RISC-V custom instructions) and software optimization with Virtualizer analysis tools. Virtualizer also supports hardware-software debug\, and is used every day in DevOps flows. \nWith the ImperasFPMs supporting RISC-V processor IP from both vendors and custom processors\, users have full flexibility to design in a RISC-V domain-specific processor\, and build the software to execute on their SoC platform. \nLarry Lapides\nExec. Director\, Business Development\nSynopsys \nEarly Performance Exploration of Kalray ManyCore IC Using App Dataflows w/Arm Performance Models\nJuly 11\, 2024 \n10:30 AM-11:00 AMPT\nSystem Architecture Design & Exploration\nEarly validation of system architecture decisions is crucial to avoid delays and meet product requirements. Kalray’s ManyCore chips\, designed for storage\, compute and AI applications\, need high compute efficiency and optimized dataflows between the chip’s interfaces\, main memory\, and local memory. The efficiency of these dataflows depends on various hardware and software parameters\, such as workload patterns\, the number of concurrent workloads\, DRAM transaction distribution\, DRAM scheduling policies\, and interconnect configurations. \nUsing Synopsys Platform Architect\, with generic IP and Arm performance models\, we created a performance SystemC simulation platform that helps validate architectural assumptions early on\, guiding data-driven decisions during chip design. Our simulation platform\, which can be quickly developed without needing RTL availability\, supports continuous integration to detect potential architecture regressions. We plan to enhance the model’s accuracy by integrating IP models as the design progresses. \nPierre-Yves Taloud\nKalray \nEnflame Virtual Prototyping for AI Chip Early SW Development\nJuly 11\, 2024 \n10:55 AM-11:25 AMPT\nSoftware Development & Test\nEnflame is an AI chip start-up company. It also develops runtime/framework SW to run AI models on its chip. Synopsys Virtualizer helps to shift-left SW development by 6 months. On virtual prototyping of the whole AI chip\, HW designer got early feedback for new architecture; Performance optimization started before chip tap-out; Hybrid virtual prototyping even help to verify RTL design. HW and its SW’s time-to-market was reduced. This session will present: \nWhy Virtual Prototyping\nVirtual Prototyping Development\nUsage Model\nAchievements and Next Steps \nGang Jia\nEnflame \nUse of Platform Architect for Architecting the Next Generation AURIX Microcontroller\nJuly 11\, 2024 \n11:00 AM-11:30 PMPT\nSystem Architecture Design & Exploration\nVirtual prototyping is key for early design space exploration and proper architecture definition for any given SoC platform. This talk focuses on how the Synopsys Platform Architect tool is used to help architect the next generation AURIX microcontroller:​ \nPrimarily\, the tool is used to execute system performance simulations for different architectural domains such as compute\, interconnect and memory. ​\nOur simulation platform comprises of several components with different modelling abstraction levels\, such as Synopsys library models\, custom developed models and even RTL models.​\nSimulations are executed using both standard code benchmarks and synthetic traffic as stimuli.​\nThe simulation results are analysed using standard metrics such as latency\, bandwidth\, etc.\, with deeper analysis using automated custom post-processing scripts​ \nSandeep Vangipuram\nInfineon Technologies \nOrchestrating SoC Design Space Exploration to Optimize Performance for Multi-Agent Core-IO Workloads\nJuly 11\, 2024 \n11:30 AM-12:00 PMPT\nSystem Architecture Design & Exploration\nOptimizing the performance of System-on-Chip (SoC) designs requires a comprehensive understanding of the workload characteristics and complex interactions between fabric interconnects\, system caches\, and DRAM controllers. In this presentation we will share a robust methodology to model different workloads and orchestrate design space exploration (DSE) for performance optimization of these critical SoC components using Synopsys Platform Architect.​ \nOur approach utilizes the advanced capabilities of Synopsys Platform Architect to create detailed and accurate workload models and use performance models of the fabric\, system cache\, and DRAM controller. By integrating these models with heuristic optimization techniques\, we conduct an efficient and exhaustive exploration of the design space\, identifying configurations that offer the best trade-offs between performance\, power\, and area (PPA). We specifically address the challenges posed by multi-agent Core-IO traffic\, focusing on the intricate interactions between compute and memory subsystems.​ \nThe results demonstrate marked improvements in design efficiency\, with optimized configurations achieving orders of improvement in Performance compared to baseline designs. This methodology equips industry practitioners with a powerful toolset for early-stage SoC DSE\, enabling more informed design decisions and enhancing the overall performance of computing systems. \nMelwyn Scudder\nIntel NEX
URL:https://marketingeda.com/event/synopsys-virtual-prototyping-2024/
CATEGORIES:EDA,Forum,IP
ATTACH;FMTTYPE=image/jpeg:https://marketingeda.com/wp-content/uploads/Synopsys-July-11-2024.jpg
END:VEVENT
BEGIN:VEVENT
DTSTART;TZID=Asia/Kolkata:20240709T120000
DTEND;TZID=Asia/Kolkata:20240709T160000
DTSTAMP:20240621T162414Z
CREATED:20240621T162353Z
LAST-MODIFIED:20240621T162414Z
UID:8103-1720526400-1720540800@marketingeda.com
SUMMARY:Ensuring my Design Verification is ISO26262 Compliant
DESCRIPTION:With the widespread of the modern automobiles\, run and regulated by automotive ECUs\, the need for advanced safety features has also become inevitable. And this is why today modern vehicles are required to adhere to the safety standards listed within the Automotive Safety Integrity Level (ASIL).In this DVClub meeting our speakers will share best practices in Verification of automotive designs that need to be ISO26262 compliant. \nAgenda (IST)\n12:00    Welcome and Introduction – Tessolve\n12:00    External Speaker\n12:30    External Speaker\n13:00    Lunch & Networking\n14:00    Sundararajan Ananthakrishnan\, Cadence Design System – Ensuring my Design Verification is ISO26262 Compliant\n15:00  Dr. Mike Bartley & Marmik Soni\, Tessolve Semiconductor Pvt Ltd – Refining ISO 26262 practices by adopting GenAI\n16:00     Refreshments & Networking \nRegister now to become a part of this event. Free to attend in-person & online. \n\nTicket Tailor- DVClub India \nDVClub India is made possible through the generous support of our sponsors: Cadence & Tessolve
URL:https://marketingeda.com/event/ensuring-my-design-verification-is-iso26262-compliant/
LOCATION:Cadence\, Bengaluru\, Sarjapur Outer Ring Road\, Bengaluru\, 560103\, India
CATEGORIES:EDA,Symposium,Webinar
ATTACH;FMTTYPE=image/jpeg:https://marketingeda.com/wp-content/uploads/DVClub-India-2024.jpg
END:VEVENT
BEGIN:VEVENT
DTSTART;TZID=America/Los_Angeles:20240709T090000
DTEND;TZID=America/Los_Angeles:20240709T100000
DTSTAMP:20240618T194728Z
CREATED:20240618T194728Z
LAST-MODIFIED:20240618T194728Z
UID:8098-1720515600-1720519200@marketingeda.com
SUMMARY:How to Reduce Thousands of False Errors in 15 Minutes
DESCRIPTION:Analyzing electrical errors across an IP or a SoC at top level\, can be a painful and long process\, often requiring extensive setup time and hundred of hours to distinguish real issues from false positives. \nTo address this challenge\, Aniah developed OneCheck\, a formal analysis tool capable of detecting 100% of electrical errors at the transistor level. With intelligent features\, it reduces false positives and groups replicated errors by root cause. \nJoin our webinar for an in-depth look at Aniah OneCheck and its SmartClustering technology\, presented by CEO Vincent Bligny. Through a live demo on a 20 million transistor SoC design\, you’ll witness OneCheck’s powerful formal analysis and SmartClustering capabilities in action\, streamlining setup\, processing\, and analysis. \nDiscover in this insightful session for technical experts how modern Electrical Rules Checking solution\, with SmartClustering intelligence can transform your verification workflows. \nSpeaker Bio :\nVincent Bligny is a renowned expert in mixed-signal verification\, particularly with transistor-level formal techniques. He spent 15 years in this industry\, mainly within STMicroelectronics’ design and verification teams\, allowing him to understand the challenges and opportunities of the EDA field. In 2019\, Vincent co-founded Aniah with the vision of delivering an ERC tool that empowers 100% of designers to find 100% of errors efficiently. Driven by a designer-centric approach\, Aniah’s tool for ERC aims to improve the verification process and bring products to market more effectively\, while simplifying the lives of designers! \n*This webinar is in partnership with SemiWiki and Aniah
URL:https://marketingeda.com/event/how-to-reduce-thousands-of-false-errors-in-15-minutes/
CATEGORIES:EDA,Webinar
ATTACH;FMTTYPE=image/png:https://marketingeda.com/wp-content/uploads/Aniah-July-9-2024.png
END:VEVENT
BEGIN:VEVENT
DTSTART;TZID=America/Los_Angeles:20240709T080000
DTEND;TZID=America/Los_Angeles:20240711T170000
DTSTAMP:20240327T191153Z
CREATED:20240327T191111Z
LAST-MODIFIED:20240327T191153Z
UID:7778-1720512000-1720717200@marketingeda.com
SUMMARY:Semicon West 2024
DESCRIPTION:SEMICON West 2024 is North America’s premier conference and exhibition that gathers the incredibly diverse global electronics supply chain together to address the semiconductor ecosystem’s greatest opportunities and changes. Join industry leaders\, experts\, and visionaries at the Moscone Center\, San Francisco\, CA from July 9–11. \nJoin us to explore groundbreaking technologies transforming the microelectronics sector and enabling smart applications. This is the perfect opportunity for top minds and manufacturers to connect\, collaborate\, innovate\, and STRONGER TOGETHER we’ll unite in our journey towards the $1T milestone! \nPrograms + Events\n\n– CEO Summit/Keynotes\n– Market Trends & Data\n– Sustainability\n– TechTALKS\n– SEMI U—Workshops\n– Test Vision Symposium\n– Smart Manufacturing\, MedTech + Mobility\n– WFD—Workforce Development\n– FLEX Conference & Exhibition\nAnd much more! \nNetworking + Activations\n\n– Lively Receptions\n– Networking Lounges\n– Beer & Wine Garden\n– Award Ceremonies\n– SEMI Booth + SEMI U\n– Private Meeting Rooms\n– Taste of San Francisco\n– Food Truck Fare\n– Media Hub\nAnd much more!
URL:https://marketingeda.com/event/semicon-west-2024/
LOCATION:Moscone Center\, 747 Howard Street\, San Francisco\, CA\, 94103\, United States
CATEGORIES:Conference,Semiconductor
ATTACH;FMTTYPE=image/jpeg:https://marketingeda.com/wp-content/uploads/Semicon-West-2024.jpg
END:VEVENT
BEGIN:VEVENT
DTSTART;TZID=Europe/Berlin:20240702T080000
DTEND;TZID=Europe/Berlin:20240704T170000
DTSTAMP:20240628T211817Z
CREATED:20240628T211817Z
LAST-MODIFIED:20240628T211817Z
UID:8111-1719907200-1720112400@marketingeda.com
SUMMARY:FPGA Conference Europe
DESCRIPTION:The FPGA Conference Europe\, organized by ELEKTRONIKPRAXIS and the FPGA training center PLC2\, is Europe’s leading specialist conference for programmable logic devices. The conference focusses on user-oriented\, practically applicable solutions that developers can quickly integrate into their own everyday work. \n\n\n\n\n\n\n\n\nIn increasingly AI-driven cloud data centres\, in telecommunications and many other high-performance applications\, Field Programmable Gate Arrays (FPGA) have proven themselves as flexible and powerful accelerator solutions for a wide range of tasks. \n\n\n\n\n\n\n\n\nFPGAs – The hidden champions of microelectronics\n\n\nFrom tiny and energy-efficient sensor fusion solutions for the automotive industry\, to intelligent platforms for condition monitoring in networked factories\, to powerful deep learning accelerators in the largest data centers\, these flexible logic devices play an important role in many applications and will be discussed during the FPGA Conference Europe in Munich.
URL:https://marketingeda.com/event/fpga-conference-europe-2/
LOCATION:NH München Ost Conference Center\, Einsteinring 20\, Munich\, Aschheim\, 85609\, Germany
CATEGORIES:Conference,EDA,IP
ATTACH;FMTTYPE=image/jpeg:https://marketingeda.com/wp-content/uploads/fpga-conference-europe-2024.jpg
END:VEVENT
BEGIN:VEVENT
DTSTART;TZID=America/Los_Angeles:20240625T100000
DTEND;TZID=America/Los_Angeles:20240625T110000
DTSTAMP:20240612T164153Z
CREATED:20240612T164153Z
LAST-MODIFIED:20240612T164153Z
UID:8090-1719309600-1719313200@marketingeda.com
SUMMARY:Developing Silicon Carbide DMOSFETS: A Digital Twin Design Reference Flow
DESCRIPTION:This webinar presents a comprehensive methodology for the design and optimization of a 1200V Silicon Carbide (SiC) Double-Diffused Metal-Oxide-Semiconductor Field-Effect Transistor (DMOS FET) utilizing Silvaco’s TCAD platform. Adhering to industry best practices\, the construction of an accurate digital twin is also presented\, ensuring conformity to real-world performance characteristics. Moreover\, we outline strategies to streamline simulation workflows\, emphasizing techniques to boost design efficiency and productivity. \nIn parallel\, this webinar explores the transformative impact of Machine Learning (ML) on traditional device design practices. By harnessing ML algorithms\, a fundamental shift occurs in the approach towards device design\, enabling process and device engineers to extract insights from vast datasets\, optimize performance\, and expedite the design iteration process. \nAdditionally\, the necessity of incorporating compact modeling into the design flow is underscored. Compact modeling serves as a crucial component in capturing device behavior accurately\, enabling efficient circuit-level simulations and facilitating rapid prototyping of devices. The integration of compact modeling enhances the design process\, facilitating a more holistic understanding of device behavior and performance characteristics. \nThrough the integration of TCAD\, simulation optimization\, ML techniques\, and compact modeling\, this webinar demonstrates a synergistic approach towards device design\, fostering innovation\, precision\, and efficiency.
URL:https://marketingeda.com/event/developing-silicon-carbide-dmosfets-a-digital-twin-design-reference-flow/
CATEGORIES:EDA,Webinar
ATTACH;FMTTYPE=image/jpeg:https://marketingeda.com/wp-content/uploads/Silvaco-June-25-2024-1.jpg
END:VEVENT
BEGIN:VEVENT
DTSTART;TZID=America/Los_Angeles:20240625T100000
DTEND;TZID=America/Los_Angeles:20240625T110000
DTSTAMP:20240529T185102Z
CREATED:20240529T185102Z
LAST-MODIFIED:20240529T185102Z
UID:8070-1719309600-1719313200@marketingeda.com
SUMMARY:Developing Silicon Carbide DMOSFETS: A Digital Twin Reference Flow
DESCRIPTION:This webinar presents a comprehensive methodology for the design and optimization of a 1200V Silicon Carbide (SiC) Double-Diffused Metal-Oxide-Semiconductor Field-Effect Transistor (DMOS FET) utilizing Silvaco’s TCAD platform. Adhering to industry best practices\, the construction of an accurate digital twin is also presented\, ensuring conformity to real-world performance characteristics. Moreover\, we outline strategies to streamline simulation workflows\, emphasizing techniques to boost design efficiency and productivity. \nIn parallel\, this webinar explores the transformative impact of Machine Learning (ML) on traditional device design practices. By harnessing ML algorithms\, a fundamental shift occurs in the approach towards device design\, enabling process and device engineers to extract insights from vast datasets\, optimize performance\, and expedite the design iteration process. \nAdditionally\, the necessity of incorporating compact modeling into the design flow is underscored. Compact modeling serves as a crucial component in capturing device behavior accurately\, enabling efficient circuit-level simulations and facilitating rapid prototyping of devices. The integration of compact modeling enhances the design process\, facilitating a more holistic understanding of device behavior and performance characteristics. \nThrough the integration of TCAD\, simulation optimization\, ML techniques\, and compact modeling\, this webinar demonstrates a synergistic approach towards device design\, fostering innovation\, precision\, and efficiency. \nThis Virtual Webinar is from 10:00-11:00am PT. \n 
URL:https://marketingeda.com/event/developing-silicon-carbide-dmosfets-a-digital-twin-reference-flow/
CATEGORIES:EDA,Webinar
ATTACH;FMTTYPE=image/jpeg:https://marketingeda.com/wp-content/uploads/Silvaco-June-25-2024.jpg
END:VEVENT
BEGIN:VEVENT
DTSTART;TZID=Europe/Berlin:20240624T080000
DTEND;TZID=Europe/Berlin:20240628T170000
DTSTAMP:20240304T193822Z
CREATED:20240304T193822Z
LAST-MODIFIED:20240304T193822Z
UID:7702-1719216000-1719594000@marketingeda.com
SUMMARY:RISC-V Summit Europe 2024
DESCRIPTION:The RISC-V Summit Europe is the premier event that connects the European movers and shakers – from industry\, government\, research\, academia and ecosystem support – that are building the future of innovation on RISC-V. \nRISC-V\, the open standard instruction set architecture (ISA)\, is enabling a range of new applications and research that will define the future of computing in Europe. The region has been central to RISC-V’s success\, with one-third of RISC-V’s global community based in Europe. \nRISC-V Summit Europe takes place from Monday 24th to Friday 28th June\, 2024. The combination of strong industrial and academic communities is key to the success of RISC-V in Europe\, and for this reason the conference is designed to help attendees to explore both commercial and research applications. \nRISC-V Summit Europe is an opportunity not to be missed. Come to Munich to be part of the new wave of European computing innovation!
URL:https://marketingeda.com/event/risc-v-summit-europe-2024/
LOCATION:MOC Conference\, Lilienthalallee 40\, Munich\, Germany
CATEGORIES:EDA,IP,Symposium
ATTACH;FMTTYPE=image/jpeg:https://marketingeda.com/wp-content/uploads/RISC-V-Summit-Europe-2024.jpg
END:VEVENT
BEGIN:VEVENT
DTSTART;TZID=America/Los_Angeles:20240623T080000
DTEND;TZID=America/Los_Angeles:20240627T170000
DTSTAMP:20240327T200918Z
CREATED:20240327T194239Z
LAST-MODIFIED:20240327T200918Z
UID:7782-1719129600-1719507600@marketingeda.com
SUMMARY:DAC 2024
DESCRIPTION:The premier event for the design and design automation of electronic chips to systems. \nAutonomous Systems\nElectronics content in modern autonomous systems (e.g.\, automotive\, robotics\, drones\, etc.) is growing at an increasingly rapid pace. Nearly every aspect of these complex systems uses smart electronics and embedded software to make our experiences safer\, more energy-efficient and enjoyable. For example\, premium vehicles can have several million lines of embedded software code running on hundreds of electronic control units. Within autonomous systems\, such as automotive\, these sub systems connect with one another by in-system networks. As the trend towards fully autonomous driving and connectivity accelerates\, the ability to deliver these innovations depends more than ever on advanced electronics and software development. \nDesign\nDAC has served as a meeting place for designers of electronic systems and providers of electronic design automation tools for over five decades. Increasingly\, the challenges faced by the industry require cross-domain interaction of researchers and practitioners working on electronic design (circuit\, architecture\, and embedded systems design) and researchers working on design methodologies and tools. DAC serves this need by covering design as a topic area in the research track\, in addition to organizing a dedicated designer track for practitioners. \nThe design topics covered in the research track include the design of cyber-physical\, SoC architectures\, accelerator-based computing\, emerging models of computation such as brain-inspired and quantum computing\, digital and analog circuits\, and emerging device technologies. \nSeparately the Designer Track allows tool users to share challenges and benefits of different tools\, flows\, and methodologies. In addition\, it provides excellent opportunities for education and networking between end users and tool developers. There is no other way to improve your “design IQ” in such a short amount of time than to attend the Designer Track. \nElectronic Design Automation\nEDA (Electronics Design Automation) is becoming ever more important with the continuous scaling of semiconductor devices and the growing complexities of their use in circuits and systems. Demands for lower-power\, higher-reliability and more agile electronic systems raise new challenges to both design and design automation of such systems. For the past five decades\, the primary focus of research track at DAC has been to showcase leading-edge research and practice in tools and methodologies for the design of circuits and systems. \nIn addition to the traditional EDA topics ranges from physical design to system architectures\, DAC features high-quality papers on design research\, design practices\, and design automation for cross-cutting topics including low-power\, reliability\, multicore/application specific/heterogeneous architectures\, 3-D integrations\, emerging device technologies\, design automation of “things”\, and their applications. DAC’s EDA technical program has been ensuring the best-in-class solutions that promise to advance EDA. \nEmbedded Systems & Software (ESS)\nEmbedded system design is the art of choosing and designing the proper combination of hardware and software components to achieve system level design goals like speed\, efficiency\, reliability\, security\, and safety. Embedded systems are an increasingly diverse\, disruptive\, and challenging field for designs ranging from mobile devices\, medical devices\, automotive\, robotics\, drones\, industrial and beyond. Embedded software is built into devices that may not necessarily be recognized as computing devices (e.g.\, thermostats\, toys\, defibrillators\, and anti-lock brakes)\, but nevertheless controls the functionality and perceived quality of these devices. \nThe ESS sessions at DAC provide a forum for discussing the challenges of embedded design and an opportunity for leaders in the industry and academia to come together to exchange ideas and roadmaps for the future for this rapidly expanding area. \nAI\nArtificial intelligence (AI) program highlights the advances in the field with a focus on design and design automation at the cross section between AI algorithms and hardware. While artificial intelligence and artificial neural network research has been ongoing for more than half a century\, recent advances in accelerating the pace and scale of machine learning enabled by tensor-flow based gradient optimization in deeply layered convolutional networks (convnets) are revolutionizing the impact of artificial intelligence on every aspect of our daily lives\, ranging from smart consumer electronics and services to self-navigating cars and personalized medicine. \nThe advances in deep learning are fueled by computing architectures tailored to the distributed nature of learning and inference in neural networks\, akin to the distributed nature of neural information processing and synaptic plasticity in the biological brain. Neuromorphic brain-inspired electronics for AI aim at porting the brain’s efficacy\, efficiency\, and resilience to noise and variability to electronic equivalents in standard CMOS and emerging technologies\, offering new design challenges and opportunities to advance computing architecture beyond Moore’s law scaling limits. \nThe AI sessions at DAC focuses on the fundamentals\, accomplishments to date\, and challenges ahead in ML/AI hardware system design and design automation\, providing a forum for researchers and practitioners across all the widely varying disciplines involved to connect\, engage\, and join in shaping the future of this exciting field. \nIP\nIntellectual Property (IP) is increasingly complex\, diverse\, innovative\, and challenging. The complexity is driven by increasing requirements for higher integration levels that are reusable; the diversity to satisfy varying environmental conditions and constraints dictated by the different target markets. In addition\, the evolution of IP is being driven by innovative architectures to address the latency-power-performance needs of new disruptive applications\, such as machine learning.  The IP challenges are to cope with the complexities of advanced technology nodes. \nIP design is the art of choosing and designing the proper combination of analog\, digital\, RF hardware and software components to achieve sub-system-level design goals like speed\, power\, latency\, efficiency\, reliability\, security\, and safety. EDA tools\, automation and methods are continuously improved to help architect\, develop\, verify and manage the ever more complex IP and IP portfolios. \nThe IP Track sessions at DAC provides a forum for presenting and discussing the challenges of IP development\, verification\, integration and management.  It also provides an opportunity for leaders in the industry and academia to come together to exchange ideas and roadmaps for the future for this rapidly expanding area. \nDesign on Cloud\nSystems and semiconductor companies realize the benefits of the cloud and how designing in the cloud can greatly accelerate their design cycle. Semiconductor design simulation\, verification\, lithography\, metrology\, yield analysis\, and many other workloads benefit from the scalability and performance of cloud design. \nFor all aspects of semiconductor design and manufacturing\, the new era of design in the cloud\, can optimize the process and increase yields. Industrial IoT\, data lake\, analytics\, and machine learning solutions allow you to develop smart factories and products\, provide insights to increase your operational efficiency\, and accelerate your pace of innovation. \nThe Design on Cloud sessions will focus on the aspects mentioned above plus high performance design\, verification\, and smart manufacturing\, supporting electronic design automation (EDA) in the cloud. \nSecurity\nSecurity sessions at DAC address an urgent need to create\, analyze\, evaluate\, and improve the hardware\, embedded systems and software base of the contemporary security solutions. Secure and trustworthy software and hardware components\, platforms and supply chains are vital to all domains including financial\, healthcare\, transportation\, and energy. Security of systems is becoming equally important. A revolution is underway in many industries that are “connecting the unconnected”. \nCyber physical systems\, e.g.\, automobiles\, smart grid\, medical devices\, etc.\, are taking advantage of integration of physical systems with the information systems. Not withstanding the numerous benefits\, these systems are appealing targets of attacks. Attacks on the cyber-part of such systems can have disastrous consequences in the physical world. The scope and variety of attacks on these systems present design challenges that span embedded hardware\, software\, networking\, and system design. \nSecurity topics will be featured through invited special sessions\, panels\, and lecture/poster presentations by both practitioners and researchers to share their knowledge and experience on this evolving environment.
URL:https://marketingeda.com/event/dac-2024/
LOCATION:Moscone West\, San Francisco\, CA\, 94103\, United States
CATEGORIES:Conference,EDA,IP
ATTACH;FMTTYPE=image/jpeg:https://marketingeda.com/wp-content/uploads/DAC61.jpg
END:VEVENT
BEGIN:VEVENT
DTSTART;TZID=America/Los_Angeles:20240620T083000
DTEND;TZID=America/Los_Angeles:20240620T113000
DTSTAMP:20240605T155921Z
CREATED:20240605T155921Z
LAST-MODIFIED:20240605T155921Z
UID:8073-1718872200-1718883000@marketingeda.com
SUMMARY:VC Formal Virtual Workshop - North America & Europe
DESCRIPTION:Location: Virtual workshop with hands-on labs. This workshop is best suited for attendees based in North America and Western Europe. \nFor attendees based in Eastern Europe or Asia\, please register for this workshop being held on June 21st instead. \n\n\n\n\n\n\n\n\n\n\nRegistration will close on June 14th. Space is limited!\n\n\n\n\n\n\n\n\n\n\n\n\n\n\nDo you want to harness the force of formal verification to ensure your mission-critical designs are ready for takeoff? Then join us for this virtual workshop! \nIn this 3-hour workshop\, attendees will experience: \n\nRunning simple formal checks or exploring functional behavior to find bugs early – no testbench\, no SVA\, and no formal knowledge required\nEngage in hands-on labs to find dead code\, FSM deadlock\, initialization issues\, X-propagation\, protocol violations\, explore design behavior and find bugs early\nSee a demo on how Generative AI can assist you in becoming even more productive with formal verification and RTL development\n\nThis workshop will be presented by Synopsys formal experts. Attendees will gain hands-on experience in live labs and walk away with the confidence to use these functionalities in current and upcoming projects. \n\n\n\n\n\n\n\n\n\n\n\n\n\nWorkshop Agenda\n*Subject to change \n\n\n\n\n\n\n\n\n\n\n\n\n\n\n\n30 min \n\n\n\n\n\n\n\n\n\n\n\n\nWelcome/introduction + review designer tasks\, challenges and how formal verification can help \n\n\n\n\n\n\n\n\n\n\n\n\n\n\n\n\n\n\n\n30 min \n\n\n\n\n\n\n\n\n\n\n\n\nDeadcode analysis\, FSM livelock and deadlock checks using automatic formal checks \n\n\n\n\n\n\n\n\n\n\n\n\n\n\n\n\n\n\n\n30 min \n\n\n\n\n\n\n\n\n\n\n\n\nInstructor-led hands-on lab #1 \n\n\n\n\n\n\n\n\n\n\n\n\n\n\n\n\n\n\n\n15 min \n\n\n\n\n\n\n\n\n\n\n\n\nBreak \n\n\n\n\n\n\n\n\n\n\n\n\n\n\n\n\n\n\n\n15 min \n\n\n\n\n\n\n\n\n\n\n\n\nX-propagation checking \n\n\n\n\n\n\n\n\n\n\n\n\n\n\n\n\n\n\n\n15 min \n\n\n\n\n\n\n\n\n\n\n\n\nVerifying standard protocol interfaces \n\n\n\n\n\n\n\n\n\n\n\n\n\n\n\n\n\n\n\n30 min \n\n\n\n\n\n\n\n\n\n\n\n\nFormal design exploration and instructor-led hands-on lab #2 \n\n\n\n\n\n\n\n\n\n\n\n\n\n\n\n\n\n\n\n10 min \n\n\n\n\n\n\n\n\n\n\n\n\nGenerative AI demos \n\n\n\n\n\n\n\n\n\n\n\n\n\n\n\n\n\n\n\n5 min \n\n\n\n\n\n\n\n\n\n\n\n\nWrap-up + Q&A
URL:https://marketingeda.com/event/vc-formal-virtual-workshop-north-america-europe/
CATEGORIES:EDA,Workshop
ATTACH;FMTTYPE=image/jpeg:https://marketingeda.com/wp-content/uploads/Synopsys-June-20-2024.jpg
END:VEVENT
BEGIN:VEVENT
DTSTART;TZID=America/Los_Angeles:20240619T080000
DTEND;TZID=America/Los_Angeles:20240619T090000
DTSTAMP:20240605T162435Z
CREATED:20240605T162435Z
LAST-MODIFIED:20240605T162435Z
UID:8076-1718784000-1718787600@marketingeda.com
SUMMARY:Design\, Manage\, and Share Data with OrCAD X Cloud Workspaces
DESCRIPTION:The OrCAD X platform allows you to manage and collaborate throughout the PCB design process. The cloud workspaces are available out-of-the-box without any additional setup of internal/external server dependencies. If you are a Librarian\, Electrical Engineer\, or a member of the PCB design team\, \nJoin us for this webinar to learn more about library and design data management within the OrCAD X platform. \n\nIn this webinar\, you will learn about: \n PCB design flow collaboration \n\nCreating a team library and sharing It with your team over cloud\nCreating a team workspace\nAccess control within the team workspace\nCollaborating on a PCB design across teams with\n\nElectrical engineers\nAnalysis engineers\nPCB designers\n\n\nDesign data management\n\nView/restore the version history of components and CAD data\nView/Restore the version history of PCB projects\n\n\n\n\nSPEAKERS: \nNitin Thapliyal\, Principal Product Engineer\, Cadence \nHOST: \nSupreeth Mannava\, Senior Principal Product Manager\, Cadence
URL:https://marketingeda.com/event/design-manage-and-share-data-with-orcad-x-cloud-workspaces/
CATEGORIES:EDA,Webinar
ATTACH;FMTTYPE=image/jpeg:https://marketingeda.com/wp-content/uploads/Cadence-June-19-2024.jpg
END:VEVENT
BEGIN:VEVENT
DTSTART;TZID=Europe/London:20240618T083000
DTEND;TZID=Europe/London:20240618T163000
DTSTAMP:20240404T172034Z
CREATED:20240222T180733Z
LAST-MODIFIED:20240404T172034Z
UID:7680-1718699400-1718728200@marketingeda.com
SUMMARY:Verification Futures Conference 2024 UK
DESCRIPTION:The Verification Futures conference provides a unique blend of conference presentations\, exhibitions\, training and industry networking sessions dedicated to discussing the challenges faced in hardware and software verification. Verification Futures provides a unique opportunity for end-users to define their current and future verification challenges and collaborate with the vendors to create solutions. It also provides an excellent opportunity to network and catch up with other verification engineers and vendors from across Europe. Finally\, we welcome students to encourage them on their first step into semiconductors as verification engineers. \n  \n\n\nConference Program\n\n\n\n\n\n\n\n\n\n\n\n\n\n\n\n\n\n\n08:30\nArrival: Breakfast and Networking\nSlides\nVideos\n\n\n09:25\nWelcome: Mike Bartley\, Tessolve Semiconductor Ltd\n\n\n\n\n\nKeynote Speakers\n\n\n\n\n09:30\nThe Ghosts of Challenges Past\, Present and Future \nAndy Bond (Axelera AI)\n\n\n\n\n10:05\nPresentation Title\, Speaker name ( Company name) – TBC\n\n\n\n\n10:20\nChallenges of Developing Silicon for Automotive \nDarren Galpin(UniSemi Power)\n\n\n\n\n10:30\nPresentation Title Speaker Name (Cadence) – Platinum Sponsor\n\n\n\n\n11:00\nRefreshments and Networking\n\n\n\n\n\nMulti-Track Session (AM)\n\n\n\n\n\nUser presentations on Formal Verification\n\n\n\n\n11:30\nPresentation Title Speaker Name (Lubis EDA) – Start – up Sponsor\n\n\n\n\n11:50\nPresentation Title Speaker Name (Company Name)\n\n\n\n\n12:10\nPresentation Title Speaker Name (Company Name)\n\n\n\n\n\nTrack 2 – Student Session 1 – TBC\n\n\n\n\n11:30\nPresentation Title Speaker Name (Doulos) – Gold Sponsor\n\n\n\n\n\nTrack 3 – VHDL Verification- TBC\n\n\n\n\n11:30\nPresentation Title Speaker Name (Company Name)\n\n\n\n\n12:30\nLunch and Networking\n\n\n\n\n13:30\nPresentation Title Speaker Name (Synopsys) – Platinum Sponsor (Keynote Speaker)\n\n\n\n\n14:00\nPresentation Title Speaker Name (Breker Verification Systems) – Gold Sponsor\n\n\n\n\n14:20\nPresentation Title Speaker Name (Company Name) – Gold Sponsor\n\n\n\n\n14:40\nPresentation Title Speaker Name (Company Name)\n\n\n\n\n15:00\nRefreshments and Networking\n\n\n\n\n\nMulti-Track Session (PM)\n\n\n\n\n\nTrack 1 – Latest topics in Verification\n\n\n\n\n15:30\nPresentation Title Tom (Company Name)\n\n\n\n\n15:50\nPresentation Title Speaker Name (Company Name)\n\n\n\n\n16:10\nPresentation Title Speaker Name (Company Name)\n\n\n\n\n\nTrack 2 – Student Session 2- TBC\n\n\n\n\n15:30\nPresentation Title Speaker Name (Doulos) – Gold Sponsor\n\n\n\n\n\nTrack 3 – VHDL Verification – TBC\n\n\n\n\n15:30\nPresentation Title Speaker Name (Company Name)\n\n\n\n\n\nTrack 4 – UVM for MS Verification\n\n\n\n\n15:30\nPeter Grove (Renesas)\n\n\n\n\n16:30\nEvent Closes\n\n\n\nA Semi-formal approach to coverage analysis and System-on-Chip debugging\n– Dr. Surinder Sood\, Principal Verification Engineer\, ARM \nThe most challenging task in the System on Chip (SoC) development cycle is design validation and assurance that validation covers the entire design exhaustively\, which is ensured using various coverage metrics. Due to tricky system level corner case scenarios\, SoC coverage holes are observed. This coverage hole analysis can be done via multiple approaches. The most often used approaches are the tracker-based approach and the Waveform Dump (WD)-based approach. The issue with the tracker-based approach is that the trackers are not timing accurate and not always reliant due to many approximations in their generation flow. \nAnother approach is to debug and analyze using WD manually. WD with integrated tools like waveform debugger is extensively used for this purpose. The compute resources and time taken to launch signal dumps and debug the waveform are massive at the SoC-level and also lead to huge compute resources or lag in many cases. The lag time specifically\, is of the order of hundreds of minutes in many cases. Consequently\, SoC debug\, micro-architectural analysis\, and post-simulation analysis involves a lot of time and effort. We address this problem by developing an offline semi-formal approach that uses a temporal logic-based query mechanism. \nThis mechanism provides us to write system-level contracts which are decomposed of component-level guarantees. These are defined using Linear Temporal Logic (LTL) properties (called queries in this case) to Timed LTL and help realize an offline property justification framework. The proposed framework helps debug the failure using timed LTL queries on the WD and results are returned within a few seconds\, consequently\, making debugging easy. Moreover\, this solution comes with a package of many allied benefits\, which are described in the paper. We claim to improve the debug effort as we get a speedup of the order of 4x while debugging failed scenarios\, as well as a significant improvement in coverage analysis. \n3 Key Points  \n\nLinear Temporal logic\nFormal verification\nSystem on Chips
URL:https://marketingeda.com/event/verification-futures-conference-2024-uk-2/
CATEGORIES:Conference,EDA
ATTACH;FMTTYPE=image/jpeg:https://marketingeda.com/wp-content/uploads/VF-2024-UK.jpg
END:VEVENT
BEGIN:VEVENT
DTSTART;TZID=Europe/Berlin:20240618T080000
DTEND;TZID=Europe/Berlin:20240619T170000
DTSTAMP:20240417T180940Z
CREATED:20240417T180940Z
LAST-MODIFIED:20240417T180940Z
UID:7870-1718697600-1718816400@marketingeda.com
SUMMARY:GSA European Executive Forum 2024
DESCRIPTION:The GSA European Executive Forum\, our flagship event in Europe\, is BACK! Join us June 18th and 19th in Munich for the event of the summer! \nThis year\, in honor of GSA’s 30th anniversary\, we want to celebrate by bringing you the very best EEF ever: amazing speakers\, most thought provoking topics and the very best attendees. \nExpect a captivating combination of high-level discussions with forward looking technology trends: a masterful CEO fireside chat\, sessions ranging from genAI impact on the semiconductor industry\, to the future of networks\, to the emergence of a chiplet ecosystem\, to automotive\, sustainability\, and even on how tantalizing close we are to unlocking the world-changing promises of nuclear fusion and clean energy for all! \n  \nVIP Dinner capacity is strictly limited. \nThe GSA European Executive Forum is our flagship event in Europe which\, over two days\, always attracts the very top speakers and attendees: 300 senior decision makers\, the majority VP and C-level profiles. \nOver the past 20 years\, it has become the reference executive event for the semiconductor industry in the EMEA region. \nHotels in Munich are already very hard to find around the event date: PLEASE BOOK YOUR HOTEL ROOM NOW. \n  \n 
URL:https://marketingeda.com/event/gsa-european-executive-forum-2024/
LOCATION:Sofitel Munich Bayerpost\, Bayerstrasse 12\, Munich\, 80335\, Germany
CATEGORIES:Forum,Foundry,Semiconductor
ATTACH;FMTTYPE=image/jpeg:https://marketingeda.com/wp-content/uploads/GSA-June-18-19-2024.jpg
END:VEVENT
BEGIN:VEVENT
DTSTART;TZID=Europe/Paris:20240618T080000
DTEND;TZID=Europe/Paris:20240618T170000
DTSTAMP:20240528T182135Z
CREATED:20240528T182135Z
LAST-MODIFIED:20240528T182135Z
UID:8066-1718697600-1718730000@marketingeda.com
SUMMARY:Open-source silicon and EDA workshop 2024
DESCRIPTION:The chip design ecosystem in Europe is challenged by expensive development tools\, legal constraints\, lock-in threats and dependency on external supply chains. \nOpen-source Electronic Design Automation (EDA) tools and open-source silicon chips are emerging as possible solutions to these problems. It is increasingly recognised that open-source development offers not only faster and cheaper development but also better products. The open-source model moreover resonates well with the core aims of the European Chips Act of reinforcing the Union’s semiconductor ecosystem by reducing dependencies\, enhancing digital sovereignty\, stimulating investment\, increasing design capacity and the resilience of the Union’s semiconductor supply chain. \nEven though some IP building blocks\, such as those based on the RISC-V open instruction set\, are already witnessing overwhelming success and industrial adoption\, the open-source EDA and chip ecosystems are still in their infancy. Their development is further hindered by the high costs of manufacturing silicon chips and by the complexity of the ecosystem which involves heterogeneous participants (from designers to EDA developers\, to foundries).
URL:https://marketingeda.com/event/open-source-silicon-and-eda-workshop-2024/
LOCATION:Sorbonne Université\, 15-21 Rue de l'École de Médecine\, Paris\, France
CATEGORIES:EDA,IP,Workshop
ATTACH;FMTTYPE=image/jpeg:https://marketingeda.com/wp-content/uploads/Open-source-2024.jpg
END:VEVENT
BEGIN:VEVENT
DTSTART;TZID=America/New_York:20240616T080000
DTEND;TZID=America/New_York:20240621T170000
DTSTAMP:20240528T171711Z
CREATED:20240528T171711Z
LAST-MODIFIED:20240528T171711Z
UID:8056-1718524800-1718989200@marketingeda.com
SUMMARY:International Microwave Symposium - IMS 2024
DESCRIPTION:We welcome you to IMS2024 in Washington D.C. The last time D.C. hosted IMS was in 1980. Our industry\, IMS and the city had a lot of changes in the last 44 years! \n\nD.C. is a kaleidoscope of tastes\, flavors\, sounds and sights. From Georgetown’s cobblestone streets and historic houses to the Wharf’s sleek new restaurants and funky music venues\, the District’s many neighborhoods have an identity all their own. Away from the political headlines of the day\, the American capital is throbbing with energy. Whether you’re sleeping blocks away from the White House or dining within the same walls that have hosted leaders from around the world\, Washington will not disappoint you. \nWashington D.C. is the nation’s capital and named after one of the USA’s founding fathers\, George Washington. George Washington later became the first president of the United States. Even today\, Washington\, the city\, is not part of border states\, Maryland\, nor Virginia. It is its own district. The district is called the District of Columbia. Columbia being the female personification of this nation\, hence Washington D.C. \nWashington\, D.C.\, was a planned city\, and many of the District’s street grids were developed in that initial plan. In 1791\, President George Washington commissioned Pierre (Peter) Charles L’Enfant\, a French-born architect and city planner\, to design the new capital\, and enlisted Scottish surveyor Alexander Ralston to help lay out the city plan. The L’Enfant Plan featured broad streets and avenues radiating out from rectangles\, providing room for open space and landscaping. L’Enfant based his design on plans of other major world cities\, including Paris\, Amsterdam\, Karlsruhe\, and Milan. \nIn June\, the weather in D.C. averages a high of 85°F (29°C) and a low of 63°F (17°C). Expect rain once every 3-4 days. We hope you take in the sights\, sounds and smells of D.C. Perhaps join us for a 5k fun run/walk around the city monuments! \nWe also want you to experience the museums in addition to the monuments. Some of our classic social events will take place in prized venues. International Spy Museum\, National Museum of the American Indian\, and National Museum of African American History and Culture all host IMS events. \nMake no mistake! We will get down to business at IMS. We expect to have participation from industry\, government and academia. We are engaged with ARL\, DARPA\, NASA-Goddard\, NRL\, NRO\, NIST\, NSWC\, and ONR to name a few. A number of aerospace and defense companies have offices or facilities in the local area\, for example BAE\, Boeing\, Chemring Sensors\, Collins Aerospace\, DRS\, General Dynamics\, Hughes Networks\, Intelsat\, iDirect\, L3Harris\, Ligado Networks\, Lockheed Martin\, Northrop Grumman\, Orbital ATK\, Raytheon\, Thales Defense and Security\, and ViaSat. \nPlease join us for an IMS you cannot afford to miss!
URL:https://marketingeda.com/event/international-microwave-symposium-ims-2024/
LOCATION:Walter E. Washington Convention Center\, 801 Allen Y. Lew Place\, Washington\, DC\, United States
CATEGORIES:Conference,EDA
ATTACH;FMTTYPE=image/jpeg:https://marketingeda.com/wp-content/uploads/IMS-2024.jpg
END:VEVENT
BEGIN:VEVENT
DTSTART;TZID=America/Los_Angeles:20240616T080000
DTEND;TZID=America/Los_Angeles:20240620T170000
DTSTAMP:20240226T234257Z
CREATED:20240226T234257Z
LAST-MODIFIED:20240226T234257Z
UID:7693-1718524800-1718902800@marketingeda.com
SUMMARY:2024 IEEE SYMPOSIUM ON VLSI TECHNOLOGY & CIRCUITS
DESCRIPTION:The five-day event will include: \n\nPlenary Sessions\, Technical Sessions\nEvening Panels\nShort Courses\nWorkshops\nDemo Session for Outstanding Papers\nSSCS / EDS Women in Engineering & Young Professionals events\nTraditional Luau Celebration\n\nThe Symposium will feature selected presentations and panel sessions as well as advanced VLSI technology developments\, innovative circuit designs\, and the applications they enable\, such as artificial intelligence\, machine learning\, IoT\, wearable/implantable biomedical applications\, big data\, cloud / edge computing\, virtual reality (VR) / augmented reality (AR)\, robotics\, and autonomous vehicles.
URL:https://marketingeda.com/event/2024-ieee-symposium-on-vlsi-technology-circuits/
LOCATION:Hilton Hawaiian Village\, 2005 Kālia Rd\, Honolulu\, HI\, 96815\, United States
CATEGORIES:Conference,EDA,IP
ATTACH;FMTTYPE=image/jpeg:https://marketingeda.com/wp-content/uploads/2024-IEEE-Symposium-on-VLSI-Technology.jpg
END:VEVENT
BEGIN:VEVENT
DTSTART;TZID=America/Los_Angeles:20240612T080000
DTEND;TZID=America/Los_Angeles:20240613T170000
DTSTAMP:20240610T171842Z
CREATED:20240610T171842Z
LAST-MODIFIED:20240610T171842Z
UID:8085-1718179200-1718298000@marketingeda.com
SUMMARY:Samsung Foundry Forum & SAFE Forum 2024 U.S.
DESCRIPTION:June 12th\, 2024\n12:30 – 5:30 PM PDT \n\n\n01:35 – 01:50 PM\nSamsung Keynote\nSiyoung Choi\nPresident and GM\, Foundry Business Samsung Electronics\n\n\n\n\n01:50 – 02:05 PM\nThe Accelerated Compute Platform for the Age of AI\nRene Haas\nCEO\nARM\n\n\n\n\n02:05 – 02:20 PM\nGroq’s Transformation of Generative AI ComputeJonathan RossCEO and Founder\n\n\n\n02:20 – 02:55 PM\nSamsung AI Solutions\nTaeJoong Song\nVP\, Head of Business Development\nIndong Kim\nVP\, Head of DRAM Product Planning\nHee Joung Joun\nVP\, AVP Marketing & Strategy Group\nSamsung Electronics\n\n\n\n\n03:25 – 04:00 PM\nProcess Technology\nJa-Hum Ku\nEVP\, Head of Technology Development\nSamsung Electronics\n\n\n\n04:00 – 04:15 PM\nManufacturing Excellence\nSang Sup Jeong\nEVP\, Head of Foundry Manufacturing Technology Center\nSamsung Electronics\n\n\n\n\n04:15 – 04:30 PM\nDesign Platform\nJongwook Kye\nEVP\, Head of Design\nPlatform Development\nSamsung Electronics\n\n\n\n\n04:30 – 04:40 PM\nBusiness & Customers\nSang-Pil Sim\nEVP\, Head of Worldwide Sales and Marketing\nSamsung Electronics\n\nJune 13th\, 2024\n9:00AM-5:30 PM PDT \n\n\n10:00 – 10:15 AM\nWelcome Remarks\nJongwook Kye\nEVP\, Head of Design\nPlatform Development\nSamsung Electronics\n\n\n\n\n10:15 – 10:35 AM\nEnabling a New Era of Design\nMike EllowCEO\nSiemens EDA Silicon Systems\n\n\n\n10:35 – 10:55 AM\nDemand for Power Efficiency in the Age of AI\nBill EnCorporate Vice President\nAMD\n\n\n\n\n10:55 – 11:15 AM\nThe Photonic FabricTM\, Optical Compute Interconnect for Accelerated Computing\nDavid Lazovsky\nCEO and Founder\nCelestial AI\n\n\n\n11:15 – 11:35 AM\nTechnology & Business Update\nTaeJoong Song\nVP\, Head of Business Development\nSamsung Electronics\n\n\n\n\n1:00 – 4:30 PM\nTech Session Ⅰ:\nAdvanced Technology and Design Enablement\nSei Seung Yoon\nEVP\, Head of Library Development\nSungwook Moon\nMaster(VP of Technology)\,\nFoundry Design Service\nSamsung Electronics\n\n1:00 – 4:30 PMTech Session Ⅱ:\nDesign Solutions of AI\, for AI\, and by AI\nJongshin Shin\nEVP\, Head of Foundry IP Ecosystem\nSamsung Electronics
URL:https://marketingeda.com/event/samsung-foundry-forum-safe-forum-2024-u-s/
LOCATION:Samsung Semiconductor US Campus\, 3655 N. First Street\, San Jose\, CA\, United States
CATEGORIES:Forum,Foundry
ATTACH;FMTTYPE=image/jpeg:https://marketingeda.com/wp-content/uploads/Samsung-SAFE-2024-US.jpg
END:VEVENT
BEGIN:VEVENT
DTSTART;TZID=America/Los_Angeles:20240612T080000
DTEND;TZID=America/Los_Angeles:20240613T170000
DTSTAMP:20240522T150924Z
CREATED:20240522T150924Z
LAST-MODIFIED:20240522T150924Z
UID:8019-1718179200-1718298000@marketingeda.com
SUMMARY:PCI-SIG 2024
DESCRIPTION:The PCI-SIG Developers Conference 2024 returned to Santa Clara on June 12-13\, 2024! Members of the PCI-SIG community including systems architects\, designers\, engineers\, and engineering managers attended this event. \nOverview\nThe PCI-SIG Developers Conferences is a free event for our 900+ member companies that develop and bring to market new products utilizing PCI Express® technology. It is an opportunity to learn directly from the industry’s PCIe® experts and participate in technical trainings to gain best practices to improve product roll-out and interoperability. \nThe presentations were captured on video and are available to all members. These recordings provide a valuable opportunity to those who were unable to attend the event and for those who want to re-experience the presentations for more in-depth learning. \nAttendee Registration – Open Now!\nOnline attendee registration is open. All employees of member companies are welcome to attend this exciting conference! \nPCI-SIG Annual Meeting\nThe PCI-SIG Annual Meeting will be held on June 12th\, 2024. This is an opportunity for members to meet with each other\, meet the newly elected PCI-SIG Board of Directors\, and receive the latest PCI-SIG update. Per the bylaws\, the PCI-SIG maintains nine Directors on its Board. Registration for the Annual meeting is the same link as the Developers Conference. \nPCI Board Panel \nFollowing a positive response from last year’s panel\, we will be holding another Board Panel at this year’s US DevCon. We are currently accepting questions from members for the Board of Directors to address during the panel discussion. If you have a question you would like to submit\, please email them to pcidevcon@pcisig.com. \nCall for Papers – Closed\nYou will not want to miss this series of presentations as PCI-SIG members present unique tips\, tricks\, and pitfalls learned during their implementation of PCI technology. \nIf you are interested in submitting an abstract for consideration\, we encourage you to review the online Call for Papers instructions and milestones.  \n*Note that registering and submitting materials does not guarantee you will be selected as a speaker at this event. We will follow up with those selected following the associated deadlines and provide notice to those not chosen.  \nSponsorship Registration – Closed\nPCI-SIG member companies will have the opportunity to demonstrate their company’s industry leadership in advancing the PCI landscape by participating as a Sponsor of the PCI-SIG DevCon 2024. Sponsor opportunities offer a variety of benefits including onsite presence and logo promotion. \nTo review sponsor opportunities\, please visit the PCI-SIG Sponsor Opportunities web page. \nConnect with us on LinkedIn and Twitter @pci_sig #PCISIGDevCon24 \nTo leverage PCI-SIG public relations services including media relations\, event and press release support\, please contact: pr@pcisig.com.
URL:https://marketingeda.com/event/pci-sig-2024/
LOCATION:Santa Clara Convention Center\, 5001 Great America Parkway\, Santa Clara\, CA\, 95054\, United States
CATEGORIES:Conference,IP
ATTACH;FMTTYPE=image/jpeg:https://marketingeda.com/wp-content/uploads/PCI-SIG-2024.jpg
END:VEVENT
BEGIN:VEVENT
DTSTART;TZID=America/Los_Angeles:20240611T090000
DTEND;TZID=America/Los_Angeles:20240611T170000
DTSTAMP:20240508T184358Z
CREATED:20240508T183624Z
LAST-MODIFIED:20240508T184358Z
UID:7972-1718096400-1718125200@marketingeda.com
SUMMARY:2024 ANDES RISC-V CON
DESCRIPTION:Recently\, RISC-V\, with its open\, streamlined\, and scalable configuration\, has become the mainstream solution adopted by leading market players\, paving the way for widespread technological innovation. In the RISC-V application field\, there has been rapid development in forward-looking areas such as automotive electronics and AI. The development application processors has attracted a lot of attention\, and the need for product information security has also increased. \nAs a Premier member and a leading brand in 32/64-bit embedded CPU cores\, Andes\, a member of RISC-V International\, will host an annual seminar on June 11 at the DoubleTree by Hilton San Jose. The theme of the seminar is “ANDES RISC-V CON: Deep Dive into Automotive/AI/Application Processors and Security Trends.” The event aims to introduce the market dynamics and development trends of RISC-V\, discuss Andes’ comprehensive product portfolio recently launched\, and assist industries in fully utilizing the high-performance/low-power characteristics of the RISC-V architecture to enhance product competitiveness and move towards a future full of opportunities. \nThe seminar will feature presentations and on-site demonstrations by numerous RISC-V ecosystem partners\, providing insights into the latest international trends and technological developments in RISC-V. Let us join hands to celebrate this event and explore the potential of RISC-V together with industry experts\, paving the way for a diverse application vision! \nHere is our event schedule \n09:00 – 09:25 Registration\n09:25 – 09:30 Opening-Market Watch\, Frankwell Lin\, Chairman & CEO\, Andes Technology\n09:30 – 09:50 Customer Use Case Presentation\n09:50 – 10:25 Unlocking RISC-V’s potential on Intelligence Application Processing\, Dr. Charlie Su\, President & CTO\, Andes Technology\n10:25 – 10:45 Safe and Secure Software Solutions for Andes RISC-V\, Robert Redfield\, Director of Business Development\, Green Hills Software\nGreen Hills Software and Andes Technology offer combined capabilities for the AndeStar™ V5 Architecture\, enabling the efficient development and confident deployment of RISC-V-based designs in systems with critical requirements for functional safety and security. Green Hills Software’s offering features real-time operating systems\, powerful compilers and advanced C/C++ development tools that leverage the company’s 40-years of microprocessor experience. \n10:45 – 11:05 Lauterbach Debug and Trace of Andes RISC-V Processors\, Dennis Griffiths\, Field Applications Engineer\, Lauterbach\nLauterbach\, the leader in RISC-V debug and trace\, will be discussing and demonstrating the TRACE32 tools for the Andes N27 on the Big Orca reference hardware.Using our TRACE32® tools you can debug and control any RISC-V core (along with all of the other cores) in any SoC via a single debug interface\, all at the same time. TRACE32® tools support real-time on- and off-chip tracing for all major RISC-V trace systems. \n11:05 – 11:35 Break\n11:35 – 11:55 Customer Use Case Presentation\n11:55 – 12:15 Ecosystem Partners Showcase – Siemens EDA\n12:15 – 13:15 Lunch\n13:15 – 14:05 RISC-V Ecosystem Panel: Open-Source is Transforming AI and Hardware\nModerator: Dylan Patel\, Chief Analyst\, SemiAnalysis\nPanelist: Charlie Cheng\, CEO\, Cucina\, Inc.\nPlease stay tuned for the mystery guest\nPlease stay tuned for the mystery guest\nPlease stay tuned for the mystery guest\nPlease stay tuned for the mystery guest\n14:05 – 14:35 Driving Safe and Secure Innovations with Andes RISC-V Solutions\, Andes Technology\n14:35 – 15:05 Break\n15:05 – 15:25 Synopsys Solutions Empower Software Development on Andes Processors\, Larry Lapides\, Business Development Director\, Synopsys\nAndes processor IP is increasingly being used in high performance applications such as AI/ML\, and in use cases where there are reliability\, safety and security requirements. For these and other advanced applications software development is critical. Starting software development early\, before RTL is ready\, can accelerate software tasks by months. Other key pieces of the software task include hardware-software co-verification\, building prototypes and enabling CI/CD software methodology in production. Synopsys tools\, including ImperasFPM fast processor models of the Andes cores\, Virtualizer for virtual prototypes\, and the HAPS and ZeBu hardware-assisted verification tools\, have been supporting and enabling Andes customers for more than 5 years. This talk will discuss software methodology in general\, and provide case studies of Andes-Synopsys joint customers. \n15:25 – 15:45 Are you a professional developer? Then why use amateur tools? Shawn Prestridge\, US FAE Manager\, IAR\nWhat can professional tools bring to a professional developer? Many features that optimize your time\, such as live instruction tracing\, complex and conditional breakpoint types\, functional safety certification\, comprehensive live technical support\, and much more. The optional code analysis tools can also help you quickly spot code issues while you are desk-checking your code to make your code fast and accurate. This session will quickly cover the benefits that each of these features brings in terms of time (and ultimately\, money) savings. Your time isn’t free – optimize it by using tools commensurate with your talent that allow you to deliver your product to market as quickly as possible! \n5:45 – 16:35 RISC-V Ecosystem Panel: Unlocking the RISC-V Application Processor Potential\nThe Application Processor market presents a tens-of-billions annual value opportunity\, which expands by an order of magnitude at the device scope\, and is similarly scaled\, if not more\, at the software application level. The target segments are diverse\, ranging from consumer electronics and industrial computing to automotive\, networking\, and communications. The incumbent compute ISAs for application processors are either Arm or x86\, but RISC-V has emerged as a fast-evolving and maturing alternative\, gaining strong traction across the value chain. This growth is fueled by the advent of AI\, whose support is becoming ubiquitous across all compute platforms\, with RISC-V offering significant value for AI computing. Initiatives like defining and ratifying an iterative set of extensions for the RISC-V application (RVA) profile have established a standard architecture base\, enabling hardware and software vendors to develop interoperable solutions. Efforts by organizations like RISE and major Linux-based and Android-based operating system providers have accelerated the software-based infrastructure support for RISC-V. Despite these advancements\, challenges remain in areas such as ecosystem maturity\, hardware performance and availability\, software compatibility\, and general public perception. This panel discussion will delve into these exciting topics to explore the opportunities\, the progress made\, and how to overcome these challenges to unlock the potential of RISC-V application processors. \nModerator: Mark Himelstein\, Heavenstone\, Inc.\nPanelist: Dr. Charlie Su\, President & CTO\, Andes Technology\nLars Bergstrom\, Director of Engineering\, Android team\, Google\nBarna Ibrahim\, Vice-Chair\, RISE\nDr. Sandro Pinto\, Co-founder\, OSYX Technologies\n16:35 – 17:00 Lucky Draw & Evening Reception
URL:https://marketingeda.com/event/2024-andes-risc-v-con/
LOCATION:The DoubleTree by Hilton\, 2050 Gateway Place\, San Jose\, CA\, United States
CATEGORIES:Conference,IP
ATTACH;FMTTYPE=image/jpeg:https://marketingeda.com/wp-content/uploads/Andes-June-11-2024.jpg
END:VEVENT
BEGIN:VEVENT
DTSTART;TZID=Europe/Berlin:20240610T080000
DTEND;TZID=Europe/Berlin:20240611T170000
DTSTAMP:20240503T162031Z
CREATED:20240503T162031Z
LAST-MODIFIED:20240503T162031Z
UID:7940-1718006400-1718125200@marketingeda.com
SUMMARY:SNUG Europe 2024
DESCRIPTION:Connecting the Synopsys User Community\nSince 1991\, the Synopsys Users Group (SNUG) has represented a global design community focused on innovating from Silicon to Software. Today\, as the electronics industry’s largest user conference\, SNUG brings together over 12\,000 Synopsys tool and technology users across North America\, Europe\, Asia\, and Japan. In addition to peer-reviewed technical presentations and insightful keynotes from industry leaders\, SNUG provides a unique opportunity to connect with Synopsys executives\, design ecosystem partners\, and members of your design community. \nJoin your fellow engineers at SNUG to hear practical information you can use on your current projects and the inspiration to create Smart Everything. \n\n\n\n\n\nTechnical Committee\n\nSNUG thanks the members of the Technical Committee who volunteer their time and expertise to support SNUG’s technical quality and deliver the benefit of their perspective to the users of Synopsys tools and technology.\n\n\n\n\n\n\n\n\n\n\n\n\n\n\nTechnical Committee Chair: \n\n\nFrank Poppen\, NXP Semiconductors \n\n\n\n\n\n\n\n\n\n\n\n\n\n\n\n\n\n\n\n\n\nCommittee Members: \nAlessandro Valerio\, STMicroelectronics \nAndreas Kuesel\, Micron Semiconductor GmbH \nAnshuman Anand\, Infineon \nCecile Specq\, STMicroelectronics \nClaus Kuntzsch\, University of Applied Sciences Nuremberg \nDidier Maurer\, IC’ALPS \nEnrico Castaldo\, STMicroelectronics \nFarid Labib\, GLOBALFOUNDRIES \nGiuseppe Notarangelo\, STMicroelectronics \nKarsten Matt\, GLOBALFOUNDRIES \nLars Graversen\, Demant (Oticon) \nLaurent Besson\, Easii IC \n\n\n\n\n\n\n\n\n\n\n\n\n\n\nMajid Ghameshlu\, Siemens AG (Austria) \nManfred Thanner\, NXP Semiconductors \nNathalie Meloux\, STMicroelectronics \nPeter Grove\, Renesas \nPierluigi Daglio\, STMicroelectronics \nRalph Goergen\, NXP Semiconductors \nRobert Siegmund\, GLOBALFOUNDRIES \nRoberto Anelli\, Nordic Semiconductor \nStefan Scharfenberg\, NXP \nSylvie Pierunek\, STMicroelectronics \nTarun Chawla\, STMicroelectronics \nThomas Buerner\, Nokia \nThomas Haase\, Renesas
URL:https://marketingeda.com/event/snug-europe-2024/
LOCATION:Hilton Munich Airport\, Terminalstraße Mitte 20\, 85356 München-Flughafen\, Munich\, Germany
CATEGORIES:EDA,IP,User Group
ATTACH;FMTTYPE=image/jpeg:https://marketingeda.com/wp-content/uploads/SNUG-Europe-2024.jpg
END:VEVENT
BEGIN:VEVENT
DTSTART;TZID=America/Los_Angeles:20240606T100000
DTEND;TZID=America/Los_Angeles:20240606T110000
DTSTAMP:20240524T015255Z
CREATED:20240524T015255Z
LAST-MODIFIED:20240524T015255Z
UID:8034-1717668000-1717671600@marketingeda.com
SUMMARY:Addressing Thermal Stress and Warpage Challenges in 3D-IC Designs
DESCRIPTION:Thermal stress analysis plays a crucial role in the design and performance optimization of packaging materials and boards\, especially in industries where temperature variations are significant. This webinar presents a comprehensive overview of recent developments in the newly-introduced Cadence Celsius Studio AI-enabled multiphysics thermal platform to solve today’s thermal stress and warpage analysis in 3D-ICs. \nCelsius Studio offers support for linear and nonlinear material structural models as well as static and quasi-static solvers for warpage and stress analysis and a moisture solver and high-temperature\, high-humidity (HTHH) analysis. Designers can perform multi-stage simulations for the design assembly process and material failure and reliability analysis. There are global and local models for 3D-IC warpage/stress simulation. \nYou will learn about: \n\nRecent developments in Celsius Studio that address thermal stress and warpage analysis in 3D-ICs\, including die-to-die sacking\, packing\, and boards warpage\nKey methods that can be used to address factors affecting thermal stress\, including nonlinear material properties\, geometric configuration\, and environmental conditions\nExample models for 3D-IC warpage/stress simulation
URL:https://marketingeda.com/event/addressing-thermal-stress-and-warpage-challenges-in-3d-ic-designs/
CATEGORIES:EDA,Webinar
ATTACH;FMTTYPE=image/jpeg:https://marketingeda.com/wp-content/uploads/Cadence-June-6-2024.jpg
END:VEVENT
BEGIN:VEVENT
DTSTART;TZID=Europe/Zurich:20240606T080000
DTEND;TZID=Europe/Zurich:20240607T170000
DTSTAMP:20240524T163724Z
CREATED:20240524T163724Z
LAST-MODIFIED:20240524T163724Z
UID:8038-1717660800-1717779600@marketingeda.com
SUMMARY:International Workshop on Logic and Synthesis - IWLS 2024
DESCRIPTION:The International Workshop on Logic and Synthesis is the premier forum for research in synthesis\, optimization\, and verification of integrated circuits and systems. Research on logic synthesis for emerging technologies and for novel computing platforms\, such as nanoscale systems and biological systems\, is also strongly encouraged. The workshop encourages the early dissemination of ideas and results. The workshop accepts complete papers highlighting important new problems in the early stages of development\, without providing complete solutions. The emphasis is on novelty and intellectual rigor. \nTopics of interest include but are not limited to: hardware synthesis and optimization; software synthesis; hardware/software co-synthesis; power and timing analysis; testing\, validation\, and verification; synthesis for reconfigurable architectures; hardware compilation for domain-specific languages; and design experiences. Submissions on modeling\, analysis\, and synthesis for emerging technologies and platforms are particularly encouraged. \nThe workshop format includes paper presentations\, invited talks\, social lunch and dinner gatherings\, and recreational activities. \nCheck out our call for papers. \nKeynotes\nCan AI Design and Verify Your Design?\nZiyad Hanna\, Cadence Design Systems\, Israel \n\nAbstract: In this talk\, I will explore the significant impact of artificial intelligence (AI) in addressing the mounting complexity and demands within chip design domain. With an anticipated exponential growth in annual revenue reaching the trillion-dollar mark\, driven by the rapid growth in key markets in 5G\, Hyperscalers\, autonomous vehicles\, AI\, and industrial IoT. The chip design market is trending into a fourfold increase in project volume with tenfold complexity. The current design and verification methodologies are lacking in capacity to meet this surge\, highlighting the shortage of qualified engineers to meet the aggressive market demand. AI technologies stand at the forefront of transforming design and verification processes\, offering unparalleled efficiency and cost-effective solutions to meet the escalating market needs. In this talk\, I will address the inherent challenges in the chip design industry\, analyze the current landscape of automation\, machine learning (ML)\, and cutting-edge generative AI technologies. I will also discuss a strategic direction for harnessing AI to enhance design synthesis and verification\, including the automatic generation of programs supported by natural language processing (NLP) and generative AI\, the creation of temporal assertions from design specifications\, the integration of high-level synthesis (HLS) and formal verification\, and the exploration of the latest advancements in AI technologies for full design and verification flow for achieving the aggressive demand on performance\, power and area. Furthermore\, the presentation emphasizes the essence for collaborative initiatives between industry and academia to drive forward transformative advancements and innovations within the chip design and verification domain with AI. \nZiyad Hanna\, Ph.D.\, is currently a corporate VP at Cadence Design Systems (CDNS)\, and the general manager of Cadence Israel\, leading R&D centers in various countries\, in the electronic design automation domain. Prior to joining Cadence Design Systems\, Dr. Hanna was a Senior VP at Jasper Design Automation\, which was acquired by Cadence in 2014. At Jasper\, Dr. Hanna worked in the fast-emerging domain of formal verification technology and applications. Dr. Hanna was also an Intel Senior Principal Engineer and R&D Group Leader at Intel Haifa\, where he was instrumental in the development of several generations of formal verification systems\, which were used on almost all Intel microprocessor designs since early 1990s\, and was twice the recipient of Intel’s highest Achievement Award (IAA). He received both his BS and MS degrees in Computer Science at Tel Aviv University\, and his PhD in Computer Science from the University of Oxford. Besides his leadership at Cadence\, Prof. Hanna is currently serving as a visiting professor of Computer Science at Oxford. Dr. Hanna is a senior IEEE member\, holds over 15 patents\, and has published more than 80 papers and talks.\n\n\nSymmetric Is Better: Can We Exploit Regularities in Logic Synthesis?\nValentina Ciriani\, University of Milano\, Italy \n\nAbstract: The standard synthesis of Boolean functions is aimed at designing optimized circuits according to given cost criteria. For this purpose\, the algebraic form of the function is manipulated\, as it directly reflects the cost of the corresponding circuit. Depending on the design needs\, different two-level or multi-level forms are considered\, and ad hoc algorithms are used to express and minimize such forms. In all cases\, the functions under consideration encode “real life” problems\, hence they often exhibit a “regular” structure that can be exploited by synthesis algorithms. This talk aims to describe several function regularities based on the EXOR operator. Moreover\, we show how these regularities can be exploited in logic synthesis for standard and emerging technologies. Finally\, we show how regularities can also ease polynomial verification. \nValentina Ciriani received the Laurea degree and the Ph.D. degree in Computer Science from the University of Pisa\, Italy\, in 1998 and 2003\, respectively. In 2003 and 2004 she was with the Department Computer Science at University Pisa\, Italy as a Ph.D. fellow. From 2005 to 2015 she was an assistant professor in Computer Science at the Department of Computer Science\, University of Milano\, Italy. She is currently an Associate Professor in Computer Science with the Department of Computer Science of the University of Milano (Italy). Her research interests include algorithms and data structures\, as well as combinational logic synthesis for classical and emerging technologies. She has authored or coauthored more than 100 research papers\, published in international journals\, conference proceedings\, and books chapters.\n\n\n\nToward Software-to-Atoms Open-Source RISC-V Computing Platforms: Is Open-Source Synthesis Ready for Prime Time?\nLuca Benini\, ETH Zurich / University of Bologna\, Switzerland / Italy \n\nAbstract: The success of the RISC-V free and open ISA has ushered us in the era Open-source computing hardware. As of today\, open-source designs exist targeting a wide range of RISC-V based computing systems\, from tiny microcontrollers to high-performance many-core\, and industry adoption of open-source computing hardware is accelerating. However a key open question is if we can\, or even should\, push further\, open sourcing design automation tools and technology libraries\, PDKs\, toward the vision of enabling “software-to-atoms” open source computing platforms. In this talk I will try assess where we stand and provide a personal view on key challenges and future trajectories\, drawing from a decade of experience in designing and industrializing open source hardware. \nLuca Benini holds the chair of digital Circuits and systems at ETHZ and is Full Professor at the Universita di Bologna. He received a PhD from Stanford University. Dr. Benini’s research interests are in energy-efficient parallel computing systems\, smart sensing micro-systems and machine learning hardware. He is a Fellow of the IEEE\, of the ACM and a member of the Academia Europaea. He is the recipient of the 2016 IEEE CAS Mac Van Valkenburg award\, the 2020 EDAA achievement Award\, the 2020 ACM/IEEE A. Richard Newton Award and the 2023 IEEE CS E.J. McCluskey Award.
URL:https://marketingeda.com/event/international-workshop-on-logic-and-synthesis-iwls-2024/
LOCATION:ETH Zurich\, Rämistrasse 101\, Zurich\, Switzerland
CATEGORIES:Conference,EDA
ATTACH;FMTTYPE=image/jpeg:https://marketingeda.com/wp-content/uploads/IWLS-2024.jpg
END:VEVENT
BEGIN:VEVENT
DTSTART;TZID=America/Chicago:20240606T080000
DTEND;TZID=America/Chicago:20240606T170000
DTSTAMP:20240506T222541Z
CREATED:20240506T222446Z
LAST-MODIFIED:20240506T222541Z
UID:7961-1717660800-1717693200@marketingeda.com
SUMMARY:Verification Academy Live: Huntsville
DESCRIPTION:Siemens Training Center\n360E Quality Circle\, Suite 500\nHuntsville\, AL 35806\n+1 (256) 705-2501 \nThis event is in-person only — there is no support for remote participation. \nAgenda \n\n\n\n9:30 – 10:00\nRegistration and Check-in \nCoffee and networking with your peers.\n\n\n10:00 – 10:05\nWelcome / Intro\nTodd Holbrook | Sr. Application Engineering Manager\, Functional Verification\n\n\n10:05 – 11:00\nBeyond Speed: Unlocking Productivity in Simulation and Debug\nMoses Satyasekaran | Director\, Simulation\nGone are the days when functional verification tools were solely measured by their performance metrics. The spotlight has shifted towards productivity enhancement in today’s fast-paced development environment. Join us as we explore how Siemens EDA prioritizes productivity and performance\, enabling customers to optimize their verification cycles and swiftly uncover bugs. Discover the transformative impact of this paradigm shift on accelerating design validation and achieving faster time-to-market.\n\n\n11:00 – Noon\nImprove Productivity and Deliver Hardware Assurance: Stimulus-free Verification\nChris Giles | Director\, Formal Verification\nLearn how Siemens’ and OneSpin have combined to deliver a best-in-class Static & Formal solution with a focus on addressing unsolved industry challenges. These solutions enable teams to achieve peak performance and deliver absolute hardware assurance.\n\n\nNoon – 1:00\nLunch and networking\n\n\n1:00 – 1:45\nThe New Leader in Verification IP: Questa + Avery Solutions\nKamlesh Mulchadani | Product Engineer\nNow that our acquisition of Avery Design Systems is complete\, Siemens EDA is the new leader for Verification IP in the industry. This session will describe the protocol and memory verification solutions you need for your next silicon verification project whether in Datacenter\, Storage\, 3DIC\, Networking\, Automotive\, or Aerospace and Defense applications.\n\n\n1:45 – 3:00\nQuesta Verification IQ: \nBoost verification predictability and efficiency with Big Data\nAustin Mam | Product Engineer\nThis session will cover Questa Verification IQ (VIQ)\, the next-generation\, data-driven verification solution from Siemens EDA that transforms the verification process using analytics\, collaboration\, and traceability. VIQ utilizes machine learning to boost verification productivity and is built on collective feedback gathered from verification teams over many years.\n\n\n3:00 – 4:00\nWrap-up and Networking
URL:https://marketingeda.com/event/verification-academy-live-huntsville/
LOCATION:Siemens Training Center\, 360E Quality Circle\, Suite 500\, Huntsville\, AL\, United States
CATEGORIES:EDA
ATTACH;FMTTYPE=image/jpeg:https://marketingeda.com/wp-content/uploads/Siemens-June-6-2024.jpg
END:VEVENT
BEGIN:VEVENT
DTSTART;TZID=America/Los_Angeles:20240604T100000
DTEND;TZID=America/Los_Angeles:20240604T110000
DTSTAMP:20240524T203508Z
CREATED:20240524T203431Z
LAST-MODIFIED:20240524T203508Z
UID:8046-1717495200-1717498800@marketingeda.com
SUMMARY:Silicon.da: The First Integrated SLM Analytics Solution from Design Through Manufacturing
DESCRIPTION:Today’s advanced node chip designs are faced with many new complexities which require more verification\, more validation and more analysis. The resulting data from these added steps has also grown exponentially and engineers need a way to efficiently analyze this information. The result is a new paradigm shift which has led to data overload requiring tools to collect huge amounts of data from design\, test and manufacturing (petabytes)\, analyze the data\, and provide actionable insights on that data. \nPart of the Synopsys.da AI analytics tools\,  Synopsys’ Silicon.da is the first integrated SLM analytics solution that addresses post-silicon challenges by increasing engineering productivity\, improving silicon efficiency and providing the tool scalability needed for today’s advanced SoC’s. Silicon.da serves a critical role as part of an overall SLM solution dedicated to improving the health and operational metrics of a silicon device across its complete lifecycle. \nIn this presentation\, Mr. Anti Tseng\, Senior Manager at MediaTek\, will explain how Silicon.da’s volume diagnostics feature identified systematic issues more efficiently than traditional methods by providing very accurate failure locations within the silicon resulting in improved yield by a single digit percentage and in a shorter amount of time – from weeks to days. Mr. Tseng will also further discuss how utilizing this volume diagnosis analysis technology improves the foundry process for advanced nodes resulting in millions of dollars of cost savings through high volume chip production for fabless companies. \n\n\n\n\n\n\n\n\n\n\nSpeakers\n\n\nListed below are the industry leaders scheduled to speak. \n\n\n\n\n\n\n\n\n\n\n\n\n\n\n\nAnti Tseng\n\n\nSenior Manager\nMediaTek \n\n\n\n\n\n\n\n\n\n\n\nAnti Tseng has been with MediaTek for 16 years and mainly covered three categories: CPU implementation/DFT/MBIST\, silicon speed binning & manufacture process debug\, in-house data platform & CAD flow development. His current focus is to enable smooth mass production of first advanced process node in MediaTek by exploring next-generation DFT architecture\, ATPG & diagnosis flow\, and AI-based data analysis. \n\n\n\n\n\n\n\n\n\n\n\n\n\n\n\n\n\n\n\n\nGuy Cortez\n\n\nProduct Management\, Principal\nSynopsys \n\n\n\n\n\n\n\n\n\n\n\nGuy Cortez is principal\, product management at Synopsys. His marketing career spans over 25 years where he has held various marketing positions including technical\, product/solution\, channel/field\, integrated/corporate\, alliance and business development for companies such as Synopsys\, Cadence\, VMware and Optimal+. Prior to that he spent 12 years as a test engineer at Hughes Aircraft Company (now Boeing)\, and later at Sunrise Test Systems (which became Viewlogic and later Synopsys). At Hughes\, he was responsible for generating all of the manufacturing test programs for the ASICs developed in the Missile Systems Group division. At Sunrise\, Cortez was a pre- and post-sales applications engineer\, and also doubled as the company’s instructor.
URL:https://marketingeda.com/event/silicon-da-the-first-integrated-slm-analytics-solution-from-design-through-manufacturing/
CATEGORIES:EDA,Webinar
ATTACH;FMTTYPE=image/jpeg:https://marketingeda.com/wp-content/uploads/Synopsys-June-4-2024.jpg
END:VEVENT
BEGIN:VEVENT
DTSTART;TZID=America/New_York:20240604T093000
DTEND;TZID=America/New_York:20240604T160000
DTSTAMP:20240506T221850Z
CREATED:20240506T221850Z
LAST-MODIFIED:20240506T221850Z
UID:7957-1717493400-1717516800@marketingeda.com
SUMMARY:Verification Academy Live: Westford (Boston Area)
DESCRIPTION:Westford Regency Inn and Conference Center\n219 Littleton Rd\nWestford\, MA 01886\n+1 (978) 692-8200 \nThis event is in-person only — there is no support for remote participation. \nAgenda \n\n\n\n9:30 – 10:00\nRegistration and Check-in \nCoffee and networking with your peers.\n\n\n10:00 – 10:05\nWelcome / Intro\nTodd Holbrook | Sr. Application Engineering Manager\, Functional Verification\n\n\n10:05 – 11:00\nBeyond Speed: Unlocking Productivity in Simulation and Debug\nMoses Satyasekaran | Director\, Simulation\nGone are the days when functional verification tools were solely measured by their performance metrics. The spotlight has shifted towards productivity enhancement in today’s fast-paced development environment. Join us as we explore how Siemens EDA prioritizes productivity and performance\, enabling customers to optimize their verification cycles and swiftly uncover bugs. Discover the transformative impact of this paradigm shift on accelerating design validation and achieving faster time-to-market.\n\n\n11:00 – Noon\nImprove Productivity and Deliver Hardware Assurance: Stimulus-free Verification\nChris Giles | Director\, Formal Verification\nLearn how Siemens’ and OneSpin have combined to deliver a best-in-class Static & Formal solution with a focus on addressing unsolved industry challenges. These solutions enable teams to achieve peak performance and deliver absolute hardware assurance.\n\n\nNoon – 1:00\nLunch and networking\n\n\n1:00 – 1:45\nThe New Leader in Verification IP: Questa + Avery Solutions\nKamlesh Mulchadani | Product Engineer\nNow that our acquisition of Avery Design Systems is complete\, Siemens EDA is the new leader for Verification IP in the industry. This session will describe the protocol and memory verification solutions you need for your next silicon verification project whether in Datacenter\, Storage\, 3DIC\, Networking\, Automotive\, or Aerospace and Defense applications.\n\n\n1:45 – 3:00\nQuesta Verification IQ: \nBoost verification predictability and efficiency with Big Data\nAustin Mam | Product Engineer\nThis session will cover Questa Verification IQ (VIQ)\, the next-generation\, data-driven verification solution from Siemens EDA that transforms the verification process using analytics\, collaboration\, and traceability. VIQ utilizes machine learning to boost verification productivity and is built on collective feedback gathered from verification teams over many years.\n\n\n3:00 – 4:00\nWrap-up and Networking
URL:https://marketingeda.com/event/verification-academy-live-westford-boston-area/
LOCATION:Westford Regency Inn and Conference Center\, 219 Littleton Rd\, Westford\, MA\, United States
CATEGORIES:EDA
ATTACH;FMTTYPE=image/jpeg:https://marketingeda.com/wp-content/uploads/Siemens-June-4-2024.jpg
END:VEVENT
BEGIN:VEVENT
DTSTART;TZID=America/Los_Angeles:20240604T080000
DTEND;TZID=America/Los_Angeles:20240607T170000
DTSTAMP:20240528T161702Z
CREATED:20240528T161702Z
LAST-MODIFIED:20240528T161702Z
UID:8052-1717488000-1717779600@marketingeda.com
SUMMARY:PCB East 2024
DESCRIPTION:The Electronics Industry’s East Coast Conference and Exhibition. \n1. Educational opportunities.\nNo matter how experienced you are\, everyone can learn! PCB East is widely acknowledged as the best technical conference in the industry. \n2. Networking with peers.\nCollaboration\, inspiration\, and more! \n3. New vendors and suppliers.\nTools and materials are always changing. Keeping up is paramount. \n4. Position yourself as an expert.\nWhy be the best-kept secret in the industry? \n5. It’s fun!\nAll work and no play gets old and fast. Manage your career growth with a social aspect!
URL:https://marketingeda.com/event/pcb-east-2024/
LOCATION:Boxboro Regency Hotel and Conference Center\, 242 Adams Pl\, Boxborough\, MA\, United States
CATEGORIES:Conference,EDA
ATTACH;FMTTYPE=image/jpeg:https://marketingeda.com/wp-content/uploads/PCB-East-2024.jpg
END:VEVENT
BEGIN:VEVENT
DTSTART;TZID=America/Los_Angeles:20240603T080000
DTEND;TZID=America/Los_Angeles:20240605T170000
DTSTAMP:20240521T161743Z
CREATED:20240521T161743Z
LAST-MODIFIED:20240521T161743Z
UID:8007-1717401600-1717606800@marketingeda.com
SUMMARY:Advantest VOICE 2024
DESCRIPTION:VOICE is a developer conference\, created by test engineers for test engineers.\n\n\n\n\n\n\n\n\nEach year\, the VOICE Developer Conference unites semiconductor test professionals representing the world’s leading integrated device manufacturers (IDMs)\, foundries\, fabless semiconductor companies and outsourced semiconductor assembly and test (OSAT) providers to exchange information about the latest technology advancements\, express new ideas\, share best practices and network with one another. \nAdvantest’s annual VOICE Developer Conference is the leading premier forum for the growing international community of users and strategic partners involved with Advantest’s V93000 and T2000 SoC test platforms as well as Advantest memory testers\, handlers and test cell solutions\, product engineering\, and test technology. \nVOICE promises a collaboration of minds and ample opportunities for peer networking. Join us at VOICE for a dynamic and memorable conference experience! \nAttendees gain valuable insights into the newest test solutions and best practices\, forge long-lasting relationships\, learn about the latest and upcoming equipment and technology from Advantest\, and much more through VOICE’s technical information-rich agenda\, which includes: \n\nKeynote speakers\nTechnical paper presentations\nPartners’ Expo\nTechnology Kiosk Showcases\nNetworking\nWorkshop Day
URL:https://marketingeda.com/event/advantest-voice-2024/
LOCATION:Hilton La Jolla Torrey Pines\, 10950 N Torrey Pines Rd\, La Jolla\, CA\, United States
CATEGORIES:Conference
ATTACH;FMTTYPE=image/jpeg:https://marketingeda.com/wp-content/uploads/VOICE-2024.jpg
END:VEVENT
BEGIN:VEVENT
DTSTART;TZID=America/Los_Angeles:20240530T100000
DTEND;TZID=America/Los_Angeles:20240530T110000
DTSTAMP:20240521T001952Z
CREATED:20240521T001952Z
LAST-MODIFIED:20240521T001952Z
UID:8004-1717063200-1717066800@marketingeda.com
SUMMARY:Addressing Real-Time Workloads in Automotive Applications with Efficient ARC-V Processors
DESCRIPTION:Many automotive applications require processing workloads with minimum latency and precise timing budgets.  This is especially true for safety-critical applications like adaptive cruise control and anti-lock braking\, where human life may be jeopardized.  These systems require processing elements that can respond to events within specific (predictable) time constraints. System reliability and availability depend on the effectiveness of this real-time processing. \nIn this webinar\, we will outline examples of safety-critical applications and why real-time processing is required to maintain the highest levels of safety and reliability.  We will also discuss Synopsys’ ARC-V™ RHX processor series and how these power/performance efficient processors address the real-time requirements of these applications. \n\n\n\n\n\n\n\n\n\n\nSpeaker\n\n\n\n\n\n\n\n\n\n\n\n\n\n\n\n\nRich Collins\n\n\nSr. Product Management Director\nSynopsys \n\n\n\n\n\n\n\n\n\n\n\nRich Collins is senior product managemet director for the ARC-V  RISC-V based processor portfolio at Synopsys and has over 30 years of experience in embedded semiconductor R&D\, product marketing and business development. Rich holds an MBA from Duke University’s Fuqua School of Business and a BSE in Electrical Engineering from Duke University.
URL:https://marketingeda.com/event/addressing-real-time-workloads-in-automotive-applications-with-efficient-arc-v-processors/
CATEGORIES:IP,Webinar
ATTACH;FMTTYPE=image/jpeg:https://marketingeda.com/wp-content/uploads/Synopsys-May-30-2024.jpg
END:VEVENT
END:VCALENDAR