BEGIN:VCALENDAR
VERSION:2.0
PRODID:-//Marketing EDA - ECPv6.18.4//NONSGML v1.0//EN
CALSCALE:GREGORIAN
METHOD:PUBLISH
X-WR-CALNAME:Marketing EDA
X-ORIGINAL-URL:https://marketingeda.com
X-WR-CALDESC:Events for Marketing EDA
REFRESH-INTERVAL;VALUE=DURATION:PT1H
X-Robots-Tag:noindex
X-PUBLISHED-TTL:PT1H
BEGIN:VTIMEZONE
TZID:America/Los_Angeles
BEGIN:DAYLIGHT
TZOFFSETFROM:-0800
TZOFFSETTO:-0700
TZNAME:PDT
DTSTART:20230312T100000
END:DAYLIGHT
BEGIN:STANDARD
TZOFFSETFROM:-0700
TZOFFSETTO:-0800
TZNAME:PST
DTSTART:20231105T090000
END:STANDARD
BEGIN:DAYLIGHT
TZOFFSETFROM:-0800
TZOFFSETTO:-0700
TZNAME:PDT
DTSTART:20240310T100000
END:DAYLIGHT
BEGIN:STANDARD
TZOFFSETFROM:-0700
TZOFFSETTO:-0800
TZNAME:PST
DTSTART:20241103T090000
END:STANDARD
BEGIN:DAYLIGHT
TZOFFSETFROM:-0800
TZOFFSETTO:-0700
TZNAME:PDT
DTSTART:20250309T100000
END:DAYLIGHT
BEGIN:STANDARD
TZOFFSETFROM:-0700
TZOFFSETTO:-0800
TZNAME:PST
DTSTART:20251102T090000
END:STANDARD
END:VTIMEZONE
BEGIN:VTIMEZONE
TZID:Europe/London
BEGIN:DAYLIGHT
TZOFFSETFROM:+0000
TZOFFSETTO:+0100
TZNAME:BST
DTSTART:20230326T010000
END:DAYLIGHT
BEGIN:STANDARD
TZOFFSETFROM:+0100
TZOFFSETTO:+0000
TZNAME:GMT
DTSTART:20231029T010000
END:STANDARD
BEGIN:DAYLIGHT
TZOFFSETFROM:+0000
TZOFFSETTO:+0100
TZNAME:BST
DTSTART:20240331T010000
END:DAYLIGHT
BEGIN:STANDARD
TZOFFSETFROM:+0100
TZOFFSETTO:+0000
TZNAME:GMT
DTSTART:20241027T010000
END:STANDARD
BEGIN:DAYLIGHT
TZOFFSETFROM:+0000
TZOFFSETTO:+0100
TZNAME:BST
DTSTART:20250330T010000
END:DAYLIGHT
BEGIN:STANDARD
TZOFFSETFROM:+0100
TZOFFSETTO:+0000
TZNAME:GMT
DTSTART:20251026T010000
END:STANDARD
END:VTIMEZONE
BEGIN:VTIMEZONE
TZID:Europe/Berlin
BEGIN:DAYLIGHT
TZOFFSETFROM:+0100
TZOFFSETTO:+0200
TZNAME:CEST
DTSTART:20230326T010000
END:DAYLIGHT
BEGIN:STANDARD
TZOFFSETFROM:+0200
TZOFFSETTO:+0100
TZNAME:CET
DTSTART:20231029T010000
END:STANDARD
BEGIN:DAYLIGHT
TZOFFSETFROM:+0100
TZOFFSETTO:+0200
TZNAME:CEST
DTSTART:20240331T010000
END:DAYLIGHT
BEGIN:STANDARD
TZOFFSETFROM:+0200
TZOFFSETTO:+0100
TZNAME:CET
DTSTART:20241027T010000
END:STANDARD
BEGIN:DAYLIGHT
TZOFFSETFROM:+0100
TZOFFSETTO:+0200
TZNAME:CEST
DTSTART:20250330T010000
END:DAYLIGHT
BEGIN:STANDARD
TZOFFSETFROM:+0200
TZOFFSETTO:+0100
TZNAME:CET
DTSTART:20251026T010000
END:STANDARD
END:VTIMEZONE
BEGIN:VTIMEZONE
TZID:Europe/Paris
BEGIN:DAYLIGHT
TZOFFSETFROM:+0100
TZOFFSETTO:+0200
TZNAME:CEST
DTSTART:20230326T010000
END:DAYLIGHT
BEGIN:STANDARD
TZOFFSETFROM:+0200
TZOFFSETTO:+0100
TZNAME:CET
DTSTART:20231029T010000
END:STANDARD
BEGIN:DAYLIGHT
TZOFFSETFROM:+0100
TZOFFSETTO:+0200
TZNAME:CEST
DTSTART:20240331T010000
END:DAYLIGHT
BEGIN:STANDARD
TZOFFSETFROM:+0200
TZOFFSETTO:+0100
TZNAME:CET
DTSTART:20241027T010000
END:STANDARD
BEGIN:DAYLIGHT
TZOFFSETFROM:+0100
TZOFFSETTO:+0200
TZNAME:CEST
DTSTART:20250330T010000
END:DAYLIGHT
BEGIN:STANDARD
TZOFFSETFROM:+0200
TZOFFSETTO:+0100
TZNAME:CET
DTSTART:20251026T010000
END:STANDARD
END:VTIMEZONE
BEGIN:VTIMEZONE
TZID:America/New_York
BEGIN:DAYLIGHT
TZOFFSETFROM:-0500
TZOFFSETTO:-0400
TZNAME:EDT
DTSTART:20230312T070000
END:DAYLIGHT
BEGIN:STANDARD
TZOFFSETFROM:-0400
TZOFFSETTO:-0500
TZNAME:EST
DTSTART:20231105T060000
END:STANDARD
BEGIN:DAYLIGHT
TZOFFSETFROM:-0500
TZOFFSETTO:-0400
TZNAME:EDT
DTSTART:20240310T070000
END:DAYLIGHT
BEGIN:STANDARD
TZOFFSETFROM:-0400
TZOFFSETTO:-0500
TZNAME:EST
DTSTART:20241103T060000
END:STANDARD
BEGIN:DAYLIGHT
TZOFFSETFROM:-0500
TZOFFSETTO:-0400
TZNAME:EDT
DTSTART:20250309T070000
END:DAYLIGHT
BEGIN:STANDARD
TZOFFSETFROM:-0400
TZOFFSETTO:-0500
TZNAME:EST
DTSTART:20251102T060000
END:STANDARD
END:VTIMEZONE
BEGIN:VTIMEZONE
TZID:Europe/Zurich
BEGIN:DAYLIGHT
TZOFFSETFROM:+0100
TZOFFSETTO:+0200
TZNAME:CEST
DTSTART:20230326T010000
END:DAYLIGHT
BEGIN:STANDARD
TZOFFSETFROM:+0200
TZOFFSETTO:+0100
TZNAME:CET
DTSTART:20231029T010000
END:STANDARD
BEGIN:DAYLIGHT
TZOFFSETFROM:+0100
TZOFFSETTO:+0200
TZNAME:CEST
DTSTART:20240331T010000
END:DAYLIGHT
BEGIN:STANDARD
TZOFFSETFROM:+0200
TZOFFSETTO:+0100
TZNAME:CET
DTSTART:20241027T010000
END:STANDARD
BEGIN:DAYLIGHT
TZOFFSETFROM:+0100
TZOFFSETTO:+0200
TZNAME:CEST
DTSTART:20250330T010000
END:DAYLIGHT
BEGIN:STANDARD
TZOFFSETFROM:+0200
TZOFFSETTO:+0100
TZNAME:CET
DTSTART:20251026T010000
END:STANDARD
END:VTIMEZONE
BEGIN:VTIMEZONE
TZID:America/Chicago
BEGIN:DAYLIGHT
TZOFFSETFROM:-0600
TZOFFSETTO:-0500
TZNAME:CDT
DTSTART:20230312T080000
END:DAYLIGHT
BEGIN:STANDARD
TZOFFSETFROM:-0500
TZOFFSETTO:-0600
TZNAME:CST
DTSTART:20231105T070000
END:STANDARD
BEGIN:DAYLIGHT
TZOFFSETFROM:-0600
TZOFFSETTO:-0500
TZNAME:CDT
DTSTART:20240310T080000
END:DAYLIGHT
BEGIN:STANDARD
TZOFFSETFROM:-0500
TZOFFSETTO:-0600
TZNAME:CST
DTSTART:20241103T070000
END:STANDARD
BEGIN:DAYLIGHT
TZOFFSETFROM:-0600
TZOFFSETTO:-0500
TZNAME:CDT
DTSTART:20250309T080000
END:DAYLIGHT
BEGIN:STANDARD
TZOFFSETFROM:-0500
TZOFFSETTO:-0600
TZNAME:CST
DTSTART:20251102T070000
END:STANDARD
END:VTIMEZONE
BEGIN:VTIMEZONE
TZID:Asia/Jerusalem
BEGIN:DAYLIGHT
TZOFFSETFROM:+0200
TZOFFSETTO:+0300
TZNAME:IDT
DTSTART:20230324T000000
END:DAYLIGHT
BEGIN:STANDARD
TZOFFSETFROM:+0300
TZOFFSETTO:+0200
TZNAME:IST
DTSTART:20231028T230000
END:STANDARD
BEGIN:DAYLIGHT
TZOFFSETFROM:+0200
TZOFFSETTO:+0300
TZNAME:IDT
DTSTART:20240329T000000
END:DAYLIGHT
BEGIN:STANDARD
TZOFFSETFROM:+0300
TZOFFSETTO:+0200
TZNAME:IST
DTSTART:20241026T230000
END:STANDARD
BEGIN:DAYLIGHT
TZOFFSETFROM:+0200
TZOFFSETTO:+0300
TZNAME:IDT
DTSTART:20250328T000000
END:DAYLIGHT
BEGIN:STANDARD
TZOFFSETFROM:+0300
TZOFFSETTO:+0200
TZNAME:IST
DTSTART:20251025T230000
END:STANDARD
END:VTIMEZONE
BEGIN:VTIMEZONE
TZID:Asia/Shanghai
BEGIN:STANDARD
TZOFFSETFROM:+0800
TZOFFSETTO:+0800
TZNAME:CST
DTSTART:20230101T000000
END:STANDARD
END:VTIMEZONE
BEGIN:VEVENT
DTSTART;TZID=America/Los_Angeles:20240619T080000
DTEND;TZID=America/Los_Angeles:20240619T090000
DTSTAMP:20240605T162435Z
CREATED:20240605T162435Z
LAST-MODIFIED:20240605T162435Z
UID:8076-1718784000-1718787600@marketingeda.com
SUMMARY:Design\, Manage\, and Share Data with OrCAD X Cloud Workspaces
DESCRIPTION:The OrCAD X platform allows you to manage and collaborate throughout the PCB design process. The cloud workspaces are available out-of-the-box without any additional setup of internal/external server dependencies. If you are a Librarian\, Electrical Engineer\, or a member of the PCB design team\, \nJoin us for this webinar to learn more about library and design data management within the OrCAD X platform. \n\nIn this webinar\, you will learn about: \n PCB design flow collaboration \n\nCreating a team library and sharing It with your team over cloud\nCreating a team workspace\nAccess control within the team workspace\nCollaborating on a PCB design across teams with\n\nElectrical engineers\nAnalysis engineers\nPCB designers\n\n\nDesign data management\n\nView/restore the version history of components and CAD data\nView/Restore the version history of PCB projects\n\n\n\n\nSPEAKERS: \nNitin Thapliyal\, Principal Product Engineer\, Cadence \nHOST: \nSupreeth Mannava\, Senior Principal Product Manager\, Cadence
URL:https://marketingeda.com/event/design-manage-and-share-data-with-orcad-x-cloud-workspaces/
CATEGORIES:EDA,Webinar
ATTACH;FMTTYPE=image/jpeg:https://marketingeda.com/wp-content/uploads/Cadence-June-19-2024.jpg
END:VEVENT
BEGIN:VEVENT
DTSTART;TZID=Europe/London:20240618T083000
DTEND;TZID=Europe/London:20240618T163000
DTSTAMP:20240404T172034Z
CREATED:20240222T180733Z
LAST-MODIFIED:20240404T172034Z
UID:7680-1718699400-1718728200@marketingeda.com
SUMMARY:Verification Futures Conference 2024 UK
DESCRIPTION:The Verification Futures conference provides a unique blend of conference presentations\, exhibitions\, training and industry networking sessions dedicated to discussing the challenges faced in hardware and software verification. Verification Futures provides a unique opportunity for end-users to define their current and future verification challenges and collaborate with the vendors to create solutions. It also provides an excellent opportunity to network and catch up with other verification engineers and vendors from across Europe. Finally\, we welcome students to encourage them on their first step into semiconductors as verification engineers. \n  \n\n\nConference Program\n\n\n\n\n\n\n\n\n\n\n\n\n\n\n\n\n\n\n08:30\nArrival: Breakfast and Networking\nSlides\nVideos\n\n\n09:25\nWelcome: Mike Bartley\, Tessolve Semiconductor Ltd\n\n\n\n\n\nKeynote Speakers\n\n\n\n\n09:30\nThe Ghosts of Challenges Past\, Present and Future \nAndy Bond (Axelera AI)\n\n\n\n\n10:05\nPresentation Title\, Speaker name ( Company name) – TBC\n\n\n\n\n10:20\nChallenges of Developing Silicon for Automotive \nDarren Galpin(UniSemi Power)\n\n\n\n\n10:30\nPresentation Title Speaker Name (Cadence) – Platinum Sponsor\n\n\n\n\n11:00\nRefreshments and Networking\n\n\n\n\n\nMulti-Track Session (AM)\n\n\n\n\n\nUser presentations on Formal Verification\n\n\n\n\n11:30\nPresentation Title Speaker Name (Lubis EDA) – Start – up Sponsor\n\n\n\n\n11:50\nPresentation Title Speaker Name (Company Name)\n\n\n\n\n12:10\nPresentation Title Speaker Name (Company Name)\n\n\n\n\n\nTrack 2 – Student Session 1 – TBC\n\n\n\n\n11:30\nPresentation Title Speaker Name (Doulos) – Gold Sponsor\n\n\n\n\n\nTrack 3 – VHDL Verification- TBC\n\n\n\n\n11:30\nPresentation Title Speaker Name (Company Name)\n\n\n\n\n12:30\nLunch and Networking\n\n\n\n\n13:30\nPresentation Title Speaker Name (Synopsys) – Platinum Sponsor (Keynote Speaker)\n\n\n\n\n14:00\nPresentation Title Speaker Name (Breker Verification Systems) – Gold Sponsor\n\n\n\n\n14:20\nPresentation Title Speaker Name (Company Name) – Gold Sponsor\n\n\n\n\n14:40\nPresentation Title Speaker Name (Company Name)\n\n\n\n\n15:00\nRefreshments and Networking\n\n\n\n\n\nMulti-Track Session (PM)\n\n\n\n\n\nTrack 1 – Latest topics in Verification\n\n\n\n\n15:30\nPresentation Title Tom (Company Name)\n\n\n\n\n15:50\nPresentation Title Speaker Name (Company Name)\n\n\n\n\n16:10\nPresentation Title Speaker Name (Company Name)\n\n\n\n\n\nTrack 2 – Student Session 2- TBC\n\n\n\n\n15:30\nPresentation Title Speaker Name (Doulos) – Gold Sponsor\n\n\n\n\n\nTrack 3 – VHDL Verification – TBC\n\n\n\n\n15:30\nPresentation Title Speaker Name (Company Name)\n\n\n\n\n\nTrack 4 – UVM for MS Verification\n\n\n\n\n15:30\nPeter Grove (Renesas)\n\n\n\n\n16:30\nEvent Closes\n\n\n\nA Semi-formal approach to coverage analysis and System-on-Chip debugging\n– Dr. Surinder Sood\, Principal Verification Engineer\, ARM \nThe most challenging task in the System on Chip (SoC) development cycle is design validation and assurance that validation covers the entire design exhaustively\, which is ensured using various coverage metrics. Due to tricky system level corner case scenarios\, SoC coverage holes are observed. This coverage hole analysis can be done via multiple approaches. The most often used approaches are the tracker-based approach and the Waveform Dump (WD)-based approach. The issue with the tracker-based approach is that the trackers are not timing accurate and not always reliant due to many approximations in their generation flow. \nAnother approach is to debug and analyze using WD manually. WD with integrated tools like waveform debugger is extensively used for this purpose. The compute resources and time taken to launch signal dumps and debug the waveform are massive at the SoC-level and also lead to huge compute resources or lag in many cases. The lag time specifically\, is of the order of hundreds of minutes in many cases. Consequently\, SoC debug\, micro-architectural analysis\, and post-simulation analysis involves a lot of time and effort. We address this problem by developing an offline semi-formal approach that uses a temporal logic-based query mechanism. \nThis mechanism provides us to write system-level contracts which are decomposed of component-level guarantees. These are defined using Linear Temporal Logic (LTL) properties (called queries in this case) to Timed LTL and help realize an offline property justification framework. The proposed framework helps debug the failure using timed LTL queries on the WD and results are returned within a few seconds\, consequently\, making debugging easy. Moreover\, this solution comes with a package of many allied benefits\, which are described in the paper. We claim to improve the debug effort as we get a speedup of the order of 4x while debugging failed scenarios\, as well as a significant improvement in coverage analysis. \n3 Key Points  \n\nLinear Temporal logic\nFormal verification\nSystem on Chips
URL:https://marketingeda.com/event/verification-futures-conference-2024-uk-2/
CATEGORIES:Conference,EDA
ATTACH;FMTTYPE=image/jpeg:https://marketingeda.com/wp-content/uploads/VF-2024-UK.jpg
END:VEVENT
BEGIN:VEVENT
DTSTART;TZID=Europe/Berlin:20240618T080000
DTEND;TZID=Europe/Berlin:20240619T170000
DTSTAMP:20240417T180940Z
CREATED:20240417T180940Z
LAST-MODIFIED:20240417T180940Z
UID:7870-1718697600-1718816400@marketingeda.com
SUMMARY:GSA European Executive Forum 2024
DESCRIPTION:The GSA European Executive Forum\, our flagship event in Europe\, is BACK! Join us June 18th and 19th in Munich for the event of the summer! \nThis year\, in honor of GSA’s 30th anniversary\, we want to celebrate by bringing you the very best EEF ever: amazing speakers\, most thought provoking topics and the very best attendees. \nExpect a captivating combination of high-level discussions with forward looking technology trends: a masterful CEO fireside chat\, sessions ranging from genAI impact on the semiconductor industry\, to the future of networks\, to the emergence of a chiplet ecosystem\, to automotive\, sustainability\, and even on how tantalizing close we are to unlocking the world-changing promises of nuclear fusion and clean energy for all! \n  \nVIP Dinner capacity is strictly limited. \nThe GSA European Executive Forum is our flagship event in Europe which\, over two days\, always attracts the very top speakers and attendees: 300 senior decision makers\, the majority VP and C-level profiles. \nOver the past 20 years\, it has become the reference executive event for the semiconductor industry in the EMEA region. \nHotels in Munich are already very hard to find around the event date: PLEASE BOOK YOUR HOTEL ROOM NOW. \n  \n 
URL:https://marketingeda.com/event/gsa-european-executive-forum-2024/
LOCATION:Sofitel Munich Bayerpost\, Bayerstrasse 12\, Munich\, 80335\, Germany
CATEGORIES:Forum,Foundry,Semiconductor
ATTACH;FMTTYPE=image/jpeg:https://marketingeda.com/wp-content/uploads/GSA-June-18-19-2024.jpg
END:VEVENT
BEGIN:VEVENT
DTSTART;TZID=Europe/Paris:20240618T080000
DTEND;TZID=Europe/Paris:20240618T170000
DTSTAMP:20240528T182135Z
CREATED:20240528T182135Z
LAST-MODIFIED:20240528T182135Z
UID:8066-1718697600-1718730000@marketingeda.com
SUMMARY:Open-source silicon and EDA workshop 2024
DESCRIPTION:The chip design ecosystem in Europe is challenged by expensive development tools\, legal constraints\, lock-in threats and dependency on external supply chains. \nOpen-source Electronic Design Automation (EDA) tools and open-source silicon chips are emerging as possible solutions to these problems. It is increasingly recognised that open-source development offers not only faster and cheaper development but also better products. The open-source model moreover resonates well with the core aims of the European Chips Act of reinforcing the Union’s semiconductor ecosystem by reducing dependencies\, enhancing digital sovereignty\, stimulating investment\, increasing design capacity and the resilience of the Union’s semiconductor supply chain. \nEven though some IP building blocks\, such as those based on the RISC-V open instruction set\, are already witnessing overwhelming success and industrial adoption\, the open-source EDA and chip ecosystems are still in their infancy. Their development is further hindered by the high costs of manufacturing silicon chips and by the complexity of the ecosystem which involves heterogeneous participants (from designers to EDA developers\, to foundries).
URL:https://marketingeda.com/event/open-source-silicon-and-eda-workshop-2024/
LOCATION:Sorbonne Université\, 15-21 Rue de l'École de Médecine\, Paris\, France
CATEGORIES:EDA,IP,Workshop
ATTACH;FMTTYPE=image/jpeg:https://marketingeda.com/wp-content/uploads/Open-source-2024.jpg
END:VEVENT
BEGIN:VEVENT
DTSTART;TZID=America/New_York:20240616T080000
DTEND;TZID=America/New_York:20240621T170000
DTSTAMP:20240528T171711Z
CREATED:20240528T171711Z
LAST-MODIFIED:20240528T171711Z
UID:8056-1718524800-1718989200@marketingeda.com
SUMMARY:International Microwave Symposium - IMS 2024
DESCRIPTION:We welcome you to IMS2024 in Washington D.C. The last time D.C. hosted IMS was in 1980. Our industry\, IMS and the city had a lot of changes in the last 44 years! \n\nD.C. is a kaleidoscope of tastes\, flavors\, sounds and sights. From Georgetown’s cobblestone streets and historic houses to the Wharf’s sleek new restaurants and funky music venues\, the District’s many neighborhoods have an identity all their own. Away from the political headlines of the day\, the American capital is throbbing with energy. Whether you’re sleeping blocks away from the White House or dining within the same walls that have hosted leaders from around the world\, Washington will not disappoint you. \nWashington D.C. is the nation’s capital and named after one of the USA’s founding fathers\, George Washington. George Washington later became the first president of the United States. Even today\, Washington\, the city\, is not part of border states\, Maryland\, nor Virginia. It is its own district. The district is called the District of Columbia. Columbia being the female personification of this nation\, hence Washington D.C. \nWashington\, D.C.\, was a planned city\, and many of the District’s street grids were developed in that initial plan. In 1791\, President George Washington commissioned Pierre (Peter) Charles L’Enfant\, a French-born architect and city planner\, to design the new capital\, and enlisted Scottish surveyor Alexander Ralston to help lay out the city plan. The L’Enfant Plan featured broad streets and avenues radiating out from rectangles\, providing room for open space and landscaping. L’Enfant based his design on plans of other major world cities\, including Paris\, Amsterdam\, Karlsruhe\, and Milan. \nIn June\, the weather in D.C. averages a high of 85°F (29°C) and a low of 63°F (17°C). Expect rain once every 3-4 days. We hope you take in the sights\, sounds and smells of D.C. Perhaps join us for a 5k fun run/walk around the city monuments! \nWe also want you to experience the museums in addition to the monuments. Some of our classic social events will take place in prized venues. International Spy Museum\, National Museum of the American Indian\, and National Museum of African American History and Culture all host IMS events. \nMake no mistake! We will get down to business at IMS. We expect to have participation from industry\, government and academia. We are engaged with ARL\, DARPA\, NASA-Goddard\, NRL\, NRO\, NIST\, NSWC\, and ONR to name a few. A number of aerospace and defense companies have offices or facilities in the local area\, for example BAE\, Boeing\, Chemring Sensors\, Collins Aerospace\, DRS\, General Dynamics\, Hughes Networks\, Intelsat\, iDirect\, L3Harris\, Ligado Networks\, Lockheed Martin\, Northrop Grumman\, Orbital ATK\, Raytheon\, Thales Defense and Security\, and ViaSat. \nPlease join us for an IMS you cannot afford to miss!
URL:https://marketingeda.com/event/international-microwave-symposium-ims-2024/
LOCATION:Walter E. Washington Convention Center\, 801 Allen Y. Lew Place\, Washington\, DC\, United States
CATEGORIES:Conference,EDA
ATTACH;FMTTYPE=image/jpeg:https://marketingeda.com/wp-content/uploads/IMS-2024.jpg
END:VEVENT
BEGIN:VEVENT
DTSTART;TZID=America/Los_Angeles:20240616T080000
DTEND;TZID=America/Los_Angeles:20240620T170000
DTSTAMP:20240226T234257Z
CREATED:20240226T234257Z
LAST-MODIFIED:20240226T234257Z
UID:7693-1718524800-1718902800@marketingeda.com
SUMMARY:2024 IEEE SYMPOSIUM ON VLSI TECHNOLOGY & CIRCUITS
DESCRIPTION:The five-day event will include: \n\nPlenary Sessions\, Technical Sessions\nEvening Panels\nShort Courses\nWorkshops\nDemo Session for Outstanding Papers\nSSCS / EDS Women in Engineering & Young Professionals events\nTraditional Luau Celebration\n\nThe Symposium will feature selected presentations and panel sessions as well as advanced VLSI technology developments\, innovative circuit designs\, and the applications they enable\, such as artificial intelligence\, machine learning\, IoT\, wearable/implantable biomedical applications\, big data\, cloud / edge computing\, virtual reality (VR) / augmented reality (AR)\, robotics\, and autonomous vehicles.
URL:https://marketingeda.com/event/2024-ieee-symposium-on-vlsi-technology-circuits/
LOCATION:Hilton Hawaiian Village\, 2005 Kālia Rd\, Honolulu\, HI\, 96815\, United States
CATEGORIES:Conference,EDA,IP
ATTACH;FMTTYPE=image/jpeg:https://marketingeda.com/wp-content/uploads/2024-IEEE-Symposium-on-VLSI-Technology.jpg
END:VEVENT
BEGIN:VEVENT
DTSTART;TZID=America/Los_Angeles:20240612T080000
DTEND;TZID=America/Los_Angeles:20240613T170000
DTSTAMP:20240610T171842Z
CREATED:20240610T171842Z
LAST-MODIFIED:20240610T171842Z
UID:8085-1718179200-1718298000@marketingeda.com
SUMMARY:Samsung Foundry Forum & SAFE Forum 2024 U.S.
DESCRIPTION:June 12th\, 2024\n12:30 – 5:30 PM PDT \n\n\n01:35 – 01:50 PM\nSamsung Keynote\nSiyoung Choi\nPresident and GM\, Foundry Business Samsung Electronics\n\n\n\n\n01:50 – 02:05 PM\nThe Accelerated Compute Platform for the Age of AI\nRene Haas\nCEO\nARM\n\n\n\n\n02:05 – 02:20 PM\nGroq’s Transformation of Generative AI ComputeJonathan RossCEO and Founder\n\n\n\n02:20 – 02:55 PM\nSamsung AI Solutions\nTaeJoong Song\nVP\, Head of Business Development\nIndong Kim\nVP\, Head of DRAM Product Planning\nHee Joung Joun\nVP\, AVP Marketing & Strategy Group\nSamsung Electronics\n\n\n\n\n03:25 – 04:00 PM\nProcess Technology\nJa-Hum Ku\nEVP\, Head of Technology Development\nSamsung Electronics\n\n\n\n04:00 – 04:15 PM\nManufacturing Excellence\nSang Sup Jeong\nEVP\, Head of Foundry Manufacturing Technology Center\nSamsung Electronics\n\n\n\n\n04:15 – 04:30 PM\nDesign Platform\nJongwook Kye\nEVP\, Head of Design\nPlatform Development\nSamsung Electronics\n\n\n\n\n04:30 – 04:40 PM\nBusiness & Customers\nSang-Pil Sim\nEVP\, Head of Worldwide Sales and Marketing\nSamsung Electronics\n\nJune 13th\, 2024\n9:00AM-5:30 PM PDT \n\n\n10:00 – 10:15 AM\nWelcome Remarks\nJongwook Kye\nEVP\, Head of Design\nPlatform Development\nSamsung Electronics\n\n\n\n\n10:15 – 10:35 AM\nEnabling a New Era of Design\nMike EllowCEO\nSiemens EDA Silicon Systems\n\n\n\n10:35 – 10:55 AM\nDemand for Power Efficiency in the Age of AI\nBill EnCorporate Vice President\nAMD\n\n\n\n\n10:55 – 11:15 AM\nThe Photonic FabricTM\, Optical Compute Interconnect for Accelerated Computing\nDavid Lazovsky\nCEO and Founder\nCelestial AI\n\n\n\n11:15 – 11:35 AM\nTechnology & Business Update\nTaeJoong Song\nVP\, Head of Business Development\nSamsung Electronics\n\n\n\n\n1:00 – 4:30 PM\nTech Session Ⅰ:\nAdvanced Technology and Design Enablement\nSei Seung Yoon\nEVP\, Head of Library Development\nSungwook Moon\nMaster(VP of Technology)\,\nFoundry Design Service\nSamsung Electronics\n\n1:00 – 4:30 PMTech Session Ⅱ:\nDesign Solutions of AI\, for AI\, and by AI\nJongshin Shin\nEVP\, Head of Foundry IP Ecosystem\nSamsung Electronics
URL:https://marketingeda.com/event/samsung-foundry-forum-safe-forum-2024-u-s/
LOCATION:Samsung Semiconductor US Campus\, 3655 N. First Street\, San Jose\, CA\, United States
CATEGORIES:Forum,Foundry
ATTACH;FMTTYPE=image/jpeg:https://marketingeda.com/wp-content/uploads/Samsung-SAFE-2024-US.jpg
END:VEVENT
BEGIN:VEVENT
DTSTART;TZID=America/Los_Angeles:20240612T080000
DTEND;TZID=America/Los_Angeles:20240613T170000
DTSTAMP:20240522T150924Z
CREATED:20240522T150924Z
LAST-MODIFIED:20240522T150924Z
UID:8019-1718179200-1718298000@marketingeda.com
SUMMARY:PCI-SIG 2024
DESCRIPTION:The PCI-SIG Developers Conference 2024 returned to Santa Clara on June 12-13\, 2024! Members of the PCI-SIG community including systems architects\, designers\, engineers\, and engineering managers attended this event. \nOverview\nThe PCI-SIG Developers Conferences is a free event for our 900+ member companies that develop and bring to market new products utilizing PCI Express® technology. It is an opportunity to learn directly from the industry’s PCIe® experts and participate in technical trainings to gain best practices to improve product roll-out and interoperability. \nThe presentations were captured on video and are available to all members. These recordings provide a valuable opportunity to those who were unable to attend the event and for those who want to re-experience the presentations for more in-depth learning. \nAttendee Registration – Open Now!\nOnline attendee registration is open. All employees of member companies are welcome to attend this exciting conference! \nPCI-SIG Annual Meeting\nThe PCI-SIG Annual Meeting will be held on June 12th\, 2024. This is an opportunity for members to meet with each other\, meet the newly elected PCI-SIG Board of Directors\, and receive the latest PCI-SIG update. Per the bylaws\, the PCI-SIG maintains nine Directors on its Board. Registration for the Annual meeting is the same link as the Developers Conference. \nPCI Board Panel \nFollowing a positive response from last year’s panel\, we will be holding another Board Panel at this year’s US DevCon. We are currently accepting questions from members for the Board of Directors to address during the panel discussion. If you have a question you would like to submit\, please email them to pcidevcon@pcisig.com. \nCall for Papers – Closed\nYou will not want to miss this series of presentations as PCI-SIG members present unique tips\, tricks\, and pitfalls learned during their implementation of PCI technology. \nIf you are interested in submitting an abstract for consideration\, we encourage you to review the online Call for Papers instructions and milestones.  \n*Note that registering and submitting materials does not guarantee you will be selected as a speaker at this event. We will follow up with those selected following the associated deadlines and provide notice to those not chosen.  \nSponsorship Registration – Closed\nPCI-SIG member companies will have the opportunity to demonstrate their company’s industry leadership in advancing the PCI landscape by participating as a Sponsor of the PCI-SIG DevCon 2024. Sponsor opportunities offer a variety of benefits including onsite presence and logo promotion. \nTo review sponsor opportunities\, please visit the PCI-SIG Sponsor Opportunities web page. \nConnect with us on LinkedIn and Twitter @pci_sig #PCISIGDevCon24 \nTo leverage PCI-SIG public relations services including media relations\, event and press release support\, please contact: pr@pcisig.com.
URL:https://marketingeda.com/event/pci-sig-2024/
LOCATION:Santa Clara Convention Center\, 5001 Great America Parkway\, Santa Clara\, CA\, 95054\, United States
CATEGORIES:Conference,IP
ATTACH;FMTTYPE=image/jpeg:https://marketingeda.com/wp-content/uploads/PCI-SIG-2024.jpg
END:VEVENT
BEGIN:VEVENT
DTSTART;TZID=America/Los_Angeles:20240611T090000
DTEND;TZID=America/Los_Angeles:20240611T170000
DTSTAMP:20240508T184358Z
CREATED:20240508T183624Z
LAST-MODIFIED:20240508T184358Z
UID:7972-1718096400-1718125200@marketingeda.com
SUMMARY:2024 ANDES RISC-V CON
DESCRIPTION:Recently\, RISC-V\, with its open\, streamlined\, and scalable configuration\, has become the mainstream solution adopted by leading market players\, paving the way for widespread technological innovation. In the RISC-V application field\, there has been rapid development in forward-looking areas such as automotive electronics and AI. The development application processors has attracted a lot of attention\, and the need for product information security has also increased. \nAs a Premier member and a leading brand in 32/64-bit embedded CPU cores\, Andes\, a member of RISC-V International\, will host an annual seminar on June 11 at the DoubleTree by Hilton San Jose. The theme of the seminar is “ANDES RISC-V CON: Deep Dive into Automotive/AI/Application Processors and Security Trends.” The event aims to introduce the market dynamics and development trends of RISC-V\, discuss Andes’ comprehensive product portfolio recently launched\, and assist industries in fully utilizing the high-performance/low-power characteristics of the RISC-V architecture to enhance product competitiveness and move towards a future full of opportunities. \nThe seminar will feature presentations and on-site demonstrations by numerous RISC-V ecosystem partners\, providing insights into the latest international trends and technological developments in RISC-V. Let us join hands to celebrate this event and explore the potential of RISC-V together with industry experts\, paving the way for a diverse application vision! \nHere is our event schedule \n09:00 – 09:25 Registration\n09:25 – 09:30 Opening-Market Watch\, Frankwell Lin\, Chairman & CEO\, Andes Technology\n09:30 – 09:50 Customer Use Case Presentation\n09:50 – 10:25 Unlocking RISC-V’s potential on Intelligence Application Processing\, Dr. Charlie Su\, President & CTO\, Andes Technology\n10:25 – 10:45 Safe and Secure Software Solutions for Andes RISC-V\, Robert Redfield\, Director of Business Development\, Green Hills Software\nGreen Hills Software and Andes Technology offer combined capabilities for the AndeStar™ V5 Architecture\, enabling the efficient development and confident deployment of RISC-V-based designs in systems with critical requirements for functional safety and security. Green Hills Software’s offering features real-time operating systems\, powerful compilers and advanced C/C++ development tools that leverage the company’s 40-years of microprocessor experience. \n10:45 – 11:05 Lauterbach Debug and Trace of Andes RISC-V Processors\, Dennis Griffiths\, Field Applications Engineer\, Lauterbach\nLauterbach\, the leader in RISC-V debug and trace\, will be discussing and demonstrating the TRACE32 tools for the Andes N27 on the Big Orca reference hardware.Using our TRACE32® tools you can debug and control any RISC-V core (along with all of the other cores) in any SoC via a single debug interface\, all at the same time. TRACE32® tools support real-time on- and off-chip tracing for all major RISC-V trace systems. \n11:05 – 11:35 Break\n11:35 – 11:55 Customer Use Case Presentation\n11:55 – 12:15 Ecosystem Partners Showcase – Siemens EDA\n12:15 – 13:15 Lunch\n13:15 – 14:05 RISC-V Ecosystem Panel: Open-Source is Transforming AI and Hardware\nModerator: Dylan Patel\, Chief Analyst\, SemiAnalysis\nPanelist: Charlie Cheng\, CEO\, Cucina\, Inc.\nPlease stay tuned for the mystery guest\nPlease stay tuned for the mystery guest\nPlease stay tuned for the mystery guest\nPlease stay tuned for the mystery guest\n14:05 – 14:35 Driving Safe and Secure Innovations with Andes RISC-V Solutions\, Andes Technology\n14:35 – 15:05 Break\n15:05 – 15:25 Synopsys Solutions Empower Software Development on Andes Processors\, Larry Lapides\, Business Development Director\, Synopsys\nAndes processor IP is increasingly being used in high performance applications such as AI/ML\, and in use cases where there are reliability\, safety and security requirements. For these and other advanced applications software development is critical. Starting software development early\, before RTL is ready\, can accelerate software tasks by months. Other key pieces of the software task include hardware-software co-verification\, building prototypes and enabling CI/CD software methodology in production. Synopsys tools\, including ImperasFPM fast processor models of the Andes cores\, Virtualizer for virtual prototypes\, and the HAPS and ZeBu hardware-assisted verification tools\, have been supporting and enabling Andes customers for more than 5 years. This talk will discuss software methodology in general\, and provide case studies of Andes-Synopsys joint customers. \n15:25 – 15:45 Are you a professional developer? Then why use amateur tools? Shawn Prestridge\, US FAE Manager\, IAR\nWhat can professional tools bring to a professional developer? Many features that optimize your time\, such as live instruction tracing\, complex and conditional breakpoint types\, functional safety certification\, comprehensive live technical support\, and much more. The optional code analysis tools can also help you quickly spot code issues while you are desk-checking your code to make your code fast and accurate. This session will quickly cover the benefits that each of these features brings in terms of time (and ultimately\, money) savings. Your time isn’t free – optimize it by using tools commensurate with your talent that allow you to deliver your product to market as quickly as possible! \n5:45 – 16:35 RISC-V Ecosystem Panel: Unlocking the RISC-V Application Processor Potential\nThe Application Processor market presents a tens-of-billions annual value opportunity\, which expands by an order of magnitude at the device scope\, and is similarly scaled\, if not more\, at the software application level. The target segments are diverse\, ranging from consumer electronics and industrial computing to automotive\, networking\, and communications. The incumbent compute ISAs for application processors are either Arm or x86\, but RISC-V has emerged as a fast-evolving and maturing alternative\, gaining strong traction across the value chain. This growth is fueled by the advent of AI\, whose support is becoming ubiquitous across all compute platforms\, with RISC-V offering significant value for AI computing. Initiatives like defining and ratifying an iterative set of extensions for the RISC-V application (RVA) profile have established a standard architecture base\, enabling hardware and software vendors to develop interoperable solutions. Efforts by organizations like RISE and major Linux-based and Android-based operating system providers have accelerated the software-based infrastructure support for RISC-V. Despite these advancements\, challenges remain in areas such as ecosystem maturity\, hardware performance and availability\, software compatibility\, and general public perception. This panel discussion will delve into these exciting topics to explore the opportunities\, the progress made\, and how to overcome these challenges to unlock the potential of RISC-V application processors. \nModerator: Mark Himelstein\, Heavenstone\, Inc.\nPanelist: Dr. Charlie Su\, President & CTO\, Andes Technology\nLars Bergstrom\, Director of Engineering\, Android team\, Google\nBarna Ibrahim\, Vice-Chair\, RISE\nDr. Sandro Pinto\, Co-founder\, OSYX Technologies\n16:35 – 17:00 Lucky Draw & Evening Reception
URL:https://marketingeda.com/event/2024-andes-risc-v-con/
LOCATION:The DoubleTree by Hilton\, 2050 Gateway Place\, San Jose\, CA\, United States
CATEGORIES:Conference,IP
ATTACH;FMTTYPE=image/jpeg:https://marketingeda.com/wp-content/uploads/Andes-June-11-2024.jpg
END:VEVENT
BEGIN:VEVENT
DTSTART;TZID=Europe/Berlin:20240610T080000
DTEND;TZID=Europe/Berlin:20240611T170000
DTSTAMP:20240503T162031Z
CREATED:20240503T162031Z
LAST-MODIFIED:20240503T162031Z
UID:7940-1718006400-1718125200@marketingeda.com
SUMMARY:SNUG Europe 2024
DESCRIPTION:Connecting the Synopsys User Community\nSince 1991\, the Synopsys Users Group (SNUG) has represented a global design community focused on innovating from Silicon to Software. Today\, as the electronics industry’s largest user conference\, SNUG brings together over 12\,000 Synopsys tool and technology users across North America\, Europe\, Asia\, and Japan. In addition to peer-reviewed technical presentations and insightful keynotes from industry leaders\, SNUG provides a unique opportunity to connect with Synopsys executives\, design ecosystem partners\, and members of your design community. \nJoin your fellow engineers at SNUG to hear practical information you can use on your current projects and the inspiration to create Smart Everything. \n\n\n\n\n\nTechnical Committee\n\nSNUG thanks the members of the Technical Committee who volunteer their time and expertise to support SNUG’s technical quality and deliver the benefit of their perspective to the users of Synopsys tools and technology.\n\n\n\n\n\n\n\n\n\n\n\n\n\n\nTechnical Committee Chair: \n\n\nFrank Poppen\, NXP Semiconductors \n\n\n\n\n\n\n\n\n\n\n\n\n\n\n\n\n\n\n\n\n\nCommittee Members: \nAlessandro Valerio\, STMicroelectronics \nAndreas Kuesel\, Micron Semiconductor GmbH \nAnshuman Anand\, Infineon \nCecile Specq\, STMicroelectronics \nClaus Kuntzsch\, University of Applied Sciences Nuremberg \nDidier Maurer\, IC’ALPS \nEnrico Castaldo\, STMicroelectronics \nFarid Labib\, GLOBALFOUNDRIES \nGiuseppe Notarangelo\, STMicroelectronics \nKarsten Matt\, GLOBALFOUNDRIES \nLars Graversen\, Demant (Oticon) \nLaurent Besson\, Easii IC \n\n\n\n\n\n\n\n\n\n\n\n\n\n\nMajid Ghameshlu\, Siemens AG (Austria) \nManfred Thanner\, NXP Semiconductors \nNathalie Meloux\, STMicroelectronics \nPeter Grove\, Renesas \nPierluigi Daglio\, STMicroelectronics \nRalph Goergen\, NXP Semiconductors \nRobert Siegmund\, GLOBALFOUNDRIES \nRoberto Anelli\, Nordic Semiconductor \nStefan Scharfenberg\, NXP \nSylvie Pierunek\, STMicroelectronics \nTarun Chawla\, STMicroelectronics \nThomas Buerner\, Nokia \nThomas Haase\, Renesas
URL:https://marketingeda.com/event/snug-europe-2024/
LOCATION:Hilton Munich Airport\, Terminalstraße Mitte 20\, 85356 München-Flughafen\, Munich\, Germany
CATEGORIES:EDA,IP,User Group
ATTACH;FMTTYPE=image/jpeg:https://marketingeda.com/wp-content/uploads/SNUG-Europe-2024.jpg
END:VEVENT
BEGIN:VEVENT
DTSTART;TZID=America/Los_Angeles:20240606T100000
DTEND;TZID=America/Los_Angeles:20240606T110000
DTSTAMP:20240524T015255Z
CREATED:20240524T015255Z
LAST-MODIFIED:20240524T015255Z
UID:8034-1717668000-1717671600@marketingeda.com
SUMMARY:Addressing Thermal Stress and Warpage Challenges in 3D-IC Designs
DESCRIPTION:Thermal stress analysis plays a crucial role in the design and performance optimization of packaging materials and boards\, especially in industries where temperature variations are significant. This webinar presents a comprehensive overview of recent developments in the newly-introduced Cadence Celsius Studio AI-enabled multiphysics thermal platform to solve today’s thermal stress and warpage analysis in 3D-ICs. \nCelsius Studio offers support for linear and nonlinear material structural models as well as static and quasi-static solvers for warpage and stress analysis and a moisture solver and high-temperature\, high-humidity (HTHH) analysis. Designers can perform multi-stage simulations for the design assembly process and material failure and reliability analysis. There are global and local models for 3D-IC warpage/stress simulation. \nYou will learn about: \n\nRecent developments in Celsius Studio that address thermal stress and warpage analysis in 3D-ICs\, including die-to-die sacking\, packing\, and boards warpage\nKey methods that can be used to address factors affecting thermal stress\, including nonlinear material properties\, geometric configuration\, and environmental conditions\nExample models for 3D-IC warpage/stress simulation
URL:https://marketingeda.com/event/addressing-thermal-stress-and-warpage-challenges-in-3d-ic-designs/
CATEGORIES:EDA,Webinar
ATTACH;FMTTYPE=image/jpeg:https://marketingeda.com/wp-content/uploads/Cadence-June-6-2024.jpg
END:VEVENT
BEGIN:VEVENT
DTSTART;TZID=Europe/Zurich:20240606T080000
DTEND;TZID=Europe/Zurich:20240607T170000
DTSTAMP:20240524T163724Z
CREATED:20240524T163724Z
LAST-MODIFIED:20240524T163724Z
UID:8038-1717660800-1717779600@marketingeda.com
SUMMARY:International Workshop on Logic and Synthesis - IWLS 2024
DESCRIPTION:The International Workshop on Logic and Synthesis is the premier forum for research in synthesis\, optimization\, and verification of integrated circuits and systems. Research on logic synthesis for emerging technologies and for novel computing platforms\, such as nanoscale systems and biological systems\, is also strongly encouraged. The workshop encourages the early dissemination of ideas and results. The workshop accepts complete papers highlighting important new problems in the early stages of development\, without providing complete solutions. The emphasis is on novelty and intellectual rigor. \nTopics of interest include but are not limited to: hardware synthesis and optimization; software synthesis; hardware/software co-synthesis; power and timing analysis; testing\, validation\, and verification; synthesis for reconfigurable architectures; hardware compilation for domain-specific languages; and design experiences. Submissions on modeling\, analysis\, and synthesis for emerging technologies and platforms are particularly encouraged. \nThe workshop format includes paper presentations\, invited talks\, social lunch and dinner gatherings\, and recreational activities. \nCheck out our call for papers. \nKeynotes\nCan AI Design and Verify Your Design?\nZiyad Hanna\, Cadence Design Systems\, Israel \n\nAbstract: In this talk\, I will explore the significant impact of artificial intelligence (AI) in addressing the mounting complexity and demands within chip design domain. With an anticipated exponential growth in annual revenue reaching the trillion-dollar mark\, driven by the rapid growth in key markets in 5G\, Hyperscalers\, autonomous vehicles\, AI\, and industrial IoT. The chip design market is trending into a fourfold increase in project volume with tenfold complexity. The current design and verification methodologies are lacking in capacity to meet this surge\, highlighting the shortage of qualified engineers to meet the aggressive market demand. AI technologies stand at the forefront of transforming design and verification processes\, offering unparalleled efficiency and cost-effective solutions to meet the escalating market needs. In this talk\, I will address the inherent challenges in the chip design industry\, analyze the current landscape of automation\, machine learning (ML)\, and cutting-edge generative AI technologies. I will also discuss a strategic direction for harnessing AI to enhance design synthesis and verification\, including the automatic generation of programs supported by natural language processing (NLP) and generative AI\, the creation of temporal assertions from design specifications\, the integration of high-level synthesis (HLS) and formal verification\, and the exploration of the latest advancements in AI technologies for full design and verification flow for achieving the aggressive demand on performance\, power and area. Furthermore\, the presentation emphasizes the essence for collaborative initiatives between industry and academia to drive forward transformative advancements and innovations within the chip design and verification domain with AI. \nZiyad Hanna\, Ph.D.\, is currently a corporate VP at Cadence Design Systems (CDNS)\, and the general manager of Cadence Israel\, leading R&D centers in various countries\, in the electronic design automation domain. Prior to joining Cadence Design Systems\, Dr. Hanna was a Senior VP at Jasper Design Automation\, which was acquired by Cadence in 2014. At Jasper\, Dr. Hanna worked in the fast-emerging domain of formal verification technology and applications. Dr. Hanna was also an Intel Senior Principal Engineer and R&D Group Leader at Intel Haifa\, where he was instrumental in the development of several generations of formal verification systems\, which were used on almost all Intel microprocessor designs since early 1990s\, and was twice the recipient of Intel’s highest Achievement Award (IAA). He received both his BS and MS degrees in Computer Science at Tel Aviv University\, and his PhD in Computer Science from the University of Oxford. Besides his leadership at Cadence\, Prof. Hanna is currently serving as a visiting professor of Computer Science at Oxford. Dr. Hanna is a senior IEEE member\, holds over 15 patents\, and has published more than 80 papers and talks.\n\n\nSymmetric Is Better: Can We Exploit Regularities in Logic Synthesis?\nValentina Ciriani\, University of Milano\, Italy \n\nAbstract: The standard synthesis of Boolean functions is aimed at designing optimized circuits according to given cost criteria. For this purpose\, the algebraic form of the function is manipulated\, as it directly reflects the cost of the corresponding circuit. Depending on the design needs\, different two-level or multi-level forms are considered\, and ad hoc algorithms are used to express and minimize such forms. In all cases\, the functions under consideration encode “real life” problems\, hence they often exhibit a “regular” structure that can be exploited by synthesis algorithms. This talk aims to describe several function regularities based on the EXOR operator. Moreover\, we show how these regularities can be exploited in logic synthesis for standard and emerging technologies. Finally\, we show how regularities can also ease polynomial verification. \nValentina Ciriani received the Laurea degree and the Ph.D. degree in Computer Science from the University of Pisa\, Italy\, in 1998 and 2003\, respectively. In 2003 and 2004 she was with the Department Computer Science at University Pisa\, Italy as a Ph.D. fellow. From 2005 to 2015 she was an assistant professor in Computer Science at the Department of Computer Science\, University of Milano\, Italy. She is currently an Associate Professor in Computer Science with the Department of Computer Science of the University of Milano (Italy). Her research interests include algorithms and data structures\, as well as combinational logic synthesis for classical and emerging technologies. She has authored or coauthored more than 100 research papers\, published in international journals\, conference proceedings\, and books chapters.\n\n\n\nToward Software-to-Atoms Open-Source RISC-V Computing Platforms: Is Open-Source Synthesis Ready for Prime Time?\nLuca Benini\, ETH Zurich / University of Bologna\, Switzerland / Italy \n\nAbstract: The success of the RISC-V free and open ISA has ushered us in the era Open-source computing hardware. As of today\, open-source designs exist targeting a wide range of RISC-V based computing systems\, from tiny microcontrollers to high-performance many-core\, and industry adoption of open-source computing hardware is accelerating. However a key open question is if we can\, or even should\, push further\, open sourcing design automation tools and technology libraries\, PDKs\, toward the vision of enabling “software-to-atoms” open source computing platforms. In this talk I will try assess where we stand and provide a personal view on key challenges and future trajectories\, drawing from a decade of experience in designing and industrializing open source hardware. \nLuca Benini holds the chair of digital Circuits and systems at ETHZ and is Full Professor at the Universita di Bologna. He received a PhD from Stanford University. Dr. Benini’s research interests are in energy-efficient parallel computing systems\, smart sensing micro-systems and machine learning hardware. He is a Fellow of the IEEE\, of the ACM and a member of the Academia Europaea. He is the recipient of the 2016 IEEE CAS Mac Van Valkenburg award\, the 2020 EDAA achievement Award\, the 2020 ACM/IEEE A. Richard Newton Award and the 2023 IEEE CS E.J. McCluskey Award.
URL:https://marketingeda.com/event/international-workshop-on-logic-and-synthesis-iwls-2024/
LOCATION:ETH Zurich\, Rämistrasse 101\, Zurich\, Switzerland
CATEGORIES:Conference,EDA
ATTACH;FMTTYPE=image/jpeg:https://marketingeda.com/wp-content/uploads/IWLS-2024.jpg
END:VEVENT
BEGIN:VEVENT
DTSTART;TZID=America/Chicago:20240606T080000
DTEND;TZID=America/Chicago:20240606T170000
DTSTAMP:20240506T222541Z
CREATED:20240506T222446Z
LAST-MODIFIED:20240506T222541Z
UID:7961-1717660800-1717693200@marketingeda.com
SUMMARY:Verification Academy Live: Huntsville
DESCRIPTION:Siemens Training Center\n360E Quality Circle\, Suite 500\nHuntsville\, AL 35806\n+1 (256) 705-2501 \nThis event is in-person only — there is no support for remote participation. \nAgenda \n\n\n\n9:30 – 10:00\nRegistration and Check-in \nCoffee and networking with your peers.\n\n\n10:00 – 10:05\nWelcome / Intro\nTodd Holbrook | Sr. Application Engineering Manager\, Functional Verification\n\n\n10:05 – 11:00\nBeyond Speed: Unlocking Productivity in Simulation and Debug\nMoses Satyasekaran | Director\, Simulation\nGone are the days when functional verification tools were solely measured by their performance metrics. The spotlight has shifted towards productivity enhancement in today’s fast-paced development environment. Join us as we explore how Siemens EDA prioritizes productivity and performance\, enabling customers to optimize their verification cycles and swiftly uncover bugs. Discover the transformative impact of this paradigm shift on accelerating design validation and achieving faster time-to-market.\n\n\n11:00 – Noon\nImprove Productivity and Deliver Hardware Assurance: Stimulus-free Verification\nChris Giles | Director\, Formal Verification\nLearn how Siemens’ and OneSpin have combined to deliver a best-in-class Static & Formal solution with a focus on addressing unsolved industry challenges. These solutions enable teams to achieve peak performance and deliver absolute hardware assurance.\n\n\nNoon – 1:00\nLunch and networking\n\n\n1:00 – 1:45\nThe New Leader in Verification IP: Questa + Avery Solutions\nKamlesh Mulchadani | Product Engineer\nNow that our acquisition of Avery Design Systems is complete\, Siemens EDA is the new leader for Verification IP in the industry. This session will describe the protocol and memory verification solutions you need for your next silicon verification project whether in Datacenter\, Storage\, 3DIC\, Networking\, Automotive\, or Aerospace and Defense applications.\n\n\n1:45 – 3:00\nQuesta Verification IQ: \nBoost verification predictability and efficiency with Big Data\nAustin Mam | Product Engineer\nThis session will cover Questa Verification IQ (VIQ)\, the next-generation\, data-driven verification solution from Siemens EDA that transforms the verification process using analytics\, collaboration\, and traceability. VIQ utilizes machine learning to boost verification productivity and is built on collective feedback gathered from verification teams over many years.\n\n\n3:00 – 4:00\nWrap-up and Networking
URL:https://marketingeda.com/event/verification-academy-live-huntsville/
LOCATION:Siemens Training Center\, 360E Quality Circle\, Suite 500\, Huntsville\, AL\, United States
CATEGORIES:EDA
ATTACH;FMTTYPE=image/jpeg:https://marketingeda.com/wp-content/uploads/Siemens-June-6-2024.jpg
END:VEVENT
BEGIN:VEVENT
DTSTART;TZID=America/Los_Angeles:20240604T100000
DTEND;TZID=America/Los_Angeles:20240604T110000
DTSTAMP:20240524T203508Z
CREATED:20240524T203431Z
LAST-MODIFIED:20240524T203508Z
UID:8046-1717495200-1717498800@marketingeda.com
SUMMARY:Silicon.da: The First Integrated SLM Analytics Solution from Design Through Manufacturing
DESCRIPTION:Today’s advanced node chip designs are faced with many new complexities which require more verification\, more validation and more analysis. The resulting data from these added steps has also grown exponentially and engineers need a way to efficiently analyze this information. The result is a new paradigm shift which has led to data overload requiring tools to collect huge amounts of data from design\, test and manufacturing (petabytes)\, analyze the data\, and provide actionable insights on that data. \nPart of the Synopsys.da AI analytics tools\,  Synopsys’ Silicon.da is the first integrated SLM analytics solution that addresses post-silicon challenges by increasing engineering productivity\, improving silicon efficiency and providing the tool scalability needed for today’s advanced SoC’s. Silicon.da serves a critical role as part of an overall SLM solution dedicated to improving the health and operational metrics of a silicon device across its complete lifecycle. \nIn this presentation\, Mr. Anti Tseng\, Senior Manager at MediaTek\, will explain how Silicon.da’s volume diagnostics feature identified systematic issues more efficiently than traditional methods by providing very accurate failure locations within the silicon resulting in improved yield by a single digit percentage and in a shorter amount of time – from weeks to days. Mr. Tseng will also further discuss how utilizing this volume diagnosis analysis technology improves the foundry process for advanced nodes resulting in millions of dollars of cost savings through high volume chip production for fabless companies. \n\n\n\n\n\n\n\n\n\n\nSpeakers\n\n\nListed below are the industry leaders scheduled to speak. \n\n\n\n\n\n\n\n\n\n\n\n\n\n\n\nAnti Tseng\n\n\nSenior Manager\nMediaTek \n\n\n\n\n\n\n\n\n\n\n\nAnti Tseng has been with MediaTek for 16 years and mainly covered three categories: CPU implementation/DFT/MBIST\, silicon speed binning & manufacture process debug\, in-house data platform & CAD flow development. His current focus is to enable smooth mass production of first advanced process node in MediaTek by exploring next-generation DFT architecture\, ATPG & diagnosis flow\, and AI-based data analysis. \n\n\n\n\n\n\n\n\n\n\n\n\n\n\n\n\n\n\n\n\nGuy Cortez\n\n\nProduct Management\, Principal\nSynopsys \n\n\n\n\n\n\n\n\n\n\n\nGuy Cortez is principal\, product management at Synopsys. His marketing career spans over 25 years where he has held various marketing positions including technical\, product/solution\, channel/field\, integrated/corporate\, alliance and business development for companies such as Synopsys\, Cadence\, VMware and Optimal+. Prior to that he spent 12 years as a test engineer at Hughes Aircraft Company (now Boeing)\, and later at Sunrise Test Systems (which became Viewlogic and later Synopsys). At Hughes\, he was responsible for generating all of the manufacturing test programs for the ASICs developed in the Missile Systems Group division. At Sunrise\, Cortez was a pre- and post-sales applications engineer\, and also doubled as the company’s instructor.
URL:https://marketingeda.com/event/silicon-da-the-first-integrated-slm-analytics-solution-from-design-through-manufacturing/
CATEGORIES:EDA,Webinar
ATTACH;FMTTYPE=image/jpeg:https://marketingeda.com/wp-content/uploads/Synopsys-June-4-2024.jpg
END:VEVENT
BEGIN:VEVENT
DTSTART;TZID=America/New_York:20240604T093000
DTEND;TZID=America/New_York:20240604T160000
DTSTAMP:20240506T221850Z
CREATED:20240506T221850Z
LAST-MODIFIED:20240506T221850Z
UID:7957-1717493400-1717516800@marketingeda.com
SUMMARY:Verification Academy Live: Westford (Boston Area)
DESCRIPTION:Westford Regency Inn and Conference Center\n219 Littleton Rd\nWestford\, MA 01886\n+1 (978) 692-8200 \nThis event is in-person only — there is no support for remote participation. \nAgenda \n\n\n\n9:30 – 10:00\nRegistration and Check-in \nCoffee and networking with your peers.\n\n\n10:00 – 10:05\nWelcome / Intro\nTodd Holbrook | Sr. Application Engineering Manager\, Functional Verification\n\n\n10:05 – 11:00\nBeyond Speed: Unlocking Productivity in Simulation and Debug\nMoses Satyasekaran | Director\, Simulation\nGone are the days when functional verification tools were solely measured by their performance metrics. The spotlight has shifted towards productivity enhancement in today’s fast-paced development environment. Join us as we explore how Siemens EDA prioritizes productivity and performance\, enabling customers to optimize their verification cycles and swiftly uncover bugs. Discover the transformative impact of this paradigm shift on accelerating design validation and achieving faster time-to-market.\n\n\n11:00 – Noon\nImprove Productivity and Deliver Hardware Assurance: Stimulus-free Verification\nChris Giles | Director\, Formal Verification\nLearn how Siemens’ and OneSpin have combined to deliver a best-in-class Static & Formal solution with a focus on addressing unsolved industry challenges. These solutions enable teams to achieve peak performance and deliver absolute hardware assurance.\n\n\nNoon – 1:00\nLunch and networking\n\n\n1:00 – 1:45\nThe New Leader in Verification IP: Questa + Avery Solutions\nKamlesh Mulchadani | Product Engineer\nNow that our acquisition of Avery Design Systems is complete\, Siemens EDA is the new leader for Verification IP in the industry. This session will describe the protocol and memory verification solutions you need for your next silicon verification project whether in Datacenter\, Storage\, 3DIC\, Networking\, Automotive\, or Aerospace and Defense applications.\n\n\n1:45 – 3:00\nQuesta Verification IQ: \nBoost verification predictability and efficiency with Big Data\nAustin Mam | Product Engineer\nThis session will cover Questa Verification IQ (VIQ)\, the next-generation\, data-driven verification solution from Siemens EDA that transforms the verification process using analytics\, collaboration\, and traceability. VIQ utilizes machine learning to boost verification productivity and is built on collective feedback gathered from verification teams over many years.\n\n\n3:00 – 4:00\nWrap-up and Networking
URL:https://marketingeda.com/event/verification-academy-live-westford-boston-area/
LOCATION:Westford Regency Inn and Conference Center\, 219 Littleton Rd\, Westford\, MA\, United States
CATEGORIES:EDA
ATTACH;FMTTYPE=image/jpeg:https://marketingeda.com/wp-content/uploads/Siemens-June-4-2024.jpg
END:VEVENT
BEGIN:VEVENT
DTSTART;TZID=America/Los_Angeles:20240604T080000
DTEND;TZID=America/Los_Angeles:20240607T170000
DTSTAMP:20240528T161702Z
CREATED:20240528T161702Z
LAST-MODIFIED:20240528T161702Z
UID:8052-1717488000-1717779600@marketingeda.com
SUMMARY:PCB East 2024
DESCRIPTION:The Electronics Industry’s East Coast Conference and Exhibition. \n1. Educational opportunities.\nNo matter how experienced you are\, everyone can learn! PCB East is widely acknowledged as the best technical conference in the industry. \n2. Networking with peers.\nCollaboration\, inspiration\, and more! \n3. New vendors and suppliers.\nTools and materials are always changing. Keeping up is paramount. \n4. Position yourself as an expert.\nWhy be the best-kept secret in the industry? \n5. It’s fun!\nAll work and no play gets old and fast. Manage your career growth with a social aspect!
URL:https://marketingeda.com/event/pcb-east-2024/
LOCATION:Boxboro Regency Hotel and Conference Center\, 242 Adams Pl\, Boxborough\, MA\, United States
CATEGORIES:Conference,EDA
ATTACH;FMTTYPE=image/jpeg:https://marketingeda.com/wp-content/uploads/PCB-East-2024.jpg
END:VEVENT
BEGIN:VEVENT
DTSTART;TZID=America/Los_Angeles:20240603T080000
DTEND;TZID=America/Los_Angeles:20240605T170000
DTSTAMP:20240521T161743Z
CREATED:20240521T161743Z
LAST-MODIFIED:20240521T161743Z
UID:8007-1717401600-1717606800@marketingeda.com
SUMMARY:Advantest VOICE 2024
DESCRIPTION:VOICE is a developer conference\, created by test engineers for test engineers.\n\n\n\n\n\n\n\n\nEach year\, the VOICE Developer Conference unites semiconductor test professionals representing the world’s leading integrated device manufacturers (IDMs)\, foundries\, fabless semiconductor companies and outsourced semiconductor assembly and test (OSAT) providers to exchange information about the latest technology advancements\, express new ideas\, share best practices and network with one another. \nAdvantest’s annual VOICE Developer Conference is the leading premier forum for the growing international community of users and strategic partners involved with Advantest’s V93000 and T2000 SoC test platforms as well as Advantest memory testers\, handlers and test cell solutions\, product engineering\, and test technology. \nVOICE promises a collaboration of minds and ample opportunities for peer networking. Join us at VOICE for a dynamic and memorable conference experience! \nAttendees gain valuable insights into the newest test solutions and best practices\, forge long-lasting relationships\, learn about the latest and upcoming equipment and technology from Advantest\, and much more through VOICE’s technical information-rich agenda\, which includes: \n\nKeynote speakers\nTechnical paper presentations\nPartners’ Expo\nTechnology Kiosk Showcases\nNetworking\nWorkshop Day
URL:https://marketingeda.com/event/advantest-voice-2024/
LOCATION:Hilton La Jolla Torrey Pines\, 10950 N Torrey Pines Rd\, La Jolla\, CA\, United States
CATEGORIES:Conference
ATTACH;FMTTYPE=image/jpeg:https://marketingeda.com/wp-content/uploads/VOICE-2024.jpg
END:VEVENT
BEGIN:VEVENT
DTSTART;TZID=America/Los_Angeles:20240530T100000
DTEND;TZID=America/Los_Angeles:20240530T110000
DTSTAMP:20240521T001952Z
CREATED:20240521T001952Z
LAST-MODIFIED:20240521T001952Z
UID:8004-1717063200-1717066800@marketingeda.com
SUMMARY:Addressing Real-Time Workloads in Automotive Applications with Efficient ARC-V Processors
DESCRIPTION:Many automotive applications require processing workloads with minimum latency and precise timing budgets.  This is especially true for safety-critical applications like adaptive cruise control and anti-lock braking\, where human life may be jeopardized.  These systems require processing elements that can respond to events within specific (predictable) time constraints. System reliability and availability depend on the effectiveness of this real-time processing. \nIn this webinar\, we will outline examples of safety-critical applications and why real-time processing is required to maintain the highest levels of safety and reliability.  We will also discuss Synopsys’ ARC-V™ RHX processor series and how these power/performance efficient processors address the real-time requirements of these applications. \n\n\n\n\n\n\n\n\n\n\nSpeaker\n\n\n\n\n\n\n\n\n\n\n\n\n\n\n\n\nRich Collins\n\n\nSr. Product Management Director\nSynopsys \n\n\n\n\n\n\n\n\n\n\n\nRich Collins is senior product managemet director for the ARC-V  RISC-V based processor portfolio at Synopsys and has over 30 years of experience in embedded semiconductor R&D\, product marketing and business development. Rich holds an MBA from Duke University’s Fuqua School of Business and a BSE in Electrical Engineering from Duke University.
URL:https://marketingeda.com/event/addressing-real-time-workloads-in-automotive-applications-with-efficient-arc-v-processors/
CATEGORIES:IP,Webinar
ATTACH;FMTTYPE=image/jpeg:https://marketingeda.com/wp-content/uploads/Synopsys-May-30-2024.jpg
END:VEVENT
BEGIN:VEVENT
DTSTART;TZID=America/Los_Angeles:20240530T080000
DTEND;TZID=America/Los_Angeles:20240530T090000
DTSTAMP:20240521T162703Z
CREATED:20240521T162703Z
LAST-MODIFIED:20240521T162703Z
UID:8011-1717056000-1717059600@marketingeda.com
SUMMARY:Optimizing connectivity between Xpedition and HFSS for RF systems design
DESCRIPTION:In today’s fast-paced technological landscape\, seamless integration between design and simulation tools is crucial for accelerating product development cycles and ensuring optimal performance of electronics\, especially RF systems. Siemens Xpedition and Ansys HFSS stand as pillars in their respective domains\, offering powerful capabilities for electronic design and electromagnetic simulation. \nIn this live conversation\, Sara Louie from Ansys and Per Viklund from Siemens will describe the two-way connectivity between Siemens Xpedition and Ansys HFSS\, revolutionizing the electronic design and simulation workflow. We delve into the details of bidirectional data exchange\, enabling engineers to seamlessly transfer layout geometries and parameters between the two platforms.
URL:https://marketingeda.com/event/optimizing-connectivity-between-xpedition-and-hfss-for-rf-systems-design/
CATEGORIES:EDA,Webinar
ATTACH;FMTTYPE=image/jpeg:https://marketingeda.com/wp-content/uploads/Xpedition-HFSS-May-30-2024.jpg
END:VEVENT
BEGIN:VEVENT
DTSTART;TZID=America/Los_Angeles:20240529T100000
DTEND;TZID=America/Los_Angeles:20240529T110000
DTSTAMP:20240521T001409Z
CREATED:20240521T001409Z
LAST-MODIFIED:20240521T001409Z
UID:8001-1716976800-1716980400@marketingeda.com
SUMMARY:Reimagining Synopsys SLM PVT Monitoring IP for Advanced Node GAA Process
DESCRIPTION:Synopsys’ SLM PVT Monitor (process detector\, voltage monitor\, temperature sensor) IP can collect voltage\, temperature\, and process parameters from different blocks within the IC in real time. These data can be analyzed and used to take meaningful action to optimize the performance of the chip at any stage of silicon lifecycle. This webinar focuses on how the monitors need to move from analog to digital sensing paradigm due to the design constraints introduced by GAA nodes. \nIn this webinar\, you will learn: \n\nSilicon Lifecycle Management (SLM) overview and the crucial role of PVT IP\nOverview of each component in the PVT IP portfolio – rearchitecting from analog to digital sensing\nPVT IP use cases in data centers\, 5G\, consumer electronics\, and automotive applications\n\n\n\n\n\n\n\n\n\n\n\nSpeaker\n\n\nListed below is the industry leader scheduled to speak. \n\n\n\n\n\n\n\n\n\n\n\n\n\n\n\n\n\n\n\n\n\n\n\n\n\n\nRohan Bhatnagar\n\n\nProduct Manager\, Senior Staff\nSynopsys\, Inc. \n\n\n\n\n\n\n\n\n\n\n\nRohan Bhatnagar is a Product Manager\, Senior Staff at Synopsys in the Silicon Lifecycle Management business group and manages the PVT Monitor IP products. He is responsible for total product management including market research and strategy for new product roadmap definition\, go-to-market planning\, product collateral generation for customer engagements and sales trainings. He has more than a decade and a half of experience in the Electronic Design Automation (EDA) industry focusing on the analog and mixed-signal design space. Rohan holds a Master’s degree in Electrical Engineering from The University of Texas.
URL:https://marketingeda.com/event/reimagining-synopsys-slm-pvt-monitoring-ip-for-advanced-node-gaa-process/
CATEGORIES:IP,Webinar
ATTACH;FMTTYPE=image/jpeg:https://marketingeda.com/wp-content/uploads/Synopsys-May-29-2024.jpg
END:VEVENT
BEGIN:VEVENT
DTSTART;TZID=Asia/Jerusalem:20240528T093000
DTEND;TZID=Asia/Jerusalem:20240528T173000
DTSTAMP:20240522T193335Z
CREATED:20240522T193335Z
LAST-MODIFIED:20240522T193335Z
UID:8027-1716888600-1716917400@marketingeda.com
SUMMARY:FV-Israel\, Summit 2024
DESCRIPTION:Connect with industry experts\, academics\, and enthusiasts for discussions on FV in Israel. \nExplore new developments from top semiconductor firms\, advanced EDA tools\, and academic research. \nEngage with leaders\, exchange insights\, and help shape the future of FV in Israel and globally. \nDistinguished Speaker \nDadi Perlmutter\nTechnology and social entrepreneur and former VP at Intel
URL:https://marketingeda.com/event/fv-israel-summit-2024/
CATEGORIES:EDA,Symposium
ATTACH;FMTTYPE=image/jpeg:https://marketingeda.com/wp-content/uploads/FV-Israel-2024.jpg
END:VEVENT
BEGIN:VEVENT
DTSTART;TZID=Asia/Shanghai:20240528T090000
DTEND;TZID=Asia/Shanghai:20240528T160000
DTSTAMP:20240522T200534Z
CREATED:20240522T194800Z
LAST-MODIFIED:20240522T200534Z
UID:8030-1716886800-1716912000@marketingeda.com
SUMMARY:TSMC 2024 China Technology Symposium
DESCRIPTION:Get the latest on:\n\nTSMC’s industry-leading HPC\, smartphone\, IoT\, and automotive platform solutions\nTSMC’s advanced technology progress on 5nm\, 4nm\, 3nm\, 2nm processes and beyond\nTSMC’s specialty technology breakthroughs on ultra-low power\, RF\, embedded memory\, power management\, sensor technologies\, and more\nTSMC 3DFabric™ advanced packaging technology advancement on InFO\, CoWoS®\, and TSMC-SoIC®\nTSMC’s manufacturing excellence\, capacity expansion plans\, and green manufacturing achievements\nTSMC’s Open Innovation Platform Ecosystem to speed up time-to-design\n\nFor more information on the TSMC Technology Symposium\, e-mail us at: symposium@tsmc.com. \nWe look forward to seeing you at the 2024 TSMC Technology Symposium! \n\n\n\n09:00 – 10:00\nRegistration & Ecosystem Pavilion\n\n\n10:00 – 10:10\nWelcome & Opening Remarks\n\n\n10:10 – 10:30\nMarket Update and Outlook\n\n\n10:30 – 11:00\nTechnology Leadership\n\n\n11:00 – 11:25\nCoffee Break & Ecosystem Pavilion\n\n\n11:25 – 11:50\nManufacturing Excellence\n\n\n11:50 – 12:15\nAdvanced Technology Design Solutions\n\n\n12:15 – 13:25\nLunch & Ecosystem Pavilion\n\n\n13:25 – 13:45\nAdvanced Technology\n\n\n13:45 – 14:05\n3DFabric Technology\n\n\n14:05 – 14:40\nCoffee Break & Ecosystem Pavilion\n\n\n14:40 – 15:00\nAutomotive & eNVM Technology\n\n\n15:00 – 15:20\nIoT Technology\n\n\n15:20 – 15:40\nAdvanced RF and Analog Technology\n\n\n15:40 – 16:00\nLucky Draw
URL:https://marketingeda.com/event/tsmc-2024-china-technology-symposium/
LOCATION:Shanghai International Convention Center\, No. 2727\, Riverside Avenue\, Shanghai\, China
CATEGORIES:EDA,Foundry,IP,Symposium
ATTACH;FMTTYPE=image/jpeg:https://marketingeda.com/wp-content/uploads/TSMC-2024-North-America.jpg
END:VEVENT
BEGIN:VEVENT
DTSTART;TZID=America/Los_Angeles:20240523T093000
DTEND;TZID=America/Los_Angeles:20240523T160000
DTSTAMP:20240506T221326Z
CREATED:20240506T221326Z
LAST-MODIFIED:20240506T221326Z
UID:7953-1716456600-1716480000@marketingeda.com
SUMMARY:Verification Academy Live: San Diego
DESCRIPTION:Siemens Digital Industries Software\n12348 High Bluff Drive\, Suite 250\nSan Diego\, CA 92130\n+1 (512) 221-7460 \nThis event is in-person only — there is no support for remote participation. \nAgenda \n\n\n\n9:30 – 10:00\nRegistration and Check-in \nCoffee and networking with your peers.\n\n\n10:00 – 10:05\nWelcome / Intro\nMel Pratt | Sr. Application Engineering Manager\, Functional Verification\n\n\n10:05 – 11:00\nBeyond Speed: Unlocking Productivity in Simulation and Debug\nMoses Satyasekaran | Director\, Simulation\nGone are the days when functional verification tools were solely measured by their performance metrics. The spotlight has shifted towards productivity enhancement in today’s fast-paced development environment. Join us as we explore how Siemens EDA prioritizes productivity and performance\, enabling customers to optimize their verification cycles and swiftly uncover bugs. Discover the transformative impact of this paradigm shift on accelerating design validation and achieving faster time-to-market.\n\n\n11:00 – Noon\nImprove Productivity and Deliver Hardware Assurance: Stimulus-free Verification\nChris Giles | Director\, Formal Verification\nLearn how Siemens’ and OneSpin have combined to deliver a best-in-class Static & Formal solution with a focus on addressing unsolved industry challenges. These solutions enable teams to achieve peak performance and deliver absolute hardware assurance.\n\n\nNoon – 1:00\nLunch and networking\n\n\n1:00 – 1:45\nThe New Leader in Verification IP: Questa + Avery Solutions\nKamlesh Mulchadani | Product Engineer\nNow that our acquisition of Avery Design Systems is complete\, Siemens EDA is the new leader for Verification IP in the industry. This session will describe the protocol and memory verification solutions you need for your next silicon verification project whether in Datacenter\, Storage\, 3DIC\, Networking\, Automotive\, or Aerospace and Defense applications.\n\n\n1:45 – 3:00\nQuesta Verification IQ: \nBoost verification predictability and efficiency with Big Data\nAustin Mam | Product Engineer\nThis session will cover Questa Verification IQ (VIQ)\, the next-generation\, data-driven verification solution from Siemens EDA that transforms the verification process using analytics\, collaboration\, and traceability. VIQ utilizes machine learning to boost verification productivity and is built on collective feedback gathered from verification teams over many years.\n\n\n3:00 – 4:00\nWrap-up and Networking
URL:https://marketingeda.com/event/verification-academy-live-san-diego/
LOCATION:Siemens Digital Industries Software\, 12348 High Bluff Drive\, Suite 250\, San Diego\, CA\, United States
CATEGORIES:EDA
ATTACH;FMTTYPE=image/jpeg:https://marketingeda.com/wp-content/uploads/Siemens-May-23-2024.jpg
END:VEVENT
BEGIN:VEVENT
DTSTART;TZID=America/New_York:20240523T080000
DTEND;TZID=America/New_York:20240523T170000
DTSTAMP:20240506T171106Z
CREATED:20240506T171106Z
LAST-MODIFIED:20240506T171106Z
UID:7946-1716451200-1716483600@marketingeda.com
SUMMARY:5 New Ways to Maximize Your Hardware Security Resilience
DESCRIPTION:Be sure to register for this high tech security webinar. You’ll learn how to identify threat scenarios quickly and why a model-based\, system-oriented solution is needed to protect your hardware. \n\n\n\n\nOverview\nConnected vehicles offer a range of benefits\, such as real-time data sharing\, app-to-car connectivity\, advanced driver assistance systems (ADAS)\, and critical safety features like location tracking\, remote parking\, and in-vehicle infotainment systems (IVIs). These advancements aim to enhance the overall driving and riding experience. However\, it is crucial to acknowledge that equipping vehicles with smart features also exposes them to potential cyberattacks. These attacks can result in customer data leakage or even compromise critical safety functionalities. \nIt’s expected to discover vulnerabilities after the product is released\, which could have been easily prevented. For instance\, as reported by Bloomberg\, a recent increase in car thefts was attributed to the absence of anti-theft computer chips in vehicle critical systems. Therefore\, it is imperative to proactively consider and address potential attack vectors right from the initial stages of development. \nThis cybersecurity vulnerability applies to many other industrial applications\, such as industrial IoT\, SmartCity\, and digital healthcare\, where every device or system is connected\, and every connection is a vulnerability. \nDesign for security is becoming mainstream and should be part of today’s standard design methodologies. \nWhat you will learn\n\nWhy a model-based and system-oriented solution is needed for automotive cybersecurity\nHow to quickly identify threat scenarios\nWhy a pre-silicon security verification flow is essential for secure ICs\nUsing AI to mitigate side-channel vulnerabilities\n\nWho should attend this presentation\nThis webinar is valuable to anyone who works with product design\, connectivity and security. \nSpeakers\nChief Technologist Christophe Bianchi
URL:https://marketingeda.com/event/5-new-ways-to-maximize-your-hardware-security-resilience/
CATEGORIES:EDA,Webinar
ATTACH;FMTTYPE=image/jpeg:https://marketingeda.com/wp-content/uploads/Ansys-May-23-2024.jpg
END:VEVENT
BEGIN:VEVENT
DTSTART;TZID=America/Los_Angeles:20240522T210000
DTEND;TZID=America/Los_Angeles:20240522T220000
DTSTAMP:20240521T182515Z
CREATED:20240521T182515Z
LAST-MODIFIED:20240521T182515Z
UID:8015-1716411600-1716415200@marketingeda.com
SUMMARY:RapidGPT: Meet Your New AI-Powered Design Assistant
DESCRIPTION:Join us for our upcoming webinar introducing RapidGPT\, a revolutionary tool developed by PrimisAI that is reshaping the field of AI-driven EDA. RapidGPT is changing the game in hardware engineering with its groundbreaking generative AI approach. Offering a natural language interface\, RapidGPT empowers designers to boost productivity and shorten time-to-market. During this session\, explore how RapidGPT simplifies the design journey for hardware engineers\, from initial concept to RTL\, transcending conventional automation and revolutionizing the hardware engineering process.
URL:https://marketingeda.com/event/rapidgpt-meet-your-new-ai-powered-design-assistant/
CATEGORIES:EDA,Webinar
ATTACH;FMTTYPE=image/jpeg:https://marketingeda.com/wp-content/uploads/PrimisAI-May-22-2024.jpg
END:VEVENT
BEGIN:VEVENT
DTSTART;TZID=America/Los_Angeles:20240522T100000
DTEND;TZID=America/Los_Angeles:20240522T110000
DTSTAMP:20240510T222103Z
CREATED:20240510T222103Z
LAST-MODIFIED:20240510T222103Z
UID:7985-1716372000-1716375600@marketingeda.com
SUMMARY:Debugging Features of UVM
DESCRIPTION:A UVM testbench is a large and complex piece of software. Like any other large and complex piece of software\, a verification environment written using UVM will require debugging at some stage. There are various debugging features built into UVM to help with this. \nIn this one-hour webinar\, Doulos Senior Member Technical Staff Doug Smith explores the various features in UVM to help you debug your UVM environment\, test cases\, and design under test. \nTopics include: \n\nDebugging the Testbench\nDebugging Stimulus\nDebugging the Design\n\nAt the end of the webinar\, we will also look at an example of the tool support features for debugging UVM using the Cadence Xcelium Logic Simulator.
URL:https://marketingeda.com/event/debugging-features-of-uvm-2/
CATEGORIES:EDA,Webinar
ATTACH;FMTTYPE=image/jpeg:https://marketingeda.com/wp-content/uploads/Cadence-May-22-2024-1.jpg
END:VEVENT
BEGIN:VEVENT
DTSTART;TZID=America/Los_Angeles:20240522T080000
DTEND;TZID=America/Los_Angeles:20240522T090000
DTSTAMP:20240508T181719Z
CREATED:20240508T181719Z
LAST-MODIFIED:20240508T181719Z
UID:7969-1716364800-1716368400@marketingeda.com
SUMMARY:Addressing the Challenges of PCB Design for Manufacturing
DESCRIPTION:Manufacturing issues can be a big reason why your project timelines get derailed and even result in costly failures. By understanding common errors that occur while designing or creating your fabrication and assembly documentation\, you can avoid making the same mistakes on future designs. With access to over 80 comprehensive Design for Test (DFT)\, Design for Assembly (DFA)\, and Design for Fabrication (DFF) checks\, automated documentation that is always synced to your layout data\, and single output manufacturing\, OrCAD X helps ensure that your designs are robust and functional from the start. \nWhether you’re a seasoned professional or new to PCB manufacturing\, this webinar will go into the power of OrCAD X and how it will streamline your manufacturing output process\, helping you eliminate late-stage PCB manufacturing problems. \n\nJoin us to learn about: \n\nCommon DFx issues seen by manufacturers/fabricators\nDFx design guidelines to follow\nIn-design DFM checking with DesignTrue DFM technology\nAutomating manufacturing documentation with Live DOC\nGenerating manufacturing outputs\n\n\nSPEAKERS: \nJohn Carney\, Product Engineering Architect\, Cadence \nKent Balius\, Director of Pre-Production Engineering. Summit Interconnect \nHOST: \nSupreeth Mannava\, Senior Principal Product Manager\, Cadence
URL:https://marketingeda.com/event/addressing-the-challenges-of-pcb-design-for-manufacturing/
CATEGORIES:EDA,Webinar
ATTACH;FMTTYPE=image/jpeg:https://marketingeda.com/wp-content/uploads/Cadence-May-22-2024.jpg
END:VEVENT
BEGIN:VEVENT
DTSTART;TZID=America/Los_Angeles:20240522T080000
DTEND;TZID=America/Los_Angeles:20240522T090000
DTSTAMP:20240502T173621Z
CREATED:20240502T173621Z
LAST-MODIFIED:20240502T173621Z
UID:7937-1716364800-1716368400@marketingeda.com
SUMMARY:Questa RDC Assist – Improving designer productivity and enabling faster RDC verification closure with machine learning
DESCRIPTION:In 2021 Siemens EDA released CDC Assist. CDC Assist is an ML powered feature that empowers users to configure\, debug\, and close CDC on designs more rapidly. Following the success of CDC Assist\, Siemens introduced RDC Assist in 2023.\n‌\nUsing the same ML technology in CDC Assist\, RDC Assist dramatically improves the time and effort required to configure\, debug\, and close reset domain crossing analysis.\n‌\nSince RDC violations often have a common cause\, RDC Assist helps users to identify the root cause for the RDC violations and errors through data mining and machine learning techniques.\n‌\nWe will discuss use models and best practices to utilize RDC Assist\, and walk through a demo showing its power.\nWhat you will learn: \n\n‌How RDC Assist helps users expedite their RDC Analysis\nHow to run RDC Assist\nHow to analyze RDC Assist results in the UI\nHow to use RDC Assist to focus on major hotspots first\nTechniques presented are applicable to both CDC and RDC analysis\n‌\n\nWho should attend: \nRTL designers\, anyone that runs CDC or RDC\, design team leads \nSpeaker:\n\n\n\n\n\n\nFarhad Ahmed\nPrincipal Product Engineer\, Siemens EDA\n\n\n\n\nFarhad Ahmed currently is a Principal Product Engineer at Siemens EDA Software.​ \nHe has been working in Chip Design and EDA companies for last 30+ years. He graduated with a B.Sc.(EE) degree from Bangladesh University of Engg. & Technology and a M.Sc.(EE) from Washington State University.​ \nHe started his career as an RTL Logic Designer for Sun Microsystems working on SPARC microprocessors.​ \nFarhad loves to read books on history\, an avid swimmer\, Squash player\, does hiking regularly and also loves kayaking.​
URL:https://marketingeda.com/event/questa-rdc-assist-improving-designer-productivity-and-enabling-faster-rdc-verification-closure-with-machine-learning/
CATEGORIES:EDA,Webinar
ATTACH;FMTTYPE=image/jpeg:https://marketingeda.com/wp-content/uploads/Siemens-May-22-2024.jpg
END:VEVENT
BEGIN:VEVENT
DTSTART;TZID=America/Los_Angeles:20240522T070000
DTEND;TZID=America/Los_Angeles:20240522T090000
DTSTAMP:20240424T164124Z
CREATED:20240424T164124Z
LAST-MODIFIED:20240424T164124Z
UID:7910-1716361200-1716368400@marketingeda.com
SUMMARY:Accelerating AI Applications Using Custom RISC-V based SIMD/VLIW DSPs
DESCRIPTION:The revolution in AI triggers an increased awareness for application-specific instruction-set processors (ASIPs). These processors implement a specialized instruction-set architecture (ISA) tailored to the AI application domain\, often starting from a baseline such as the RISC-V ISA.  ASIPs can replace traditional fixed-function hardware accelerators\, thereby introducing software-programmability in the AI acceleration domain\, and thus more flexibility and agility in both the design process and the eventual product.  By maintaining a RISC-V ISA baseline\, compatibility with and reuse of existing processor ecosystem elements is facilitated. \nSynopsys ASIP Designer is the industry-leading tool to design\, implement\, program and verify application-specific instruction-set processors. Starting from a single processor specification\, designers immediately obtain an optimizing C/C++ compiler\, cycle-accurate simulator and synthesizable hardware implementation of the ASIP.  Using a unique compiler-in-the-loop™ and synthesis-in-the-loop™ methodology\, the ISA and microarchitecture can be tuned quickly to the application domain. \nThis seminar introduces you to the ASIP Designer tool-suite. It features a tutorial and two case studies from AI application domains. The tutorial introduces the typical architectural features needed to accelerate AI algorithms\, such as specialization\, SIMD\, and VLIW\, and how ASIP Designer supports them. The first case study demonstrates a SIMD/VLIW architecture with a RISC-V baseline processor for accelerating activation functions. The second case study shows a RISC-V based ASIP for medium-throughput convolutional neural networks (CNN) with programming support for TensorFlowLite for Microcontrollers (TFLM). \n\n\n\nWho Should Attend? \nIf you are a design engineer\, algorithm developer\, software engineer\, system architect\, or design manager focusing on advanced SoCs requiring application-specific optimizations\, you won’t want to miss this event.
URL:https://marketingeda.com/event/accelerating-ai-applications-using-custom-risc-v-based-simd-vliw-dsps/
CATEGORIES:EDA,IP,Webinar
ATTACH;FMTTYPE=image/jpeg:https://marketingeda.com/wp-content/uploads/Synopsys-May-22-2024.jpg
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BEGIN:VEVENT
DTSTART;TZID=America/Los_Angeles:20240521T100000
DTEND;TZID=America/Los_Angeles:20240521T110000
DTSTAMP:20240503T190402Z
CREATED:20240503T190402Z
LAST-MODIFIED:20240503T190402Z
UID:7943-1716285600-1716289200@marketingeda.com
SUMMARY:The Next Generation of 3DIC Interposer/InFO Design
DESCRIPTION:In recent years\, the semiconductor industry has experienced a breakthrough in the onset of 2.5D and 3D chiplet-based products. These products promise to extend the limits of Moore’s Law while demolishing limitations on speed and capacity for our highest tiers of compute. But for all the adulation we heap upon the 3DIC paradigm\, we seemingly pay very little attention to the humble interposer die that enables communication between these groundbreaking chiplets. \n  \nWhat Attendees Will Learn: \nSynopsys tools can now improve the construction and signoff process for all styles of interposers. AMD has tested these tools and will present a comprehensive update on what we see as a step forward in interposer design. This flow is driven primarily within the Synopsys 3DIC Compiler platform\, though other noteworthy tools and engines are employed at key stages to ensure a high standard of quality. The Synopsys webinar begins with a brief overview of the current interposer design flow\, including pros and cons to the current approach and opportunities for new development. We’ll then cover an end-to-end design flow that addresses these opportunities across the span of floorplanning\, construction\, extraction\, and signoff. Finally\, we’ll wrap up with conclusions and future work. \n\n\n\n\n\n\n\n\n\n\nSpeakers\n\n\nListed below are the industry leaders scheduled to speak. \n\n\n\n\n\n\n\n\n\n\n\n\n\n\n\n\n\n\n\n\n\n\n\n\n\n\nKenneth Larsen\n\n\nProduct Management\, Sr Director\nSynopsys \n\n\n\n\n\n\n\n\nKenneth Larsen is a director of product management in the EDA Group at Synopsys\, focusing on 3D Heterogeneous Integration and Advanced Packaging. He has 30 years of experience in IC design verification and validation. Before joining Synopsys\, Kenneth was worldwide senior technical director at Mentor. \n\n\n\n\n\n\n\n\n\n\n\n\n\n\n\n\n\n\n\n\n\n\n\n\n\n\n\n\n\n\n\nNitin Navale\n\n\nPrincipal Member of Technical Staff\nAMD \n\n\n\n\n\n\n\n\nNitin Navale has worked across AMD & Xilinx since 2008 and currently serves as Principal Member of Technical Staff in the CAD/Methodology team. His current role is Technical Lead for 3DIC Methodology\, though he has previously also worked on design automation that ranges across STA\, EM/IR\, Thermal\, ESD\, SOC Floorplanning & Construction\, IP Management\, Netlisting\, and Characterization. Nitin earned his BS and MS in Electrical Engineering from the University of Illinois\, Urbana-Champaign. Outside of work\, he is consumed by his devotion to board games and strategy. He’s also an avid musician who plays multiple instruments with an active interest in music theory. \n\n\n\n\n\n\n\n\n\n\n\n\n\n\n\n\n\n\n\n\n\n\n\n\n\n\n\n\n\n\nAkshata Sonnad\n\n\nMember of Technical Staff\nAMD \n\n\n\n\n\n\n\n\nAkshata Sonnad is a Member of Technical Staff at AMD\, working on developing methodologies and flows for floor planning\, signoff\, and interposer/ InFO routing for next-generation multi-die systems. She graduated from University of Southern California with a Master’s degree in Electrical Engineering and worked as a CAD engineer on the physical design and verification of block level IPs and SOCs\, before making a transition to 3DIC Design Methodology.
URL:https://marketingeda.com/event/the-next-generation-of-3dic-interposer-info-design/
CATEGORIES:EDA,Webinar
ATTACH;FMTTYPE=image/jpeg:https://marketingeda.com/wp-content/uploads/Synopsys-May-21-2024.jpg
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