BEGIN:VCALENDAR
VERSION:2.0
PRODID:-//Marketing EDA - ECPv6.18.4//NONSGML v1.0//EN
CALSCALE:GREGORIAN
METHOD:PUBLISH
X-WR-CALNAME:Marketing EDA
X-ORIGINAL-URL:https://marketingeda.com
X-WR-CALDESC:Events for Marketing EDA
REFRESH-INTERVAL;VALUE=DURATION:PT1H
X-Robots-Tag:noindex
X-PUBLISHED-TTL:PT1H
BEGIN:VTIMEZONE
TZID:Europe/Rome
BEGIN:DAYLIGHT
TZOFFSETFROM:+0100
TZOFFSETTO:+0200
TZNAME:CEST
DTSTART:20230326T010000
END:DAYLIGHT
BEGIN:STANDARD
TZOFFSETFROM:+0200
TZOFFSETTO:+0100
TZNAME:CET
DTSTART:20231029T010000
END:STANDARD
BEGIN:DAYLIGHT
TZOFFSETFROM:+0100
TZOFFSETTO:+0200
TZNAME:CEST
DTSTART:20240331T010000
END:DAYLIGHT
BEGIN:STANDARD
TZOFFSETFROM:+0200
TZOFFSETTO:+0100
TZNAME:CET
DTSTART:20241027T010000
END:STANDARD
BEGIN:DAYLIGHT
TZOFFSETFROM:+0100
TZOFFSETTO:+0200
TZNAME:CEST
DTSTART:20250330T010000
END:DAYLIGHT
BEGIN:STANDARD
TZOFFSETFROM:+0200
TZOFFSETTO:+0100
TZNAME:CET
DTSTART:20251026T010000
END:STANDARD
END:VTIMEZONE
BEGIN:VTIMEZONE
TZID:Europe/London
BEGIN:DAYLIGHT
TZOFFSETFROM:+0000
TZOFFSETTO:+0100
TZNAME:BST
DTSTART:20230326T010000
END:DAYLIGHT
BEGIN:STANDARD
TZOFFSETFROM:+0100
TZOFFSETTO:+0000
TZNAME:GMT
DTSTART:20231029T010000
END:STANDARD
BEGIN:DAYLIGHT
TZOFFSETFROM:+0000
TZOFFSETTO:+0100
TZNAME:BST
DTSTART:20240331T010000
END:DAYLIGHT
BEGIN:STANDARD
TZOFFSETFROM:+0100
TZOFFSETTO:+0000
TZNAME:GMT
DTSTART:20241027T010000
END:STANDARD
BEGIN:DAYLIGHT
TZOFFSETFROM:+0000
TZOFFSETTO:+0100
TZNAME:BST
DTSTART:20250330T010000
END:DAYLIGHT
BEGIN:STANDARD
TZOFFSETFROM:+0100
TZOFFSETTO:+0000
TZNAME:GMT
DTSTART:20251026T010000
END:STANDARD
END:VTIMEZONE
BEGIN:VTIMEZONE
TZID:America/Los_Angeles
BEGIN:DAYLIGHT
TZOFFSETFROM:-0800
TZOFFSETTO:-0700
TZNAME:PDT
DTSTART:20230312T100000
END:DAYLIGHT
BEGIN:STANDARD
TZOFFSETFROM:-0700
TZOFFSETTO:-0800
TZNAME:PST
DTSTART:20231105T090000
END:STANDARD
BEGIN:DAYLIGHT
TZOFFSETFROM:-0800
TZOFFSETTO:-0700
TZNAME:PDT
DTSTART:20240310T100000
END:DAYLIGHT
BEGIN:STANDARD
TZOFFSETFROM:-0700
TZOFFSETTO:-0800
TZNAME:PST
DTSTART:20241103T090000
END:STANDARD
BEGIN:DAYLIGHT
TZOFFSETFROM:-0800
TZOFFSETTO:-0700
TZNAME:PDT
DTSTART:20250309T100000
END:DAYLIGHT
BEGIN:STANDARD
TZOFFSETFROM:-0700
TZOFFSETTO:-0800
TZNAME:PST
DTSTART:20251102T090000
END:STANDARD
END:VTIMEZONE
BEGIN:VTIMEZONE
TZID:Asia/Tokyo
BEGIN:STANDARD
TZOFFSETFROM:+0900
TZOFFSETTO:+0900
TZNAME:JST
DTSTART:20230101T000000
END:STANDARD
END:VTIMEZONE
BEGIN:VTIMEZONE
TZID:Europe/Berlin
BEGIN:DAYLIGHT
TZOFFSETFROM:+0100
TZOFFSETTO:+0200
TZNAME:CEST
DTSTART:20230326T010000
END:DAYLIGHT
BEGIN:STANDARD
TZOFFSETFROM:+0200
TZOFFSETTO:+0100
TZNAME:CET
DTSTART:20231029T010000
END:STANDARD
BEGIN:DAYLIGHT
TZOFFSETFROM:+0100
TZOFFSETTO:+0200
TZNAME:CEST
DTSTART:20240331T010000
END:DAYLIGHT
BEGIN:STANDARD
TZOFFSETFROM:+0200
TZOFFSETTO:+0100
TZNAME:CET
DTSTART:20241027T010000
END:STANDARD
BEGIN:DAYLIGHT
TZOFFSETFROM:+0100
TZOFFSETTO:+0200
TZNAME:CEST
DTSTART:20250330T010000
END:DAYLIGHT
BEGIN:STANDARD
TZOFFSETFROM:+0200
TZOFFSETTO:+0100
TZNAME:CET
DTSTART:20251026T010000
END:STANDARD
END:VTIMEZONE
BEGIN:VTIMEZONE
TZID:America/New_York
BEGIN:DAYLIGHT
TZOFFSETFROM:-0500
TZOFFSETTO:-0400
TZNAME:EDT
DTSTART:20230312T070000
END:DAYLIGHT
BEGIN:STANDARD
TZOFFSETFROM:-0400
TZOFFSETTO:-0500
TZNAME:EST
DTSTART:20231105T060000
END:STANDARD
BEGIN:DAYLIGHT
TZOFFSETFROM:-0500
TZOFFSETTO:-0400
TZNAME:EDT
DTSTART:20240310T070000
END:DAYLIGHT
BEGIN:STANDARD
TZOFFSETFROM:-0400
TZOFFSETTO:-0500
TZNAME:EST
DTSTART:20241103T060000
END:STANDARD
BEGIN:DAYLIGHT
TZOFFSETFROM:-0500
TZOFFSETTO:-0400
TZNAME:EDT
DTSTART:20250309T070000
END:DAYLIGHT
BEGIN:STANDARD
TZOFFSETFROM:-0400
TZOFFSETTO:-0500
TZNAME:EST
DTSTART:20251102T060000
END:STANDARD
END:VTIMEZONE
BEGIN:VTIMEZONE
TZID:Indian/Maldives
BEGIN:STANDARD
TZOFFSETFROM:+0500
TZOFFSETTO:+0500
TZNAME:+05
DTSTART:20230101T000000
END:STANDARD
END:VTIMEZONE
BEGIN:VTIMEZONE
TZID:America/Phoenix
BEGIN:STANDARD
TZOFFSETFROM:-0700
TZOFFSETTO:-0700
TZNAME:MST
DTSTART:20230101T000000
END:STANDARD
END:VTIMEZONE
BEGIN:VEVENT
DTSTART;TZID=Europe/Rome:20240514T100000
DTEND;TZID=Europe/Rome:20240514T120000
DTSTAMP:20240423T010041Z
CREATED:20240423T010017Z
LAST-MODIFIED:20240423T010041Z
UID:7896-1715680800-1715688000@marketingeda.com
SUMMARY:Introduction to the Open-source EDA Ecosystem
DESCRIPTION:Open-source hardware in the European Chips Act\nMatthew Xuereb\, European Commission \nFree and open-source semiconductor ecosystem\nLuca Alloatti\, Free Silicon Foundation ETS \nOpen-source EDA software and semiconductor design\nJean-Paul Chaput\, Sorbonne University\, Coriolis Foundation \nEuropean roadmap on the advancement of open-source EDA tools\nRihards Novickis\, Latvian Institute of Electronics and Computer Science
URL:https://marketingeda.com/event/introduction-to-the-open-source-eda-ecosystem/
CATEGORIES:EDA,Workshop
ATTACH;FMTTYPE=image/jpeg:https://marketingeda.com/wp-content/uploads/Open-source-EDA-ecosystem.jpg
END:VEVENT
BEGIN:VEVENT
DTSTART;TZID=Europe/London:20240514T080000
DTEND;TZID=Europe/London:20240514T170000
DTSTAMP:20240503T191344Z
CREATED:20240430T203151Z
LAST-MODIFIED:20240503T191344Z
UID:7935-1715673600-1715706000@marketingeda.com
SUMMARY:TSMC 2024 Technology Symposium - Europe
DESCRIPTION:Agenda\n\n\nEurope Technology Symposium\n*The agenda is subject to change\n\n\n\n08:30 – 09:30\n\nRegistration & Ecosystem Pavilion\n\n\n\n09:30 – 09:40\n\nWelcome & Opening Remarks\n\n\n\n09:40 – 10:20\n\nCEO Perspectives\n\n\n\n10:20 – 10:40\n\nMarket Update and Outlook\n\n\n\n10:40 – 11:10\n\nTechnology Leadership\n\n\n\n11:10 – 11:30\n\nCoffee Break & Ecosystem Pavilion\n\n\n\n11:30 – 11:55\n\nManufacturing Excellence\n\n\n\n11:55 – 12:20\n\nAdvanced Technology Design Solutions\n\n\n\n12:20 – 13:40\n\nLunch & Ecosystem Pavilion\n\n\n\n13:40 – 14:05\n\nHPC Platform – Advanced Technology and 3DFabric\n\n\n\n14:05 – 14:25\n\neNVM Technology Platform\n\n\n\n14:25 – 14:45\n\nAutomotive Platform\n\n\n\n14:45 – 15:15\n\nCoffee Break & Ecosystem Pavilion\n\n\n\n15:15 – 15:30\n\nAdvanced RF and Analog Technology Platform\n\n\n\n15:30 – 15:45\n\nIoT Technology Platform\n\n\n\n15:45 – 16:00\n\nHigh Voltage BCD/Power GaN Technology\n\n\n\n16:10 – 17:00\n\nSocial Hour
URL:https://marketingeda.com/event/tsmc-2024-technology-symposium-europe/
LOCATION:Hilton Amsterdam Airport Schiphol\, Schiphol Boulevard 701 Amsterdam\, Amsterdam\, Netherlands
CATEGORIES:Foundry,Symposium
ATTACH;FMTTYPE=image/jpeg:https://marketingeda.com/wp-content/uploads/TSMC-2024-North-America.jpg
END:VEVENT
BEGIN:VEVENT
DTSTART;TZID=America/Los_Angeles:20240513T080000
DTEND;TZID=America/Los_Angeles:20240517T170000
DTSTAMP:20240514T181939Z
CREATED:20240514T181805Z
LAST-MODIFIED:20240514T181939Z
UID:7992-1715587200-1715965200@marketingeda.com
SUMMARY:SEE\, MAPLD 2024
DESCRIPTION:Our workshop will feature content including\, but not limited to\, the following areas: \n\n\n\n\nArtificial Intelligence & Machine Learning (AI / ML)\n\nContinuing Education & Workforce Development\n\n\n\nDesigning with Field Programmable Gate Arrays (FPGAs) / Systems on a Chip (SoCs) / New Devices\n\nFPGA & SoC Assurance\n\n\n\nGuidelines and Standards\n\nOn-Orbit Experiments & Model Validation\n\n\n\nRadiation Hardness Assurance (RHA)\n\nSEE Test Facilities\n\n\n\nSEE in Devices & Circuits / Mechanisms & Modeling\n\nSpace Environments
URL:https://marketingeda.com/event/see-mapld-2024/
LOCATION:Marriott La Jolla\, 4240 La Jolla Village Drive\, La Jolla\, CA\, United States
CATEGORIES:EDA,IP,Workshop
ATTACH;FMTTYPE=image/jpeg:https://marketingeda.com/wp-content/uploads/SEE-MAPLD.jpg
END:VEVENT
BEGIN:VEVENT
DTSTART;TZID=America/Los_Angeles:20240509T173000
DTEND;TZID=America/Los_Angeles:20240509T203000
DTSTAMP:20240328T160417Z
CREATED:20240328T160417Z
LAST-MODIFIED:20240328T160417Z
UID:7787-1715275800-1715286600@marketingeda.com
SUMMARY:ESD Alliance CEO/Executive Outlook
DESCRIPTION:Key executives from leading semiconductor EDA and IP companies will gather to discuss the latest industry trends\, challenges and opportunities Thursday\, May 9\, in Santa Clara\, California at the annual CEO Executive Outlook\, hosted by the Electronic System Design Alliance (ESD Alliance)\, a SEMI Technology Community\, and Keysight Technologies. Registration is open. \nKicking off the program\, Calista Redmond\, CEO of RISC-V International\, the industry group representing the RISC-V ecosystem\, and Patrick Little\, CEO of SiFive\, a RISC-V IP provider\, will address the state of the developing RISC-V market. \nA panel discussion with executives from leading companies in the design ecosystem will immediately follow. Participants include: \n\nNiels Faché of Keysight\nAki Fujimura of D2S\nDave Kelf of Breker\nJohn Kibarian of PDF Solutions\nPrakash Narain of Real Intent\nModerator: Bob Smith\, Executive Director of the ESD Alliance\n\nThe event will be held at Keysight Technologies\, 5301 Stevens Creek Blvd. in Santa Clara\, beginning at 5:30 p.m. with networking\, dinner and beverages. The RISC-V speaker program starts at 6:45 p.m. with the executive panel discussion to follow at 7:30 p.m. Tickets for the event are $25 per person for SEMI members and $50 per person for non-members. \nAbout The ESD Alliance \nThe ESD Alliance\, a SEMI Technology Community\, represents members of the design ecosystem that provide goods and services spanning the conceptualization\, design\, verification\, manufacturing and deployment of semiconductor chips and electronic systems. \nThe ESD Alliance focuses on: \n\nCoordinating and amplifying the collective voice of the design industry\nPromoting the value the design industry delivers to the global semiconductor and electronics industry\nAddressing and defending against threats and reducing risks\nAchieving efficiencies for the industry\nMarketing the attractiveness of the design industry as an ideal place to pursue a career\nEnabling networking\, sharing and collaboration among its members\n\nEngage with the ESD Alliance \nwww.esd-alliance.org\nESD Alliance Bridging the Frontier blog\nX @ESDAlliance\nLinkedIn\nFacebook \n  \nAbout SEMI\nSEMI® is the global industry association connecting over 3\,000 member companies and 1.5 million professionals worldwide across the semiconductor and electronics design and manufacturing supply chain. We accelerate member collaboration on solutions to top industry challenges through Advocacy\, Workforce Development\, Sustainability\, Supply Chain Management and other programs. Our SEMICON® expositions and events\, technology communities\, standards and market intelligence help advance our members’ business growth and innovations in design\, devices\, equipment\, materials\, services and software\, enabling smarter\, faster\, more secure electronics. Visit www.semi.org\, contact a regional office\, and connect with SEMI on LinkedIn and X to learn more. \nAll trademarks and registered trademarks are the property of their respective owners.
URL:https://marketingeda.com/event/esd-alliance-ceo-executive-outlook/
LOCATION:Keysight\, 5301 Stevens Creek Blvd\, Building 5\, Santa Clara\, 95051\, United States
CATEGORIES:EDA,Forum,IP
ATTACH;FMTTYPE=image/jpeg:https://marketingeda.com/wp-content/uploads/ESD-Alliance-May-9-2024.jpg
END:VEVENT
BEGIN:VEVENT
DTSTART;TZID=Asia/Tokyo:20240509T150000
DTEND;TZID=Asia/Tokyo:20240509T160000
DTSTAMP:20240429T161300Z
CREATED:20240429T161300Z
LAST-MODIFIED:20240429T161300Z
UID:7922-1715266800-1715270400@marketingeda.com
SUMMARY:Innovative Approach to SoC Power Optimization
DESCRIPTION:Power is the biggest factor impacting semiconductors from custom silicon to CPU/GPU products. System-level Power modeling and simulation is needed to measure power accurately and efficiently. The scope of power studies has expanded to include the software\, thermal and generation to feed into the UVM/UPF methodology. At this Webinar we will highlight a new system-level power methodology that integrates micro-architecture power storage\, consumption\, management and thermal assessments. Case studies will be presented on Chiplet power\, mapping strategy of DNN on AI Engines and Tensor cores\, hardware-software partitioning\, and testing power management for mobile and low-power devices.
URL:https://marketingeda.com/event/innovative-approach-to-soc-power-optimization/
CATEGORIES:EDA,IP,Webinar
ATTACH;FMTTYPE=image/jpeg:https://marketingeda.com/wp-content/uploads/Mirabilis-May-9-2024.jpg
END:VEVENT
BEGIN:VEVENT
DTSTART;TZID=America/Los_Angeles:20240509T100000
DTEND;TZID=America/Los_Angeles:20240509T110000
DTSTAMP:20240429T161925Z
CREATED:20240429T161925Z
LAST-MODIFIED:20240429T161925Z
UID:7925-1715248800-1715252400@marketingeda.com
SUMMARY:Cracking the Power Code: Innovative Approach to SoC Power Optimization
DESCRIPTION:Power is the biggest factor impacting semiconductors from custom silicon to CPU/GPU products. System-level Power modeling and simulation is needed to measure power accurately and efficiently. The scope of power studies has expanded to include the software\, thermal and generation to feed into the UVM/UPF methodology. At this Webinar we will highlight a new system-level power methodology that integrates micro-architecture power storage\, consumption\, management and thermal assessments. Case studies will be presented on Chiplet power\, mapping strategy of DNN on AI Engines and Tensor cores\, hardware-software partitioning\, and testing power management for mobile and low-power devices.
URL:https://marketingeda.com/event/cracking-the-power-code-innovative-approach-to-soc-power-optimization/
CATEGORIES:EDA,Webinar
ATTACH;FMTTYPE=image/jpeg:https://marketingeda.com/wp-content/uploads/Mirabilis-May-9-2024-USA.jpg
END:VEVENT
BEGIN:VEVENT
DTSTART;TZID=America/Los_Angeles:20240509T100000
DTEND;TZID=America/Los_Angeles:20240509T110000
DTSTAMP:20240419T172547Z
CREATED:20240419T172547Z
LAST-MODIFIED:20240419T172547Z
UID:7883-1715248800-1715252400@marketingeda.com
SUMMARY:AI-Driven 3D System Analysis & Optimization for EM Antenna/RF Problems
DESCRIPTION:Antenna/RF design problems often involve the optimization of many variables\, requiring numerous evaluations (EM simulations) using traditional optimization methods. Design engineers need an intelligent\, accurate\, and easy-to-use simulation platform and analysis solution that reduces repetitive design cycles while increasing user productivity and efficiency. \nLeveraging an advanced AI-enabled methodology\, the Cadence Optimality Intelligent System Explorer delivers quality results leading to the optimal performance of electrical systems. Optimality Explorer utilizes a novel surrogate model-aware mechanism that significantly reduces the number of required EM simulations. In addition\, the seamless integration between different Cadence solver technologies (Clarity 3D Solver\, AWR Microwave Office\, and Optimality Explorer) enables full-cycle circuit-field co-simulation and optimization for RF/antenna design problems. \nWith the integration of Clarity 3D Solver and AWR Microwave Office\, RF/antenna designers will have ready access to high-capacity EM analysis for design verification and signoff of large\, complex RF mixed-signal systems beyond the capabilities offered by conventional solvers thanks to the Clarity distributed multiprocessing technology. \nThis webinar demonstrates the efficacy of the Optimality Explorer and Clarity 3D Solver engines for several complex high-dimensional antenna/RF problems. \nKey takeaways: \n\nOptimality Explorer leverages an advanced AI-enabled methodology to deliver quality results leading to the optimal performance of electrical systems\nThe seamless integration between Clarity 3D Solver\, AWR Microwave Office\, and Optimality Explorer enables full-cycle circuit-field co-simulation and optimization for RF/antenna design problems\nDemonstration of the efficacy of the Optimality Explorer and Clarity 3D Solver engines for several complex high-dimensional antenna/RF problems
URL:https://marketingeda.com/event/ai-driven-3d-system-analysis-optimization-for-em-antenna-rf-problems/
CATEGORIES:EDA,Webinar
ATTACH;FMTTYPE=image/jpeg:https://marketingeda.com/wp-content/uploads/Cadence-May-9-2024.jpg
END:VEVENT
BEGIN:VEVENT
DTSTART;TZID=America/Los_Angeles:20240509T083000
DTEND;TZID=America/Los_Angeles:20240509T170000
DTSTAMP:20240415T181329Z
CREATED:20240415T181329Z
LAST-MODIFIED:20240415T181329Z
UID:7853-1715243400-1715274000@marketingeda.com
SUMMARY:TSMC Technology Workshop 2024 - Boston
DESCRIPTION:08:30 – 09:30\nRegistration & Partner Pavilion\n\n\n09:30 – 09:40\nWelcome & Opening Remarks\n\n\n09:40 – 10:00\nMarket Outlook – Powering AI Together\n\n\n10:00 – 10:30\nAdvanced Technology Leadership\n\n\n10:30 – 11:00\nCoffee Break & Ecosystem Pavilion\n\n\n11:00 – 11:25\nSpecialty Technology Leadership\n\n\n11:25 – 11:50\nManufacturing Excellence\n\n\n11:50 – 13:00\nLunch & Ecosystem Pavilion\n\n\n13:00 – 13:20\nAdvanced Technology Design Solutions\n\n\n13:20 – 13:40\nAdvanced Technology\n\n\n13:40 – 14:00\n3DFabric Technology\n\n\n14:00 – 14:30\nCoffee Break & Ecosystem Pavilion\n\n\n14:30 – 14:50\nAutomotive and eNVM Technology\n\n\n14:50 – 15:10\nIoT Technology\n\n\n15:10 – 15:30\nAdvanced RF and Analog Technology\n\n\n15:30 – 16:40\nSocial Hour
URL:https://marketingeda.com/event/tsmc-technology-workshop-2024-boston/
LOCATION:Boston Marriott Burlington\, One Burlington Mall Road\, Burlington\, MA\, 01803\, United States
CATEGORIES:EDA,Foundry,IP,Workshop
ATTACH;FMTTYPE=image/jpeg:https://marketingeda.com/wp-content/uploads/TSMC-2024-North-America.jpg
END:VEVENT
BEGIN:VEVENT
DTSTART;TZID=Europe/Berlin:20240507T090000
DTEND;TZID=Europe/Berlin:20240507T220000
DTSTAMP:20240429T170320Z
CREATED:20240429T170320Z
LAST-MODIFIED:20240429T170320Z
UID:7928-1715072400-1715119200@marketingeda.com
SUMMARY:User2User Europe 2024
DESCRIPTION:User2User is the perfect opportunity to learn\, share and network with fellow technical experts who design leading-edge products using Siemens EDA tools. \nDedicated to end-users of Siemens EDA solutions\, this conference is free to attend and includes innovative keynotes from industry leaders\, enriching technical sessions as well as a chance to network with colleagues and peers. \nThe full programme includes papers on these topics\n\nDesign For Test & Embedded Analytics\nElectronic System Design/PCB Design analysis and manufacturing\nFunctional Design & Verification\nHardware Assisted Verification\nHigh Level Synthesis: Digital design in C++/SystemC\nCustom IC Verification\nIC Backend\nSemiconductor packaging design\, analysis and manufacturing\n\nKeynotes\nEnabling imagination – An integrated approach to system design – Mike Ellow \nMike Ellow is the Executive Vice President of Electronic Design Automation (EDA) Global Sales Services and Customer Support for Siemens in North America. \nDelivering Silicon at Cloud Scale – Ronen Laviv \nRonen Laviv is the Enterprise Account Manager and EDA Sales Consultant at Amazon Web Services (AWS) based in Israel. \nTechnical breakouts\n\nIC Backend Track 1\n\nImproving the accuracy of Design for Manufacturability (DFM) sign-off checks with machine learning\nSignoff with Calibre as platform independent application\nUtilizing Calibre Tools for Chipfinishing within a Markefile\n\n\nIC Backend Track 2\n\nPERC-LDL Auto Waivers flow applied to Voltage Dependent Rules in BCD technologies\nMission IR Possible – Full Chip IR Drop Analysis of CMOS Cine-Image Sensor with Mpower\n\n\nCustom IC Verification\n\nSymphony Pro enablement in STMicroelectronics SmartPower Technologies\nHow AWS cloud compute helps scale custom IC verification workloads\nPLL Design and Simulation using the Advanced SPICE technology\nAccelerating verification of high frequency PLLs for Wireless Application in a Smarter World\n\n\nDesign for Test & Embedded Analytics\n\nAdvancing DFT with the Power of AI: Grand challenges
URL:https://marketingeda.com/event/user2user-europe-2024/
LOCATION:Hilton Munich Airport\, Terminalstraße Mitte 20\, 85356 München-Flughafen\, Munich\, Germany
CATEGORIES:EDA,IP,User Group
ATTACH;FMTTYPE=image/jpeg:https://marketingeda.com/wp-content/uploads/User2User-Europe-2024.jpg
END:VEVENT
BEGIN:VEVENT
DTSTART;TZID=America/Los_Angeles:20240507T080000
DTEND;TZID=America/Los_Angeles:20240508T170000
DTSTAMP:20240503T163652Z
CREATED:20240419T171240Z
LAST-MODIFIED:20240503T163652Z
UID:7877-1715068800-1715187600@marketingeda.com
SUMMARY:ChipEx 2024
DESCRIPTION:ChipEx2024\, the largest annual event of the Israeli semiconductor industry\, will be held on May 7-8\, 2024 in Tel Aviv\, Israel. ChipEx2024 showcases companies including manufacturers\, developers and suppliers of advanced hardware technologies & services. It also includes a technical seminar where the world’s leading experts address the industry’s most relevant issues. \nThe event is produced by ASG Ltd. in cooperation with SIA\, Semiconductor Industry Association and with Semi\, the largest global industry association. \nThe goal of ChipEx2024 is to update all professionals involved with the Israeli semiconductor industry with the latest technological innovations and future directions of the industry. \nChipEx2024 target audience are all people involved with the semiconductor industry including engineers\, R&D managers\, industry experts\, senior executives in microelectronics related companies\, multinational design centers\, consultants\, venture capital managers as well as electrical/electronic/computer science students & professors from the various universities around Israel. \nChipEx2024 consists of three main parts: \nVendors’ Exhibition \nThe ChipEx exhibition includes booths in various sizes for presentations and demonstrations of new design and development tools. This year\, the ChipEx2024 exhibition will take place on May 7\, 2024 at the Tel-Aviv Expo Center and will include industry vendors\, service providers\, and manufacturers of electronic design tools\, components and manufacturing equipment from Israel and around the globe. These exhibitors will exhibit and update the visitors with the latest developments in tools and services for the semiconductor industry. \nTechnical Seminar \nTechnical lectures given by industry experts\, senior executives from the semiconductor industry\, vendors\, and university professors. The format of the sessions intends to cultivate and promote an instructive and productive interchange of ideas and solutions among industry developers and designers. The lectures are divided to various tracks in separate halls and address the major topics related to the microelectronics industry. This year\, the ChipEx2024 technical seminar will take place on May 7\, 2024 at the Tel-Aviv Expo Center. \nChipEx2024 Executive Summit \nThe Closing session of ChipEx2024 will take place on May 8\, 2024 at Peres Center for Peace and Innovation and will include top industry figures and will act as the Executive summit of ChipEx2024 targeting Industry leaders and top executives from Israel and around the globe. \nChipEx2024 is a great opportunity for any industry vendor or service provider to meet its target audience as well as interact with the decision makers in the various Israeli semiconductor companies. \nWe invite you to take part in ChipEx2024 as an exhibitor\, a speaker and/or as a sponsor.
URL:https://marketingeda.com/event/chipex-2024/
LOCATION:Tel Aviv Convention Center\, Rokach Boulevard 101\, Tel Aviv\, Israel
CATEGORIES:Conference,EDA,Foundry,IP
ATTACH;FMTTYPE=image/jpeg:https://marketingeda.com/wp-content/uploads/ChipEx-2024.jpg
END:VEVENT
BEGIN:VEVENT
DTSTART;TZID=America/Los_Angeles:20240502T093000
DTEND;TZID=America/Los_Angeles:20240502T160000
DTSTAMP:20240424T162043Z
CREATED:20240424T162005Z
LAST-MODIFIED:20240424T162043Z
UID:7901-1714642200-1714665600@marketingeda.com
SUMMARY:Keysight EDA Connect Tour - Austin
DESCRIPTION:Keysight is excited to announce the next destination stops of our EDA Connect World Tour: Austin\, TX and Burlington\, MA. \nSave the dates for our upcoming events in Austin\, TX on May 2 or Burlington\, MA on May 16\, where we’ll explore the future of AI in 6G to 3D Module integration. \nThese technical sessions promise to recharge your design productivity\, refresh your knowledge base\, and renew contacts with fellow design professionals. \nDon’t miss out on this opportunity to be at the forefront of innovation with Keysight. \nAs AI is redefining communication and connectivity\, your ability to design\, simulate\, and test — using an intelligent and automated workflow — is what will set you apart. \nJoin us for a half-day event that brings together top industry experts and innovators to explore modern RF circuit and system design\, including advanced topics like phased array analysis\, EM-circuit co-simulation\, and AI-enhanced workflow. \nOur interactive sessions are tailored to bring the local design community together and help you walk away feeling armed with the latest and greatest insights that power you to accelerate your time-to-market and achieve cost-effective scalability. \nLight breakfast and lunch will be provided. \nAgenda\n\n\n\n09:30\nCheck-in & Breakfast\n\n\n10:00\nWelcome – Keynote\n\n\n10:10\nAnalyzing Die-To-Die Interfaces In Multi-Die High-Speed Digital Designs\n\n\n11:00\nRF System Design / New System Verification Tools in ADS for Circuit Designers\n\n\n12:00\nSolving 3D Module Integration Challenges for High-Performance Microwave Design (Integration is our differentiator)\n\n\n12:45\nRF Switch Design with Keysight ADS\n\n\n1:30-4:00\nLunch Break / Golf
URL:https://marketingeda.com/event/keysight-eda-connect-tour-austin/
LOCATION:Topgolf Austin\, 2700 Esperanza Crossing\, Austin\, TX\, 78758\, United States
CATEGORIES:EDA,Forum
ATTACH;FMTTYPE=image/jpeg:https://marketingeda.com/wp-content/uploads/Keysight-Austin-2024.jpg
END:VEVENT
BEGIN:VEVENT
DTSTART;TZID=America/Los_Angeles:20240502T090000
DTEND;TZID=America/Los_Angeles:20240502T100000
DTSTAMP:20240422T161648Z
CREATED:20240422T161648Z
LAST-MODIFIED:20240422T161648Z
UID:7886-1714640400-1714644000@marketingeda.com
SUMMARY:Smart methods for DFT chip architecture & validation
DESCRIPTION:Combining market-leading design-for-test (DFT) technologies with best-in-class netlist synthesis allows you to achieve DFT success more quickly. Many customers\, including those for emulation and IC test\, have challenges with scaling architectures. This webinar describes how Siemens emulation and silicon test solutions can work together to provide a smart DFT plug-and-play architecture for Veloce ICs. \nThe Veloce hardware-assisted verification system can efficiently handle large\, full-chip GLE designs. Tessent Streaming Scan Network (SSN)\, a once-in-a-decade technology\, packetizes test data to dramatically reduce DFT implementation effort and reduce manufacturing test cost. The Veloce DFT application enables SSN\, as well as other test functions such as TestKompress\, BIST pattern validation\, functional fault grading\, power profiling and estimation\, by accelerating multiple orders of magnitude faster than traditional software simulation. Combining Veloce Strato and Tessent SSN can accelerate your time to DFT success. \nTarget audience: \n\nDFT Engineers\nDFT Managers\nProduct and Test Engineers and Managers\n\nWhat you will learn: \n\nIntroduction to Veloce DFT App and how it helps validate Tessent DFT logic/patterns\nDFT Power Profiling and Fault grading using Veloce Power App\nApplying SSN to solve the Veloce chip design challenges\n\n\n\nSpeakers:\n\n\n\n\n\n\nRobert Serphillips\nProduct Manager\, Verification\, Siemens EDA\n\n\n\n\nRobert Serphillips has worked in the pre-silicon verification\, post-silicon validation\, and production design-for-test (DFT) fields. He has designed and debugged ATE test patterns on multiple stand alone and SoC devices spanning close to 20 years in the semiconductor industry. The products include a mix of consumer\, automotive\, industrial\, military\, networking and mixed signal. Robert is currently a product manager with the Siemens EDA hardware-assisted verification business unit. \n\n\n\n\n\n\n\nRon Press\nSr. Director of Technology Enablement\, Tessent\, Siemens EDA – Tessent\n\n\n\n\nRon Press\, a 30-year veteran of the test and DFT industry\, is a member of the International Test Conference (ITC) Steering Committee\, a Golden Core member of the IEEE Computer Society and a Senior Member of IEEE. Ron has patents on reduced-pin-count testing\, glitch-free clock switching and on 3D DFT. He started his work in the test industry at Raytheon Company working on test and consulting throughout the company on test and built-in test. He co-developed the Testability Design Rating System (TDRS) for the US Air Force and received the Raytheon inventor’s award for a built-in test analysis system. Ron led the development of a state-of-the-art RF/digital tester at Harris RF starting in 1995.
URL:https://marketingeda.com/event/smart-methods-for-dft-chip-architecture-validation/
CATEGORIES:EDA,Webinar
ATTACH;FMTTYPE=image/jpeg:https://marketingeda.com/wp-content/uploads/Siemens-May-2-2024.jpg
END:VEVENT
BEGIN:VEVENT
DTSTART;TZID=America/Los_Angeles:20240502T083000
DTEND;TZID=America/Los_Angeles:20240502T173000
DTSTAMP:20240415T181052Z
CREATED:20240415T181052Z
LAST-MODIFIED:20240415T181052Z
UID:7850-1714638600-1714671000@marketingeda.com
SUMMARY:TSMC 2024 Technology Workshop – Austin
DESCRIPTION:08:30 – 09:30\nRegistration & Partner Pavilion\n\n\n09:30 – 09:40\nWelcome & Opening Remarks\n\n\n09:40 – 10:00\nMarket Outlook – Powering AI Together\n\n\n10:00 – 10:30\nAdvanced Technology Leadership\n\n\n10:30 – 11:00\nCoffee Break & Ecosystem Pavilion\n\n\n11:00 – 11:25\nSpecialty Technology Leadership\n\n\n11:25 – 11:50\nManufacturing Excellence\n\n\n11:50 – 13:00\nLunch & Ecosystem Pavilion\n\n\n13:00 – 13:20\nAdvanced Technology Design Solutions\n\n\n13:20 – 13:40\nAdvanced Technology\n\n\n13:40 – 14:00\n3DFabric Technology\n\n\n14:00 – 14:30\nCoffee Break & Ecosystem Pavilion\n\n\n14:30 – 14:50\nAutomotive and eNVM Technology\n\n\n14:50 – 15:10\nIoT Technology\n\n\n15:10 – 15:30\nAdvanced RF and Analog Technology\n\n\n15:30 – 16:40\nSocial Hour
URL:https://marketingeda.com/event/tsmc-2024-technology-workshop-austin/
LOCATION:JW Marriott Austin\, 110 E 2nd St\, Austin\, TX\, United States
CATEGORIES:EDA,Foundry,IP,Semiconductor,Workshop
ATTACH;FMTTYPE=image/jpeg:https://marketingeda.com/wp-content/uploads/TSMC-2024-North-America.jpg
END:VEVENT
BEGIN:VEVENT
DTSTART;TZID=America/Los_Angeles:20240430T080000
DTEND;TZID=America/Los_Angeles:20240501T170000
DTSTAMP:20240416T193144Z
CREATED:20240416T193144Z
LAST-MODIFIED:20240416T193144Z
UID:7866-1714464000-1714582800@marketingeda.com
SUMMARY:CXL DevCon 2024
DESCRIPTION:The CXL Consortium is looking forward to hosting the first Compute Express Link® (CXL®) DevCon from April 30 – May 1\, 2024\, in Santa Clara\, California! \nCXL DevCon is a unique opportunity for our Members to learn directly from CXL technology experts. Attendees will participate in CXL technical training\, view available products and technology demonstrations\, and network with industry peers. \nRegister for the event HERE. \nIf you are not currently a member of the CXL Consortium\, learn about our membership benefits HERE and contact admin@computeexpresslink.org with any questions or for additional information. \n  \nCONFERENCE PROGRAM \n\n\n\n\n\n\n\nDevCon 2024 Day 1 – Compliance & Implementation\n\n\nTime\nTitle\nPresenter(s)\n\n\n8:00 – 9:00\nRegistration\n\n\n\n9:00 – 9:15\nWelcome\nJim Pappas\, Intel – CXL Chairman\n\n\n9:15 – 9:45\nKeynote – History of CXL\nLarrie Carr\, Rambus – CXL President\n\n\n9:45 – 10:15\nCXL Specifications Overview\nDebendra Das Sharma\, Intel – TTF Co-Chair\n\n\n10:15 – 10:45\nCoffee Break & Exhibit\n\n\n\n10:45 – 11:30\nTechnical Spec Training (1.0/2.0)\nMahesh Wagh\, AMD – TTF Co-Chair\n\n\n11:30 – 12:00\nCXL Use Case – CXL Native Memory\nBill Gervasi\, Wolley\n\n\n12:00 – 1:00\nLunch & Exhibit\n\n\n\n1:00 – 1:20\nProving CXL scale-out and ROI in the data center\nIra Weiny\, Linux\n\n\n1:20 – 1:40\nCXL Software Ecosystem: The Software Stack for CXL\nSteve Scargall\, MemVerge\n\n\n1:40 – 2:00\nExploring Sunfish™: An Open-source Composable Disaggregated Infrastructure Framework\nMichael Aguilar\, OpenFabrics Alliance – OFA Secretary\n\n\n2:00 – 2:20\nRAS for Resilient Data Centric Platforms using a CXL Memory Controller\nSandeep Dattaprasad\, Astera Labs\n\n\n2:20 – 2:40\nMember Implementation: CXL Memory Latency Measurement Tutorial\nTam Do\, Microchip\n\n\n2:40 – 3:10\nBreak & Exhibit\n\n\n\n3:10 – 3:30\nUnderstanding the Need for Compliance\nAnil Godbole\, Intel\n\n\n3:30 – 3:50\nTesting CXL links using Exercisers & Analyzers\nYamini Shastry\, Viavi\n\n\n3:50 – 4:10\nCXL Testing – Protocol Layers & Testing Examples\nGordon Getty\, Teledyne LeCroy\n\n\n4:10 – 4:40\nFocusing on the Future of CXL Compliance\nNathan White\, Intel – CWG Co-Chair\n\n\n4:40 – 5:00\nDay 1 Open Q&A\nCWG / TTF Panel\n\n\n5:00 – 6:30\nNetworking Reception & Exhibit\n\n\n\n\n  \n\n\n\n\n\n\n\nDevCon 2024 Day 2 – Emerging & Future\n\n\nTime\nTitle\nPresenter(s)\n\n\n8:00 – 8:30\nRegistration and Exhibit\n\n\n\n8:30 – 9:30\nTechnical Spec Training (3.0/3.1)\nRob Blankenship\, Intel – PWG Co-Chair\n\n\n9:30 – 10:00\nMember Implementation: Streamlining CXL Adoption for Hyperscale Efficiency\nNilesh Shah\, ZeroPoint Technologies\n\n\n10:00 – 10:30\nTechnical Training – Security: Integrity and Data Encryption (IDE) Trends and Verification Challenges in CXL\nZongyao Wen\, Synopsys\n\n\n10:30 – 11:00\nCoffee Break & Exhibit\n\n\n\n11:00 – 11:20\nMember Implementation\nDr. Miryeong Kwon\, Panmnesia\n\n\n11:20 – 11:40\nMember Implementation\nGeof Findley\, Montage Technology\n\n\n11:40 – 12:10\nMember Implementation: Using a CXL 2.0 switch for CXL memory expansion\, pooling and sharing\nJianping (JP) Jiang\, PhD\, Xconn Technologies\n\n\n12:10 – 12:30\nMember Implementation: Building Composable and Disaggregated Systems of the Future with CXL 3.0\nRaju Pudota\, Cadence\n\n\n12:30 – 1:30\nLunch & Exhibit\n\n\n\n1:30 – 1:50\nMember Implementation: Improving system memory bandwidth with CXL software interweaving\nRavi Kiran Gummaluri\, Micron\n\n\n1:50 – 2:10\nMember Implementation: Exploring system memory expansion and memory pooling/tiering\nKapil Sethi\, Samsung\n\n\n2:10 -2:30\nMember Implementation: Enabling CXL Memory Module\, Exploring Memory Expansion Use Cases & Beyond\nThomas Won Ha Choi\, PhD\, SK hynix\n\n\n2:30 – 2:50\nMember Implementation: Optical Applications of CXL\nDavid Kulansky\, Alphawave Semi\n\n\n2:50 – 3:30\nBreak & Exhibit\n\n\n\n3:30 – 4:30\nFireside chat – open discussion + audience Q&A\nLeadership Panel\n\n\n4:30 – 5:00\nClosing comments and Call to Action\nKurtis Bowman\, AMD – MWG Co-Chair
URL:https://marketingeda.com/event/cxl-devcon-2024/
LOCATION:Santa Clara Marriott\, 2700 Mission College Blvd\, Santa Clara\, CA\, 95054\, United States
CATEGORIES:Conference,IP
ATTACH;FMTTYPE=image/jpeg:https://marketingeda.com/wp-content/uploads/CXL-DevCon-2024.jpg
END:VEVENT
BEGIN:VEVENT
DTSTART;TZID=America/Los_Angeles:20240430T060000
DTEND;TZID=America/Los_Angeles:20240430T070000
DTSTAMP:20240416T003939Z
CREATED:20240416T003939Z
LAST-MODIFIED:20240416T003939Z
UID:7858-1714456800-1714460400@marketingeda.com
SUMMARY:DFT for chiplets & 3D ICs using Tessent Multi-die
DESCRIPTION:3D IC (2.5D/3D) designs are on the rise. Design for Test (DFT) for chiplets must be general purpose so they can be tested stand alone and easy to test after assembly into 2.5D or 3D devices. In this webinar you will learn how to use Tessent Multi-die and still adhere to standards like IEEE 1149.1\, IEEE 1500\, IEEE 1687\, and IEEE 1838. \nWho should attend:\n\nAnyone planning to implement chiplets\, 2.5D/3D designs and would like to learn about design for test.\nDFT Engineers\nDFT Managers\nDesign Engineers\nTest Engineers\nProject Managers for ASIC/design\n\nWhat you will learn:\n\nHow Tessent Multi-die will aid in 3D IC design for test\nIntro to what IEEE 1838 standard is and how Tessent solution can be used. Use of Tessent Streaming Scan Network (SSN) as flexible parallel port (FPP)\nHow in 2.5D device\, boundary scan-based interconnect test can be performed with Tessent Multi-die\n\n\n\nSpeaker:\n\n\n\n\n\n\nItamar Tsachi\nEurope DFT Manager\, Siemens EDA\n\n\n\n\nItamar Tsachi has more than 20 years of experience in the semiconductor industry and has collaborated with many local and international Siemens EDA customers on a wide range of solutions targeting DFT and RTL->GDSII flows. Before joining Mentor Graphics\, Itamar ramped up IBM’s Physical Design Group in Israel developing SoCs using IBM’s leading-edge technology. Itamar was also a Physical Implementation Consultant and Leader at multiple startups like Mysticom\, BrightCom technologies and Silicon Value\, where he began his chip design career in a variety of roles\, from Digital / Analog layout design to Place & Route and CAD development. Itamar holds one Patent” Placement Driving Routing (PDR) – “A method and apparatus for placement driven routing with a minimum number of changes in the placement.”
URL:https://marketingeda.com/event/dft-for-chiplets-3d-ics-using-tessent-multi-die/
CATEGORIES:EDA,Webinar
ATTACH;FMTTYPE=image/jpeg:https://marketingeda.com/wp-content/uploads/Siemens-April-30-2024.jpg
END:VEVENT
BEGIN:VEVENT
DTSTART;TZID=Europe/London:20240429T100000
DTEND;TZID=Europe/London:20240429T143000
DTSTAMP:20240322T163227Z
CREATED:20240322T163227Z
LAST-MODIFIED:20240322T163227Z
UID:7746-1714384800-1714401000@marketingeda.com
SUMMARY:TechNES FPGA Front Runner Event
DESCRIPTION:The FPGA Front Runners event will be hosted by Renishaw at their venue in Wotton-under-Edge. \nThe event will focus on “Using AI in development and product for FPGA”. \nIf you are interested in speaking at this event please email mike.bartley@techworks.org.uk \nTopics for talks: \n\nWhat AI support is being built into the FPGA fabrics?\nHow are they used?\nWhat input language is used and how does it find it’s way into the FPGA?\nHow is the AI trained?
URL:https://marketingeda.com/event/technes-fpga-front-runner-event/
LOCATION:New Mills\, Wotton-under-Edge\, GL12 8JR\, United Kingdom
CATEGORIES:Forum,IP
ATTACH;FMTTYPE=image/jpeg:https://marketingeda.com/wp-content/uploads/TechNES-29-April-2024.jpg
END:VEVENT
BEGIN:VEVENT
DTSTART;TZID=America/Los_Angeles:20240425T111500
DTEND;TZID=America/Los_Angeles:20240425T170000
DTSTAMP:20240411T001153Z
CREATED:20240411T001153Z
LAST-MODIFIED:20240411T001153Z
UID:7836-1714043700-1714064400@marketingeda.com
SUMMARY:Tech Summit: ASC Sunstone & Screaming Circuits
DESCRIPTION:Calling all PCB designers and engineers to join us for an exclusive Technical Summit and Casino Excursion for Designers & Engineers! \nThis summit is crafted to bring together PCB engineers and technical professionals for a day of immersive learning\, cutting-edge insights\, and many networking opportunities. \nJoin us to expand your knowledge\, establish invaluable connections\, and stay at the forefront of PCB innovation! Dive into the latest advancements\, share knowledge\, and forge meaningful connections within the PCB design and engineering community. \nOnce we have all had a chance to share and digest\, we will board a bus to Ilani Casino for some fun and entertainment! We’ll even have you back at a decent hour so you can be fresh for work on Friday. \n11:15 AM – 11:45 AM \nIntroduction/Box Lunch \nAnaya Vardya \nMatt Stevenson \n\nAnaya – CEO American Standar Circuits/Sunstone Circuits -CEO of American Standard Circuits/Sunstone Circuits – Over thirty years of experience in electronics manufacturing with experiences in the US\, Canada and the Far East. Matt Stevenson – VP and General Mgr ASC Sunstone Circuits – has extensive experience in the PCB industry and has proven his skill and dedication to Sunstone by continuing to grow the company’s revenue and enhance the customer experience. \n11:45 AM – 12:30 PM \nBest Practices – PCB Design \nStephen Chavez \n\nSenior Product Marketing Manager – SME PCB Design\, MIT\, CID+\, CPCD – Chairman – Printed Circuit Engineering Association (PCEA) – Steph is a senior printed circuit engineer with three decades’ experience. He spent the past 12 years as a Principal Engineer and global subject matter expert of PCB design for Collins Aerospace (Raytheon Technologies). He is an IPC Certified Master Instructor Trainer (MIT) for PCB design\, an IPC Certified Advanced PCB Designer (CID+)\, and a Certified Printed Circuit Designer (CPCD). He is chairman of the Printed Circuit Engineering Association (PCEA) where his focus is on the continuous improvement\, professional development\, and the evolution of the printed circuit engineer throughout the industry. An active IPC member since 2003\, he is currently involved in several subcommittees including specifications IPC-6012\, IPC-2221/2222. Chavez is recognized as an industry subject matter expert in PCB design by PCEA\, IPC\, and several leading industry publications. \n12:35 PM – 1:15 PM \nDFM/DFA\nMike Galloway \nMike Galloway has extensive experience in the electronics manufacturing industry\, specializing in prototype process development with a focus on Surface Mount Technology (SMT). With over 15 years at Screaming Circuits as a Senior Manufacturing Engineer\, he plays a crucial role in prototyping and providing short-run production support. Before joining Screaming Circuits\, Mike built his experience at various Contract Manufacturers (CMs) and Original Equipment Manufacturers (OEMs) as well as working with tooling firms serving the electronics industry. Mike’s expertise lies in optimizing manufacturing processes for prototypes\, particularly in the realm of SMT and scaling into production volumes. \n1:30 PM – 2:10 PM \nThermal Management\nAnaya Vardya \nCEO of American Standard Circuits/Sunstone Circuits – Over thirty years of experience in electronics manufacturing with experiences in the US\, Canada and the Far East. He has over a decade of executive management experience in public companies manufacturing PWBs. In addition\, he writes about a variety of subjects but he us particularly focused on partnerships\, technology and manufacturing techniques. \n2:15 PM – 3:00 PM \nUltra HDI\nJohn Johnson \nDirector of Quality at American Standard Circuits – John has a long tenure in Material and Printed Circuit manufacturing. After obtaining an Masters of Science in Organic Chemistry from The Ohio State University\, he has held positions as an R&D Chemist\, Quality Engineer\, Sr. Process Engineer\, Quality Manager\, Sales Rep\, Director of Sales\, General Manager\, President/CEO. Prior to joining ASC as a Director of Business Development\, he was VP of Sales and Customer Support at Averatek Corp and focused on Ultra Fine Line technology. John currently serves as ASC’s Director of Quality and is ASC’s Technology Expert on Ultra High Density Interconnects. \n3:05 PM – 3:45 PM\nFlex/Rigid-Flex PCBs \nJoe Fjelstad \nFounder/President Verdant Electronics – is an international authority and innovator in the field of electronic interconnection and packaging technologies with more than 185 U.S. patents issued or pending. He is the author of Flexible Circuit Technology and author\, co-author or editor of several other books including Chip Scale Packaging for Modern Electronics. He has also authored numerous technical papers and articles. He frequently presents seminars on PCB\, flex circuit and chip scale packaging technologies at industry conferences. \n4:00 PM – 5:00 PM\nPanel Discussion \nOpen floor for Q & A with all speakers. Any questions not able to fit in can be emailed to marketing@sunstone.com. \n5:00 PM – 10:00 PM \nOptional Bus to Ilani Casino with Casino Bucks – Ridgefield Wa
URL:https://marketingeda.com/event/tech-summit-asc-sunstone-screaming-circuits/
LOCATION:Holiday Inn Portland – Columbia Riverfront\, 909 North Hayden Island Drive\, Portland\, OR\, 97217\, United States
CATEGORIES:EDA,Forum
ATTACH;FMTTYPE=image/jpeg:https://marketingeda.com/wp-content/uploads/Tech-Summit-April-25-2024.jpg
END:VEVENT
BEGIN:VEVENT
DTSTART;TZID=America/New_York:20240425T110000
DTEND;TZID=America/New_York:20240425T120000
DTSTAMP:20240401T181039Z
CREATED:20240401T181039Z
LAST-MODIFIED:20240401T181039Z
UID:7800-1714042800-1714046400@marketingeda.com
SUMMARY:Improving Semiconductor Wafer Fabrication Process Efficiencies Using Ansys Solutions
DESCRIPTION:Ansys Semiconductor Manufacturing Webinar Series: Part 1 of 3. \nJoin us on Thursday\, April 25th for an in-depth view of multi-physics simulation in the semiconductor fabrication process. \nOverview\nAccurate design and optimization of the semiconductor fabrication process/equipment for yield improvements and faster time-to-market require multiphysics simulation\, which can address various physical interactions and phenomena. By encompassing factors from contamination challenges to ensuring uniform product outcomes\, engineers can leverage such simulations to generate innovative ideas for optimized processes and cutting-edge solutions in semiconductor fabrication. \nThis webinar will demonstrate the practical application of Ansys tools in understanding the impact of various parameters on diverse wafer fabrication processes and fine-tuning them to improve yields and reduce wafer cycle time. \nWhat you will learn\n\nImportance of simulation in fabrication processes\nReduce wafer cycle time\nModel fabrication process with Ansys tools\nOptimize of fabrication processes\nSystem-level modeling of fabrication processes\n\nWho should attend\nEngineers and Engineering Managers/Directors\, Manufacturing teams\, Etch teams\, Deposition teams\, NPI teams and Aftermarket teams \nSpeaker\n\nNima Bohlooli\, Senior Application Engineer\, Ansys
URL:https://marketingeda.com/event/improving-semiconductor-wafer-fabrication-process-efficiencies-using-ansys-solutions/
CATEGORIES:EDA,Semiconductor,Webinar
ATTACH;FMTTYPE=image/jpeg:https://marketingeda.com/wp-content/uploads/April-25-2024-Ansys.jpg
END:VEVENT
BEGIN:VEVENT
DTSTART;TZID=America/Los_Angeles:20240425T090000
DTEND;TZID=America/Los_Angeles:20240425T170000
DTSTAMP:20240423T003845Z
CREATED:20240423T003845Z
LAST-MODIFIED:20240423T003845Z
UID:7893-1714035600-1714064400@marketingeda.com
SUMMARY:Siemens User2User Verification Forum 2024 India
DESCRIPTION:Join us at the Siemens User2User Verification Forum 2024 in India next week! \nGain insights on Smart Verification – Using AI in Functional Verification and learn best practices in design and verification flows that can speed up your ASIC and FPGA design & verification cycle.\nDon’t miss the chance to leverage AI and ML based flows in some of the technologies. \nHyderabad on April 23\, 2024\, and Bangalore on April 25\, 2024\, at 9AM IST.
URL:https://marketingeda.com/event/siemens-user2user-verification-forum-2024-india-2/
LOCATION:Hotel Radission Blu\, Marathalli ORR\, 90/4 Outer Ring Road\, Bengaluru\, India
CATEGORIES:EDA,User Group
ATTACH;FMTTYPE=image/jpeg:https://marketingeda.com/wp-content/uploads/Siemens-User2User-Verification-India-2024.jpg
END:VEVENT
BEGIN:VEVENT
DTSTART;TZID=America/New_York:20240425T090000
DTEND;TZID=America/New_York:20240425T100000
DTSTAMP:20240401T180250Z
CREATED:20240401T180042Z
LAST-MODIFIED:20240401T180250Z
UID:7797-1714035600-1714039200@marketingeda.com
SUMMARY:The Era of Software-Defined Everything: Chiplets and Bespoke Silicon
DESCRIPTION:From fintech to automotive\, defense to healthcare\, everyone wants bespoke computing platforms to build “software-defined solutions” that are differentiated in their respective markets. Sign up and save your spot for this special presentation. \nOverview\nWith the advent of 3D ICs and heterogeneous semiconductor integration\, mapping a system on a customized chip/hardware is accessible to “everyone.” \nThe semiconductor suppliers are gearing themselves for the change\, and\, as Jensen Huang (NVIDIA CEO) was recently quoted\, “2024 is the year where every industry is becoming a high-tech industry.” \nFrom fintech to automotive\, defense to healthcare\, everyone wants bespoke computing platforms to build “software-defined solutions” that are differentiated in their respective markets. \nBut this (r)evolution faces a multitude of challenges\, such as \n\nIs the workforce (engineering community at large) ready for this massive deployment of semiconductor technologies?\nAre the design methodologies\, both semiconductor and system\, ready and enabling?\nWhat is the level of over-engineering that drives this sequence?\n\nWhat you will learn\n\nHow to harness 3D-IC and chiplets to accelerate the transition to software-defined everything\nHow chiplets can give your business a competitive edge\nWhat is the best use of AI for the transition?\n\nWho should attend and why\nIf you are responsible for an engineering department or in charge of NPI and Product Development /Strategy\, sign up for this online webinar. \nSpeaker\n\nChief Technologist Christopher Bianchi
URL:https://marketingeda.com/event/the-era-of-software-defined-everything-chiplets-and-bespoke-silicon/
CATEGORIES:EDA,IP,Webinar
ATTACH;FMTTYPE=image/jpeg:https://marketingeda.com/wp-content/uploads/Ansys-April-25-2024.jpg
END:VEVENT
BEGIN:VEVENT
DTSTART;TZID=America/Los_Angeles:20240425T080000
DTEND;TZID=America/Los_Angeles:20240425T170000
DTSTAMP:20240410T171939Z
CREATED:20240410T171409Z
LAST-MODIFIED:20240410T171939Z
UID:7830-1714032000-1714064400@marketingeda.com
SUMMARY:IP-SoC Silicon Valley 2024
DESCRIPTION:A worldwide connected Event !! \nD&R IP-SoC Silicon Valley 2024 Day is the unique worldwide Spring event fully dedicated to IP (Silicon Intellectual Property) and IP based Electronic Systems. \nIP-SoC providers\, the seed of innovation in Electronic Industry\, are invited to highlight their latest products and services and share their vision about the next innovation steps in the Electronic Industry. \nIP consumers can view at a glance the latest Technology trends and exciting Innovative IP/SoC products. Through a global view\, Electronic systems leaders may identify disruptive innovation leading to new market segment growth. \nAny question? Please contact us
URL:https://marketingeda.com/event/ip-soc-silicon-valley-2024/
LOCATION:Hyatt Regency Santa Clara\, 5101 Great America Parkway\, Santa Clara\, CA\, 95054\, United States
CATEGORIES:Conference,IP
ATTACH;FMTTYPE=image/jpeg:https://marketingeda.com/wp-content/uploads/IP-SoC-Silicon-Valley-24.jpg
END:VEVENT
BEGIN:VEVENT
DTSTART;TZID=America/Los_Angeles:20240425T080000
DTEND;TZID=America/Los_Angeles:20240425T114500
DTSTAMP:20240329T165734Z
CREATED:20240329T165734Z
LAST-MODIFIED:20240329T165734Z
UID:7790-1714032000-1714045500@marketingeda.com
SUMMARY:AI Driving Fabs of the Future… People\, Technology\, Infrastructure
DESCRIPTION:This is an incredibly exciting time for semiconductor manufacturing. After the supply chain disruption in the early 2020s\, companies are rapidly expanding and enhancing operations to meet market demands. Over the next few years\, many new fully automated 300mm fabs will bring major advancements to the industry. Get first-hand information—Join us in person or online. REGISTER TODAY. \nAttend the Pacific Northwest Breakfast Forum hosted at Analog Devices in Beaverton\, Oregon to hear experts discuss— \n\nKEYNOTE: The 5th Industrial Revolution: The Adjacent Possible of AI in Semiconductor Manufacturing—Analog Devices\nMacro Trends and Value Creation in the Semiconductor Industry—McKinsey & Company\nWhat Does It Mean for the Existing 200mm Legacy Fabs?—Microchip Technology\nSEMI Smart Manufacturing Initiative—Microchip Technology\nAI Use Cases in the Fab—Applied Materials\nEXECUTIVE PANEL: Discussion for Talent Acquisition\, Workforce Development\, Labor Shortage\n\nEXPERT SPEAKERS\nKEYNOTE\nDANIEL BURLINGAME\nANALOG DEVICES\n\n\nDAVID HANNY\nAPPLIED MATERIALS\n\n\n\nHENRY MARCIL\nMCKINSEY & COMPANY\n\n\n\nGARY STINSON\nMICROCHIP TECHNOLOGY
URL:https://marketingeda.com/event/ai-driving-fabs-of-the-future-people-technology-infrastructure/
LOCATION:Analog Devices\, 14320 SW Jenkins Road\, Beaverton\, OR\, 97005\, United States
CATEGORIES:Forum,Semiconductor
ATTACH;FMTTYPE=image/jpeg:https://marketingeda.com/wp-content/uploads/SEMI-April-25-2024.jpg
END:VEVENT
BEGIN:VEVENT
DTSTART;TZID=America/Los_Angeles:20240424T080000
DTEND;TZID=America/Los_Angeles:20240424T170000
DTSTAMP:20240325T163321Z
CREATED:20240325T163321Z
LAST-MODIFIED:20240325T163321Z
UID:7759-1713945600-1713978000@marketingeda.com
SUMMARY:TSMC 2024 Technology Symposium - North America
DESCRIPTION:Learn about:\n\nTSMC’s industry-leading HPC\, smartphone\, IoT\, and automotive platform solutions\nTSMC’s advanced technology progress on 5nm\, 4nm\, 3nm\, 2nm processes and beyond\nTSMC’s specialty technology breakthroughs on ultra-low power\, RF\, embedded memory\, power management\, sensor technologies\, and more\nTSMC 3DFabric™ advanced packaging technology advancement on InFO\, CoWoS®\, and TSMC-SoIC®\nTSMC’s manufacturing excellence\, capacity expansion plans\, and green manufacturing achievements\nTSMC’s Open Innovation Platform® ecosystem to speed up time-to-design
URL:https://marketingeda.com/event/tsmc-2024-technology-symposium-north-america/
LOCATION:Santa Clara Convention Center\, 5001 Great America Parkway\, Santa Clara\, CA\, 95054\, United States
CATEGORIES:Foundry,Symposium
ATTACH;FMTTYPE=image/jpeg:https://marketingeda.com/wp-content/uploads/TSMC-2024-North-America.jpg
END:VEVENT
BEGIN:VEVENT
DTSTART;TZID=America/Los_Angeles:20240424T080000
DTEND;TZID=America/Los_Angeles:20240424T090000
DTSTAMP:20240416T183848Z
CREATED:20240416T183848Z
LAST-MODIFIED:20240416T183848Z
UID:7863-1713945600-1713949200@marketingeda.com
SUMMARY:Deploying Solido Design Environment AI Workflows on AWS
DESCRIPTION:Utilizing AWS cloud resources to accelerate variation-aware verification   \n\nAI-powered Solido Design Environment provides SPICE-accurate variation-aware verification for 3\, 4\, 5\, 6 and higher sigma targets\, orders of magnitude faster than traditional brute-force methods. With cloud computing made more accessible than before\, many teams are considering running design and verification workloads\, including Solido Design Environment\, on the cloud. \nSiemens and AWS’ strategic collaboration enables a Siemens EDA portfolio that is even more accessible\, scalable\, flexible\, and secure on AWS. Today\, Solido Design Environment users can leverage the power of AWS cloud computing to manage and deploy SPICE-level verification\, resulting in accelerated verification schedules and significantly higher capacity for peak workload demands. \nIn this Masterclass webinar\, co-presented by Siemens EDA and AWS\, we explore best practices and resources available for deploying Solido Design Environment on AWS. Join us and learn more about AWS’ solutions for SPICE-level verification\, tried-and-tested cloud configurations for Solido Design Environment\, and a Q&A session with Siemens and AWS experts to get started confidently and leverage AWS compute to maximize verification throughput and address peak demand on Solido Design Environment. \nTopic Include:\n– The need for cloud scalability for  semiconductor design\n– Solido Design Environment overview\n– Best practices and considerations\n– AWS capabilities for SPICE verification\, including example cloud configuration\n– Resources available for teams deploying to AWS cloud\n– Interactive Q&A \nFeatured Products:  Solido Design Environment\, AWS Cloud Platform \nSpeakers:\n\n\n\n\nWei-Lii Tan\nDirector of Product Management\, Siemens EDA\n\n\nWei-Lii Tan is Director of Product Management in Siemens DISW’s Custom IC Verification division for Solido’s AI-enabled verification & characterization\, and IP validation product lines. Wei-Lii has 15 years of experience in semiconductor and EDA\, having worked on both digital and analog methodologies. He has a master’s degree in electrical engineering from Mississippi State University\, and an M.B.A. from Santa Clara University. \n\nAzim Siddique\nSenior Solutions Architect\, Amazon Web Services\n\n\nAzim works with AWS Enterprise customers on their Cloud adoption journey. Azim has 20+ years of experience working at large global organizations in the manufacturing and industrials domain\, architecting and delivering innovative solutions at scale to generate business value. Azim is passionate about being part of transformational changes driven by technological innovation.
URL:https://marketingeda.com/event/deploying-solido-design-environment-ai-workflows-on-aws/
CATEGORIES:EDA,Webinar
ATTACH;FMTTYPE=image/jpeg:https://marketingeda.com/wp-content/uploads/Siemens-April-24-2024.jpg
END:VEVENT
BEGIN:VEVENT
DTSTART;TZID=Europe/London:20240423T120000
DTEND;TZID=Europe/London:20240423T130000
DTSTAMP:20240410T161505Z
CREATED:20240410T161505Z
LAST-MODIFIED:20240410T161505Z
UID:7823-1713873600-1713877200@marketingeda.com
SUMMARY:DVClub Europe - Formal Verification
DESCRIPTION:13 days to go the next DVClub Europe meeting takes place on Tuesday 23rd April with a theme of “Formal Verification“.\n\nFormal Verification can help you find bugs earlier in the design cycle and accelerate root cause analysis. But success with Formal requires the effective selection and implementation of the right formal technologies and methods. In this DVClub meeting our speakers will share their experiences adopting Formal Verification and then open the floor for discussion followed by the usual networking opportunities.\n\nAgenda (BST) \n12:00   Welcome and Introduction – Mike Bartley\, Tessolve\n12:00 Brajmohan Sharma\, Marvel Technology – Advanced Formal Verification and Robust Regression Strategies for Highly Parameterized Designs\n12:20 Easwaran Krishnan & Savita Suresh Lohar\, Tessolve Semiconductor\n12:40 Gayatri Padhy\, Object Automation – Formal Verification with AI/ML\n13:00 Cadence Design System\n13:15 Neena Chandawale \,Agnisys\n13:30 Close \nRegister now to become a part of this event. Free to attend online. \nTicket Tailor- DVClub Europe 
URL:https://marketingeda.com/event/dvclub-europe-formal-verification/
CATEGORIES:EDA,Webinar
ATTACH;FMTTYPE=image/jpeg:https://marketingeda.com/wp-content/uploads/DVClub-Europe-23-April-2024.jpg
END:VEVENT
BEGIN:VEVENT
DTSTART;TZID=America/Los_Angeles:20240423T100000
DTEND;TZID=America/Los_Angeles:20240424T123000
DTSTAMP:20240409T163519Z
CREATED:20240409T163519Z
LAST-MODIFIED:20240409T163519Z
UID:7820-1713866400-1713961800@marketingeda.com
SUMMARY:osmosis Aerospace and Defense 2024 A Formal Verification Virtual Event
DESCRIPTION:osmosis Aerospace and Defense (A&D) is about sharing the success in using formal techniques to address the demanding verification requirements and challenges of DO-254 compliant and other high-consequence systems. \n‌ \nWe have put together the following program covering a wide range of formal verification topics.\n Day 1 – Tuesday\, April 23 \n\n10:00am Pacific | 1:00pm Eastern\n\nKeynote: Importance of Microelectronics Assurance \nCody Wagner | US Navy CRANE \n\n10:30am Pacific | 1:30pm Eastern\n\nTrusted and Assured Microelectronics Begin Long Before Silicon\nJohn Hallman | Siemens \n\n11:00am Pacific | 2:00pm Eastern\n\nEnverite PV-Bit: Bitstream Verification for FPGA Design Assurance\nDr. Jonathan Graf | Graf Research \n\n11:30am Pacific | 2:30pm Eastern\n\nOptimizing FPGA Equivalence Checking for A&D Designs \nKevin Urish | Siemens \n\nNoon Pacific | 3:00pm Eastern\n\nSupply Chain Traceability and Assurance \nBrett Attaway | Siemens Government Technologies \n‌\n Day 2 – Wednesday\, April 24 \n‌ \n\n10:00am Pacific | 1:00pm Eastern\n\nDecoding Design Mysteries: Revolutionize Your Architectural Insights with \nQuesta Analyze Architecture \nChristopher Diltz | Edaptive \n\n10:30am Pacific | 1:30pm Eastern\n\nEnhanced Assurance for FPGA EDA Tools \nChristopher Clark | GTRI \n\n11:00am Pacific | 2:00pm Eastern\n\nDriving efficient execution with Continuous Integration \nKevin Campbell | Siemens \n\n11:30am Pacific | 2:30pm Eastern\n\nNew AI Horizons in Static & Formal Verification A&D \nDan Yu | Siemens \nIf you have any questions (including whether you could “bump” one of our R&D presenters to share your formal verification story)\, email osmosis.sisw@siemens.com with the “osmosis A&D 2024” keyword in the subject header. \n‌ \nWe look forward to seeing you online! \n‌ \nThe Siemens Formal Verification Team
URL:https://marketingeda.com/event/osmosis-aerospace-and-defense-2024-a-formal-verification-virtual-event/
CATEGORIES:EDA,Forum
ATTACH;FMTTYPE=image/jpeg:https://marketingeda.com/wp-content/uploads/Osmosis-2024.jpg
END:VEVENT
BEGIN:VEVENT
DTSTART;TZID=Indian/Maldives:20240423T090000
DTEND;TZID=Indian/Maldives:20240423T170000
DTSTAMP:20240423T003434Z
CREATED:20240423T003434Z
LAST-MODIFIED:20240423T003434Z
UID:7889-1713862800-1713891600@marketingeda.com
SUMMARY:Siemens User2User Verification Forum 2024 India
DESCRIPTION:Join us at the Siemens User2User Verification Forum 2024 in India next week! \nGain insights on Smart Verification – Using AI in Functional Verification and learn best practices in design and verification flows that can speed up your ASIC and FPGA design & verification cycle.\nDon’t miss the chance to leverage AI and ML based flows in some of the technologies. \nHyderabad on April 23\, 2024\, and Bangalore on April 25\, 2024\, at 9AM IST.
URL:https://marketingeda.com/event/siemens-user2user-verification-forum-2024-india/
LOCATION:Hyatt Place\, Banjara Hills\, Road no 1\, Banjara Hills\, Hyderabad\, India
CATEGORIES:EDA,User Group
ATTACH;FMTTYPE=image/jpeg:https://marketingeda.com/wp-content/uploads/Siemens-User2User-Verification-India-2024.jpg
END:VEVENT
BEGIN:VEVENT
DTSTART;TZID=America/Phoenix:20240422T080000
DTEND;TZID=America/Phoenix:20240424T170000
DTSTAMP:20240201T020320Z
CREATED:20240201T020320Z
LAST-MODIFIED:20240201T020320Z
UID:7567-1713772800-1713978000@marketingeda.com
SUMMARY:42nd VLSI Test Symposium
DESCRIPTION:The IEEE VLSI Test Symposium (VTS) explores emerging trends and novel concepts in test\, validation\, yield\, reliability\, and security of microelectronic circuits and systems.\n\nThe symposium will take place on April 22-24 2024\, in Tempe\, AZ\, USA.\nThe program includes keynotes\, scientific paper presentations\, short industrial application paper presentations\, special sessions\, and Innovative Practices sessions. \nYou are invited to participate and submit your contributions to VTS’24. The areas of interest include (but are not limited to) the following topics: \nVTS Topics\n\n\n  \n\n\n\n\n\nAnalog – Mixed-Signal – RF Test\nATPG & Compression\nSilicon Debug\nAutomotive Test & Safety\nBuilt-In Self-Test (BIST)\nDefect & Current Based Test\nDefect & Fault Tolerance\nDelay & Performance Test\nDesign for Testability – Yield or Reliability\nPre-silicon Design Verification & Validation\nPost-silicon Validation\nHardware Security\nEmbedded System & Board Test\nEmbedded Test Methods\nEmerging Technologies Test and Reliability\nFault Modeling and Simulation\nLow-Power IC Test\nFunctional safety and test methods to ensure functional safety\n\n\n\n\nMachine Learning in Test – Yield and Reliability\nMicrosystems/MEMS/Sensors Test\nMemory Test and Repair\n2.5D – 3D & SiP Test\nYield Optimization\nOn-Line Test & Error Correction\nPower & Thermal Issues in Test\nSystem-on-Chip (SOC) Test\nTest & Reliability of Biomedical Devices\nTest & Reliability of High-Speed I/O\nTest & Reliability of Machine Learning Systems\nTest Quality & Reliability\nTest Standards & Economics\nTest Resource Partitioning\nTransient & Soft Errors\nFPGA Test\n\n\n\n\n\n  \n\n\n  \n\n\n\n\nNew Hot Topics\n\n  \n\nThis year\, VTS puts particular emphasis on enlarging its scope soliciting submissions on aspects on silent data corruption test\, reliability and security of AI\, fault models and reliability of in-memory computing hardware\, and quantum computing\, and functional safety.
URL:https://marketingeda.com/event/42nd-vlsi-test-symposium/
LOCATION:Memorial Union Conference Center\, 1151 S Forest Ave\, Tempe\, AZ\, United States
ATTACH;FMTTYPE=image/jpeg:https://marketingeda.com/wp-content/uploads/VLSI-Test-Symposium-2024.jpg
END:VEVENT
BEGIN:VEVENT
DTSTART;TZID=America/Los_Angeles:20240421T080000
DTEND;TZID=America/Los_Angeles:20240424T170000
DTSTAMP:20240419T164318Z
CREATED:20240419T164152Z
LAST-MODIFIED:20240419T164318Z
UID:7873-1713686400-1713978000@marketingeda.com
SUMMARY:CICC 2024
DESCRIPTION:The IEEE Custom Integrated Circuits Conference is a premier conference devoted to IC development. The conference program is a blend of oral presentations\, exhibits\, panels and forums. The conference sessions present original first published technical work and innovative circuit techniques that tackle practical problems. CICC is the conference to find out how to solve design problems\, improve circuit design techniques\, get exposure to new technology areas\, and network with peers\, authors and industry experts. \nThere are 3 days of Technical Sessions that include lecture presentations addressing state of the art developments in integrated circuit design. The Educational Sessions are a full day of tutorials instructed by recognized invited speakers. The Panels\, and Forums are presented throughout the conference to enrich the learning experience of the attendees. The Panel Discussions and Forums are presented by leaders from the IC industry. CICC includes an Exhibits Hall that is open in the evenings where Semiconductor manufacturers\, software tool suppliers\, silicon IP providers\, design-service houses\, and technical book publishers offer displays and demonstrations of their products. CICC is sponsored by the IEEE Solid-State Circuits Society and technically co-sponsored by the IEEE Electron Devices Society.
URL:https://marketingeda.com/event/cicc-2024/
LOCATION:DoubleTree by Hilton Denver\, 3203 Quebec Street\, Denver\, CO\, United States
CATEGORIES:Conference,EDA,Foundry,IP
ATTACH;FMTTYPE=image/jpeg:https://marketingeda.com/wp-content/uploads/CICC-2024.jpg
END:VEVENT
BEGIN:VEVENT
DTSTART;TZID=America/Los_Angeles:20240419T080000
DTEND;TZID=America/Los_Angeles:20240421T170000
DTSTAMP:20240408T222220Z
CREATED:20240212T205659Z
LAST-MODIFIED:20240408T222220Z
UID:7610-1713513600-1713718800@marketingeda.com
SUMMARY:Latch-Up 2024: Boston
DESCRIPTION:Friday to Sunday April 19–21\, 2024 in Boston\, MA\, USA \nThe Latch-Up conference is a weekend of presentations and networking dedicated to free and open source silicon. It’s an event for the open source digital design community\, much like its European sister conference ORConf\, run by the FOSSi Foundation. \n\n\n\n\n\nYou are all invited!\nThe FOSSi Foundation is proud to announce Latch-Up\, a conference dedicated to free and open source silicon to be held over the weekend of Friday April 19 to Sunday April 21 in Boston\, MA\, USA. \nLatch-Up is a weekend of presentations and networking for the open source digital design community\, much like its European sister conference ORConf. \nSo save the date\, register to attend\, and submit a presentation or proposal if you have a project or idea on the topic to share! \nQuestions? Ping the organizers via @LatchUpConf or send an email to latch-up@fossi-foundation.org. \n\n\n\nSubmit a talk\nWe encourage anybody involved in the open source semiconductor engineering space to come along and share your work or experience. Presentations slots as short as 3 minute lightning-talks and up to 30 minute talks including Q and A are available. \nSo if you’ve designed\, worked on or even just used open source IP cores and/or management systems\, verification IP\, build flows\, SoCs\, simulators\, synthesis tools\, FPGA and ASIC implementation tools\, languages and DSLs\, compilers\, or anything related we’d love to have you join us to share your experience. \nPresentations are submitted through the registration process and we will let you know if your presentation was accepted. \nTickets and registration\nAttendance of Latch-Up is free of charge. To help us organizing the event\, you are required to register on Eventbrite. Please register as soon as possible\, as we have to close registrations as soon as the room capacity is reached. \nAttendees who are joining us at Latch-Up on behalf of their company and/or can claim the conference as professional training expense are encouraged to purchase a professional ticket. These ticket sales help us provide all that we do at Latch-Up and keep the event accessible to all members of the community. Professional ticket holders are able to get their company name printed on their name badge and receive a special treat. \nWe ask all Latch-Up participants to adhere to the the FOSSi Foundation code of conduct throughout the event. \nFriday\n\n\n\nWhen\nWhat\n\n\n\n\n9:00\nWelcome\n\n\n9:20\nCaster: An Open-source E-Ink Controller\n\n\n9:40\nTeaching Modern EDA using a Tapeout-Centric University Course\n\n\n10:00\nBreak\n\n\n10:20\nCedarEDA for open source silicon\n\n\n10:40\nCohort: Software-Oriented Acceleration for You\, Me\, and Our Heterogeneous SoCs\n\n\n11:00\nTowards xBGAS on CHERI: Examining the Benefits of a Secure Distributed Architecture\n\n\n11:20\nLunch\n\n\n12:20\nTowards Cycle-accurate Simulation of xBGAS\n\n\n12:40\nArtifact Evaluation for the Field Programmable Gate Array Community\n\n\n13:00\nChisel 6 and beyond\n\n\n13:20\nMRPHS: Enabling Transaction-level Deductive Formal Verification Through PDVL\n\n\n13:40\nBreak\n\n\n14:40\nRiding The Wave: Building Wave Pipelines in FPGAs\n\n\n15:00\nGiving Students A Byte of Open-Source: Advancing Hardware Education\n\n\n15:20\nBreak\n\n\n15:40\nOpen-source resources for learning the Bluespec HL-HDLs\n\n\n16:00\nPyHDL-IF: An Easy-to-Use Python/HDL Cross-Calling Interface\n\n\n16:20\nTransition to Draper\n\n\n17:00\nTalks(30-40m) at Draper\n\n\n18:00\nTransition to lightning Talks\n\n\n19:00\nLightning Talks\n\n\n20:00\nGo home\n\n\n\nSaturday\n\n\n\nWhen\nWhat\n\n\n\n\n8:40\nWelcome\n\n\n9:00\nOpen source RTL verification with Verilator\n\n\n9:20\nSonata: A development platform to enable exploring the use of CHERI for embedded applications\n\n\n9:40\nTransparent Checkpointing for Fault Tolerance in RISC-V\n\n\n10:00\nBreak\n\n\n10:20\nHDLAgent\, Enhancing Hardware Language in the age of LLMs\n\n\n10:40\nSpade: An HDL Inspired By Modern Software Languages\n\n\n11:00\nSwitchboard: Calling All Hardware Models\n\n\n11:20\nLunch\n\n\n12:20\nFrom an Open-Source ISA to Open-Source HW to Open-Source Silicon\n\n\n12:40\nOpen Source Hardware: Hacking Silicon for Fun (instead of profit)\n\n\n13:00\nA History of TL-Verilog Google Summer of Code Projects under FOSSi Foundation\n\n\n13:20\nUMI: Universal Memory Interface\n\n\n13:40\nBreak\n\n\n14:20\nABC: The Way It Should Have Been Designed\n\n\n14:40\nBYOL (Build Your Own Linter) – UVMLint for IEEE-UVM core code development\n\n\n15:00\nBeyond EDA lies Edalize\n\n\n15:20\nBreak\n\n\n15:40\nRF Front-end receiver design for 2.4GH/5GHz WiFi application\n\n\n16:00\nCACE Study: Open source analog and mixed-signal design flow\n\n\n16:20\nIHP Open Source PDK: Announcement\, Setup\, Current State and Experiences\, and look ahead\n\n\n16:40\nTiny Tapeout: custom silicon open to all\n\n\n17:20\nMeet at Flattops\n\n\n\nSunday\nComing soon
URL:https://marketingeda.com/event/latch-up-2024-boston/
LOCATION:Massachusetts Institute of Technology\, 77 Massachusetts Avenue\, Boston\, MA\, United States
CATEGORIES:Conference,EDA,IP
ATTACH;FMTTYPE=image/jpeg:https://marketingeda.com/wp-content/uploads/Latch-Up-2024.jpg
END:VEVENT
END:VCALENDAR