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DTSTART;TZID=Europe/London:20240423T120000
DTEND;TZID=Europe/London:20240423T130000
DTSTAMP:20240410T161505Z
CREATED:20240410T161505Z
LAST-MODIFIED:20240410T161505Z
UID:7823-1713873600-1713877200@marketingeda.com
SUMMARY:DVClub Europe - Formal Verification
DESCRIPTION:13 days to go the next DVClub Europe meeting takes place on Tuesday 23rd April with a theme of “Formal Verification“.\n\nFormal Verification can help you find bugs earlier in the design cycle and accelerate root cause analysis. But success with Formal requires the effective selection and implementation of the right formal technologies and methods. In this DVClub meeting our speakers will share their experiences adopting Formal Verification and then open the floor for discussion followed by the usual networking opportunities.\n\nAgenda (BST) \n12:00   Welcome and Introduction – Mike Bartley\, Tessolve\n12:00 Brajmohan Sharma\, Marvel Technology – Advanced Formal Verification and Robust Regression Strategies for Highly Parameterized Designs\n12:20 Easwaran Krishnan & Savita Suresh Lohar\, Tessolve Semiconductor\n12:40 Gayatri Padhy\, Object Automation – Formal Verification with AI/ML\n13:00 Cadence Design System\n13:15 Neena Chandawale \,Agnisys\n13:30 Close \nRegister now to become a part of this event. Free to attend online. \nTicket Tailor- DVClub Europe 
URL:https://marketingeda.com/event/dvclub-europe-formal-verification/
LOCATION:OR
CATEGORIES:EDA,Webinar
ATTACH;FMTTYPE=image/jpeg:https://marketingeda.com/wp-content/uploads/DVClub-Europe-23-April-2024.jpg
END:VEVENT
BEGIN:VEVENT
DTSTART;TZID=America/Los_Angeles:20240423T100000
DTEND;TZID=America/Los_Angeles:20240424T123000
DTSTAMP:20240409T163519Z
CREATED:20240409T163519Z
LAST-MODIFIED:20240409T163519Z
UID:7820-1713866400-1713961800@marketingeda.com
SUMMARY:osmosis Aerospace and Defense 2024 A Formal Verification Virtual Event
DESCRIPTION:osmosis Aerospace and Defense (A&D) is about sharing the success in using formal techniques to address the demanding verification requirements and challenges of DO-254 compliant and other high-consequence systems. \n‌ \nWe have put together the following program covering a wide range of formal verification topics.\n Day 1 – Tuesday\, April 23 \n\n10:00am Pacific | 1:00pm Eastern\n\nKeynote: Importance of Microelectronics Assurance \nCody Wagner | US Navy CRANE \n\n10:30am Pacific | 1:30pm Eastern\n\nTrusted and Assured Microelectronics Begin Long Before Silicon\nJohn Hallman | Siemens \n\n11:00am Pacific | 2:00pm Eastern\n\nEnverite PV-Bit: Bitstream Verification for FPGA Design Assurance\nDr. Jonathan Graf | Graf Research \n\n11:30am Pacific | 2:30pm Eastern\n\nOptimizing FPGA Equivalence Checking for A&D Designs \nKevin Urish | Siemens \n\nNoon Pacific | 3:00pm Eastern\n\nSupply Chain Traceability and Assurance \nBrett Attaway | Siemens Government Technologies \n‌\n Day 2 – Wednesday\, April 24 \n‌ \n\n10:00am Pacific | 1:00pm Eastern\n\nDecoding Design Mysteries: Revolutionize Your Architectural Insights with \nQuesta Analyze Architecture \nChristopher Diltz | Edaptive \n\n10:30am Pacific | 1:30pm Eastern\n\nEnhanced Assurance for FPGA EDA Tools \nChristopher Clark | GTRI \n\n11:00am Pacific | 2:00pm Eastern\n\nDriving efficient execution with Continuous Integration \nKevin Campbell | Siemens \n\n11:30am Pacific | 2:30pm Eastern\n\nNew AI Horizons in Static & Formal Verification A&D \nDan Yu | Siemens \nIf you have any questions (including whether you could “bump” one of our R&D presenters to share your formal verification story)\, email osmosis.sisw@siemens.com with the “osmosis A&D 2024” keyword in the subject header. \n‌ \nWe look forward to seeing you online! \n‌ \nThe Siemens Formal Verification Team
URL:https://marketingeda.com/event/osmosis-aerospace-and-defense-2024-a-formal-verification-virtual-event/
LOCATION:OR
CATEGORIES:EDA,Forum
ATTACH;FMTTYPE=image/jpeg:https://marketingeda.com/wp-content/uploads/Osmosis-2024.jpg
END:VEVENT
BEGIN:VEVENT
DTSTART;TZID=Indian/Maldives:20240423T090000
DTEND;TZID=Indian/Maldives:20240423T170000
DTSTAMP:20240423T003434Z
CREATED:20240423T003434Z
LAST-MODIFIED:20240423T003434Z
UID:7889-1713862800-1713891600@marketingeda.com
SUMMARY:Siemens User2User Verification Forum 2024 India
DESCRIPTION:Join us at the Siemens User2User Verification Forum 2024 in India next week! \nGain insights on Smart Verification – Using AI in Functional Verification and learn best practices in design and verification flows that can speed up your ASIC and FPGA design & verification cycle.\nDon’t miss the chance to leverage AI and ML based flows in some of the technologies. \nHyderabad on April 23\, 2024\, and Bangalore on April 25\, 2024\, at 9AM IST.
URL:https://marketingeda.com/event/siemens-user2user-verification-forum-2024-india/
LOCATION:Hyatt Place\, Banjara Hills\, Road no 1\, Banjara Hills\, Hyderabad\, India
CATEGORIES:EDA,User Group
ATTACH;FMTTYPE=image/jpeg:https://marketingeda.com/wp-content/uploads/Siemens-User2User-Verification-India-2024.jpg
END:VEVENT
BEGIN:VEVENT
DTSTART;TZID=America/Phoenix:20240422T080000
DTEND;TZID=America/Phoenix:20240424T170000
DTSTAMP:20240201T020320Z
CREATED:20240201T020320Z
LAST-MODIFIED:20240201T020320Z
UID:7567-1713772800-1713978000@marketingeda.com
SUMMARY:42nd VLSI Test Symposium
DESCRIPTION:The IEEE VLSI Test Symposium (VTS) explores emerging trends and novel concepts in test\, validation\, yield\, reliability\, and security of microelectronic circuits and systems.\n\nThe symposium will take place on April 22-24 2024\, in Tempe\, AZ\, USA.\nThe program includes keynotes\, scientific paper presentations\, short industrial application paper presentations\, special sessions\, and Innovative Practices sessions. \nYou are invited to participate and submit your contributions to VTS’24. The areas of interest include (but are not limited to) the following topics: \nVTS Topics\n\n\n  \n\n\n\n\n\nAnalog – Mixed-Signal – RF Test\nATPG & Compression\nSilicon Debug\nAutomotive Test & Safety\nBuilt-In Self-Test (BIST)\nDefect & Current Based Test\nDefect & Fault Tolerance\nDelay & Performance Test\nDesign for Testability – Yield or Reliability\nPre-silicon Design Verification & Validation\nPost-silicon Validation\nHardware Security\nEmbedded System & Board Test\nEmbedded Test Methods\nEmerging Technologies Test and Reliability\nFault Modeling and Simulation\nLow-Power IC Test\nFunctional safety and test methods to ensure functional safety\n\n\n\n\nMachine Learning in Test – Yield and Reliability\nMicrosystems/MEMS/Sensors Test\nMemory Test and Repair\n2.5D – 3D & SiP Test\nYield Optimization\nOn-Line Test & Error Correction\nPower & Thermal Issues in Test\nSystem-on-Chip (SOC) Test\nTest & Reliability of Biomedical Devices\nTest & Reliability of High-Speed I/O\nTest & Reliability of Machine Learning Systems\nTest Quality & Reliability\nTest Standards & Economics\nTest Resource Partitioning\nTransient & Soft Errors\nFPGA Test\n\n\n\n\n\n  \n\n\n  \n\n\n\n\nNew Hot Topics\n\n  \n\nThis year\, VTS puts particular emphasis on enlarging its scope soliciting submissions on aspects on silent data corruption test\, reliability and security of AI\, fault models and reliability of in-memory computing hardware\, and quantum computing\, and functional safety.
URL:https://marketingeda.com/event/42nd-vlsi-test-symposium/
LOCATION:Memorial Union Conference Center\, 1151 S Forest Ave\, Tempe\, AZ\, United States
ATTACH;FMTTYPE=image/jpeg:https://marketingeda.com/wp-content/uploads/VLSI-Test-Symposium-2024.jpg
END:VEVENT
BEGIN:VEVENT
DTSTART;TZID=America/Los_Angeles:20240421T080000
DTEND;TZID=America/Los_Angeles:20240424T170000
DTSTAMP:20240419T164318Z
CREATED:20240419T164152Z
LAST-MODIFIED:20240419T164318Z
UID:7873-1713686400-1713978000@marketingeda.com
SUMMARY:CICC 2024
DESCRIPTION:The IEEE Custom Integrated Circuits Conference is a premier conference devoted to IC development. The conference program is a blend of oral presentations\, exhibits\, panels and forums. The conference sessions present original first published technical work and innovative circuit techniques that tackle practical problems. CICC is the conference to find out how to solve design problems\, improve circuit design techniques\, get exposure to new technology areas\, and network with peers\, authors and industry experts. \nThere are 3 days of Technical Sessions that include lecture presentations addressing state of the art developments in integrated circuit design. The Educational Sessions are a full day of tutorials instructed by recognized invited speakers. The Panels\, and Forums are presented throughout the conference to enrich the learning experience of the attendees. The Panel Discussions and Forums are presented by leaders from the IC industry. CICC includes an Exhibits Hall that is open in the evenings where Semiconductor manufacturers\, software tool suppliers\, silicon IP providers\, design-service houses\, and technical book publishers offer displays and demonstrations of their products. CICC is sponsored by the IEEE Solid-State Circuits Society and technically co-sponsored by the IEEE Electron Devices Society.
URL:https://marketingeda.com/event/cicc-2024/
LOCATION:DoubleTree by Hilton Denver\, 3203 Quebec Street\, Denver\, CO\, United States
CATEGORIES:Conference,EDA,Foundry,IP
ATTACH;FMTTYPE=image/jpeg:https://marketingeda.com/wp-content/uploads/CICC-2024.jpg
END:VEVENT
BEGIN:VEVENT
DTSTART;TZID=America/Los_Angeles:20240419T080000
DTEND;TZID=America/Los_Angeles:20240421T170000
DTSTAMP:20240408T222220Z
CREATED:20240212T205659Z
LAST-MODIFIED:20240408T222220Z
UID:7610-1713513600-1713718800@marketingeda.com
SUMMARY:Latch-Up 2024: Boston
DESCRIPTION:Friday to Sunday April 19–21\, 2024 in Boston\, MA\, USA \nThe Latch-Up conference is a weekend of presentations and networking dedicated to free and open source silicon. It’s an event for the open source digital design community\, much like its European sister conference ORConf\, run by the FOSSi Foundation. \n\n\n\n\n\nYou are all invited!\nThe FOSSi Foundation is proud to announce Latch-Up\, a conference dedicated to free and open source silicon to be held over the weekend of Friday April 19 to Sunday April 21 in Boston\, MA\, USA. \nLatch-Up is a weekend of presentations and networking for the open source digital design community\, much like its European sister conference ORConf. \nSo save the date\, register to attend\, and submit a presentation or proposal if you have a project or idea on the topic to share! \nQuestions? Ping the organizers via @LatchUpConf or send an email to latch-up@fossi-foundation.org. \n\n\n\nSubmit a talk\nWe encourage anybody involved in the open source semiconductor engineering space to come along and share your work or experience. Presentations slots as short as 3 minute lightning-talks and up to 30 minute talks including Q and A are available. \nSo if you’ve designed\, worked on or even just used open source IP cores and/or management systems\, verification IP\, build flows\, SoCs\, simulators\, synthesis tools\, FPGA and ASIC implementation tools\, languages and DSLs\, compilers\, or anything related we’d love to have you join us to share your experience. \nPresentations are submitted through the registration process and we will let you know if your presentation was accepted. \nTickets and registration\nAttendance of Latch-Up is free of charge. To help us organizing the event\, you are required to register on Eventbrite. Please register as soon as possible\, as we have to close registrations as soon as the room capacity is reached. \nAttendees who are joining us at Latch-Up on behalf of their company and/or can claim the conference as professional training expense are encouraged to purchase a professional ticket. These ticket sales help us provide all that we do at Latch-Up and keep the event accessible to all members of the community. Professional ticket holders are able to get their company name printed on their name badge and receive a special treat. \nWe ask all Latch-Up participants to adhere to the the FOSSi Foundation code of conduct throughout the event. \nFriday\n\n\n\nWhen\nWhat\n\n\n\n\n9:00\nWelcome\n\n\n9:20\nCaster: An Open-source E-Ink Controller\n\n\n9:40\nTeaching Modern EDA using a Tapeout-Centric University Course\n\n\n10:00\nBreak\n\n\n10:20\nCedarEDA for open source silicon\n\n\n10:40\nCohort: Software-Oriented Acceleration for You\, Me\, and Our Heterogeneous SoCs\n\n\n11:00\nTowards xBGAS on CHERI: Examining the Benefits of a Secure Distributed Architecture\n\n\n11:20\nLunch\n\n\n12:20\nTowards Cycle-accurate Simulation of xBGAS\n\n\n12:40\nArtifact Evaluation for the Field Programmable Gate Array Community\n\n\n13:00\nChisel 6 and beyond\n\n\n13:20\nMRPHS: Enabling Transaction-level Deductive Formal Verification Through PDVL\n\n\n13:40\nBreak\n\n\n14:40\nRiding The Wave: Building Wave Pipelines in FPGAs\n\n\n15:00\nGiving Students A Byte of Open-Source: Advancing Hardware Education\n\n\n15:20\nBreak\n\n\n15:40\nOpen-source resources for learning the Bluespec HL-HDLs\n\n\n16:00\nPyHDL-IF: An Easy-to-Use Python/HDL Cross-Calling Interface\n\n\n16:20\nTransition to Draper\n\n\n17:00\nTalks(30-40m) at Draper\n\n\n18:00\nTransition to lightning Talks\n\n\n19:00\nLightning Talks\n\n\n20:00\nGo home\n\n\n\nSaturday\n\n\n\nWhen\nWhat\n\n\n\n\n8:40\nWelcome\n\n\n9:00\nOpen source RTL verification with Verilator\n\n\n9:20\nSonata: A development platform to enable exploring the use of CHERI for embedded applications\n\n\n9:40\nTransparent Checkpointing for Fault Tolerance in RISC-V\n\n\n10:00\nBreak\n\n\n10:20\nHDLAgent\, Enhancing Hardware Language in the age of LLMs\n\n\n10:40\nSpade: An HDL Inspired By Modern Software Languages\n\n\n11:00\nSwitchboard: Calling All Hardware Models\n\n\n11:20\nLunch\n\n\n12:20\nFrom an Open-Source ISA to Open-Source HW to Open-Source Silicon\n\n\n12:40\nOpen Source Hardware: Hacking Silicon for Fun (instead of profit)\n\n\n13:00\nA History of TL-Verilog Google Summer of Code Projects under FOSSi Foundation\n\n\n13:20\nUMI: Universal Memory Interface\n\n\n13:40\nBreak\n\n\n14:20\nABC: The Way It Should Have Been Designed\n\n\n14:40\nBYOL (Build Your Own Linter) – UVMLint for IEEE-UVM core code development\n\n\n15:00\nBeyond EDA lies Edalize\n\n\n15:20\nBreak\n\n\n15:40\nRF Front-end receiver design for 2.4GH/5GHz WiFi application\n\n\n16:00\nCACE Study: Open source analog and mixed-signal design flow\n\n\n16:20\nIHP Open Source PDK: Announcement\, Setup\, Current State and Experiences\, and look ahead\n\n\n16:40\nTiny Tapeout: custom silicon open to all\n\n\n17:20\nMeet at Flattops\n\n\n\nSunday\nComing soon
URL:https://marketingeda.com/event/latch-up-2024-boston/
LOCATION:Massachusetts Institute of Technology\, 77 Massachusetts Avenue\, Boston\, MA\, United States
CATEGORIES:Conference,EDA,IP
ATTACH;FMTTYPE=image/jpeg:https://marketingeda.com/wp-content/uploads/Latch-Up-2024.jpg
END:VEVENT
BEGIN:VEVENT
DTSTART;TZID=Asia/Tokyo:20240418T150000
DTEND;TZID=Asia/Tokyo:20240418T160000
DTSTAMP:20240415T174855Z
CREATED:20240415T174855Z
LAST-MODIFIED:20240415T174855Z
UID:7844-1713452400-1713456000@marketingeda.com
SUMMARY:Optimizing Chiplet architectures of RISC-V clusters\, GPU and DNN using System-Level IP
DESCRIPTION:Multi-die SoC containing multiple RISC-V clusters\, GPU\, NPU\, accelerators and DNN have considerable benefits for applications in automotive\, space and industrial. Architecture exploration of the chiplet-based SoC requires multiple interconnect protocol models\, and multiple coherent and non-coherent compute resources. This Webinar will demonstrate a methodology for rapid modeling and architecture trade-off using UCIe in modeling and simulating a multi-die SoC in a matter of weeks. These models can be used for UCIe setup\, task partitioning\, distribution of compute resources across dies\, sharing coherency between RISC-V clusters\, GPU and AI Engines. We will show how workloads and application task graphs can be used to optimize the settings to meet the requirements\, identify system bottlenecks and optimize for PPA. Results from actual hardware designs with different configurations and allocations will be discussed during the session.
URL:https://marketingeda.com/event/optimizing-chiplet-architectures-of-risc-v-clusters-gpu-and-dnn-using-system-level-ip/
LOCATION:OR
CATEGORIES:EDA,IP,Webinar
ATTACH;FMTTYPE=image/jpeg:https://marketingeda.com/wp-content/uploads/Mirabilis-18-April-2024.jpg
END:VEVENT
BEGIN:VEVENT
DTSTART;TZID=America/Los_Angeles:20240418T100000
DTEND;TZID=America/Los_Angeles:20240418T110000
DTSTAMP:20240415T175505Z
CREATED:20240415T175505Z
LAST-MODIFIED:20240415T175505Z
UID:7847-1713434400-1713438000@marketingeda.com
SUMMARY:Optimizing Chiplet architectures of RISC-V clusters\, GPU and DNN using System-Level IP
DESCRIPTION:Multi-die SoC containing multiple RISC-V clusters\, GPU\, NPU\, accelerators and DNN have considerable benefits for applications in automotive\, space and industrial. Architecture exploration of the chiplet-based SoC requires multiple interconnect protocol models\, and multiple coherent and non-coherent compute resources. This Webinar will demonstrate a methodology for rapid modeling and architecture trade-off using UCIe in modeling and simulating a multi-die SoC in a matter of weeks. These models can be used for UCIe setup\, task partitioning\, distribution of compute resources across dies\, sharing coherency between RISC-V clusters\, GPU and AI Engines. We will show how workloads and application task graphs can be used to optimize the settings to meet the requirements\, identify system bottlenecks and optimize for PPA. Results from actual hardware designs with different configurations and allocations will be discussed during the session.
URL:https://marketingeda.com/event/optimizing-chiplet-architectures-of-risc-v-clusters-gpu-and-dnn-using-system-level-ip-2/
LOCATION:OR
CATEGORIES:EDA,IP,Webinar
ATTACH;FMTTYPE=image/jpeg:https://marketingeda.com/wp-content/uploads/Mirabilis-April-18-2024.jpg
END:VEVENT
BEGIN:VEVENT
DTSTART;TZID=America/Los_Angeles:20240417T090000
DTEND;TZID=America/Los_Angeles:20240417T103000
DTSTAMP:20240415T184123Z
CREATED:20240415T184123Z
LAST-MODIFIED:20240415T184123Z
UID:7855-1713344400-1713349800@marketingeda.com
SUMMARY:Introduction to ParagonX
DESCRIPTION:Are you ready to supercharge your design process? Introducing our Diakopto Training Program – your gateway to a faster\, easier\, and more intuitive approach to design analysis and optimization! \nIn this course\, you’ll learn how to:\n Analyze and visualize layout parasitics with precision using R/C/delay/I maps.\n Perform net matching for accurate and refined designs.\n Identify the root cause of bottlenecks in post-layout simulation results with ease.\n Iterate over layout improvements efficiently before running post-layout simulations using the powerful Diakopto – ParagonX tool. \nCourse Details:-\nDate: Wednesday\, April 17th \, 2024\nTime: 9:00 am to 10:30 am Pacific Time (PDT)\nInstructor: Maxim Ershov\, Senior Director R&D\, USA \nRegister here:- https://ansys.me/3x6p95i\nDon’t miss this opportunity to revolutionize your design workflow and unlock new levels of efficiency and precision. Sign up for the Diakopto ParagonX Training today!
URL:https://marketingeda.com/event/introduction-to-paragonx/
LOCATION:OR
CATEGORIES:EDA,Webinar
ATTACH;FMTTYPE=image/jpeg:https://marketingeda.com/wp-content/uploads/Ansys-April-17-2024.jpg
END:VEVENT
BEGIN:VEVENT
DTSTART;TZID=America/Los_Angeles:20240417T081500
DTEND;TZID=America/Los_Angeles:20240417T170000
DTSTAMP:20240306T181435Z
CREATED:20240306T181435Z
LAST-MODIFIED:20240306T181435Z
UID:7716-1713341700-1713373200@marketingeda.com
SUMMARY:CadenceLIVE Silicon Valley 2024
DESCRIPTION:Join us for CadenceLIVE Silicon Valley 2024 on April 17 at the Santa Clara Convention Center. This annual user conference features peer presentations that offer solutions for today’s design challenges that will impact tomorrow’s products. \nCadenceLIVE brings users\, developers\, and industry experts together to connect\, share ideas\, and inspire design creativity. Attendees have the opportunity to view captivating keynotes\, attend engaging user presentations\, and interact with Cadence experts\, peers\, and our sponsors in the Designer Expo. \nRegister today to secure your spot. \n\n\nApril 17\, 2024 08:15\n\nRegistration\n\n\n\n\n\n\nApril 17\, 2024 09:00\n\nSession Tracks\n\n\n\n\n\n\nApril 17\, 2024 10:15\n\nKeynotes\n\n\n\n\n\n\nApril 17\, 2024 11:45\n\nDesigner Expo and Lunch\n\n\n\n\n\n\nApril 17\, 2024 13:15\n\nSession Tracks\n\n\n\n\n\n\nApril 17\, 2024 15:45\n\nClosing Keynote\n\n\n\n\n\n\nApril 17\, 2024 16:30\n\nDesigner Expo / Reception / Awards
URL:https://marketingeda.com/event/cadencelive-silicon-valley-2024/
LOCATION:Santa Clara Convention Center\, 5001 Great America Parkway\, Santa Clara\, CA\, 95054\, United States
CATEGORIES:EDA,IP,User Group
ATTACH;FMTTYPE=image/jpeg:https://marketingeda.com/wp-content/uploads/Cadence-April-17-2024.jpg
END:VEVENT
BEGIN:VEVENT
DTSTART;TZID=America/Los_Angeles:20240417T080000
DTEND;TZID=America/Los_Angeles:20240417T090000
DTSTAMP:20240327T173831Z
CREATED:20240327T173831Z
LAST-MODIFIED:20240327T173831Z
UID:7774-1713340800-1713344400@marketingeda.com
SUMMARY:Exploring the Advancement of Chiplet Technology and the Ecosystem
DESCRIPTION:Semiconductor companies are making transistors smaller and cramming more into chips to meet the demands of today’s high-tech industries and applications. In fact\, in a recent article from the Financial Times\, technology industry consultants McKinsey forecast that semiconductors will become a trillion-dollar industry by the end of this decade. Even with this massive growth\, manufacturers recognize the need to balance costs with chip performance and are working to solve this challenge by shifting toward chiplet manufacturing – creating smaller\, modular chiplets\, designed for a specific function\, that can be connected to build a larger system. Chiplets enable design flexibility for end-users seeking to match chip designs based on requirements. \n​ \nUCIe™ (Universal Chiplet Interconnect Express™) provides an industry standard for interface and is driving the adoption of chiplet technology. The open specification defines the interconnect between chiplets within a package\, enabling an open chiplet ecosystem and ubiquitous interconnect at the package level. \nThis webinar aims to explore the industry trends that prompted the development of chiplet technology and how an interoperable solution meets industry demand. Our panelists will also discuss how UCIe fosters collaboration in the industry toward the future of chiplet innovation in markets such as AI\, ML\, aerospace\, and automotive.
URL:https://marketingeda.com/event/exploring-the-advancement-of-chiplet-technology-and-the-ecosystem/
LOCATION:OR
CATEGORIES:IP,Webinar
ATTACH;FMTTYPE=image/jpeg:https://marketingeda.com/wp-content/uploads/UCIe-April-17-2024.jpeg
END:VEVENT
BEGIN:VEVENT
DTSTART;TZID=America/Los_Angeles:20240416T100000
DTEND;TZID=America/Los_Angeles:20240416T110000
DTSTAMP:20240411T185913Z
CREATED:20240411T185913Z
LAST-MODIFIED:20240411T185913Z
UID:7841-1713261600-1713265200@marketingeda.com
SUMMARY:Streamline MMIC Design  Efficiency with Intelligent  Design Data Management
DESCRIPTION:In the fast-evolving world of monolithic microwave integrated circuit (MMIC) design\, meeting higher-frequency requirements is just the beginning. Are you seeking insights on achieving dimensional accuracy for both analog and RF components? Wondering about the automatic synchronization of schematics and layouts across various electronic design automation (EDA) tools? \nTrusted by hundreds of IC design organizations worldwide\, Keysight Design Data Management (SOS) transforms design data chaos into intelligence. Attend to experience a live demonstration showcasing the synergy of Cadence Virtuoso Studio\, Keysight ADS\, and Keysight SOS in action. \nJoin our upcoming webinar for practical insights from Keysight design experts Karim Khalfan and Nupur Bhonge. Learn how to: \n\nSecure and simplify data transfer and design collaboration across the enterprise.\nReduce network storage with smart caching.\nFacilitate efficient co-simulation across Cadence Virtuoso Studio and Keysight ADS with real-time analytics.\nEliminate versioning issues with comprehensive virtualization.\n\n  \nRegister now to streamline your design data management and expedite your MMIC design cycles.  \n\nHandouts\nRequest a personalized demo View/Download\nApply for a free trial View/Download\nBrochure – Keysight Design Data Management SOS View/Download\neBook – Essential IP-Based Design Strategies for Chiplet Success View/Download\n\n\nPresenters\n\nKarim Khalfan\nDirector Solutions Engineering\, Data and IP Management\, at Keysight Technologies.\nKarim leads solutions engineering for data and IP management for Keysight EDA. Before joining Keysight in May 2023 through the acquisition of Cliosoft Inc.\, Karim was Vice President of Applications Engineering managing the Application Engineering group and the office of customer advocacy for the previous 18 years. He has led various efforts to ensure the broad deployment of Keysight design data and IP management across the semiconductor industry. Karim has received his Bachelor of Science degree in Computer Science from the University of Texas. He has authored several articles and white papers on the importance and need of SoC design management solutions. He also has a patent on defining a universal data management adapter to be used for integration with any EDA tool.\n\n\n\nNupur Bhonge\nSenior Solutions Engineer at Keysight Technologies\nNupur works with IC design teams on Keysight Design Data Management (SOS) and IP design (HUB) management platforms. She specializes in deploying EDA workloads to the cloud and new product integrations with SOS and HUB. With a Master’s Degree in Computer Engineering from Syracuse University\, she brings in-depth knowledge and experience with EDA tools and workflows to her work.
URL:https://marketingeda.com/event/streamline-mmic-design-efficiency-with-intelligent-design-data-management/
LOCATION:OR
CATEGORIES:EDA,Webinar
ATTACH;FMTTYPE=image/jpeg:https://marketingeda.com/wp-content/uploads/Keysight-April-16-2024.jpg
END:VEVENT
BEGIN:VEVENT
DTSTART;TZID=Europe/Brussels:20240416T080000
DTEND;TZID=Europe/Brussels:20240417T170000
DTSTAMP:20240410T165555Z
CREATED:20240410T165555Z
LAST-MODIFIED:20240410T165555Z
UID:7826-1713254400-1713373200@marketingeda.com
SUMMARY:CS Inernational Conference
DESCRIPTION:he 14th CS International builds on the strengths of its predecessors\, with around 40 leaders from industry and academia delivering presentations that fall within five key themes: Ensuring SiC’s Phenomenal Success; Expanding Horizons for Surface Emitters; Accelerating the Growth of GaN; Taking Power from the Photon; and New Frontiers for the LED. \nThose attending these sessions will be rewarded with greater insight into device technologies while learning of the latest opportunities and trends within the compound semiconductor industry. Delegates will also discover significant advances in tools and processes that enable enhanced yield and throughput. \nAttendees at this two-day conference will also meet a wide variety of key players within the community\, from investors and analysts to fab engineers and managers. \nCS International is part of AngelTech\, which delivers a portfolio of insightful\, informative\, highly valued chip-level conferences. Bringing together 3 conferences with more than 120 presentations\, more than 800 delegates and over 80 exhibitors\, AngelTech is the premier global event covering compound semiconductor\, photonic integrated circuit and power electronic technologies. With a significant overlap between the three conferences\, attendees and exhibitors are exposed to the full relevant supply chains and customer and supplier bases.
URL:https://marketingeda.com/event/cs-inernational-conference/
LOCATION:Sheraton Brussels Airport Hotel\, Brussels\, Belgium
CATEGORIES:Conference,EDA,Semiconductor
ATTACH;FMTTYPE=image/jpeg:https://marketingeda.com/wp-content/uploads/CS-2024.jpg
END:VEVENT
BEGIN:VEVENT
DTSTART;TZID=Indian/Christmas:20240416T080000
DTEND;TZID=Indian/Christmas:20240416T170000
DTSTAMP:20240301T172523Z
CREATED:20240301T172523Z
LAST-MODIFIED:20240301T172523Z
UID:7699-1713254400-1713286800@marketingeda.com
SUMMARY:DVClub India - Ensuring my Design Verification is ISO26262 Compliant
DESCRIPTION:TBD
URL:https://marketingeda.com/event/dvclub-india-ensuring-my-design-verification-is-iso26262-compliant/
LOCATION:Cadence\, Bengaluru\, Sarjapur Outer Ring Road\, Bengaluru\, 560103\, India
CATEGORIES:EDA
ATTACH;FMTTYPE=image/jpeg:https://marketingeda.com/wp-content/uploads/DVClub-India-April-16-2024.jpg
END:VEVENT
BEGIN:VEVENT
DTSTART;TZID=America/Los_Angeles:20240416T080000
DTEND;TZID=America/Los_Angeles:20240416T090000
DTSTAMP:20240326T180707Z
CREATED:20240326T180707Z
LAST-MODIFIED:20240326T180707Z
UID:7763-1713254400-1713258000@marketingeda.com
SUMMARY:Win The Tick to Trade Race by Root Causing Bugs Faster with the Latest Innovations In QuestaSim
DESCRIPTION:Root causing RTL design or simulation testbench bugs can be tedious process\, especially if just relying on traditional waveform viewing and debug. Also\, it can be costly if more sophisticated debug ties up precious simulation resources during the debug process.\n‌\nLearn how the latest innovations in QuestaSim address these challenges by enabling full off-line debugging freeing up simulation licenses for more simulations runs per day. Also\, learn how unique debugging features like driver tracing\, biometric search\, temporal causality trace back\, and much more will enable you root cause bugs more straight forward and faster. All the while delivering industry-leading performance and capacity through aggressive\, global compile and simulation optimization algorithms for SystemVerilog\, VHDL\, and SystemC. \nWhat you will learn: \nIn this Web Seminar\, we will highlight the key innovations in QuestaSim that enable full debug visibility with significant reduction in simulation performance overhead and waveform database size. For existing QuestaSim users\, we will show the simple change to scripts to see a 2X performance boost and 3X reduction in waveform database.\n‌\nWe will highlight the debug features in our Visualizer debugger now included as part of every QuestaSim license\, such as:\n‌ \n\nDriver/receiver tracing from wave and source code\n‘x’ tracing through sequential logic and time\nFSM debug & cross probing\nSchematics exploration with smart hierarchical flattening and pruning.\nWaveforms with cross probing & biometric search\nDesign search by type\n\n‌\nWe will step through some design and testbench examples showing how these features can speed up root causing bugs and tackle complex logic that may be impossible for humans to figure out.\n‌ \nWho should attend: \nUltra Low Latency FPGA Designers in the High Frequency Trade industry \n\n\nWhat/Which Products are Covered:   \n\nQuestaSim with Visualizer Debugger\n\n\n\nSpeaker:\n\n\n\n\n\n\nRich Edelman\nProduct Engineer\, Siemens EDA\n\n\n\n\nRich Edelman is a Product Engineer at Siemens EDA and is responsible for the Visualizer Debug Environment. He holds a Bachelor of Science Degree in Electrical Engineering\, a Bachelor of Science Degree in Computer Science\, and a Master of Science Degree in Computer Science from Washington University in St. Louis. Prior to Siemens EDA\, Rich worked for a C Synthesis company\, a compute farm company\, Design Acceleration\, and a couple of ASIC houses. Rich’s best days are in Yosemite backpacking – or at least dreaming about it.
URL:https://marketingeda.com/event/win-the-tick-to-trade-race-by-root-causing-bugs-faster-with-the-latest-innovations-in-questasim/
LOCATION:OR
CATEGORIES:EDA,Webinar
ATTACH;FMTTYPE=image/jpeg:https://marketingeda.com/wp-content/uploads/Siemens-April-16-2024.jpg
END:VEVENT
BEGIN:VEVENT
DTSTART;TZID=America/Los_Angeles:20240415T130000
DTEND;TZID=America/Los_Angeles:20240415T174500
DTSTAMP:20240403T192855Z
CREATED:20240403T192855Z
LAST-MODIFIED:20240403T192855Z
UID:7807-1713186000-1713203100@marketingeda.com
SUMMARY:Open Source Summit - North America
DESCRIPTION:Registration Cost: $15 \nThis half day program will Introduce the audience to the many aspects of open source hardware and software development\, and how it is helping the industry to accelerate beyond what Moore’s law has predicted. \nTalks will cover numerous aspects of hardware / software development and provide motivation to learn more about the challenges of open hardware and software design together. \nAGENDA\n \n\nHow can software developers help keep Moore’s law alive? – Michael Gielda\, Antmicro\nOpen Hardware Design: Lessons Learned from OSS – Stefano Cetola\, Intel\nUnderstanding hardware security vulnerabilities: Hardware Bill of Materials – Kate Stewart\, Linux Foundation\nScaling hardware design: squeezing every bit of performance of the open source OpenROAD ASIC toolchain – Karol Gugala\, Antmicro\nAccelerating EDA Flows in the AWS Cloud – David Pellerin\, AWS\nAn Introduction to RISC-V – Keith Graham\, Codasip\nAccelerating the RISC-V Software Development Ecosystem – Jeffrey Osier-Mixon\, Red Hat\nCaliptra: Open Source Root of Trust – Caleb Whitehead\, Microsoft\nGetting “Ware” You Need to Go – Managing Open Hardware with Software (Part 1) – Maximillian Schmidt\, University of Oregon\nGetting “Ware” You Need to Go – AI Software on Open Hardware (Part 2) – Christopher Sullivan\, University of Oregon
URL:https://marketingeda.com/event/open-source-summit-north-america/
LOCATION:Seattle Convention Center\, 900 Pine Street\, Seattle\, WA\, United States
CATEGORIES:Conference,EDA
ATTACH;FMTTYPE=image/jpeg:https://marketingeda.com/wp-content/uploads/Open-Source-Summit-North-America-2024.jpg
END:VEVENT
BEGIN:VEVENT
DTSTART;TZID=America/Los_Angeles:20240411T110000
DTEND;TZID=America/Los_Angeles:20240411T120000
DTSTAMP:20240408T161908Z
CREATED:20240408T161857Z
LAST-MODIFIED:20240408T161908Z
UID:7813-1712833200-1712836800@marketingeda.com
SUMMARY:Making a Structured VHDL Testbench – A Demo for Beginners
DESCRIPTION:Abstract: \nThis demonstrated tutorial is intended for designers and verification engineers who want to learn to make better and more structured testbenches. \nThis session will show you what is needed for any good testbench\, irrespective of its complexity.\nWe will make a testbench from scratch for a simple VHDL module and do the following:\n\nAdd a balanced and controllable clock generator\nAdd logging of progress in a simple way\nCheck default values and reset\nAccess module via an interface – using BFMs (Bus Functional models)\nCheck output signals with and without a positive acknowledge\nWait for flag or interrupt or a given value – with a timeout\nCheck that signals have been stable – without pulses or spikes for a given time\nReport an alert summary\n… and more\n\n…all  using well-documented VHDL procedures and functions from UVVM\, the open source fastest growing VHDL verification methodology.\nThe presented solution will use UVVM Utility Library and BFMs\, but the principles and mechanisms are 100% general verification methodology; i.e.\, independent of library and available functionality.\nAlthough this testbench is applied on a very simple design under test (DUT)\, the same principles also apply to advanced testbenches for complex DUTs. (But the advanced testbenches need more on top.)\nAgenda\n\nQuality and Efficiency Enablers\nThe simple DUT and simple TB architecture\nUVVM: Concepts\, Download and Compile\nMaking the testbench – prior to test cases\nAdding clock generator and starting logging and checking\nBFMs: Explained\, Usage\, Making simple overloads\nAlert handling\, Verbosity control and Timeouts\nConclusion\nQ&A\n\nWebinar Duration\n\n45 min presentation/live demo\n15 min Q&A\n\nPresenter \n \nBio: \nEspen is also the author and architect of UVVM and founder of previous Bitvis. He has a strong interest for methodology cultivation and pragmatic efficiency and quality improvement\, and he has given many presentations on various international conferences with great feedback. He has also given courses on FPGA Design and Verification world-wide.
URL:https://marketingeda.com/event/making-a-structured-vhdl-testbench-a-demo-for-beginners/
LOCATION:OR
CATEGORIES:EDA,Webinar
ATTACH;FMTTYPE=image/jpeg:https://marketingeda.com/wp-content/uploads/Aldec-April-11-2024.jpg
END:VEVENT
BEGIN:VEVENT
DTSTART;TZID=America/Los_Angeles:20240411T100000
DTEND;TZID=America/Los_Angeles:20240411T110000
DTSTAMP:20240314T180820Z
CREATED:20240314T180820Z
LAST-MODIFIED:20240314T180820Z
UID:7736-1712829600-1712833200@marketingeda.com
SUMMARY:Cadence Managed Cloud for Cost Efficient and Productive Chip Design
DESCRIPTION:Join us for an informative webinar\, as we unveil the capabilities of our cloud solutions designed to revolutionize EDA workloads. Whether you require completely hosted environments or need peak/burst capacity\, our cloud solutions offer unparalleled flexibility and efficiency. \nWe will discuss how Cadence Managed Cloud can optimize cost-efficiency and productivity for your chip design projects. Learn how to harness the full potential of cloud technology to streamline your EDA workflows and achieve remarkable results. \nDon’t miss our live demonstration of Cadence Managed Cloud\, where we’ll showcase its robust productivity and security features. Plus\, discover how you can kickstart your journey with a 30-day free trial. \nWho should attend:\nChip designers\, Cloud IT Architects\, CAD Platform team\, and business decision makers. \nPresenters: \nKushal Koolwal\, Business Development Director\, Cadence \nMike Stranton\, IT Group Director\, Cadence
URL:https://marketingeda.com/event/cadence-managed-cloud-for-cost-efficient-and-productive-chip-design/
LOCATION:OR
CATEGORIES:EDA,Webinar
ATTACH;FMTTYPE=image/jpeg:https://marketingeda.com/wp-content/uploads/Cadence-April-11-2024.jpg
END:VEVENT
BEGIN:VEVENT
DTSTART;TZID=Europe/Paris:20240411T080000
DTEND;TZID=Europe/Paris:20240411T170000
DTSTAMP:20240322T164706Z
CREATED:20240322T164706Z
LAST-MODIFIED:20240322T164706Z
UID:7750-1712822400-1712854800@marketingeda.com
SUMMARY:Siemens EDA - TechDay Grenoble 2024
DESCRIPTION:Siemens EDA Technology Day in Grenoble is your opportunity to learn\, grow and connect with fellow technical experts who design leading-edge products using Siemens EDA tools. This event is dedicated to end users of Siemens EDA solutions. This conference is free to attend and includes keynotes from industry leaders and enriching technical sessions. \n  \n\nAnalog/Mixed-Signal Verification\nCalibre Design Solutions\nDigital IC Implementation\nFunctional Design & Verification\nHardware-Assisted Verification\nNext Gen Packaging and DFM\nPCB Design & Simulation\nTessent Test Solutions and Embedded Analytics
URL:https://marketingeda.com/event/siemens-eda-techday-grenoble-2024/
LOCATION:OR
CATEGORIES:Conference,EDA
ATTACH;FMTTYPE=image/jpeg:https://marketingeda.com/wp-content/uploads/Siemens-April-11-2024.jpg
END:VEVENT
BEGIN:VEVENT
DTSTART;TZID=America/Los_Angeles:20240410T100000
DTEND;TZID=America/Los_Angeles:20240410T110000
DTSTAMP:20240221T221535Z
CREATED:20240221T221535Z
LAST-MODIFIED:20240221T221535Z
UID:7677-1712743200-1712746800@marketingeda.com
SUMMARY:Virtuoso - Finding Hidden Treasures to Accelerate Routing Your Layout
DESCRIPTION:Every layout designer frets over routing all the interconnects DRC clean and correct as per the circuit designer’s expectations. On the one hand\, you want a magic wand that just hooks up all the connections with perfect smartness. On the other hand\, you need to guide the connections carefully while weaving your own creative magic – too tough to tell the auto-router the exact constraints. With the assisted routing features in your familiar layout editor in Virtuoso Studio\, you have the Swiss army knife to finish your routing tasks more than 10X faster. Finish more work in the same amount of time or regain your work-life balance with the assisted routing functionality. \nThis webinar takes you on a treasure hunt to find the hidden gems – some you already had but didn’t know\, and some that are part of Virtuoso Studio. Strap your seat belts and learn about: \n\nHow simulation-driven routing goes a step ahead than the create-verify-fix paradigm\nReplicate complicated yet similar bus structures with more than just a simple shape copy\n Fast interactive routing with auto twigs feature\nOptimal routing widths in advanced node with WSP compliance\, wire stranding and wire stacking\nAuto Via Assistant\n\nWebinar #1: March 12\nAccelerate Layout Creation with Automated Place and Route in Virtuoso Studio \nWebinar #2: March 19\nSaving on Signoff Effort with iPegasus Verification System for Virtuoso Studio – In-Design DRC and Fill \nWebinar #3: April 4\nMaximizing the Benefits of Virtuoso Layout Suite XL \nWebinar #4: April 10\nFinding Hidden Treasures to Accelerate Routing Your Layout
URL:https://marketingeda.com/event/virtuoso-finding-hidden-treasures-to-accelerate-routing-your-layout/
LOCATION:OR
CATEGORIES:EDA,Webinar
ATTACH;FMTTYPE=image/jpeg:https://marketingeda.com/wp-content/uploads/Cadence-March-2024.jpg
END:VEVENT
BEGIN:VEVENT
DTSTART;TZID=Europe/Berlin:20240409T080000
DTEND;TZID=Europe/Berlin:20240411T170000
DTSTAMP:20240403T194345Z
CREATED:20240119T022657Z
LAST-MODIFIED:20240403T194345Z
UID:7529-1712649600-1712854800@marketingeda.com
SUMMARY:Embedded World 2024
DESCRIPTION:The embedded world Exhibition&Conference provides a global platform and a place to meet for the entire embedded community\, including leading experts\, key players and industry associations. It offers unprecedented insight into the world of embedded systems\, from components and modules to operating systems\, hardware and software design\, M2M communication\, services\, and various issues related to complex system design. \nIts expertise and sharp focus on technologies\, processes and future-oriented products make it unparalleled in international comparisons – and THE must-attend event for developers\, system architects\, product managers and technical management. \nKnowledge platform #ew24\nKnow-how at the highest level\nAt the embedded world Conference and the electronic displays Conference\, top-class speakers from research\, development and practice will share their knowledge with you. They discuss the state of the art and possible future developments in the industry. The exhibitor’s forums and top-class discussion panels in the halls also contribute to the high-quality transfer of knowledge. Current topics will be highlighted in numerous expert lectures and panels. And\, of course\, there will be opportunities for intensive technical discussions. \nGuided tours\, tours for trainees and students and special presentations as well as the networking event for women in the embedded systems industry #women4ew complete the offer. \nThe No. 1 hub for the international embedded community\n\nAs the global platform and the industry place to meet for the embedded community\, embedded world attracts the top experts\, key players and industry associations from all over the world. \nBecome part of the community and use THE industry platform to network and make valuable business contacts!
URL:https://marketingeda.com/event/embedded-world-2024/
LOCATION:NürnbergMesse\, Messezentrum 1\, Nurnberg\, Germany
CATEGORIES:Conference,EDA,IP
ATTACH;FMTTYPE=image/jpeg:https://marketingeda.com/wp-content/uploads/Embedded-World-2024.jpg
END:VEVENT
BEGIN:VEVENT
DTSTART;TZID=America/Los_Angeles:20240409T080000
DTEND;TZID=America/Los_Angeles:20240409T170000
DTSTAMP:20240401T175124Z
CREATED:20240401T175124Z
LAST-MODIFIED:20240401T175124Z
UID:7794-1712649600-1712682000@marketingeda.com
SUMMARY:Ansys 2024 R1: High Frequency Electronics What’s New
DESCRIPTION:Learn about the latest improvements and new features to the high frequency electronics simulation tools. There are many enhancements for engineers involved in RF\, automotive\, A&D\, and consumer electronics designs that our subject matter experts will discuss. \n\n\nOverview\nThis Ansys 2024 R1 webinar will review the high-frequency electronics tool updates\, enhancements\, and new features – HFSS\, Q3D\, SIwave\, and NuHertz. Engineers developing PCBs\, antennas\, and other RF capabilities for telecommunications\, HPC\, automotive\, A&D\, and IoT applications will find many new capabilities and improvements in this update. \nWhat you will learn\n\nEncrypted technology file support in HFSS 3D Layout IC Mode\nEnhanced support for FlexPCB in HFSS 3D\nHFSS Finite Array metadata export and mask automation\nIcepak Thermal Mesh Fusion\nSolver enhancements for SIwave and Q3D\nImprovements to HPC/Distributed Computing support for all products\n\nWho should attend and why\nEngineers involved in new product development for any electronics market \nSpeaker\n\nJuliano Mologni\n\n\n\n\n\nJuliano Mologni is a Lead Product Manager in the Electronics Business Unit at Ansys\, responsible for all HF electronics products. He has over 20 years of experience in computational electromagnetics and is the author of multiple patents and more than 60 journal and conference papers. Juliano is involved in many RF and EMC projects with top automotive\, A&D\, appliances\, and high tech companies. He holds a BSc degree in telecommunication engineering and an MSc in microelectronics and has authored a PhD thesis on automotive EMC and signal integrity.
URL:https://marketingeda.com/event/ansys-2024-r1-high-frequency-electronics-whats-new/
LOCATION:OR
CATEGORIES:EDA,Webinar
ATTACH;FMTTYPE=image/jpeg:https://marketingeda.com/wp-content/uploads/Ansys-April-9-2024.jpg
END:VEVENT
BEGIN:VEVENT
DTSTART;TZID=America/Los_Angeles:20240409T080000
DTEND;TZID=America/Los_Angeles:20240409T090000
DTSTAMP:20240402T170530Z
CREATED:20240402T170530Z
LAST-MODIFIED:20240402T170530Z
UID:7803-1712649600-1712653200@marketingeda.com
SUMMARY:Guiding your aerospace electrical journey
DESCRIPTION:Aerospace electrical/electronic (EE) design requires a delicate balance between innovative technology and uncompromising reliability. Meanwhile\, the pressure to get products to market faster is growing exponentially. Finding ways to design electrical systems quickly\, cost-effectively and efficiently has become a central focus of manufacturers. \nSiemens has the solutions and partnerships to guide the development of best-in-class solutions to these problems. This session will highlight how Capital plays a part in these solutions. \nMeet the speaker\n\n\n\n\n\n\nSIEMENS IES\nChad Holley\nTechnical Product Manager \n\nChad Holley is a Technical Product Manager in IES supporting our Connectivity offerings. He has been working for Siemens for over 8 years and has supported many customers in their Capital deployments. Prior to Siemens\, Chad has held varying positions in wiring and systems design in both the automotive and aerospace and defense industries. Chad is a veteran of the United States Navy as an electrician and holds a bachelor’s degree in Electrical Engineering from Michigan State University.
URL:https://marketingeda.com/event/guiding-your-aerospace-electrical-journey/
LOCATION:OR
CATEGORIES:EDA,Webinar
ATTACH;FMTTYPE=image/jpeg:https://marketingeda.com/wp-content/uploads/Siemens-April-9-2024.jpg
END:VEVENT
BEGIN:VEVENT
DTSTART;TZID=America/Los_Angeles:20240404T110000
DTEND;TZID=America/Los_Angeles:20240404T120000
DTSTAMP:20240311T212213Z
CREATED:20240311T212000Z
LAST-MODIFIED:20240311T212213Z
UID:7730-1712228400-1712232000@marketingeda.com
SUMMARY:High-Performance RTL Simulation Workflow with Libero and Active-HDL
DESCRIPTION:Based on recent industry research\, the FPGA market was valued at approximately USD 7.5 Billion in 2023\, with an expected compound annual growth rate (CAGR) of around 10% by 2032. More and more engineers will be adopting FPGAs due to their versatility\, acceleration capability\, power efficiency and lower non-recurring engineering (NRE) costs (compared to ASICs). Major FPGA vendors like AMD\, Altera and Microchip are continuously innovating their technologies\, architectures\, and IPs – and consequently enhancing their respective design capabilities and workflows. For example\, Vivado\, Quartus and Libero all provide useful design and RTL simulation features. Aldec collaborates closely with the FPGA vendors as partners to ensure seamless simulation of all their IPs and libraries using Aldec’s simulation tool\, Active-HDL. \nIn terms of verification\, FPGA designs undergo testing directly in the lab or through simulations\, depending on factors such as design size\, complexity\, and project objectives. While some FPGA designs may find adequate simulation support from the FPGA vendor tools\, many require higher simulation performance and a more comprehensive language support\, particularly those with larger designs with complex logic and deep hierarchies. \nSimulation stands as the primary verification method for FPGA designs\, essential for minimizing non-trivial bugs escaping into production. The ability to run more simulation enables the verification of a wider range of test scenarios\, thus elevating verification quality. Aldec’s Active-HDL offers a faster compilation/simulation engine\, robust debugging features and comprehensive language support for the latest versions of VHDL\, SystemVerilog\, and SystemC. \nIn this three-part webinar series\, we will show how to turbocharge FPGA simulation workflows by using Active-HDL as the default simulator within AMD® Vivado\, Altera® Quartus and Microchip® Libero SoC. \n  \nAbstract: \nIn the concluding part of this three-part webinar series\, we will show how to simulate a Microchip design example. We will generate a design example from Libero SoC and simulate it using Active-HDL as the default simulator. We will discuss various tips that you can use to optimize compilation and simulation run times. The tips will be categorized from zero-cost effort to high-cost effort and\, depending on your budget/resource constraints\, you will have a path to speed up your simulation by a huge factor. We will turn on Profiler so that you can determine the bottlenecks in your design/testbench and we will perform debugging using Breakpoints\, Xtrace\, Drivers/Readers and Advanced Dataflow. \nAgenda\n\nWorkflow with Libero SoC and Active-HDL\nTips on how to optimize simulation performance\nPerformance bottleneck analysis with Design Profiler\nBreakpoints\, Xtrace and Advanced Dataflow\, Drivers and Readers\nLive Demo\nQ&A\n\nWebinar Duration\n\n45 min presentation/live demo\n15 min Q&A\n\nPresenter Bio: \n \nLouie De Luna\, Director of Marketing at Aldec \nLouie De Luna is Aldec’s Director of Marketing with 20+ years’ experience in FPGA/SoC design verification and EDA tools. He currently directs the overall product and technical marketing of Aldec’s design verification solutions. He earned his B.S. in Computer Engineering from University of Nevada\, Las Vegas\, in 2001.  His practical engineering experience includes simulation-based verification\, linting\, CDC analysis\, and hardware-assisted verification.
URL:https://marketingeda.com/event/high-performance-rtl-simulation-workflow-with-libero-and-active-hdl/
LOCATION:OR
CATEGORIES:EDA,Webinar
ATTACH;FMTTYPE=image/jpeg:https://marketingeda.com/wp-content/uploads/Aldec-April-4-2024.jpg
END:VEVENT
BEGIN:VEVENT
DTSTART;TZID=America/Los_Angeles:20240404T100000
DTEND;TZID=America/Los_Angeles:20240404T110000
DTSTAMP:20240318T163105Z
CREATED:20240318T163105Z
LAST-MODIFIED:20240318T163105Z
UID:7740-1712224800-1712228400@marketingeda.com
SUMMARY:Hierarchical Analysis of EM Crosstalk with EMX Planar 3D Solver
DESCRIPTION:Identifying sources of electromagnetic (EM) coupling and safeguarding today’s complex electronic designs from EM crosstalk are daunting tasks. For designs with multiple levels of hierarchy\, identification\, and detailed analysis of the “EM-sensitive” content is a challenge. The manual creation of wrapper cells or new layout views to enable this quickly becomes a time-consuming and error-prone task. \nLearn how the Cadence EMX Planar 3D Solver black-box flow lets you specify hierarchical layout cells to be excluded from the EM analysis\, saving design time and eliminating errors. Automate the flow and integrate with Virtuoso ADE Suite and Spectre Simulation platforms for more control during circuit analysis. \nLearn through real-life circuit examples how to achieve: \n\nFaster design cycles: Streamline your analysis process and free up time for innovation.\nReduced errors and rework: Eliminate manual tasks and minimize the risk of mistakes.\nEnhanced confidence in your designs: Gain superior control over signal integrity for optimal performance.
URL:https://marketingeda.com/event/hierarchical-analysis-of-em-crosstalk-with-emx-planar-3d-solver/
LOCATION:OR
CATEGORIES:EDA,Webinar
ATTACH;FMTTYPE=image/jpeg:https://marketingeda.com/wp-content/uploads/Cadence-April-4-2024.jpg
END:VEVENT
BEGIN:VEVENT
DTSTART;TZID=America/Los_Angeles:20240404T100000
DTEND;TZID=America/Los_Angeles:20240404T110000
DTSTAMP:20240221T221413Z
CREATED:20240221T221413Z
LAST-MODIFIED:20240221T221413Z
UID:7675-1712224800-1712228400@marketingeda.com
SUMMARY:Maximizing the Benefits of Virtuoso Layout Suite XL
DESCRIPTION:Find out how the Virtuoso Layout Suite XL you’ve known for many years is setting new standards in custom layout authoring. The connectivity-driven paradigm keeps the layout in synch with the circuit design and ensures that the design intents are always honored. Learn how we strengthened the layout editor in Virtuoso Studio\, launched in 2023\, with new features that empower you to achieve tasks much faster. In this webinar\, you will learn about: \n\nNew features such as Schematic Assistant\, Incremental Check Against Source\nWhether Group Array can solve your historical problem of mosaics conflicting with Virtuoso Layout Suite XL\nStreamlining the daunting task of managing the sanctity of review process using the design review feature in Virtuoso Studio\nPerformance improvements you will gain if you switch to Virtuoso Studio\n\nWebinar #1: March 12\nAccelerate Layout Creation with Automated Place and Route in Virtuoso Studio \nWebinar #2: March 19\nSaving on Signoff Effort with iPegasus Verification System for Virtuoso Studio – In-Design DRC and Fill \nWebinar #3: April 4\nMaximizing the Benefits of Virtuoso Layout Suite XL \nWebinar #4: April 10\nFinding Hidden Treasures to Accelerate Routing Your Layout
URL:https://marketingeda.com/event/maximizing-the-benefits-of-virtuoso-layout-suite-xl/
LOCATION:OR
CATEGORIES:EDA,Webinar
ATTACH;FMTTYPE=image/jpeg:https://marketingeda.com/wp-content/uploads/Cadence-March-2024.jpg
END:VEVENT
BEGIN:VEVENT
DTSTART;TZID=America/Los_Angeles:20240403T080000
DTEND;TZID=America/Los_Angeles:20240405T170000
DTSTAMP:20240326T185839Z
CREATED:20230918T162548Z
LAST-MODIFIED:20240326T185839Z
UID:6808-1712131200-1712336400@marketingeda.com
SUMMARY:ISQED Symposium 2024
DESCRIPTION:A pioneer and leading interdisciplinary conference\, the 25thInternational Symposium on Quality Electronic Design (ISQED’24) accepts and promotes original and unpublished papers related to the topics shown below. \nISQED’24 theme is AI/ML& Electronic Design\, Hardware Security\, Quantum Computing\, 3D Integration\, and IoT. Authors are invited to submit papers in following topics (please visit the website for detail list of all tracks and subjects): \n\nHardware and System Security\nElectronic Design Automation Tools and Methodologies\nDesign for Test and Verification\nEmerging Device and Process Technologies and Applications\nCircuit Design\, 3D Integration and Advanced Packaging\nSystem-level Design and Methodologies\nCognitive Computing Hardware\n\nThis must-attend conference starts on Wednesday April 3\, and continues until the early afternoon of Friday April 5. The program includes keynote speeches\, embedded tutorials\, invited talks\, panel discussion\, and many peer-reviewed technical presentations. \nKeynote Speakers\n\nCross-Layer Optimization of Energy Harvesting and Storage\nDr. Naehyuck Chang\nExecutive Vice President\, Samsung SDI America\nWhy we did not have flying cars for 100 years\nJim Dukhovny\nCEO\, Alef Aeronautics\nReflections on Microelectronic and Microelectromechanical Technologies and the Challenges of Implementing Emerging Technologies\nClare D. Thiem\nAir Force Research Laboratory/RITB\n\nEmbedded Tutorials\n\nAdvanced Packaging for Heterogenous Integration\nDr. Tolga Acikalin\nIntel Labs\nSecuring Ubiquitous Devices with Lightweight Circuit Primitives\nProf. Kaiyuan Yang\nRice University\n\nPanel Discussion\n\nAI Hardware: Opportunities and Challenges\n\nTechnical Sessions\nTechnical program consists of over 20 technical sessions featuring over 100 peer-reviewed and invited technical presentations on various challenging topics related to AI/ML & Electronic Design\, Security\, IoT\, Quantum Computing\, etc. See the ISQED 2024 program for details. \nISQED Awards\nISQED best paper award ceremony will be held during plenary session on the morning of Wednesday April 3.
URL:https://marketingeda.com/event/isqed-symposium-2024/
LOCATION:Seven Hills Conference Center\, 800 Font Blvd\, San Francisco\, CA\, 94132\, United States
CATEGORIES:Conference,EDA,Semiconductor
ATTACH;FMTTYPE=image/jpeg:https://marketingeda.com/wp-content/uploads/ISQED-2024.jpg
END:VEVENT
BEGIN:VEVENT
DTSTART;TZID=America/Los_Angeles:20240403T080000
DTEND;TZID=America/Los_Angeles:20240404T170000
DTSTAMP:20240212T202640Z
CREATED:20240212T202640Z
LAST-MODIFIED:20240212T202640Z
UID:7607-1712131200-1712250000@marketingeda.com
SUMMARY:Siemens EDA User2User Conference
DESCRIPTION:Engineer a smarter future\, faster at Siemens EDA User2User Conference \nApril 3-4\, 2024 Santa Clara\, CA. \nJoin your colleagues from around the industry for a day of technical sessions\, networking\, keynote sessions\, labs and more. User2User is free of charge for Siemens EDA customers and includes sessions\, lunch\, and parking. \nTechnology tracks covering the latest from: \n• 3DIC/Chiplet Package Design \n• Aprisa Digital IC Implementation \n• Calibre Design Solutions & Power Integrity Analysis \n• Custom IC Verification \n• Functional Design and Verification \n• Hardware Assisted Verification \n• High-Level Synthesis/Verification & RTL Power Estimation/Optimization \n• Package/PCB Analysis & Verification \n• Tessent Test and Embedded Analytics Solutions \nNEW this year\, the option to attend a full day of training from our Learning Services team. \nWe are excited to offer a unique training opportunity on Wednesday\, April 3rd\, the day before User2User! Our experts will deliver curated material from our most sought-after courses in a condensed format. User2User attendees who participate in either class will also take home a free ODT subscription for the full self-paced training course to expand your knowledge on the topic and perform hands-on labs in our virtual cloud-enabled environment. Space is extremely limited\, so click below to learn how you can get into this User2User-exclusive!
URL:https://marketingeda.com/event/siemens-eda-user2user-conference/
LOCATION:Santa Clara Marriott\, 2700 Mission College Blvd\, Santa Clara\, CA\, 95054\, United States
CATEGORIES:EDA,IP,User Group
ATTACH;FMTTYPE=image/jpeg:https://marketingeda.com/wp-content/uploads/Siemens-April-3-4-2024.jpg
END:VEVENT
BEGIN:VEVENT
DTSTART;TZID=America/Los_Angeles:20240402T100000
DTEND;TZID=America/Los_Angeles:20240402T110000
DTSTAMP:20240327T160224Z
CREATED:20240327T160224Z
LAST-MODIFIED:20240327T160224Z
UID:7768-1712052000-1712055600@marketingeda.com
SUMMARY:RISC-V Instruction Set Architecture: Enhancing Computing Power
DESCRIPTION:*Work email required for registration*  \nDon’t miss out on this exclusive opportunity to stay ahead in the rapidly evolving landscape of chip design. Join us for an engaging discussion that promises to inspire and inform: \n– Gain insights into the latest trends shaping chip design. \n– Learn from industry leaders about the strategies behind successful SoC design. \n– Discover how RISC-V and software-defined products are shaping the future of chip architecture. \n– Network with professionals and experts in the field. \nSoftware Defined Products: Meeting the Challenges of Change \nAndes Technology Corp.  \nPresenter: Bing Yu\, Computer and AI Architect\, Andes Technology USA Corp. The adoption of the RISC-V instruction set architecture has revolutionized chip design. For the first time\, designers can extend the instruction set architecture to achieve significant improvements in performance or reductions in power consumption. Bing Yu will delve into how this trend has propelled Andes Technology Corp. to success. \nMenta SAS  \nPresenter: Gareth Baron\, Applications Engineering Director\, Menta SAS North America. As the industry moves towards software-defined products\, there’s an increasing demand for flexibility in chip design\, including the flexibility to update some portions of the logic post-fab. Gareth Baron will explore this trend\, drawing from examples like Software Defined vehicles. Learn how Menta SAS has navigated the challenges of designing for change in silicon. \n*This webinar is in partnership with SemiWiki\, Andes\, and Menta SaS*
URL:https://marketingeda.com/event/risc-v-instruction-set-architecture-enhancing-computing-power/
LOCATION:OR
CATEGORIES:EDA,IP,Webinar
ATTACH;FMTTYPE=image/jpeg:https://marketingeda.com/wp-content/uploads/Amdes-Menta-April-2-2024.jpg
END:VEVENT
BEGIN:VEVENT
DTSTART;TZID=America/Los_Angeles:20240328T110000
DTEND;TZID=America/Los_Angeles:20240328T120000
DTSTAMP:20240311T211521Z
CREATED:20240311T211521Z
LAST-MODIFIED:20240311T211521Z
UID:7727-1711623600-1711627200@marketingeda.com
SUMMARY:High-Performance RTL Simulation Workflow with Quartus and Active-HDL
DESCRIPTION:Based on recent industry research\, the FPGA market was valued at approximately USD 7.5 Billion in 2023\, with an expected compound annual growth rate (CAGR) of around 10% by 2032. More and more engineers will be adopting FPGAs due to their versatility\, acceleration capability\, power efficiency and lower non-recurring engineering (NRE) costs (compared to ASICs). Major FPGA vendors like AMD\, Altera and Microchip are continuously innovating their technologies\, architectures\, and IPs – and consequently enhancing their respective design capabilities and workflows. For example\, Vivado\, Quartus and Libero all provide useful design and RTL simulation features. Aldec collaborates closely with the FPGA vendors as partners to ensure seamless simulation of all their IPs and libraries using Aldec’s simulation tool\, Active-HDL. \nIn terms of verification\, FPGA designs undergo testing directly in the lab or through simulations\, depending on factors such as design size\, complexity\, and project objectives. While some FPGA designs may find adequate simulation support from the FPGA vendor tools\, many require higher simulation performance and a more comprehensive language support\, particularly those with larger designs with complex logic and deep hierarchies. \nSimulation stands as the primary verification method for FPGA designs\, essential for minimizing non-trivial bugs escaping into production. The ability to run more simulation enables the verification of a wider range of test scenarios\, thus elevating verification quality. Aldec’s Active-HDL offers a faster compilation/simulation engine\, robust debugging features and comprehensive language support for the latest versions of VHDL\, SystemVerilog\, and SystemC. \nIn this three-part webinar series\, we will show how to turbocharge FPGA simulation workflows by using Active-HDL as the default simulator within AMD® Vivado\, Altera® Quartus and Microchip® Libero SoC. \nAbstract: \nIn part two of this three-part webinar series\, we will show how to simulate an Altera design example. We will generate a design example from Quartus and simulate it using Active-HDL as the default simulator. We will discuss various tips that you can use to optimize compilation and simulation run times. The tips will be categorized from zero-cost effort to high-cost effort and\, depending on your budget/resource constraints\, you will have a path to speed up your simulation by a huge factor. We will turn on Profiler so that you can determine the bottlenecks in your design/testbench\, and we will show how you to do a post-simulation debug using Waveform Viewer\, Hierarchy\, Object and Watch windows. \n\nAgenda\n\nWorkflow with Quartus and Active-HDL\nTips on how to optimize simulation performance\nPerformance bottleneck analysis with Profiler\nPost-simulation debugging with Waveform Viewer\, Hierarchy and Watch window\nLive demo\nQ&A\n\nWebinar Duration\n\n45 min presentation/live demo\n15 min Q&A\n\nPresenter Bio: \n \nLouie De Luna\, Director of Marketing at Aldec \nLouie De Luna is Aldec’s Director of Marketing with 20+ years’ experience in FPGA/SoC design verification and EDA tools. He currently directs the overall product and technical marketing of Aldec’s design verification solutions. He earned his B.S. in Computer Engineering from University of Nevada\, Las Vegas\, in 2001.  His practical engineering experience includes simulation-based verification\, linting\, CDC analysis\, and hardware-assisted verification.
URL:https://marketingeda.com/event/high-performance-rtl-simulation-workflow-with-quartus-and-active-hdl/
LOCATION:OR
CATEGORIES:EDA,Webinar
ATTACH;FMTTYPE=image/jpeg:https://marketingeda.com/wp-content/uploads/Akdec-March-28-2024.jpg
END:VEVENT
END:VCALENDAR