Marketing EDA

Deliver Next-gen Smartphones
2023-08-08 08:30 - 09:15 (America/Los_Angeles) | CA
Stefan Rosinger, Senior Director, Product Management – Arm

About this talk
Join us for a look at how the latest Arm Cortex compute cluster launched as part of Arm’s Total Compute Solution 2023 can help OEMs deliver next-level immersion, AI intelligence and security while promoting greater efficiency in their mobiles, laptops, home, and wearable devices. We will cover:

-How Cortex-X4 achieves double-digit performance gains, as well as great efficiency
-Cortex-A720 & Cortex-A520 processor efficiency gains, and how they are benefitting not just flagship but also mid-range and entry-level devices
-The performance, scalability and efficiency provided by the DynamIQ Shared Unit 120 (DSU-120)
-How the cluster is being utilized for AI and other new demanding workloads
-How the industry-leading Armv9.2 architecture and the move to 64-bit clusters has changed developer access to more security and performance

Share this:
Click to share on LinkedIn (Opens in new window)
LinkedIn

Click to share on X (Opens in new window)
X

Click to share on Facebook (Opens in new window)
Facebook
Like this:Like Loading...

Flash Memory Summit
2023-08-08 08:00 - 2023-08-10 17:00 (America/Los_Angeles) | Santa Clara Convention Center, 5001 Great America Parkway, Santa Clara, CA, 95054, United States
Why Attend Flash Memory Summit?
Flash Memory Summit (FMS) is an all-inclusive international memory and storage showcase. It is the event for the memory and storage industry. It is the one-stop place to catch up on the latest technologies, see the hottest products, and learn about what’s happening and where the latest trends are heading. FMS is now the largest memory and storage industry show with the most high-level keynoters from leading companies, the largest exhibits, and the most sessions covering everything from applications and architectures through enterprise storage, controllers, and new technologies.
Our industry continues to thrive and grow with new technology and more applications than ever. FMS has expanded to an all- inclusive memory and storage summit welcoming all emerging memory and storage solutions The scope of FMS23 will include DRAM, DNA data storage, UCIe chiplet interconnects, Compute Express Link (CXL), wearables, automotive, AI/ML, data centers, and entertainment applications, along with 3D flash, NVMe, ZNS, and important industry announcements. As one past attendee put it, “Flash is a big society and FMS is the right show.”
Why You Should Participate
• Establish your company as a leader in the emerging memory and storage market.
• Display your products and expertise to an audience known to be interested in memory and storage.
• Promote memory and storage to a wider market of equipment manufacturers, solution providers, system integrators, consultants.
How You Can Participate:
• Attend: Register online for the sessions
• Exhibit: Promote your latest products – exhibit booths
• Sponsor: Receive special recognition both at the event and in publicity
• Present: Display your knowledge and commitment to flash memory
Share this:
Click to share on LinkedIn (Opens in new window)
LinkedIn

Click to share on X (Opens in new window)
X

Click to share on Facebook (Opens in new window)
Facebook
Like this:Like Loading...

Synopsys Static Verification SIG 2023
2023-08-08 08:00 - 17:00 (America/Los_Angeles) | Synopsys, 675 Almanor Ave, Sunnyvale, CA, 94085, United States
Join us in-person on August 8th for the Synopsys Static Verification Special Interest Group (SIG) event. This event provides an opportunity for users, managers, and enthusiasts to stay connected with the latest innovations, techniques and methodologies. Attendees will hear about groundbreaking and successful applications and deployments of Synopsys VC SpyGlass RTL static signoff solution.
Full agenda coming soon!
Share this:
Click to share on LinkedIn (Opens in new window)
LinkedIn

Click to share on X (Opens in new window)
X

Click to share on Facebook (Opens in new window)
Facebook
Like this:Like Loading...

ISPLED 2023
2023-08-07 08:00 - 2023-08-08 17:00 (Europe/Vienna) | TU Wien, Gußhausstraße 27-29/384, Vienna, Austria
The International Symposium on Low Power Electronics and Design (ISLPED) is the premier forum for presentation of innovative research in all aspects of low power electronics and design, ranging from process technologies and analog/digital circuits, simulation and synthesis tools, system-level design and optimization, to system software and applications.

Share this:
Click to share on LinkedIn (Opens in new window)
LinkedIn

Click to share on X (Opens in new window)
X

Click to share on Facebook (Opens in new window)
Facebook
Like this:Like Loading...

An Introduction to Correct-by-Construction Golden Specification-based IP/SoC Development
2023-08-03 09:00 - 10:00 (America/Los_Angeles) | CA
This webinar explores front-end automation advances that encompass an innovative register information management system to capture hardware functionality and addressable register map in a single “executable” specification.
Appropriate Audience:
● Architects/RTL Designers
● Verification Engineers
● Pre-Silicon Validation Teams
● Post-Silicon Lab Bring-up Team Members
● Technical Writers
● Firmware Engineers
● Embedded Programmers
Learn How To:
● Quickly and efficiently create correct-by-construction reusable designs
● Quickly and comprehensively verify registers and memories
● Swiftly generate device drivers
● Automatically generate derived documentation for Tech-Pubs, Lab, internal and external customers
● Eliminate inefficiencies in the design process
● Prevent errors from entering the system by giving appropriate error messages in the specification itself
● Carefully manage register information – and any inevitable changes – throughout the design process
● Increase entire development team productivity with auto generation of Register database information in the formats desired by the various teams.
● Reduce design cost by reducing iterations that result due to lack of accurate communication between various teams Specification Automation Benefits & Capabilities:
● Deliver the ease of a document editor to the system architect or designer for the creation of an executable specification
● Executable specification contains everything needed to fully describe the design including documentation and register descriptions
● All downstream views are generated from this single specification
● Dramatically increase productivity while reducing risk
Presenter Bio:
Nikita Gulliya, RnD Engineer, joined Agnisys in 2017 and serves on the product engineering team. A SystemRDL expert, she has led various SystemRDL trainings for Agnisys customers around the globe.
*This webinar is in partnership with SemiWiki and Agnisys
Share this:
Click to share on LinkedIn (Opens in new window)
LinkedIn

Click to share on X (Opens in new window)
X

Click to share on Facebook (Opens in new window)
Facebook
Like this:Like Loading...

Accelerate Coverage Closure with Synopsys VSO.ai
2023-08-02 10:00 - 11:00 (America/Los_Angeles) | CA
70% of engineering time is spent verifying a design but it is largely a manual effort. As the industry faces ongoing engineering shortages companies are forced to make their engineering teams 10 times more productive at finding and isolating bugs per day. Increasing design complexities are also driving up the compute resources needed to verify todays designs.

To address these resource challenges, teams need to shift from an entirely manual verification process to utilizing autonomous verification – where human interaction is reduced, enabling the ability to achieve coverage closure faster. The goal is that once a coverage target is set, the system works autonomously to reach the target as quickly and cheaply as possible with the highest quality of results.

This Synopsys webinar will introduce and explore the Synopsys VSO.ai™ solution, Verification Space Optimization, using machine learning technologies to identify and eliminate redundancies in regressions, automate coverage root cause analysis, and infer coverage from RTL and stimulus to identify coverage gaps and provide coverage guidance.

Speakers

Listed below are the industry leaders scheduled to speak.

Will Chen

Principal Applications Engineer
Synopsys

Will Chen is a Principal Applications engineer in Synopsys’ Customer Success EDA Group. Will has over 20 years of experience with account and project management for functional verification. He has recently been focusing on using AI/ML to improve verification efficiency and productivity.

Taruna Reddy

Staff Product Manager
Synopsys

Taruna Reddy is a Staff Product Manager in the EDA Group at Synopsys. Taruna has 18 years of experience in EDA and functional verification. Prior to joining Synopsys, Taruna held field applications and verification engineering positions at Mentor Graphics, Verilab and Xtreme-EDA.

Share this:
Click to share on LinkedIn (Opens in new window)
LinkedIn

Click to share on X (Opens in new window)
X

Click to share on Facebook (Opens in new window)
Facebook
Like this:Like Loading...

EMC+SIPI 2023
2023-07-31 08:00 - 2023-08-04 17:00 (America/Los_Angeles) | DeVos Place, 303 Monroe Ave NW, Grand Rapids, MI, United States
EMC+SIPI 2023 leads the industry in providing state-of-the-art education on EMC and Signal Integrity and Power Integrity techniques. Don’t miss out on this valuable opportunity to learn from and network with industry leaders and peers.
Share this:
Click to share on LinkedIn (Opens in new window)
LinkedIn

Click to share on X (Opens in new window)
X

Click to share on Facebook (Opens in new window)
Facebook
Like this:Like Loading...

A Novel Approach to Implementing Logical ECOs with Synopsys Formality ECO on High Performance RISC-V Cores
2023-07-26 10:00 - 11:00 (America/Los_Angeles) | CA
RTL engineering change order (ECO) is vital to ensuring proper functionality of integrated circuits (ICs). Retiming and auto ungrouping optimize RTL implementation and enhance PPA. However, aggressive optimizations in CPU RTL designs present challenges due to increased design complexity and potential mapping issues.

Synopsys Formality ECO offers an efficient and accurate solution for RTL ECO by automating the comprehensive ECO flow, analyzing differences between original RTL and ECO RTL, generating patches, and validating changes. Formality ECO also supports aggressive RTL optimization techniques, including retiming and auto ungrouping, while providing advanced analysis and debug features to streamline the ECO process.

In this Synopsys webinar, presenters from SiFive will share the advantages of Synopsys Formality ECO on their overall ECO cycle which has enhanced patching capabilities and resulted in faster verification runtime leading to improved TAT. With the retimed and flattened design, it is difficult to generate the sizable patch for fast CPUs designs targeted by SiFive. SiFive designs have strict requirements on the patch size, patch affecting hierarchies, changes applicable to RTL and ease of implementation at route_opt stage. By using Synopsys Formality ECO suite, SiFive has been able to generate a hassle-free patch and verify it 3-5x faster than traditional formal verification ensuring performance of the CPU.

Speakers

Listed below are the industry leaders scheduled to speak.

Vivek Upadhyaya

Technical Director
SiFive

Vivek Upadhyaya brings over 20 years of extensive experience in VLSI industry, specializing in High-Speed CPU Implementation. Currently he is holding esteemed position as a Technical Director at SiFive in Physical Implementation Group. His previous roles encompassed notable companies such as Broadcom, Cadence, Intel, and STMicroelectronics, focusing on RTL-to-GDSII implementation. He is graduate from CCS University Meerut, UP.

Rupali Kale Gaikwad

Staff Engineer
Synopsys

Rupali Kale Gaikwad is a Staff Engineer at Synopsys, holds Master’s degree in Microelectronics from BITS, Pilani. Over a span of 12 years, she has worked on various advanced node ASIC designs of different sectors including automotive, networking, modem, healthcare, high speed CPU implementation. In Synopsys she is responsible for Ecosystem customer success for complete RTL2GDS solution.

Share this:
Click to share on LinkedIn (Opens in new window)
LinkedIn

Click to share on X (Opens in new window)
X

Click to share on Facebook (Opens in new window)
Facebook
Like this:Like Loading...

Solution for 3D-IC Interposer Signal Integrity
2023-07-26 10:00 - 11:00 (America/Los_Angeles) | CA
3D-IC design requires early analysis of thermal properties, power delivery, and signal integrity. This webinar will work through the process of simulating heterogeneously integrated chiplets. Learn about the integrated workflow that begins with silicon design data being accurately modeled with 3D FEM extraction. The Cadence Clarity 3D Solver has the unique ability to efficiently import and solve for complex structures, including degassing holes. Accurate interconnect models can then be cascaded with IBIS I/O models for end-to-end signal integrity analysis and confirm that high-speed signals meet compliance testing.
Included will be a step-by-step approach to importing GDS into the simulation environment. The interposer multiblock analysis workflow in Clarity 3D Solver will show how to edit the layout, simulate, and then view all simulation results.
If you think performing channel extractions on a large interposer is a complex and time-consuming process, this is the perfect webinar for you.
Share this:
Click to share on LinkedIn (Opens in new window)
LinkedIn

Click to share on X (Opens in new window)
X

Click to share on Facebook (Opens in new window)
Facebook
Like this:Like Loading...

Solution for 3D-IC Interposer Signal Integrity
2023-07-26 10:00 - 11:00 (America/Los_Angeles) | CA
Our upcoming CadenceTECHTALK: Solution for 3D-IC Interposer Signal Integrity is designed to teach engineers to translate a GDSII stream format (GDSII) file and partition it into simulation blocks for the Clarity 3D field solver.
First, you will learn to use GDS-supporting files to simplify GDS to SPD translation and reuse those files to make the translation effortlessly repeatable. You will then learn to use the interposer multiblock analysis workflow in Clarity, edit the layout, if necessary, using scripts, create ports concurrently, set up computer resources, and then view all simulation results.
If you think performing channel extractions on a large interposer is a complex and time-consuming process, this is the perfect webinar for you.
For questions, inquiries, or issues with registration, send an email to events@cadence.com
Share this:
Click to share on LinkedIn (Opens in new window)
LinkedIn

Click to share on X (Opens in new window)
X

Click to share on Facebook (Opens in new window)
Facebook
Like this:Like Loading...

ITC India 2023
2023-07-23 08:00 - 2023-07-25 17:00 (America/Los_Angeles) | Hotel Radisson Blu, Marathalli ORR, Bengaluru, India
Keynote speakers

Fadi Maamari

VP of Engineering at Synopsys

Sule Ozev

Arizona State University

About Us

International Test Conference is the world’s premier venue dedicated to the electronic test of devices, boards and systems-covering the complete cycle from design verification, design-for-test, design-for-manufacturing, silicon debug, manufacturing test, system test, diagnosis, reliability and failure analysis, and back to process and design improvement.

At ITC India, design, test, and yield professionals can confront challenges faced by the industry, and learn how these challenges are being addressed by the combined efforts of academia, design tool and equipment suppliers, designers, and test engineers.

Share this:
Click to share on LinkedIn (Opens in new window)
LinkedIn

Click to share on X (Opens in new window)
X

Click to share on Facebook (Opens in new window)
Facebook
Like this:Like Loading...

International Test Conference - India, 2023
2023-07-23 08:00 - 2023-07-25 17:00 (Asia/Karachi) | Radisson Blu, Outer King Road, Bengaluru, India
International Test Conference is the world’s premier venue dedicated to the electronic test of devices, boards and systems-covering the complete cycle from design verification, design-for-test, design-for-manufacturing, silicon debug, manufacturing test, system test, diagnosis, reliability and failure analysis, and back to process and design improvement.

At ITC India, design, test, and yield professionals can confront challenges faced by the industry, and learn how these challenges are being addressed by the combined efforts of academia, design tool and equipment suppliers, designers, and test engineers.

Share this:
Click to share on LinkedIn (Opens in new window)
LinkedIn

Click to share on X (Opens in new window)
X

Click to share on Facebook (Opens in new window)
Facebook
Like this:Like Loading...

Achieve First-pass Silicon Leveraging SDC Verification Early with No Noise
2023-07-20 10:00 - 11:00 (America/Los_Angeles) | CA
As today’s designs are getting more complex, design constraints complexity also increases multifold. While ensuring design correctness typically gets a lot of attention including code review, functional verification, implementation, etc., correctness of constraints requires the same level of attention. Quality of implementation and timing analysis is highly dependent on quality of constraints. For achieving first-past silicon efficiently, it is imperative to ensure that the constraints are correct and complete early at RTL before progressing to late design stages of implementation and timing analysis.

In this presentation, we will focus on the conceptual foundations of constraints verification at RTL using Synopsys Timing Constraints Manager. Further, we will cover the types of constraints issues flagged and noise reduction techniques using built in formal verification. Lastly, we will discuss the need for timing exception verification (MCP/FP) and the use of formal and simulation techniques to deliver complete verification results to pinpoint incorrect timing exceptions.

Speaker

Listed below is the industry leader scheduled to speak.

Rimpy Chugh

Senior Product Marketing Manager
Synopsys

Rimpy Chugh is a Senior Product Marketing Manager in the Verification Group at Synopsys, with 10 years of varied experience in EDA and functional verification. Prior to joining Synopsys, Rimpy held field applications and verification engineering positions at Mentor Graphics, Cadence and HCL Technologies. She holds an MBA from Indian Institute of Management, Bangalore and a Bachelor of Technology from YMCA Institute of Technology, India.

Share this:
Click to share on LinkedIn (Opens in new window)
LinkedIn

Click to share on X (Opens in new window)
X

Click to share on Facebook (Opens in new window)
Facebook
Like this:Like Loading...

3D-IC Foundry Frameworks
2023-07-20 08:00 - 09:00 (America/Los_Angeles) | CA
Join us on July 20th; Ansys R&D members will discuss an overview of the 3D-IC technology development frameworks offered by TSMC, Samsung, and Intel and how Ansys simulation tools and workflows fit into those frameworks.

About this Webinar
Semiconductor applications such as Mobile (5G), Automotive, and Datacenter (HPC, AI) demand better scaling, performance, and lower power usage. Advanced packaging is moving towards 3DIC systems to address these needs, as evidenced by the technology directions from TSMC, Samsung, and Intel. We’ll present a comprehensive overview of these technologies, and the Ansys flows to address EMIR, Thermal integrity, and mechanical stress challenges posed by these 3DIC systems.
What You Will Learn

Advanced 3DIC packaging trends and challenges faced by engineers
3DIC system data flows from P&R to analysis tools
EMIR and Thermal Integrity flows using RedHawk SCTM and RedHawk SC ElectroThermalTM

Speakers
Mallik Vusirikala

Mallik Vusirikala is a Director Product Specialist at Ansys, responsible for strategic directions and deployment of the RedHawk product line for Power integrity and related solutions. He has been with Ansys for over 12 years. Prior to that he was with Texas instruments in the CAD flow/ methodology group developing multiple flows for standard cell library creation. He obtained his bachelor’s degree with Honors in Computer Science and Engineering from the National Institute of Technology, Hamirpur (India).
Dr. Lang Lin

Dr. Lang Lin is a principal product manager of Ansys Inc. based in San Jose, California. He is dedicated into developing 3D-IC multiphysics simulation and security verification methodologies to worldwide semiconductor customers. Before joining Ansys, he worked for Intel Corp. as a design engineer. He has published 50+ technical papers and patents, served as reviewer, program committee or tutorial speaker of several IEEE conferences such as HOST, ICCAD, DAC and ASPDAC.

Share this:
Click to share on LinkedIn (Opens in new window)
LinkedIn

Click to share on X (Opens in new window)
X

Click to share on Facebook (Opens in new window)
Facebook
Like this:Like Loading...

Achieve Optimal PPA Targets Using AI-Driven Technology
2023-07-19 10:00 - 11:00 (America/Los_Angeles) | CA
Complexity brought on by advanced process nodes have opened the door to challenges in achieving optimal power, performance, and area (PPA). Manual methods are no longer viable given shrinking market windows. The need to drive for better results faster is increasing, and traditional methods cannot keep pace often taking months of tuning using 100s of trials. Even then, results are not optimal. AI-driven technology can help.

This Synopsys webinar discusses the challenges facing engineers creating complex designs and introduces Synopsys Design Space Optimization solution, DSO.ai™. The industry’s first autonomous artificial intelligence (AI) application for chip design, Synopsys DSO.ai searches for optimization targets in very large solution spaces of chip design, utilizing reinforcement learning to enhance power, performance, and area. RTL-to-GDSII full flow optimization unlocks PPA potential across both logical and physical domains with reported productivity enhancements of more than 3x, power reductions of up to 15%, and substantial die size reductions. We’ll explore case studies from AMD, Intel, and STMicro on how they are applying this technology to surpass the most challenging goals in chip design and reach new levels of productivity.
Share this:
Click to share on LinkedIn (Opens in new window)
LinkedIn

Click to share on X (Opens in new window)
X

Click to share on Facebook (Opens in new window)
Facebook
Like this:Like Loading...

Automated Verification for Cache Coherent RISC-V SoCs
2023-07-18 11:00 - 12:00 (America/Los_Angeles) | CA
RISC-V SoC design complexity continues to increase and create new verification challenges. Private caches, shared caches, and shared main memory create potential caches/memory coherency problems that require modern, automated verification approaches.
In this webinar, we’ll demonstrate how Perspec System Verifier, with the pre-defined System Traffic Library (STL), provides an out-of-the-box verification plan and test suite for heterogeneous, multi-core, and cache-coherent processors. STL has built-in atomic actions and coherency scenarios to allow verification engineers to quickly generate test scenarios, such as targeting false sharing, true sharing, cache state transitions, snoop traffic, coherency irritators, extreme stress scenarios, IO coherency, and many more areas. Perspec System Verifier also helps visualize scenarios and analyze coverage before test execution.
Share this:
Click to share on LinkedIn (Opens in new window)
LinkedIn

Click to share on X (Opens in new window)
X

Click to share on Facebook (Opens in new window)
Facebook
Like this:Like Loading...

Key MAC Considerations for the Road to 1.6T Ethernet Success
2023-07-18 10:00 - 11:00 (America/Los_Angeles) | CA
224G SerDes designs are a reality and the path to 1.6T is clearer than ever. This webinar delves into the considerations, challenges and solutions designers need to know for the MAC required for these 224G Ethernet PHY IP designs. Dive deep into the nuances of PHY/MAC layer interactions, timing considerations, and forward error correction. We will shed light on key challenges for bandwidth hungry applications including latency optimization, and SI techniques. Discover how Synopsys MAC IP solutions can help ensure your product is first to market.

Speakers

Listed below are the industry leaders scheduled to speak.

John Swanson

HPC Controller & Datapath Product Line Manager
Synopsys

John Swanson is the HPC Controller & Datapath Product Line Manager in Synopsys’ Solutions Group. John has worked in the development and deployment of verification, integration, and implementation tools, IP, standards, and methodologies used in IP based design for over 25 years. His assignments have encompassed engineering, methodology, business development, and marketing. John has also been involved in various standards activities including Chair of the Verification Technical Working Group in the SPIRIT Consortium; Synopsys representative on the Power.org technical subcommittee and is active in many IEEE and consortium groups today.
Prior to joining Synopsys, he worked for Amoco Oil working on wellhead automation and control systems. He is an Honor graduate from DeVry Institute of Technology where he completed his Engineering degree with Presidents List Honors.

Jon Ames

Sr. Staff Product Marketing Manager
Synopsys

Jon Ames is a Sr. Staff Product Marketing Manager for the Synopsys Ethernet Controller IP portfolio. Jon has been working in the communications industry since 1988 and has led engineering and market activities from the early days of 10/100 Switched Ethernet through Metro and Transport variants to the latest Data Center and High-Performance Computing Ethernet technologies. Since graduating in Computer Science and Electronic Engineering the in UK, Jon has worked at the leading companies in the networking and silicon solution industries.

Share this:
Click to share on LinkedIn (Opens in new window)
LinkedIn

Click to share on X (Opens in new window)
X

Click to share on Facebook (Opens in new window)
Facebook
Like this:Like Loading...

Rambus Design Summit 2023
2023-07-18 08:00 - 2023-07-19 17:00 (America/Los_Angeles) | CA
Back for its fourth year, the Rambus Design Summit is a virtual conference focused on the key technologies critical to enabling performance and security for data center, AI/ML, automotive and IoT applications.

Agenda + Abstracts

Rambus Design Summit will take place over two days, with day one focusing on memory & interface solutions, and day two on security solutions. Take a look at the agenda below – all times in Pacific Daylight Time (PDT).

Tuesday, July 18: Memory & Interface Solutions

Tackling advanced data center workloads requires ever increasing levels of memory bandwidth and capacity, as well as high-speed interconnects. Hear Rambus technology experts share their insights on future memory and interconnect requirements in the data center covering critical enabling technologies including DDR5, HBM3, PCIe 6.0, GDDR6, LPDDR5X, CXL, and MIPI/VESA video compression.

Time
Session

8:00am
Keynote: CXL Technology: Revolutionizing the Data Center
Speaker: Mark Orthodoxou, Vice President of Strategic Marketing
Abstract: The need for more memory bandwidth and capacity continues to rise, with applications like generative AI pushing current data center infrastructure to the limit. The leading companies at every level of the data center value chain are coalescing around CXL technology as a path to revolutionize the data center. Join Mark Orthodoxou to hear how CXL promises tremendous gains in computing performance by bridging the latency gap between direct-attached DRAM main memory and solid-state storage, as well as enabling new tiered-memory solutions and composable architectures.

8:30am
Innovations in CXL 3.0: Novel Device Types, Capabilities, and Interconnects
Speaker: Danny Moore, Senior Product Marketing Manager
Abstract: CXL 3.0 introduces several compelling new features to address the rapidly evolving demands of future data centers. A new device type, CXL Multi-Headed Devices, has been introduced to support simultaneous connection to multiple hosts. CXL Dynamic Capacity Device (DCD) capability simplifies migration of memory resources between hosts. New CXL Fabrics offer substantial scale and flexibility in architectural design. Danny Moore will discuss these important new developments in the CXL standard.

9:00am
System Level Design Considerations for PCIe 6.0
Speaker: Lou Ternullo, Senior Director of Product Marketing
Abstract: PCIe 6.0 offers many new and exciting features including a 64 GT/s data rate, PAM4 signaling, forward error correction, and a low power L0p mode. In this presentation, Lou Ternullo will walk you through all the system design considerations you will need to know before getting started on your PCIe 6.0 design, including how to get the most out of each of the PCIe devices.

9:30am
Leveraging VESA Video Compression & MIPI DSI-2 for High-Performance Displays
Speakers: Simon Bussières, Director of Systems Architecture
Joe Rodriguez, Product Marketing Manager
Abstract: Visually lossless video compression is essential for handling the growing bandwidth requirements of cutting-edge displays with higher resolutions, faster refresh rates, and greater pixel depths. This presentation will show designers how they can develop cutting-edge display products without compromising on display quality, battery life or cost using a combination of VESA video compression and MIPI DSI-2 technology.

10:00am
Meeting the Needs of Generative AI Training with HBM3
Speaker: Frank Ferro, Senior Director of Product Marketing
Abstract: Generative AI training models are growing in both size and sophistication at a lightning pace, requiring more and more bandwidth. With its unique 2.5D/3D architecture, HBM3 can deliver Terrabytes per second of bandwidth at a system level. Join Frank Ferro to hear how HBM helps designers address the needs of state-of-the-art AI training models.

10:30am
Powering AI/ML Inference with GDDR6 Memory
Speaker: Frank Ferro, Senior Director of Product Marketing
Abstract: GDDR6 memory offers an impressive combination of bandwidth, capacity, latency and power. Frank Ferro will discuss how these features make it the ideal memory choice for AI/ML inference at the edge and highlight some of the key design considerations you need to keep in mind when implementing GDDR6 memory at ultra-high data rates.

11:00am
LPDDR5X: Delivering High Bandwidth and Power Efficiency
Speaker: Vinitha Seevaratnam, Senior Product Marketing Manager
Abstract: The bandwidth and low power characteristics of LPDDR make it an increasingly attractive choice of memory for applications in IoT, automotive, and edge computing. LPDDR5X takes performance to the next level with a data rate of up to 8.5 Gbps. Join Vinitha Seevaratnam to learn which applications can benefit from using LPDDR memory.

11:30am
What’s Next for DDR5 Memory?
Speaker: John Eble, Vice President of Product Marketing
Abstract: With the industry now firmly on the path to enabling the next generation of servers with DDR5 memory, this presentation will look at what’s next in the DDR5 journey. Hear from John Eble on how DDR5 will scale to advanced performance levels, be deployed in new applications beyond RDIMMs, and how it is tailored for client computing systems.

12:00pm
High-Performance Memory: Ask Me Anything
Speakers: Tim Messegee, Senior Director of Solutions Marketing
Steven Woo, Fellow and Distinguished Inventor
John Eble, Vice President of Product Marketing
Mark Orthodoxou, Vice President of Strategic Marketing
Frank Ferro, Senior Director of Product Marketing
Abstract: Generative AI is just one of the many applications driving the relentless need for better memory performance, capacity and efficiency in the data center. Join our experts as they discuss some of the biggest memory challenges facing the industry today, contemplate how the industry will innovate to meet future data center memory needs, and answer all your questions!

Wednesday, July 19: Security Solutions

Security anchored in hardware provides the foundation for protecting data and devices at all stages of the semiconductor lifecycle. Join Rambus Security experts as they share their insights on security threats facing the industry including those that will arise in the era of quantum computers. Learn how you can protect hardware and data at rest, in motion and in use with Root of Trust, MACsec, Inline Memory Encryption, and more.

Time
Session

8:00am
Keynote: Emerging Security Challenges in Highly Interconnected Semiconductor Systems
Speaker: Neeraj Paliwal, VP General Manager
Abstract: The swift advancements and growing intricacy of highly interconnected semiconductor systems have led to numerous security challenges that pose risks to the integrity, reliability, and performance of modern AI-driven systems. This presentation delves into the primary emerging security threats, such as supply chain attacks, intellectual property theft, hardware Trojans, side-channel attacks, fault injection attacks, and the looming threat of quantum computers. Neeraj Paliwal will examine the consequences of these threats across different industries and discuss how a hardware “secure by design” architectural approach is essential to secure semiconductor systems.

8:30am
Selecting the right Root of Trust HSM Design for Your Next Project
Speaker: Bart Stevens, Senior Director of Product Marketing
Abstract: A Root of Trust is the secure security foundation for a semiconductor or electronic system. In this presentation, Bart Stevens will guide you through the labyrinth of Root of Trust designs, including what problems they can solve and what solutions are available to implement in your next silicon design.

9:00am
Protecting Devices and Data in the Quantum Era
Speakers: Gijs Willemse, Senior Director of Product Management
Abstract: Quantum computers will eventually become powerful enough to break traditional asymmetric cryptographic methods, that is, some of the most common security protocols used to protect sensitive electronic data. This presentation will highlight the recent developments in post-quantum cryptography and discuss how designers can get ready for the quantum era.

9:30am
Hardware Security: Ask Me Anything
Speaker: Tim Messegee, Senior Director of Solutions Marketing
Bart Stevens, Senior Director of Product Marketing
Gijs Willemse, Senior Director of Product Management
Scott Best, Senior Technical Director
Abstract: Whether it’s security technology trends, the threat of quantum computers, implementation issues or anything in between, our security experts are ready to tackle your questions in this Ask Me Anything session.

10:00am
Securing MCUs with SCA Protection in IoT Designs
Speaker: Marcel Van Loon, Senior Principal Engineer Systems Architecture
Abstract: A side-channel attack (SCA) is a security exploit that attempts to extract secrets from a chip or a system. This presentation will give an overview of some of the most common types of SCA and highlight the countermeasures that designers can implement to diminish risk in low-power IoT designs.

10:30am
Cybersecurity: A Top Priority for the Automotive Industry
Speaker: Adiel Bahrouch, Director of Business Development
Abstract: Automotive systems, and the semiconductors used within them, are some of the most complex electronics seen today. That complexity is set to dramatically rise as cars reach new levels of automation. This presentation will explore how designers can navigate the delicate balance between achieving new levels of performance and automation, while meeting the safety and security requirements unique to the automotive industry.

11:00am
The Convergence of MACsec and IPsec in Data Center Silicon Designs
Speaker: Maxim Demchenko, Technical Director
Abstract: Data centers continue to adopt full line-rate security at various levels and use cases. Layer 2 (MACsec) and Layer 3 (IPsec) protocols are used to protect either full links or specific subnets or even customer-driven virtual networks. The integration of multiple security protocols is becoming an important requirement for data center silicon that aims to support multiple use cases. Join Maxim Demchenko to learn about the requirements for adding MACsec/IPsec into data center silicon designs.

11:30am
Memory Encryption for Data in Use Protection to Enable Confidential Computing in Data Center Designs
Speaker: Ajay Kapoor, Senior Principal Engineer Systems Architecture
Abstract: There is a growing industry consensus on the imperative of incorporating memory encryption in computing architectures for protecting data in use. Designing and implementing a secure memory encryption system can be complex and comes with unique challenges from both the memory and security technology perspectives. Join Ajay Kapoor to learn how memory encryption can be used in your next data center design to enable confidential computing.

12:00pm
Securing the Semiconductor Supply Chain with Silicon Provisioning and Cloud Key Management
Speaker: Matt Orzen, Technical Director Systems Architecture
Abstract: The semiconductor industry is the lifeblood of the digital economy. The design, manufacturing and consumption of chips is a global ecosystem, and competition is fierce as scaling and cost reductions based on Moore’s law are diminishing. Counterfeit and other unauthorized chips create real risks in areas of reliability, functionality, performance and safety. This presentation will discuss how semiconductor companies can protect their IP and business by securely provisioning silicon, and the means to provide the ecosystem-wide capabilities needed to verify the identity and provenance of semiconductor devices.

Share this:
Click to share on LinkedIn (Opens in new window)
LinkedIn

Click to share on X (Opens in new window)
X

Click to share on Facebook (Opens in new window)
Facebook
Like this:Like Loading...

Comprehensive Static Verification for FPGA and ASIC RTL Designers
2023-07-13 10:00 - 11:00 (America/Los_Angeles) | CA
As designs get increasingly complex, design teams are looking to find bugs earlier, to reduce rework and shorten time-to-market. The ultimate “shift left” is to put easy-to-use static verification in the hands of RTL designers to eliminate bugs at their source.
This webinar covers comprehensive static verification capabilities in the Cadence® Jasper™ Superlint and CDC apps for lint, design-for-test (DFT), clock domain crossing (CDC), and reset domain crossing (RDC).

What You Will Learn

All the static checks that should be performed to hand off better-quality RTL
How Jasper apps provide easy-to-use debug capabilities, leveraging Jasper’s industry-leading formal verification technology to reduce noise and automate violation handling and waivers
Automatic formal checks, which do not require any formal verification experience, add significant value beyond the structural-only checks that most designers are used to

FPGA designs have grown immensely in complexity and are just as prone to CDC bug escapes as ASIC designs, so we encourage all RTL designers to attend.
Share this:
Click to share on LinkedIn (Opens in new window)
LinkedIn

Click to share on X (Opens in new window)
X

Click to share on Facebook (Opens in new window)
Facebook
Like this:Like Loading...

An AI/ML Driven High-Level Synthesis Solution
2023-07-12 12:00 - 13:00 (America/Los_Angeles) | CA
High-Level Synthesis (HLS) tools yield better PPA when the “right set” of optimization constraints and tool settings are applied. Determining the right set of constraints and settings requires design and tool experience and exploration. AI/ML technology has proven highly effective at exploring the solution space and lowering the required tool expertise. This CadenceTECHTALK™ presents details on the integration of Stratus HLS with the Cadence Cerebrus™ Intelligent Chip Explorer. Join us and learn how the Cadence Cerebrus/Stratus integration efficiently explores the solution space and lowers the learning curve for producing expert-quality HLS results.
Share this:
Click to share on LinkedIn (Opens in new window)
LinkedIn

Click to share on X (Opens in new window)
X

Click to share on Facebook (Opens in new window)
Facebook
Like this:Like Loading...

Embedded UVM (eUVM)
2023-07-11 12:00 - 13:00 (Europe/London) | CA
This is to inform you that the next DVClub Europe meeting takes place on Tuesday 11th July with a theme of “Embedded UVM(eUVM)”.

Introduction to Embedded UVM to enable HPC-Powered UVM Testbenches with MultiCore Performance.

Agenda (BST)
12:00 Welcome and Introduction – Mike Bartley, Senior Vice President – VLSI Design, Tessolve
12:00 Puneet Goel, Coverify Systems Technology LLP – HPC-Powered UVM Testbenching
13:00 TBD
Register now to become a part of this event. Free to attend online.
Eventbrite – DVClub Europe
Share this:
Click to share on LinkedIn (Opens in new window)
LinkedIn

Click to share on X (Opens in new window)
X

Click to share on Facebook (Opens in new window)
Facebook
Like this:Like Loading...

Free Silicon Conference - FSiC2023
2023-07-10 08:00 - 2023-07-12 17:00 (Europe/Paris) | Sorbonne Université, 15-21 Rue de l'École de Médecine, Paris, France
The 2023 Free Silicon Conference (FSiC) will take place in Paris (Sorbonne) on July 10,11,12 2023 (Monday to Wednesday). This event will build on top of the past FSiC2019 and FSiC2022 editions. The conference will connect experts and enthusiasts who want to build a complete Free and Open Source CAD ecosystem for designing analog and digital integrated circuits. The conference will cover the full spectrum of the design process, from system architecture, to layout and verification. After the daily talks, the discussion will continue until late in an informal and relaxed atmosphere.
Tentative program

High-level design
Hardware security
On-going FOS silicon projects
Memories
Foundries and PDKs
Transistor modelling
Place-and-route tools
Parasitic extraction
Design rule checking
Schematic editors
Photonics
Sustainability

Share this:
Click to share on LinkedIn (Opens in new window)
LinkedIn

Click to share on X (Opens in new window)
X

Click to share on Facebook (Opens in new window)
Facebook
Like this:Like Loading...

FPGA Conference Europe 2023
2023-07-04 08:00 - 2023-07-06 17:00 (Europe/Paris) | NH München Ost Conference Center, Einsteinring 20, Munich, Aschheim, 85609, Germany
FPGAs have made a regular evolutional leap forward in terms of new approaches and solutions for both hardware- and software developers.
The FPGA Conference Europe, organized by ELEKTRONIKPRAXIS and the FPGA training center PLC2, is addressing that progress across all major manufacturers. It focusses on user-oriented, practically applicable solutions that developers can quickly integrate into their own everyday work. At this year’s event, one focus is on the energy efficiency of flexible logic devices. This applies in particular to small, low-power components that rely on special production techniques or deliberately have only a limited number of programmable cells.
PGAs belong to the hidden champions of microelectronics and are at the forefront of embedded development. From tiny and energy-efficient sensor fusion solutions for the automotive industry, to intelligent platforms for condition monitoring in networked factories, to powerful deep learning accelerators in the largest data centers, these flexible logic devices play an important role in many applications and will be discussed on the FPGA Conference.
Share this:
Click to share on LinkedIn (Opens in new window)
LinkedIn

Click to share on X (Opens in new window)
X

Click to share on Facebook (Opens in new window)
Facebook
Like this:Like Loading...

TSMC 2023 Technology Symposium - Japan
2023-06-30 08:00 - 17:00 (Asia/Tokyo) | The Yokohama Bay Hotel Tokyu, 2-3-7, Minatomirai, Nishi-ku, Yokohama, Japan
Japan Technology Symposium

Date
Friday, June 30
Time
9:30 a.m. – 5:20 p.m.
Venue
The Yokohama Bay Hotel Tokyu
2-3-7, Minatomirai, Nishi-ku, Yokohama 220-8543
Registration will be closed on 6/21. Seats are limited.

VoD (Video on Demand) will be available starting from 7/21.
Registration will close on 7/12.
Get the latest on:

TSMC’s smartphone, HPC, IoT, and automotive platform solutions
TSMC’s advanced technology progress on 5nm, 4nm, 3nm, 2nm processes and beyond
TSMC’s specialty technology breakthroughs on ultra-low power, RF, embedded memory, power management, sensor technologies, and more
TSMC 3DFabric™ advanced packaging technology advancement on InFO, CoWoS®, and SoIC
TSMC’s manufacturing excellence, capacity expansion plan, and green manufacturing achievement
TSMC’s Open Innovation Platform® Ecosystem to speed up time-to-design

Share this:
Click to share on LinkedIn (Opens in new window)
LinkedIn

Click to share on X (Opens in new window)
X

Click to share on Facebook (Opens in new window)
Facebook
Like this:Like Loading...

UCIe PHY Modeling and Simulation with XMODEL
2023-06-29 14:00 - 15:30 (America/Los_Angeles) | CA
Chiplets are emerging as a new way of building IC systems via heterogeneous integration, and Universal Chip Interconnect Express (UCIe) is one of the standards defining the interconnects among chiplets. This webinar presents the SystemVerilog models of a Universal Chiplet Interconnect Express (UCIe) interface, including both the analog circuits in the electrical layer and digital FSMs in the logical layer. The whole physical layer (PHY) model can be efficiently simulated in SystemVerilog, using Scientific Analog’s XMODEL.
This webinar is organized in two parts. The first part gives a brief overview of the UCIe standard and explains why XMODEL is the best way to model and verify UCIe PHY, especially considering the close interactions between its electrical layer and logical layer. It will show how to model various analog circuits in the electrical layer, including the phase-locked loop (PLL), delay-locked loop (DLL), duty-cycle corrector, phase interpolator, and transmitter/receiver circuits. Each circuit block is modeled using XMODEL primitives, which enable fast and accurate simulation of their analog behaviors in SystemVerilog.
The second part shows how you can design the finite-state machines (FSMs) in the logical layer, performing digital training and calibrations on the reference voltage levels, clock-to-data timing, lane-to-lane skews, and link data rate via a series of data transmission tests with pseudo-random bit sequences. All the FSMs are described in SystemVerilog, and with XMODEL, you can simulate this logical layer model interacting with the electrical layer model entirely in SystemVerilog. It implies that you can also use various features of SystemVerilog to check the thoroughness of your simulation, such as checking the FSM state coverage.
This webinar will be beneficial to everyone who is interested in the design and verification of UCIe PHY. For analog circuit designers, the presented models will help understand the requirements posed on each circuit block, such as the scaling of bandwidth to support a wide range of data rates from 4GT/s to 32GT/s. For digital verification engineers, the presented testbenches will show how to perform SystemVerilog-based verification on the systems containing analog circuits. And most importantly, by running the simulations with the provided models, you can gain a hands-on understanding on how the various components of a UCIe PHY work to realize a high-bandwidth interconnect between chiplets.
Share this:
Click to share on LinkedIn (Opens in new window)
LinkedIn

Click to share on X (Opens in new window)
X

Click to share on Facebook (Opens in new window)
Facebook
Like this:Like Loading...

30th MIXDES Conference
2023-06-29 08:00 - 2023-06-30 17:00 (Europe/Budapest) | Lodz Univesity of Technology, Wólczańska 221/223, Lodz, Poland
The aim of the MIXDES conference is to provide an annual Central-European forum for the presentation and discussion of recent advances in design, modeling, simulation, testing and manufacturing in various areas such as micro- and nanoelectronics, semiconductors, sensors, actuators and power devices.
The MIXDES conference papers will be submitted for inclusion into IEEE Xplore, subject to IEEE Xplore’s scope and quality requirements.
Share this:
Click to share on LinkedIn (Opens in new window)
LinkedIn

Click to share on X (Opens in new window)
X

Click to share on Facebook (Opens in new window)
Facebook
Like this:Like Loading...

Verisium Debug for UPF Low Power Design
2023-06-27 11:00 - 12:00 (America/Los_Angeles) | CA
Verisium Debug offers comprehensive debugging capabilities. From RTL, UVM testbench to UPF low-power designs, users can use the Cadence unified debugging platform for debugging. In this webinar, users will learn about the available features in Verisium Debug for UPF power-aware designs and using the unique capabilities to visualize and debug UPF low-power designs.
What you will learn

Understand features available in Verisium Debug
​Learn about the low-power debug capabilities available in Verisium Debug
Learn how to debug UPF low-power designs with Verisium Debug

Who should attend

Design engineers
Verification engineers
CAD engineers

Share this:
Click to share on LinkedIn (Opens in new window)
LinkedIn

Click to share on X (Opens in new window)
X

Click to share on Facebook (Opens in new window)
Facebook
Like this:Like Loading...

2023 Andes RISC-V CON
2023-06-27 09:30 - 17:00 (America/Los_Angeles) | The DoubleTree by Hilton, 2050 Gateway Place, San Jose, CA, United States
RISC-V is revolutionizing the future of Artificial Intelligence (AI) in industries such as automotive, data center, communications, and IoT. Its open-source instruction set architecture (ISA) provides higher performance, lower power, and compact silicon footprint, features highly desired by these industry segments. RISC-V has gained rapid widespread adoption due to its compact instruction set and extensibility. The upcoming RISC-V CON, an annual conference organized by Andes Technology, will focus on the theme of “RISC-V: Redefining AI’s Future in Automotive, Data Center, Communications, and IoT” The event will provide a perfect opportunity to connect with the RISC-V community and showcase the latest trends, market developments, emerging applications, and technological breakthroughs in this revolutionary ISA.
Share this:
Click to share on LinkedIn (Opens in new window)
LinkedIn

Click to share on X (Opens in new window)
X

Click to share on Facebook (Opens in new window)
Facebook
Like this:Like Loading...

SFF & SAFE™ Forum 2023 San Jose, CA
2023-06-27 08:00 - 2023-06-28 17:00 (America/Los_Angeles) | Signia by Hilton, 170 S Market Street, San Jose, CA, 95113, United States
Day 1 June 27th, 2023

12:00 – 1:00pm PDT
Networking Lunch & Registration

1:00 – 1:05pm PDT
Opening
Jinman Han
EVP, Head of DSA Office,
Samsung Electronics

1:05 – 1:20pm PDT
Samsung Keynote
Siyoung Choi
President and GM, Foundry Business,
Samsung Electronics

1:20 – 1:35pm PDT
An Energy Efficient Future of AI
Joe Macri
SVP, CTO of Computing & Graphics,
AMD

1:35 – 1:50pm PDT
Meeting System User Demands in a Slowing Moore’s Law Era
Chidi Chidambaram
Fellow, Technology and Foundry Engineering, Qualcomm

1:50 – 2:05pm PDT
Break

2:05 – 2:35pm PDT
Process Technology
Gitae Jeong
EVP, Head of Technology Development,
Samsung Electronics
Ohkyum Kwon
VP, Head of 8-inch Manufacturing Technology Team,
Samsung Electronics

2:35 – 2:50pm PDT
Manufacturing Excellence
Sang Sup Jeong
EVP, Head of Foundry Manufacturing Technology Center,
Samsung Electronics

2:50 – 3:10pm PDT
Design Platform
Jongwook Kye
EVP, Head of Foundry Design Platform Development,
Samsung Electronics

3:10 – 3:25pm PDT
Sustainability
Claire Hyun
Jung Seo
VP, DS Corporate Sustainability Management Office,
Samsung Electronics

3:25 – 3:40pm PDT
Break

3:40 – 3:55pm PDT
RiscV, AI and the Next Generation of Compute
Jim Keller
President and CEO,
Tenstorrent

3:55 – 4:15pm PDT
Advanced Heterogeneous Integration
MoonSoo Kang
EVP, Head of AVP Business Team,
Samsung Electronics

4:15 – 4:35pm PDT
Business & Customers
Sang-Pil Sim
EVP, Head of Foundry Worldwide Sales and Marketing,
Samsung Electronics

4:35 – 4:40pm PDT
Closing
Marco Chisari
EVP, Head of U.S. Foundry and SSIC,
Samsung Electronics

4:40 – 5:30pm PDT
Partner Pavilion & Networking

Day 2 June 28th, 2023

9:00 – 10:00am PDT
Registration

10:00 – 10:05am PDT
Opening
Jinman Han
EVP, Head of DSA Office,
Samsung Electronics

10:05 – 10:15am PDT
Welcoming Remarks
Jongwook Kye
EVP, Head of Foundry Design Platform Development,
Samsung Electronics

10:15 – 10:35am PDT
The 3Ps of 3D-ICs
Ajei Gopal
President and CEO,
Ansys

10:35 – 10:55am PDT
Unleashing a New Era of Compute with Chiplet-Powered Silicon
Tony E. Pialis
President and CEO,
Alphawave Semi

10:55 – 11:15am PDT
High-Performance Design in Samsung Foundry
Leon Stok
VP, EDA, IBM Infrastructure,
IBM

11:15 – 11:35am PDT
Samsung Foundry Process & Business Update
Gibong Jeong
EVP, Head of Foundry Business Development Team,
Samsung Electronics

11:35 – 12:45pm PDT
Lunch

12:45 – 1:00pm PDT
Break

1:00 – 4:15pm PDT
Tech Session I: Advanced Technology and Design Infrastructure
Sangyun Kim
(Tech Talk) VP, Head of Foundry Design Technology Team,
Samsung Electronics
Synopsys, ARM, ADTechnology, Cadence, Ansys

1:00 – 4:15pm PDT
Tech Session II: Advanced Design Solutions for HPC and Automotive
Jongshin Shin
(Tech Talk) EVP, Head of Foundry IP Ecosystem,
Samsung Electronics
Cadence, Alphawave, Samsung AVP, CoAsia, Siemens, Synopsys, SemiFive

4:15 – 4:30pm PDT
Closing
Marco Chisari
EVP, Head of U.S. Foundry and SSIC,
Samsung Electronics

4:30 – 5:30pm PDT
Partner Pavilion & Networking

Share this:
Click to share on LinkedIn (Opens in new window)
LinkedIn

Click to share on X (Opens in new window)
X

Click to share on Facebook (Opens in new window)
Facebook
Like this:Like Loading...

3D & Systems Summit
2023-06-26 08:00 - 2023-06-28 17:00 (America/Los_Angeles) | Dresden Hilton Hotel, An der Frauenkirche 5 D, Dresden, Germany
The SEMI 3D & Systems Summit this year is dedicated to Smarter Systems through Heterogeneous Integration. The semiconductor industry has had several changes in market, products, and tech advancements brought by disruptive technologies and Moore’s Law plateauing. Therefore, continued developments and innovation are essential to growing the business.
Industry experts will share their insights into 3D and Heterogeneous Integration Roadmap (HIR) processes for semiconductor manufacturing and applications.
Participants can enjoy the exclusive exhibition areas that will feature the most prominent names in the industry alongside new and innovative companies.
Several B2B matching opportunities await during the conference, including networking reception, coffee breaks, lunches, and a unique Networking Dinner Cruise at the beautiful Elbe River.
Share this:
Click to share on LinkedIn (Opens in new window)
LinkedIn

Click to share on X (Opens in new window)
X

Click to share on Facebook (Opens in new window)
Facebook
Like this:Like Loading...
