Marketing EDA

Advantest VOICE 2024
2024-06-03 08:00 - 2024-06-05 17:00 (America/Los_Angeles) | Hilton La Jolla Torrey Pines, 10950 N Torrey Pines Rd, La Jolla, CA, United States
VOICE is a developer conference, created by test engineers for test engineers.

Each year, the VOICE Developer Conference unites semiconductor test professionals representing the world’s leading integrated device manufacturers (IDMs), foundries, fabless semiconductor companies and outsourced semiconductor assembly and test (OSAT) providers to exchange information about the latest technology advancements, express new ideas, share best practices and network with one another.
Advantest’s annual VOICE Developer Conference is the leading premier forum for the growing international community of users and strategic partners involved with Advantest’s V93000 and T2000 SoC test platforms as well as Advantest memory testers, handlers and test cell solutions, product engineering, and test technology.
VOICE promises a collaboration of minds and ample opportunities for peer networking. Join us at VOICE for a dynamic and memorable conference experience!
Attendees gain valuable insights into the newest test solutions and best practices, forge long-lasting relationships, learn about the latest and upcoming equipment and technology from Advantest, and much more through VOICE’s technical information-rich agenda, which includes:

Keynote speakers
Technical paper presentations
Partners’ Expo
Technology Kiosk Showcases
Networking
Workshop Day

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Addressing Real-Time Workloads in Automotive Applications with Efficient ARC-V Processors
2024-05-30 10:00 - 11:00 (America/Los_Angeles)
Many automotive applications require processing workloads with minimum latency and precise timing budgets. This is especially true for safety-critical applications like adaptive cruise control and anti-lock braking, where human life may be jeopardized. These systems require processing elements that can respond to events within specific (predictable) time constraints. System reliability and availability depend on the effectiveness of this real-time processing.
In this webinar, we will outline examples of safety-critical applications and why real-time processing is required to maintain the highest levels of safety and reliability. We will also discuss Synopsys’ ARC-V™ RHX processor series and how these power/performance efficient processors address the real-time requirements of these applications.

Speaker

Rich Collins

Sr. Product Management Director
Synopsys

Rich Collins is senior product managemet director for the ARC-V RISC-V based processor portfolio at Synopsys and has over 30 years of experience in embedded semiconductor R&D, product marketing and business development. Rich holds an MBA from Duke University’s Fuqua School of Business and a BSE in Electrical Engineering from Duke University.

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Optimizing connectivity between Xpedition and HFSS for RF systems design
2024-05-30 08:00 - 09:00 (America/Los_Angeles)
In today’s fast-paced technological landscape, seamless integration between design and simulation tools is crucial for accelerating product development cycles and ensuring optimal performance of electronics, especially RF systems. Siemens Xpedition and Ansys HFSS stand as pillars in their respective domains, offering powerful capabilities for electronic design and electromagnetic simulation.
In this live conversation, Sara Louie from Ansys and Per Viklund from Siemens will describe the two-way connectivity between Siemens Xpedition and Ansys HFSS, revolutionizing the electronic design and simulation workflow. We delve into the details of bidirectional data exchange, enabling engineers to seamlessly transfer layout geometries and parameters between the two platforms.
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Reimagining Synopsys SLM PVT Monitoring IP for Advanced Node GAA Process
2024-05-29 10:00 - 11:00 (America/Los_Angeles)
Synopsys’ SLM PVT Monitor (process detector, voltage monitor, temperature sensor) IP can collect voltage, temperature, and process parameters from different blocks within the IC in real time. These data can be analyzed and used to take meaningful action to optimize the performance of the chip at any stage of silicon lifecycle. This webinar focuses on how the monitors need to move from analog to digital sensing paradigm due to the design constraints introduced by GAA nodes.
In this webinar, you will learn:

Silicon Lifecycle Management (SLM) overview and the crucial role of PVT IP
Overview of each component in the PVT IP portfolio – rearchitecting from analog to digital sensing
PVT IP use cases in data centers, 5G, consumer electronics, and automotive applications

Speaker

Listed below is the industry leader scheduled to speak.

Rohan Bhatnagar

Product Manager, Senior Staff
Synopsys, Inc.

Rohan Bhatnagar is a Product Manager, Senior Staff at Synopsys in the Silicon Lifecycle Management business group and manages the PVT Monitor IP products. He is responsible for total product management including market research and strategy for new product roadmap definition, go-to-market planning, product collateral generation for customer engagements and sales trainings. He has more than a decade and a half of experience in the Electronic Design Automation (EDA) industry focusing on the analog and mixed-signal design space. Rohan holds a Master’s degree in Electrical Engineering from The University of Texas.

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FV-Israel, Summit 2024
2024-05-28 09:30 - 17:30 (Asia/Jerusalem)
Connect with industry experts, academics, and enthusiasts for discussions on FV in Israel.
Explore new developments from top semiconductor firms, advanced EDA tools, and academic research.
Engage with leaders, exchange insights, and help shape the future of FV in Israel and globally.
Distinguished Speaker
Dadi Perlmutter
Technology and social entrepreneur and former VP at Intel
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TSMC 2024 China Technology Symposium
2024-05-28 09:00 - 16:00 (Asia/Shanghai) | Shanghai International Convention Center, No. 2727, Riverside Avenue, Shanghai, China
Get the latest on:

TSMC’s industry-leading HPC, smartphone, IoT, and automotive platform solutions
TSMC’s advanced technology progress on 5nm, 4nm, 3nm, 2nm processes and beyond
TSMC’s specialty technology breakthroughs on ultra-low power, RF, embedded memory, power management, sensor technologies, and more
TSMC 3DFabric™ advanced packaging technology advancement on InFO, CoWoS®, and TSMC-SoIC®
TSMC’s manufacturing excellence, capacity expansion plans, and green manufacturing achievements
TSMC’s Open Innovation Platform Ecosystem to speed up time-to-design

For more information on the TSMC Technology Symposium, e-mail us at: symposium@tsmc.com.
We look forward to seeing you at the 2024 TSMC Technology Symposium!

09:00 – 10:00
Registration & Ecosystem Pavilion

10:00 – 10:10
Welcome & Opening Remarks

10:10 – 10:30
Market Update and Outlook

10:30 – 11:00
Technology Leadership

11:00 – 11:25
Coffee Break & Ecosystem Pavilion

11:25 – 11:50
Manufacturing Excellence

11:50 – 12:15
Advanced Technology Design Solutions

12:15 – 13:25
Lunch & Ecosystem Pavilion

13:25 – 13:45
Advanced Technology

13:45 – 14:05
3DFabric Technology

14:05 – 14:40
Coffee Break & Ecosystem Pavilion

14:40 – 15:00
Automotive & eNVM Technology

15:00 – 15:20
IoT Technology

15:20 – 15:40
Advanced RF and Analog Technology

15:40 – 16:00
Lucky Draw

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Verification Academy Live: San Diego
2024-05-23 09:30 - 16:00 (America/Los_Angeles) | Siemens Digital Industries Software, 12348 High Bluff Drive, Suite 250, San Diego, CA, United States
Siemens Digital Industries Software
12348 High Bluff Drive, Suite 250
San Diego, CA 92130
+1 (512) 221-7460
This event is in-person only — there is no support for remote participation.
Agenda

9:30 – 10:00
Registration and Check-in
Coffee and networking with your peers.

10:00 – 10:05
Welcome / Intro
Mel Pratt | Sr. Application Engineering Manager, Functional Verification

10:05 – 11:00
Beyond Speed: Unlocking Productivity in Simulation and Debug
Moses Satyasekaran | Director, Simulation
Gone are the days when functional verification tools were solely measured by their performance metrics. The spotlight has shifted towards productivity enhancement in today’s fast-paced development environment. Join us as we explore how Siemens EDA prioritizes productivity and performance, enabling customers to optimize their verification cycles and swiftly uncover bugs. Discover the transformative impact of this paradigm shift on accelerating design validation and achieving faster time-to-market.

11:00 – Noon
Improve Productivity and Deliver Hardware Assurance: Stimulus-free Verification
Chris Giles | Director, Formal Verification
Learn how Siemens’ and OneSpin have combined to deliver a best-in-class Static & Formal solution with a focus on addressing unsolved industry challenges. These solutions enable teams to achieve peak performance and deliver absolute hardware assurance.

Noon – 1:00
Lunch and networking

1:00 – 1:45
The New Leader in Verification IP: Questa + Avery Solutions
Kamlesh Mulchadani | Product Engineer
Now that our acquisition of Avery Design Systems is complete, Siemens EDA is the new leader for Verification IP in the industry. This session will describe the protocol and memory verification solutions you need for your next silicon verification project whether in Datacenter, Storage, 3DIC, Networking, Automotive, or Aerospace and Defense applications.

1:45 – 3:00
Questa Verification IQ:
Boost verification predictability and efficiency with Big Data
Austin Mam | Product Engineer
This session will cover Questa Verification IQ (VIQ), the next-generation, data-driven verification solution from Siemens EDA that transforms the verification process using analytics, collaboration, and traceability. VIQ utilizes machine learning to boost verification productivity and is built on collective feedback gathered from verification teams over many years.

3:00 – 4:00
Wrap-up and Networking

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5 New Ways to Maximize Your Hardware Security Resilience
2024-05-23 08:00 - 17:00 (America/New_York)
Be sure to register for this high tech security webinar. You’ll learn how to identify threat scenarios quickly and why a model-based, system-oriented solution is needed to protect your hardware.

Overview
Connected vehicles offer a range of benefits, such as real-time data sharing, app-to-car connectivity, advanced driver assistance systems (ADAS), and critical safety features like location tracking, remote parking, and in-vehicle infotainment systems (IVIs). These advancements aim to enhance the overall driving and riding experience. However, it is crucial to acknowledge that equipping vehicles with smart features also exposes them to potential cyberattacks. These attacks can result in customer data leakage or even compromise critical safety functionalities.
It’s expected to discover vulnerabilities after the product is released, which could have been easily prevented. For instance, as reported by Bloomberg, a recent increase in car thefts was attributed to the absence of anti-theft computer chips in vehicle critical systems. Therefore, it is imperative to proactively consider and address potential attack vectors right from the initial stages of development.
This cybersecurity vulnerability applies to many other industrial applications, such as industrial IoT, SmartCity, and digital healthcare, where every device or system is connected, and every connection is a vulnerability.
Design for security is becoming mainstream and should be part of today’s standard design methodologies.
What you will learn

Why a model-based and system-oriented solution is needed for automotive cybersecurity
How to quickly identify threat scenarios
Why a pre-silicon security verification flow is essential for secure ICs
Using AI to mitigate side-channel vulnerabilities

Who should attend this presentation
This webinar is valuable to anyone who works with product design, connectivity and security.
Speakers
Chief Technologist Christophe Bianchi

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RapidGPT: Meet Your New AI-Powered Design Assistant
2024-05-22 21:00 - 22:00 (America/Los_Angeles)
Join us for our upcoming webinar introducing RapidGPT, a revolutionary tool developed by PrimisAI that is reshaping the field of AI-driven EDA. RapidGPT is changing the game in hardware engineering with its groundbreaking generative AI approach. Offering a natural language interface, RapidGPT empowers designers to boost productivity and shorten time-to-market. During this session, explore how RapidGPT simplifies the design journey for hardware engineers, from initial concept to RTL, transcending conventional automation and revolutionizing the hardware engineering process.
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Debugging Features of UVM
2024-05-22 10:00 - 11:00 (America/Los_Angeles)
A UVM testbench is a large and complex piece of software. Like any other large and complex piece of software, a verification environment written using UVM will require debugging at some stage. There are various debugging features built into UVM to help with this.
In this one-hour webinar, Doulos Senior Member Technical Staff Doug Smith explores the various features in UVM to help you debug your UVM environment, test cases, and design under test.
Topics include:

Debugging the Testbench
Debugging Stimulus
Debugging the Design

At the end of the webinar, we will also look at an example of the tool support features for debugging UVM using the Cadence Xcelium Logic Simulator.
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Addressing the Challenges of PCB Design for Manufacturing
2024-05-22 08:00 - 09:00 (America/Los_Angeles)
Manufacturing issues can be a big reason why your project timelines get derailed and even result in costly failures. By understanding common errors that occur while designing or creating your fabrication and assembly documentation, you can avoid making the same mistakes on future designs. With access to over 80 comprehensive Design for Test (DFT), Design for Assembly (DFA), and Design for Fabrication (DFF) checks, automated documentation that is always synced to your layout data, and single output manufacturing, OrCAD X helps ensure that your designs are robust and functional from the start.
Whether you’re a seasoned professional or new to PCB manufacturing, this webinar will go into the power of OrCAD X and how it will streamline your manufacturing output process, helping you eliminate late-stage PCB manufacturing problems.

Join us to learn about:

Common DFx issues seen by manufacturers/fabricators
DFx design guidelines to follow
In-design DFM checking with DesignTrue DFM technology
Automating manufacturing documentation with Live DOC
Generating manufacturing outputs

SPEAKERS:
John Carney, Product Engineering Architect, Cadence
Kent Balius, Director of Pre-Production Engineering. Summit Interconnect
HOST:
Supreeth Mannava, Senior Principal Product Manager, Cadence
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Questa RDC Assist – Improving designer productivity and enabling faster RDC verification closure with machine learning
2024-05-22 08:00 - 09:00 (America/Los_Angeles)
In 2021 Siemens EDA released CDC Assist. CDC Assist is an ML powered feature that empowers users to configure, debug, and close CDC on designs more rapidly. Following the success of CDC Assist, Siemens introduced RDC Assist in 2023.
‌
Using the same ML technology in CDC Assist, RDC Assist dramatically improves the time and effort required to configure, debug, and close reset domain crossing analysis.
‌
Since RDC violations often have a common cause, RDC Assist helps users to identify the root cause for the RDC violations and errors through data mining and machine learning techniques.
‌
We will discuss use models and best practices to utilize RDC Assist, and walk through a demo showing its power.
What you will learn:

‌How RDC Assist helps users expedite their RDC Analysis
How to run RDC Assist
How to analyze RDC Assist results in the UI
How to use RDC Assist to focus on major hotspots first
Techniques presented are applicable to both CDC and RDC analysis
‌

Who should attend:
RTL designers, anyone that runs CDC or RDC, design team leads
Speaker:

Farhad Ahmed
Principal Product Engineer, Siemens EDA

Farhad Ahmed currently is a Principal Product Engineer at Siemens EDA Software.​
He has been working in Chip Design and EDA companies for last 30+ years. He graduated with a B.Sc.(EE) degree from Bangladesh University of Engg. & Technology and a M.Sc.(EE) from Washington State University.​
He started his career as an RTL Logic Designer for Sun Microsystems working on SPARC microprocessors.​
Farhad loves to read books on history, an avid swimmer, Squash player, does hiking regularly and also loves kayaking.​

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Accelerating AI Applications Using Custom RISC-V based SIMD/VLIW DSPs
2024-05-22 07:00 - 09:00 (America/Los_Angeles)
The revolution in AI triggers an increased awareness for application-specific instruction-set processors (ASIPs). These processors implement a specialized instruction-set architecture (ISA) tailored to the AI application domain, often starting from a baseline such as the RISC-V ISA. ASIPs can replace traditional fixed-function hardware accelerators, thereby introducing software-programmability in the AI acceleration domain, and thus more flexibility and agility in both the design process and the eventual product. By maintaining a RISC-V ISA baseline, compatibility with and reuse of existing processor ecosystem elements is facilitated.
Synopsys ASIP Designer is the industry-leading tool to design, implement, program and verify application-specific instruction-set processors. Starting from a single processor specification, designers immediately obtain an optimizing C/C++ compiler, cycle-accurate simulator and synthesizable hardware implementation of the ASIP. Using a unique compiler-in-the-loop™ and synthesis-in-the-loop™ methodology, the ISA and microarchitecture can be tuned quickly to the application domain.
This seminar introduces you to the ASIP Designer tool-suite. It features a tutorial and two case studies from AI application domains. The tutorial introduces the typical architectural features needed to accelerate AI algorithms, such as specialization, SIMD, and VLIW, and how ASIP Designer supports them. The first case study demonstrates a SIMD/VLIW architecture with a RISC-V baseline processor for accelerating activation functions. The second case study shows a RISC-V based ASIP for medium-throughput convolutional neural networks (CNN) with programming support for TensorFlowLite for Microcontrollers (TFLM).

Who Should Attend?
If you are a design engineer, algorithm developer, software engineer, system architect, or design manager focusing on advanced SoCs requiring application-specific optimizations, you won’t want to miss this event.

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The Next Generation of 3DIC Interposer/InFO Design
2024-05-21 10:00 - 11:00 (America/Los_Angeles)
In recent years, the semiconductor industry has experienced a breakthrough in the onset of 2.5D and 3D chiplet-based products. These products promise to extend the limits of Moore’s Law while demolishing limitations on speed and capacity for our highest tiers of compute. But for all the adulation we heap upon the 3DIC paradigm, we seemingly pay very little attention to the humble interposer die that enables communication between these groundbreaking chiplets.

What Attendees Will Learn:
Synopsys tools can now improve the construction and signoff process for all styles of interposers. AMD has tested these tools and will present a comprehensive update on what we see as a step forward in interposer design. This flow is driven primarily within the Synopsys 3DIC Compiler platform, though other noteworthy tools and engines are employed at key stages to ensure a high standard of quality. The Synopsys webinar begins with a brief overview of the current interposer design flow, including pros and cons to the current approach and opportunities for new development. We’ll then cover an end-to-end design flow that addresses these opportunities across the span of floorplanning, construction, extraction, and signoff. Finally, we’ll wrap up with conclusions and future work.

Speakers

Listed below are the industry leaders scheduled to speak.

Kenneth Larsen

Product Management, Sr Director
Synopsys

Kenneth Larsen is a director of product management in the EDA Group at Synopsys, focusing on 3D Heterogeneous Integration and Advanced Packaging. He has 30 years of experience in IC design verification and validation. Before joining Synopsys, Kenneth was worldwide senior technical director at Mentor.

Nitin Navale

Principal Member of Technical Staff
AMD

Nitin Navale has worked across AMD & Xilinx since 2008 and currently serves as Principal Member of Technical Staff in the CAD/Methodology team. His current role is Technical Lead for 3DIC Methodology, though he has previously also worked on design automation that ranges across STA, EM/IR, Thermal, ESD, SOC Floorplanning & Construction, IP Management, Netlisting, and Characterization. Nitin earned his BS and MS in Electrical Engineering from the University of Illinois, Urbana-Champaign. Outside of work, he is consumed by his devotion to board games and strategy. He’s also an avid musician who plays multiple instruments with an active interest in music theory.

Akshata Sonnad

Member of Technical Staff
AMD

Akshata Sonnad is a Member of Technical Staff at AMD, working on developing methodologies and flows for floor planning, signoff, and interposer/ InFO routing for next-generation multi-die systems. She graduated from University of Southern California with a Master’s degree in Electrical Engineering and worked as a CAD engineer on the physical design and verification of block level IPs and SOCs, before making a transition to 3DIC Design Methodology.

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Verification Academy Live: El Segundo
2024-05-21 09:30 - 16:00 (America/Los_Angeles) | Embassy Suites by Hilton, LAX South, 1440 East Imperial Avenue, El Segundo, CA, United States
Embassy Suites by Hilton, LAX South
1440 East Imperial Avenue
El Segundo, CA 90245
+1 (310) 640-3600
This event is in-person only — there is no support for remote participation.
Agenda

9:30 – 10:00
Registration and Check-in
Coffee and networking with your peers.

10:00 – 10:05
Welcome / Intro
Todd Holbrook | Sr. Application Engineering Manager, Functional Verification

10:05 – 11:00
Beyond Speed: Unlocking Productivity in Simulation and Debug
Moses Satyasekaran | Director, Simulation
Gone are the days when functional verification tools were solely measured by their performance metrics. The spotlight has shifted towards productivity enhancement in today’s fast-paced development environment. Join us as we explore how Siemens EDA prioritizes productivity and performance, enabling customers to optimize their verification cycles and swiftly uncover bugs. Discover the transformative impact of this paradigm shift on accelerating design validation and achieving faster time-to-market.

11:00 – Noon
Improve Productivity and Deliver Hardware Assurance: Stimulus-free Verification
Chris Giles | Director, Formal Verification
Learn how Siemens’ and OneSpin have combined to deliver a best-in-class Static & Formal solution with a focus on addressing unsolved industry challenges. These solutions enable teams to achieve peak performance and deliver absolute hardware assurance.

Noon – 1:00
Lunch and networking

1:00 – 1:45
The New Leader in Verification IP: Questa + Avery Solutions
Kamlesh Mulchadani | Product Engineer
Now that our acquisition of Avery Design Systems is complete, Siemens EDA is the new leader for Verification IP in the industry. This session will describe the protocol and memory verification solutions you need for your next silicon verification project whether in Datacenter, Storage, 3DIC, Networking, Automotive, or Aerospace and Defense applications.

1:45 – 3:00
Questa Verification IQ:
Boost verification predictability and efficiency with Big Data
Austin Mam | Product Engineer
This session will cover Questa Verification IQ (VIQ), the next-generation, data-driven verification solution from Siemens EDA that transforms the verification process using analytics, collaboration, and traceability. VIQ utilizes machine learning to boost verification productivity and is built on collective feedback gathered from verification teams over many years.

3:00 – 4:00
Wrap-up and Networking

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Embedded Vision Summit 2024
2024-05-21 08:00 - 2024-05-23 17:00 (America/Los_Angeles) | Santa Clara Convention Center, 5001 Great America Parkway, Santa Clara, CA, 95054, United States
The Summit attracts a global audience of technology professionals from companies developing computer vision and edge AI-enabled products including embedded systems, cloud solutions and mobile applications.

Why Attend? It’s a First-Rate Program with Powerful Insights into Practical Perceptual AI.

Join us for three days of learning—from tutorials to Deep-Dive Day, covering the latest technical insights, business trends and vision technologies—all with a focus on practical, deployable computer vision and visual/perceptual AI. The Summit connects the theories from great academic conferences, like CVPR, to the concrete needs of innovators building real-world products.

Four Reasons the Embedded Vision Summit is Different from Other Conferences

The Summit is by innovators, for innovators.

We have a relentless focus on practical information for people incorporating vision and AI into products to solve real-world problems.

We’ve been doing this for 13 years.

A whopping 99% of our attendees would recommend the Summit to a colleague.

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AI-Driven EM-IR Design Closure
2024-05-16 10:00 - 11:00 (America/Los_Angeles)
IR drop closure is becoming a major challenge for designers on advanced nodes. The number of violations at signoff has increased significantly, leading to longer turnaround time (TAT) or violations being waived. To solve this challenge, IR drop needs to be addressed early in the implementation phase with an automated IR prevention and fixing methodology.
In this webinar, we will present an AI-driven EM-IR closure solution integrated into the implementation flow. This solution uses AI methods to automatically root cause the IR drop violations and selects the most efficient PPA- and DRC-aware methods to fix the IR drop issues. The solution also uses AI models to enable fast incremental IR inferencing to validate the benefit of the design improvements.
Come learn about this breakthrough solution that will significantly improve your IR drop closure TAT.
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Keysight EDA Connect Tour - Burlington
2024-05-16 09:30 - 14:00 (America/Los_Angeles) | Eddie V’s Restaurant, 50 South Avenue, Burlington, MA, United States
As AI is redefining communication and connectivity, your ability to design, simulate, and test — using an intelligent and automated workflow — is what will set you apart.
Join us for a half-day event that brings together top industry experts and innovators to explore modern RF circuit and system design, including advanced topics like phased array analysis, EM-circuit co-simulation, and AI-enhanced workflow.
Our interactive sessions are tailored to bring the local design community together and help you walk away feeling armed with the latest and greatest insights that power you to accelerate your time-to-market and achieve cost-effective scalability.
Agenda

09:30 a.m.
Doors open

10:00 a.m.
Welcome

10:10 a.m.
Rapid EM-Circuit Co-Design of Microwave ICs, Packages, and Modules

11:00 a.m.
Analyzing Die-To-Die Interfaces In Multi-Die High-Speed Digital Designs/ Chiplets

11:45 a.m.
Load Pull Design Techniques for Power Amplifiers Leveraging Measurements and AI/ML

12:30 p.m.
New System Verification Tools in ADS for Circuit Designers

1:00 p.m.
Lunch Session- Keysight Eggplant- Software Test Automation

1:30 p.m.
Keysight Design Data and IP Management

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Innovative Technologies, Tools, and Methodologies for Space Applications
2024-05-15 13:00 - 14:00 (America/Los_Angeles)
In the world of space applications, reliability is paramount. As the space sector continues to experience rapid growth and evolution, new challenges are emerging to meet the demands of various mission types and requirements, such as robust functional safety protections, high reliability, and dependable operation. Join us for an exclusive panel discussion hosted by Lattice Semiconductor, where we delve into the dynamic landscape of the space industry and the indispensable role of the groundbreaking technology solutions enabling the growing demands of mission-critical requirements and application development.
Speakers
Jim T., Business Development, Lattice Semiconductor
Khalid Khan, Directory of Applications Engineer, Synopsys
Melanie Berg, Founder and CEO, Space R3
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Ansys - Simulation World 2024
2024-05-14 10:00 - 2024-05-16 14:00 (America/New_York)
Did you know that simulation helped Pratt & Whitney design a game-changing engine architecture that has saved aircraft operators over a million gallons in fuel? Or that sustainable energy start-up Amogy is using simulation to build a novel, portable, carbon-free energy system to convert ammonia into renewable fuel that will power green transportation solutions of the future? Or that medical researchers at the University of Zaragoza are relying on multiscale simulation frameworks to model solid tumor growth at the subcellular, cellular, tissue, and organ level to better assess and treat cancer?
Across industries, Ansys customers are using simulation to do some pretty heavy lifting — from electrifying mobility, to advancing safer medical treatments, to keeping satellites in orbit, to name a few. There are few limits to how simulation can be applied.

Of course, all of these innovations have one thing in common. They began with ideas from people just like you, who, with the right tools at the right time, made their industry-changing ideas reality. From May 14-16, you’ll have the opportunity to hear from many of them during Simulation World 2024, a virtual event demonstrating how Ansys technologies can put the power of innovation in your hands.
Simulation World 2024 celebrates our customers’ engineering achievements to inspire you. It connects you with the tools and solvers you need to work smarter, not harder to test your own theories. And it shows you how Ansys technologies can help you act on your ideas to make your breakthrough ideas reality.

Discover Where the Power of Ansys Simulation Can Take You in 14 Great Tracks
This year’s free, virtual event takes place over three days, organized into 14 distinct tracks that speak to the transformative power of simulation to inspire, equip, and empower you on the way to technological innovation and exploration:
Day 1: Inspire

Create What’s Next in Mobility: Learn how simulation is transforming mobility to address unprecedented challenges and deliver cost-effective, competitively differentiated solutions, from safer, more sustainable designs to the complex electronics and embedded software that define them.
Digital Engineering for Mission Success: The aerospace and defense industries must operate on the cutting edge to deliver advanced capabilities. Learn how digital engineering helps them increase flexibility, update legacy programs, and speed new technology into service.
Accelerate Cleaner Energy Development: See how industries rely on simulation to streamline production and distribution of safer, cleaner, more reliable energy through fuel-to-power conversions, and to accelerate scaling of low-carbon energy solutions.
Digitize and Personalize Medicine: Safer medical treatments can require more testing and clinical trials, making traditional approaches less affordable. Discover how simulation-driven in silico methods reduce market costs and facilitate breakthrough innovation, without compromising patient safety.
Ensure First-Time Silicon Success: Hear how integrated chip (IC) designers are tackling significant challenges rising from bespoke silicon trends and 3D-IC packaging technology to ensure first-time silicon success.

Day 2: Empower:

Tackle Engineering Complexity with Numerics: This track demonstrates how the application of advanced physics models and numerical methods for multiphysics simulation can tackle difficult design challenges and analyze real-world scenarios to overcome increasing product complexity.
Engineer without Limits: Learn why having the flexibility and open ecosystem needed to simulate modern, complex products and systems at scale requires the latest advancements in hyperscale and cloud computing.
Transform Simulation at the Speed of AI: AI-augmented simulation technology is a real game-changer, bringing unprecedented speed, innovation, and accessibility to engineering. See why it’s not just about accelerating simulation, it’s about making it more accessible.
Connect Digital Threads: This track discusses the ability of digital engineering to sort through complexity to reduce time, cost, and risk — increasing accuracy and performance with physics rigor to deliver a design infrastructure and open ecosystem along a two-way digital thread.

Day 3: Equip

Power Up Intelligent Connectivity: Discover the power of electromagnetic simulation to successfully model, analyze, and design many high- and low-frequency electronics, including computing platforms, generators and transformers, communications systems and satellites, and advanced driver-assistance systems.
Reinforce Structural Integrity: This track shows how simulation solves complex structural engineering challenges quickly and efficiently through finite element analysis (FEA), customized and automated solutions for structural mechanics, and multiple design scenario analyses to ensure greater product integrity.
Go with the Computational Flow: Get a better perspective of computational fluid dynamics (CFD) analysis and how it delivers insights to help companies make critical design decisions that reduce energy consumption and improve product performance.
Innovate at the Speed of Light: See how optics-specific tools and workflows help optical designers innovate across an entire industry to expedite groundbreaking product development and improve performance, reliability, and yield — from the nano to the micro scale.
Optimize Across the Board: Learn how comprehensive multiphysics EM/IR, thermal, and electromagnetic simulation are accelerating 3D-IC design, bespoke silicon, and intelligent connectivity to increase the speed and efficiency of semiconductor manufacturing.

Register Now for Simulation World 2024
At Simulation World 2024, you’ll hear from members of the global product development community as they come together to inspire you — and each other — with tales of agility, innovation, determination, and discovery on the way to solving them.
In this virtual setting, you can view and rearrange your schedule before or during live sessions — all from the comfort of your personal workspace. Curate your own agenda based on track or topic, then view, download, and share them with others, or export them to your calendar.
Every day, Ansys technologies are powering innovations that drive advancement. Simulation World 2024 is a chance for you see how they can help you do the same — whether you’ve got a seed of an idea you’d like to grow, or are well on your way to innovating something new. And participation is free.
So be sure to sign up for Simulation World 2024 today and encourage your colleagues to do the same.

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Introduction to the Open-source EDA Ecosystem
2024-05-14 10:00 - 12:00 (Europe/Rome)
Open-source hardware in the European Chips Act
Matthew Xuereb, European Commission
Free and open-source semiconductor ecosystem
Luca Alloatti, Free Silicon Foundation ETS
Open-source EDA software and semiconductor design
Jean-Paul Chaput, Sorbonne University, Coriolis Foundation
European roadmap on the advancement of open-source EDA tools
Rihards Novickis, Latvian Institute of Electronics and Computer Science
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TSMC 2024 Technology Symposium - Europe
2024-05-14 08:00 - 17:00 (Europe/London) | Hilton Amsterdam Airport Schiphol, Schiphol Boulevard 701 Amsterdam, Amsterdam, Netherlands
Agenda

Europe Technology Symposium
*The agenda is subject to change

08:30 – 09:30

Registration & Ecosystem Pavilion

09:30 – 09:40

Welcome & Opening Remarks

09:40 – 10:20

CEO Perspectives

10:20 – 10:40

Market Update and Outlook

10:40 – 11:10

Technology Leadership

11:10 – 11:30

Coffee Break & Ecosystem Pavilion

11:30 – 11:55

Manufacturing Excellence

11:55 – 12:20

Advanced Technology Design Solutions

12:20 – 13:40

Lunch & Ecosystem Pavilion

13:40 – 14:05

HPC Platform – Advanced Technology and 3DFabric

14:05 – 14:25

eNVM Technology Platform

14:25 – 14:45

Automotive Platform

14:45 – 15:15

Coffee Break & Ecosystem Pavilion

15:15 – 15:30

Advanced RF and Analog Technology Platform

15:30 – 15:45

IoT Technology Platform

15:45 – 16:00

High Voltage BCD/Power GaN Technology

16:10 – 17:00

Social Hour

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SEE, MAPLD 2024
2024-05-13 08:00 - 2024-05-17 17:00 (America/Los_Angeles) | Marriott La Jolla, 4240 La Jolla Village Drive, La Jolla, CA, United States
Our workshop will feature content including, but not limited to, the following areas:

Artificial Intelligence & Machine Learning (AI / ML)

Continuing Education & Workforce Development

Designing with Field Programmable Gate Arrays (FPGAs) / Systems on a Chip (SoCs) / New Devices

FPGA & SoC Assurance

Guidelines and Standards

On-Orbit Experiments & Model Validation

Radiation Hardness Assurance (RHA)

SEE Test Facilities

SEE in Devices & Circuits / Mechanisms & Modeling

Space Environments

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ESD Alliance CEO/Executive Outlook
2024-05-09 17:30 - 20:30 (America/Los_Angeles) | Keysight, 5301 Stevens Creek Blvd, Building 5, Santa Clara, 95051, United States
Key executives from leading semiconductor EDA and IP companies will gather to discuss the latest industry trends, challenges and opportunities Thursday, May 9, in Santa Clara, California at the annual CEO Executive Outlook, hosted by the Electronic System Design Alliance (ESD Alliance), a SEMI Technology Community, and Keysight Technologies. Registration is open.
Kicking off the program, Calista Redmond, CEO of RISC-V International, the industry group representing the RISC-V ecosystem, and Patrick Little, CEO of SiFive, a RISC-V IP provider, will address the state of the developing RISC-V market.
A panel discussion with executives from leading companies in the design ecosystem will immediately follow. Participants include:

Niels Faché of Keysight
Aki Fujimura of D2S
Dave Kelf of Breker
John Kibarian of PDF Solutions
Prakash Narain of Real Intent
Moderator: Bob Smith, Executive Director of the ESD Alliance

The event will be held at Keysight Technologies, 5301 Stevens Creek Blvd. in Santa Clara, beginning at 5:30 p.m. with networking, dinner and beverages. The RISC-V speaker program starts at 6:45 p.m. with the executive panel discussion to follow at 7:30 p.m. Tickets for the event are $25 per person for SEMI members and $50 per person for non-members.
About The ESD Alliance
The ESD Alliance, a SEMI Technology Community, represents members of the design ecosystem that provide goods and services spanning the conceptualization, design, verification, manufacturing and deployment of semiconductor chips and electronic systems.
The ESD Alliance focuses on:

Coordinating and amplifying the collective voice of the design industry
Promoting the value the design industry delivers to the global semiconductor and electronics industry
Addressing and defending against threats and reducing risks
Achieving efficiencies for the industry
Marketing the attractiveness of the design industry as an ideal place to pursue a career
Enabling networking, sharing and collaboration among its members

Engage with the ESD Alliance
www.esd-alliance.org
ESD Alliance Bridging the Frontier blog
X @ESDAlliance
LinkedIn
Facebook

About SEMI
SEMI® is the global industry association connecting over 3,000 member companies and 1.5 million professionals worldwide across the semiconductor and electronics design and manufacturing supply chain. We accelerate member collaboration on solutions to top industry challenges through Advocacy, Workforce Development, Sustainability, Supply Chain Management and other programs. Our SEMICON® expositions and events, technology communities, standards and market intelligence help advance our members’ business growth and innovations in design, devices, equipment, materials, services and software, enabling smarter, faster, more secure electronics. Visit www.semi.org, contact a regional office, and connect with SEMI on LinkedIn and X to learn more.
All trademarks and registered trademarks are the property of their respective owners.
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Innovative Approach to SoC Power Optimization
2024-05-09 15:00 - 16:00 (Asia/Tokyo)
Power is the biggest factor impacting semiconductors from custom silicon to CPU/GPU products. System-level Power modeling and simulation is needed to measure power accurately and efficiently. The scope of power studies has expanded to include the software, thermal and generation to feed into the UVM/UPF methodology. At this Webinar we will highlight a new system-level power methodology that integrates micro-architecture power storage, consumption, management and thermal assessments. Case studies will be presented on Chiplet power, mapping strategy of DNN on AI Engines and Tensor cores, hardware-software partitioning, and testing power management for mobile and low-power devices.
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Cracking the Power Code: Innovative Approach to SoC Power Optimization
2024-05-09 10:00 - 11:00 (America/Los_Angeles)

AI-Driven 3D System Analysis & Optimization for EM Antenna/RF Problems
2024-05-09 10:00 - 11:00 (America/Los_Angeles)
Antenna/RF design problems often involve the optimization of many variables, requiring numerous evaluations (EM simulations) using traditional optimization methods. Design engineers need an intelligent, accurate, and easy-to-use simulation platform and analysis solution that reduces repetitive design cycles while increasing user productivity and efficiency.
Leveraging an advanced AI-enabled methodology, the Cadence Optimality Intelligent System Explorer delivers quality results leading to the optimal performance of electrical systems. Optimality Explorer utilizes a novel surrogate model-aware mechanism that significantly reduces the number of required EM simulations. In addition, the seamless integration between different Cadence solver technologies (Clarity 3D Solver, AWR Microwave Office, and Optimality Explorer) enables full-cycle circuit-field co-simulation and optimization for RF/antenna design problems.
With the integration of Clarity 3D Solver and AWR Microwave Office, RF/antenna designers will have ready access to high-capacity EM analysis for design verification and signoff of large, complex RF mixed-signal systems beyond the capabilities offered by conventional solvers thanks to the Clarity distributed multiprocessing technology.
This webinar demonstrates the efficacy of the Optimality Explorer and Clarity 3D Solver engines for several complex high-dimensional antenna/RF problems.
Key takeaways:

Optimality Explorer leverages an advanced AI-enabled methodology to deliver quality results leading to the optimal performance of electrical systems
The seamless integration between Clarity 3D Solver, AWR Microwave Office, and Optimality Explorer enables full-cycle circuit-field co-simulation and optimization for RF/antenna design problems
Demonstration of the efficacy of the Optimality Explorer and Clarity 3D Solver engines for several complex high-dimensional antenna/RF problems

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TSMC Technology Workshop 2024 - Boston
2024-05-09 08:30 - 17:00 (America/Los_Angeles) | Boston Marriott Burlington, One Burlington Mall Road, Burlington, MA, 01803, United States
08:30 – 09:30
Registration & Partner Pavilion

09:30 – 09:40
Welcome & Opening Remarks

09:40 – 10:00
Market Outlook – Powering AI Together

10:00 – 10:30
Advanced Technology Leadership

10:30 – 11:00
Coffee Break & Ecosystem Pavilion

11:00 – 11:25
Specialty Technology Leadership

11:25 – 11:50
Manufacturing Excellence

11:50 – 13:00
Lunch & Ecosystem Pavilion

13:00 – 13:20
Advanced Technology Design Solutions

13:20 – 13:40
Advanced Technology

13:40 – 14:00
3DFabric Technology

14:00 – 14:30
Coffee Break & Ecosystem Pavilion

14:30 – 14:50
Automotive and eNVM Technology

14:50 – 15:10
IoT Technology

15:10 – 15:30
Advanced RF and Analog Technology

15:30 – 16:40
Social Hour

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User2User Europe 2024
2024-05-07 09:00 - 22:00 (Europe/Berlin) | Hilton Munich Airport, Terminalstraße Mitte 20, 85356 München-Flughafen, Munich, Germany
User2User is the perfect opportunity to learn, share and network with fellow technical experts who design leading-edge products using Siemens EDA tools.
Dedicated to end-users of Siemens EDA solutions, this conference is free to attend and includes innovative keynotes from industry leaders, enriching technical sessions as well as a chance to network with colleagues and peers.
The full programme includes papers on these topics

Design For Test & Embedded Analytics
Electronic System Design/PCB Design analysis and manufacturing
Functional Design & Verification
Hardware Assisted Verification
High Level Synthesis: Digital design in C++/SystemC
Custom IC Verification
IC Backend
Semiconductor packaging design, analysis and manufacturing

Keynotes
Enabling imagination – An integrated approach to system design – Mike Ellow
Mike Ellow is the Executive Vice President of Electronic Design Automation (EDA) Global Sales Services and Customer Support for Siemens in North America.
Delivering Silicon at Cloud Scale – Ronen Laviv
Ronen Laviv is the Enterprise Account Manager and EDA Sales Consultant at Amazon Web Services (AWS) based in Israel.
Technical breakouts

IC Backend Track 1

Improving the accuracy of Design for Manufacturability (DFM) sign-off checks with machine learning
Signoff with Calibre as platform independent application
Utilizing Calibre Tools for Chipfinishing within a Markefile

IC Backend Track 2

PERC-LDL Auto Waivers flow applied to Voltage Dependent Rules in BCD technologies
Mission IR Possible – Full Chip IR Drop Analysis of CMOS Cine-Image Sensor with Mpower

Custom IC Verification

Symphony Pro enablement in STMicroelectronics SmartPower Technologies
How AWS cloud compute helps scale custom IC verification workloads
PLL Design and Simulation using the Advanced SPICE technology
Accelerating verification of high frequency PLLs for Wireless Application in a Smarter World

Design for Test & Embedded Analytics

Advancing DFT with the Power of AI: Grand challenges

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ChipEx 2024
2024-05-07 08:00 - 2024-05-08 17:00 (America/Los_Angeles) | Tel Aviv Convention Center, Rokach Boulevard 101, Tel Aviv, Israel
ChipEx2024, the largest annual event of the Israeli semiconductor industry, will be held on May 7-8, 2024 in Tel Aviv, Israel. ChipEx2024 showcases companies including manufacturers, developers and suppliers of advanced hardware technologies & services. It also includes a technical seminar where the world’s leading experts address the industry’s most relevant issues.
The event is produced by ASG Ltd. in cooperation with SIA, Semiconductor Industry Association and with Semi, the largest global industry association.
The goal of ChipEx2024 is to update all professionals involved with the Israeli semiconductor industry with the latest technological innovations and future directions of the industry.
ChipEx2024 target audience are all people involved with the semiconductor industry including engineers, R&D managers, industry experts, senior executives in microelectronics related companies, multinational design centers, consultants, venture capital managers as well as electrical/electronic/computer science students & professors from the various universities around Israel.
ChipEx2024 consists of three main parts:
Vendors’ Exhibition
The ChipEx exhibition includes booths in various sizes for presentations and demonstrations of new design and development tools. This year, the ChipEx2024 exhibition will take place on May 7, 2024 at the Tel-Aviv Expo Center and will include industry vendors, service providers, and manufacturers of electronic design tools, components and manufacturing equipment from Israel and around the globe. These exhibitors will exhibit and update the visitors with the latest developments in tools and services for the semiconductor industry.
Technical Seminar
Technical lectures given by industry experts, senior executives from the semiconductor industry, vendors, and university professors. The format of the sessions intends to cultivate and promote an instructive and productive interchange of ideas and solutions among industry developers and designers. The lectures are divided to various tracks in separate halls and address the major topics related to the microelectronics industry. This year, the ChipEx2024 technical seminar will take place on May 7, 2024 at the Tel-Aviv Expo Center.
ChipEx2024 Executive Summit
The Closing session of ChipEx2024 will take place on May 8, 2024 at Peres Center for Peace and Innovation and will include top industry figures and will act as the Executive summit of ChipEx2024 targeting Industry leaders and top executives from Israel and around the globe.
ChipEx2024 is a great opportunity for any industry vendor or service provider to meet its target audience as well as interact with the decision makers in the various Israeli semiconductor companies.
We invite you to take part in ChipEx2024 as an exhibitor, a speaker and/or as a sponsor.
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