Marketing EDA

Rise Together Beyond RTL : Practical Techniques for Improving ASIC Design Efficiency and Early Verification
2024-11-12 11:00 - 12:00 (America/Los_Angeles)
High-level design techniques and automation tools to address the limitations of traditional RTL, reduce verification times, improve performance, and manage growing design complexity—integrating seamlessly.

What You’ll Learn:

This Lunch & Learn offers an in-depth look at Rise Design Automation tools and illustrates how high-level design and early verification techniques can bring value to your projects. No prior experience with high-level design is necessary, but familiarity with hardware design and RTL synthesis is recommended.
Some key takeaways you can expect:
** Rise Design Automation Overview – Introduction to the tools, use cases, methodologies, and project value of raising the abstraction beyond RTL with Rise.
** SystemVerilog – Technical details of how to use SystemVerilog for high-level design – highlighting both “loosely-timed” and “untimed” SystemVerilog.
** Handling Control and Data Flow – Learn practical approaches to optimizing control and data paths to meet timing and performance requirements without adding unnecessary complexity.
** Applying Design Space Exploration – Explore design configurations by adjusting loop unrolling, pipelining, and scheduling to optimize power, performance, and area—while gaining early insights into trade-offs.
** Improving Early Verification – How to integrate verification earlier in the design process to detect bugs faster and reduce the risk of late-stage rework.
** Real-World Use Cases – See how high-level design techniques are used to efficiently build a high-performance compute accelerator for applications like machine learning, DSP, and video/image processing.
** Learn how collaboration between system architects, RTL designers, and verification engineers speeds up development and delivers more reliable hardware.

Who should attend:

** Design Engineers looking to improve control paths, data flow, and performance, while adopting new methods gradually and with minimal risk.
** Verification Engineers looking to implement earlier, more efficient verification processes to minimize risk and accelerate timelines, without overhauling their current flows.
** Project Leads managing trade-offs in timelines, power, performance, and area, while ensuring smooth integration of new techniques into existing processes.
** System Architects looking to model, explore, and validate architectural decisions early, focusing on performance, power, and area trade-offs without late-stage surprises.

Speakers

Mike Fingeroff, Chief of High-Level Synthesis (HLS) With over 20 years of experience in hardware design automation, Mike has specialized in High-Level Synthesis (HLS), focusing on machine learning and early performance modeling using SystemVerilog, SystemC, and MatchLib. He is the author of The High-Level Synthesis Blue Book, and his expertise includes C++, SystemC, and video and wireless algorithms.

Allan Klinck, Co-Founder Allan is a co-founder of RDA and a technology leader with expertise in high-level design and AI/ML frameworks for verification. He has driven innovation in verification and low-power technologies, helping teams enhance efficiency and performance in modern, complex designs.

Ellie Burns currently serves as the Head of Marketing at Rise Design Automation (RDA). With over 30 years of experience in the semiconductor and EDA industries, she has held diverse roles in engineering, applications engineering, technical marketing, product management, and senior leadership, specializing in driving business growth through strategic marketing.

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IEEE World Technology Summit - AI INFRASTRUCTURE
2024-11-12 08:00 - 2024-11-14 17:00 (America/Los_Angeles) | San Jose Convention Center, 150 W San Carlos Street, San Jose, CA, 95113, United States
This event features top executives from around the world who describe the burning issues surrounding AI and how to solve our immediate problems, focusing on these core areas:

AI applications and their required infrastructure
Silicon to support AI applications
Systems to support AI applications
Security and Standards

AI is critical to our future. Please join us in California for the first-ever IEEE World Technology Summit, where companies, governments, and researchers come together to solve the technical challenges involved in creating the latest competitive products and services. This is a pre-product examination of key technical issues and solutions.
The main focus of this conference is AI Infrastructure.
To deliver value we need the infrastructure for AI to work!!! This infrastructure includes software, data storage, computing, communications, power and energy, standards, and security.
To form an event to address the above issues, we asked leaders in companies engaged in building this infrastructure to list the issues they saw as critical for the development of future products. These leaders helped provide the topics for IEEE WTS. And they are bringing senior speakers to address concerns, challenges, solutions, and engagement during pre-product development. This cooperation should lead to stronger more effective infrastructure for AI, which is critical to make AI work.
Companies are invited to sponsor, engage, and have employees attend this event.
If interested, contact us at: wtscontact@ieee.org
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APCCAS 2024
2024-11-07 08:00 - 2024-11-09 17:00 (Asia/Taipei) | Chang Yung-Fa Foundation, No. 11, Zhongshan S. Rd., Taipei City, Taiwan
The APCCAS is a major international forum for researchers, scientists, educators, students and engineers to exchange their latest findings in circuits and systems. It covers a wide range of topics including, but not limited to the following：

Artificial Intelligence Circuits, Systems, and Applications
Digital Integrated Circuits and Systems
Analog and Mixed Signal Circuits and Systems
Power and Energy Circuits and Systems
Biomedical Circuits and Systems
Sensory Circuits and Systems
RF/Communications Circuits and Systems
Beyond CMOS: Nanoelectronics and Hybrid Systems Integration

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Navigating COTS-IP in DO-254: Strategies for Safe and Efficient FPGA Design
2024-11-07 07:00 - 08:00 (America/Los_Angeles)
The integration of COTS-IP (Commercial Off-The-Shelf Intellectual Property) components in FPGA-based Avionics systems can significantly speed up development and enhance performance. However, it also introduces unique challenges, as these components may not align with the strict aviation development assurance standards required for DO-254 compliance. This webinar will guide you through the process of balancing the benefits and risks associated with COTS-IP in Avionics designs.
In this joint webinar with friends and partners, Aldec, we’ll explore different types of IPs available on the market, their roles in the design assurance process, and practical strategies for integrating them safely. You’ll discover key factors for choosing the right vendor and IP, best practices for verification, and effective planning and execution techniques to ensure your systems meet safety requirements.
What you’ll learn:
1. COTS-IP usage:
a. What are COTS-IPs and what are the different IP types
b. Applicable guidance for COTS-IP
c. Verification strategies and methods
d. Methods for achieving coverage
e. Putting it all together and showing compliance
Speakers:
Martin Beeby, Head of Advanced Avionics Systems and Managing Director of ConsuNova EU, ConsuNova With over 35 years of experience in the development of avionics Systems, Hardware and Software, Martin has a wealth of certification experience with systems ranging from DAL-A to DAL-D. Martin is an active contributor to many industry standard working groups developing new guidance for Avionics development and is an active CVE on multiple European programs.
Janusz Kitel, DO-254 Program Manager, Aldec Janusz brings over 18 years of experience in software and hardware design and verification, with more than a decade dedicated to mastering DO-254 compliance. His work ensures that Aldec products meet the strict standards of the aerospace industry, while also providing customers with valuable support in overcoming tooling challenges in airborne electronic hardware (AEH) projects.
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Phil Kaufman Award & Banquet
2024-11-06 18:30 - 21:00 (America/Los_Angeles) | Hayes Mansion, 200 Edenvale Avenue, San Jose, CA, United States
The Phil Kaufman Award honors individuals who have had a demonstrable impact on the field of electronic system design through technology innovations, education/mentoring, or business or industry leadership. The award was established as a tribute to Phil Kaufman, the late industry pioneer who turned innovative technologies into commercial businesses that have benefited electronic designers.
Electronic System Design Alliance—ESDA and IEEE Council on EDA—CEDA are proud to honor
DR. JASON CONG
Distinguished Professor and Volgenau Chair for Engineering Excellence at the University of California, Los Angeles (UCLA) with the
2024 Phil Kaufman Award
2024 Award Recipient
Dr. Jason Cong will be honored for sustained fundamental contributions to Field-Programmable Gate Array (FPGA) design automation technology, from circuit to system levels, with widespread industrial impact. His contributions cover four key areas of EDA:
Algorithmic Foundations for FPGA Synthesis
Interconnect Optimization
Domain Specific FPGA Computing
Neural Nets in FPGA
In addition to being an excellent educator, Dr. Cong has an outstanding track record of transforming his research results to EDA tools to benefit the EDA industry.
Dr. Jason Cong will be honored at the 2024 Phil Kaufman Award Ceremony and Banquet on November 6, 2024 in San Jose, CA.
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Navigating Trends and Tools in Automotive Design with Cadence
2024-11-06 10:00 - 11:00 (America/Los_Angeles)
Join us for our first webinar in this insightful series, where we explore the rapidly evolving automotive landscape. We will focus on the rise of autonomous and electric vehicles, highlighting key trends such as ADAS, software-defined vehicles, and zonal architectures.
Learn how Cadence’s advanced automotive solutions are addressing the increasing compute demands and in-vehicle networking requirements while prioritizing power efficiency and safety.
Equip yourself with the knowledge to thrive in this dynamic environment. We look forward to traveling this road together!
What will be covered:

Emerging trends in ADAS, software-defined vehicles, zonal architectures, connectivity, and electrification
How high-performance centralized computing, cloud-native software development, power management, safety design support, and system design and analysis are creating new opportunities for industry players and reshaping automotive design.

Who Should Attend:

This free event is a terrific opportunity for design/CAD engineers, CAD managers, IT managers, and business leaders seeking to optimize their design flow and technology infrastructure within the automotive industry.

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Verification Academy Live: Austin
2024-11-06 09:30 - 17:00 (America/Chicago) | Top Golf Austin, 2700 Esperanza Crossing, Austin, TX, United States
Overview
This seminar will update you on technologies and techniques you can adopt to
increase your verification productivity today. Specifically, we will cover:

How the new AI/ML paradigm shift across the industry is enabling functional verification productivity gains.
Protocol and memory verification solutions you need for your next silicon verification project.
Data-driven verification with automated analytics, collaboration, and traceability capabilities.
Technologies and techniques you can adopt to increase your DFT productivity.

‌
‌
Agenda
9:30 am – 10:00 am
Registration and check-in
Coffee and networking with your peers
‌
10:00 am – 10:05 am
Welcome/Intro
Mel Pratt | Sr. Application Engineering Manager, Functional Verification
‌
10:05 am – 11:00 am
KeyNote: Smart Verification – Faster is not Enough
Abhi Kolpekwar | VP & GM, Digital Verification Technologies Division
The electronics industry is on the brink of an unprecedented paradigm shift. The AI/ML-focused chips account for 20% of the semiconductor market, a figure set to skyrocket to 73% by 2030, fueled by the ongoing digital transformation. This seismic shift will significantly impact the architecture, design, and manufacturing of computing, networking, and communication solutions, necessitating careful consideration of power, performance, security, and safety concerns. Conventional verification flows, reliant on disparate point tools, will struggle to meet the demands of emerging systems. This keynote explores the prevailing macro-trends shaping today’s digital transformation before outlining a visionary approach to functional verification. By leveraging collective wisdom across tools, technologies, workflows, and methodologies, this new paradigm promises productivity gains beyond the reach of traditional methods.
‌
11:00 am – Noon
Questa Verification IQ:
Boost verification predictability and efficiency with Big Data
Ahmed ElKady | Product Engineer
This session will cover Questa Verification IQ (VIQ), the next-generation, data-driven verification solution from Siemens EDA that transforms the verification process using analytics, collaboration, and traceability. VIQ utilizes machine learning to boost.
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Noon – 12:45 pm
Lunch and networking
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12:45 pm – 1:15 pm
Questa Verification IQ: Sneak Peek of Debug IQ and Regression IQ
‌
Continuation of the Questa Verification IQ session.
‌
1:15 pm – 2:00 pm
The New Leader in Verification IP: Questa + Avery Solutions
Luis Rodriguez | Senior Technical Product Manager & VIP Architect
Now that our acquisition of Avery Design Systems is complete, Siemens EDA is the new leader for Verification IP in the industry. This session will describe the protocol and memory verification solutions you need for your next silicon verification project whether in Datacenter, Storage, 3DIC, Networking, Automotive, or Aerospace and Defense applications.
‌
2:00 pm – 2:30 pm
Capturing additional DFT coverage thru Functional Fault Grading
Byron Brinson | Product Engineer
Ideally, for manufacturing test coverage the goal is to achieve 100%. This becomes even more important for chips used in safety critical applications. However, there are usually limitations regarding the amount of coverage that the DFT infrastructure can provide within a chip. Functional Fault Grading provides a methodology to capture additional manufacturing test coverage without modifying the existing DFT architecture.
‌
b
Accelerating Verification Closure with Siemens DFT Tailored Verification Solutions
Rick Koster | Product Engineer
As semiconductor designs evolve to more complex architectures, 3DICs, and heterogeneous integration, verification engineers face increasing pressure to accelerate DFT verification closure. Siemens offers a comprehensive technology suite tailored to industry leading Tessent solutions, designed to address the growing complexity and increasing challenges in Design for Test (DFT). This session details how Siemens DFT centric verification technology tackles these challenges by providing a unified platform streamlined to Tessent flows, delivering industry leading performance and enhanced user experience, accelerating DFT verification closure while reducing cost and risk to reach DFT sign-off.
‌
3:00 pm- 5:00 pm
TopGolf happy hour & networking
‌
We look forward to seeing you!
‌
Siemens Advanced Functional Verification Team
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ITC 2024
2024-11-03 08:00 - 2024-11-08 17:00 (America/Los_Angeles) | Hilton San Diego Bayfront, 1 Park Blvd, San Diego, CA, United States
International Test Conference, the cornerstone of TestWeek™ events, is the world’s premier conference dedicated to the electronic test of devices, boards and systems-covering the complete cycle from design verification, test, diagnosis, failure analysis and back to process and design improvement. At ITC, test and design professionals can confront the challenges the industry faces, and learn how these challenges are being addressed by the combined efforts of academia, design tool and equipment suppliers, designers, and test engineers.
We are holding the conference in beautiful San Diego, CA. We have a fantastic program that addresses new test technology challenges that significantly affect today’s electronic products!
ITC is the world’s premier conference dedicated to electronics test. This year’s ITC continues with its mission to play a unique role as an information sharing forum, where the wide range of its offerings allows ITC participants to learn, network and conduct business. This year’s program includes a top-notch technical program, vibrant exhibitors, information-packed tutorials, interactive technical panels, three workshops, as well as the all-important networking that these events can provide. The technical program has been designed to optimize personal interactions on all levels. This year’s program will include papers from a pool of impressive submissions and solicited papers. Of these submissions, a large number will focus on AI, automotive, memory, and hardware security. In complement to the paper presentations, there will be special sessions on hardware security certification, chiplet integration, silicon lifecycle management, computing in memory, as well as design and test of high-power compound devices and quantum electronics.
We are continuing and expanding on the inclusion of the Industrial Practice papers sessions as ITC has a very strong focus on industry practice as well as industry and academia advances.
ITC 2024 features a vibrant exhibition showcasing relevant companies. The exhibition will serve as a convenient one-stop-shop for all the elements of test technology.
This year’s live event will enable us to embrace all of the features of the conference such as personal interaction and networking. Join us for the Wine and Cheese event after the Monday evening panel which kicks off ITC 2024. The ITC Grand Reception will be held Tuesday evening.
Last, but not least, I would like to recognize the enormous efforts of the multitude of dedicated volunteers who made ITC possible by donating their time, expertise, and enthusiasm. Without their hard work and dedication, ITC would not be possible. Please feel free to contact us if you would like to join our exciting team in the future.
ITC is the premier event for networking, where professionals from all over the world converge to sharpen skills, exchange ideas and do business. Join us, throughout the conference, for networking activities and to unwind.
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Verifying the next generation High Bandwidth Memory controllers for AI and HPC applications
2024-10-30 09:00 - 10:00 (America/Los_Angeles)
High Bandwidth Memory (HBM) has revolutionized AI, machine learning, and High-Performance Computing by significantly increasing data transfer speeds and alleviating performance bottlenecks. The introduction of next-generation HBM4 is especially transformative, enabling faster training and execution of complex AI models. JEDEC has announced that the HBM4 specification is nearing finalization. In this webinar, you will learn how Siemens’s scalable and customizable Avery HBM Verification IP helps companies like Rambus verify their industry-leading HBM4 Controller IP through rigorous testing to ensure reliability and performance.

What You Will Learn:

What’s new in HBM4
Challenges involved in verifying advanced HBM generations
Unique features in Siemens’s HBM4 memory models
Rambus’s newly-announced HBM4 memory controller IP

Who Should Attend:

Design & Verification Engineers, Architects
Managers and Directors for memory controllers

What/Which Products are Covered:

Siemens Avery HBM4 Verification IP
Rambus HBM4 Memory Controller

Speakers:

Kamlesh Mulchandani
Application Engineering Consultant, Siemens EDA

Kamlesh Mulchandani is an Application Engineering Consultant at Siemens EDA. In his role as a Verification IP AE, Kamlesh bridges the gap between Verification IP technology and customer needs through collaboration, technical support and by tailoring Siemens solutions for specific user applications. Prior to Siemens, Kamlesh worked at Cadence as a Memory Subsystem Design & Verification Engineer where he worked on verifying LPDDRx/DDRx & GDDRx IPs.

Nidish Kamath
Director of Product Management for Memory Interface IP, Rambus

Nidish Kamath is the Director of Product Management for Memory Interface IP at Rambus.  He previously held marketing and product management roles at AMD, Kioxia (formerly Toshiba Memory), Avalanche Technologies, Brocade and Qualcomm, where he worked on computational storage, SmartNICs and GPU cluster networking solutions. He has served in various standards and industry associations such as SNIA, Center for Open Source Software (CROSS), CXL Consortium, UEC and JEDEC.

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ICCAD 2024
2024-10-27 08:00 - 2024-10-31 17:00 (America/New_York) | Newark Liberty International Airport Marriott, 1 Hotel Rd, Newark, NJ, United States
The International Conference on Computer-Aided Design focuses on advancements and research in the field of electronic design automation (EDA) and computer-aided design (CAD) for integrated circuits and systems. Topics include innovations in design methodologies, tools, algorithms, and technologies related to the development of electronic systems.
The International Conference on Computer-Aided Design focuses on advancements and research in the field of electronic design automation (EDA) and computer-aided design (CAD) for integrated circuits and systems. Topics include innovations in design methodologies, tools, algorithms, and technologies related to the development of electronic systems.
Jointly sponsored by IEEE and ACM, ICCAD is the premier forum to explore new challenges, present leading-edge innovative solutions, and identify emerging technologies in the electronic design automation research areas. ICCAD covers the full range of CAD topics – from device and circuit level up through system level, as well as post-CMOS design. ICCAD has a longstanding tradition of producing cutting-edge, innovative technical program for attendees.
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TSMC OIP Ecosystem Forum Japan 2024
2024-10-25 09:30 - 17:30 (Asia/Tokyo) | Grand Hyatt Tokyo, 6-10-3, Roppongi, Minato-ku, Tokyo, Japan
Learn About:

Latest updates on TSMC 3DFabric™ chip stacking and advanced packaging processes, InFO, CoWoS®, and SoIC, 3DFabric Alliance, and 3Dblox™ standard, plus innovative 3Dblox-based design enablement technologies and solutions, targeting HPC, AI/ML, and mobile applications
Comprehensive design solutions for specialty technologies enabling ultra-low power, ultra-low voltage, analog migration, RF, mmWave, and automotive designs targeting 5G, automotive, and IoT designs
Ecosystem-specific AI-assisted design flow implementations for 2D and 3DIC design productivity and optimization
Successful, real-life applications of design technologies, IP solutions, and cloud-based designs from TSMC’s Open Innovation Platform® Ecosystem members and TSMC customers to speed up time-to-design and time-to-market.

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Hardware Verification using VirtuaLAB
2024-10-23 09:00 - 10:00 (America/Los_Angeles)
VirtuaLAB protocol solutions offer a full-stack testing environment with seamless connectivity and stimulus traffic generation for designs under test. It operates autonomously, adapting to scenarios without requiring protocol knowledge from the user. VirtuaLAB significantly reduces test and compliance suite regression times, running at high emulation speeds, integrated with Protocol Analyzer for complete protocol visibility and performance metrics. Supporting any scenario, it enables users to focus on their design’s unique value while ensuring reliable standard protocol interactions.
Who Should Attend:

Engineers and Managers responsible for System Design Verification of complex SoCs
Engineers and Managers responsible for design performance verification

What you will learn:

Attendees will learn how VirtuaLAB protocol solutions provide a full stack from the physical to the application layer to connect to your design under test and create stimulus traffic as a host, or respond to commands in the form of a compliant device.
Attendees will learn the ease of bring-up of a VirtuaLAB environment with no testbench required, but how to use real-world software to create workloads exactly matching the end-user of your silicon.
Attendees will see a demonstration of VirtuaLAB running a back-to-back UFS4 host model and RTL SSD model DUT, running the LLAMA 3.1 LLM, and providing query responses in real-time.

Speaker:

Ben Whitehead
Director of Product Management, Siemens EDA

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RISC-V Summit - North America 2024
2024-10-22 08:00 - 2024-10-23 17:00 (America/Los_Angeles) | Santa Clara Convention Center, 5001 Great America Parkway, Santa Clara, CA, 95054, United States
RISC-V is defining the future of open computing by providing unprecedented freedom to innovate. More than 13 billion RISC-V cores have shipped, powering new innovations in AI/ML, wireless, automotive. data center, space, IoT, embedded and more. Each day, thousands of engineers around the world collaborate and contribute to advance RISC-V. The RISC-V community shares the technical investment and helps shape the architecture’s strategic future so everyone may create more rapidly, enjoy a new level of design freedom, and substantially reduce the cost of innovation. Anyone, anywhere can benefit from these contributions.
This October, the global RISC-V community – including technical, industry, domain, ecosystem and special interest groups who define the architecture’s specifications – will meet in Santa Clara, California to share technology breakthroughs, industry milestones, and case studies, as well as to network and build relationships. Come be part of the RISC-V movement.

The festivities kick off with RISC-V Member Day, where technical and industry working groups meet in person to share updates on the status of various efforts.
Next, the RISC-V Summit North America features two days of compelling technical and industry keynotes and conference sessions, paired with an expo featuring dozens of community members showcasing their the latest solutions.

It’s community-curated content, research and innovation driving the next wave of growth for RISC-V.
Learn about software, systems, development tools, security, the latest use cases in key markets and more. It’s all here.
Define the future. Build your knowledge and expertise. Grow your network. It’s all during RISC-V Summit North America. Come join us!
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Jasper User Group San Jose 2024
2024-10-22 08:00 - 2024-10-23 17:00 (America/Los_Angeles) | Cadence Design Systems, Bldg 10, 2655 Seeley Avenue, San Jose, CA, United States
The CadenceCONNECT: Jasper User Group San Jose will be held in person on October 22 – 23 at the Cadence San Jose campus. This interactive, in-depth technical conference connects designers, verification engineers, and engineering managers from around the world to share the latest design and verification practices based on Cadence’s Jasper formal verification technologies and methodologies.
Share Your Story
We’re seeking your unique perspectives on using Jasper technologies and methodologies to achieve better results. If your presentation is accepted, you can:

Increase industry visibility for you and your team’s field of expertise
Improve and fine-tune your methods with insights from colleagues across the industry
Earn wide acclaim with a Best Presentation Award nomination

Please visit the website for further information. Accepted authors are expected to attend the conference and present in person. The deadline for abstract submission is 5:00pm PDT on Monday, August 26, 2024.
Conference registration will open at the end of August. We look forward to meeting you at Jasper User Group San Jose 2024!
Questions? Please email us.
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Static and Dynamic CDC Verification of AXI4 Stream-based IPs
2024-10-17 11:00 - 12:00 (America/Los_Angeles)
The AXI4 Stream protocol is used as a standard interface to exchange data between connected IPs within FPGA designs. For crossing clock domains, the AXI4 Stream interconnect is based on switches capable of transferring data to another asynchronous clock domain. The alternative solution is a dual-port AXI4 Stream IP, capable of changing clock domains when packet routing is not required.
Static and dynamic clock domain crossing (CDC) verification methods complement each other to ensure flawless operation of multi-clock designs. ALDEC_CDC rules plugin contains 58 rules for checking design quality, design constraints, and clock and reset trees. It is also used for validating design synchronization circuits. However, static CDC verification methods alone may not guarantee the completeness of the CDC verification task. Dynamic CDC verification is crucial. The two main methods for dynamic CDC verification are checking with CDC assertions and modeling of random delay insertion on clock domain crossings.

In this webinar, we will introduce both static and dynamic verification methods for CDC verification of AXI4 Stream-based IPs. We will discuss the CDC assertions that are auto-generated from ALINT-PRO, and we will also demonstrate the design and usage of the synchronizer models with random delay insertion.

Agenda:

CDC verification process overview

Static CDC verification checks
Assertions usage in CDC verification
The concept of delay randomization at CDC crossing in functional simulation

AXI Stream protocol overview
AXI CDC Port Verification

Running CDC static checks with ALINT-PRO
Generation SV Assertion with ALINT-PRO
Developing the testbench for AXI CDC Port dynamic verification
Simulating design with generated CDC assertions
Simulating design with random delay insertion in synchronizer models

Conclusion
Q&A

Webinar Duration

45 min presentation/live demo

Bio:
Alex Gnusin, Aldec’s ALINT-PRO Product Manager
Alex accumulated 27 years of hands-on experience in various aspects of ASIC and FPGA design and verification. As a verification prime for a multi-million gates project in companies such as IBM, Nortel, Ericsson and Synopsys Inc, he combined various verification methods such as static linting, formal property checking, dynamic simulation and hardware-assisted acceleration to efficiently achieve design verification goals. He received his M.S. in Electronics from Technion, Israel Institute of Technology.
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OSMOSIS 2024
2024-10-17 08:00 - 17:00 (America/Los_Angeles) | Holiday Inn City Center, Hochstraße 3, Munich, 81669, Germany
Elevate your success with osmosis 2024
The annual osmosis event is a dynamic platform for exchanging successes achieved through applying formal techniques to overcome verification challenges. It offers a unique opportunity to connect and engage with our accomplished research and development (R&D) experts and participants. If you possess a compelling achievement narrative, we invite you to unveil it at osmosis.
You will benefit from increased industry visibility as a subject matter expert, and the conversations that follow may help you and others improve formal-based verification solutions.

Abstract guidelines
Craft a concise narrative outlining the essential bits of your success story, encompassing:

the intricate problem you addressed
rationale for employing formal technology-based solutions
tangible outcomes, ideally quantifiable
key learnings and findings

For utmost impact, please limit your abstract to a single page, front and back.
Include diagrams and code examples if desired.
If you have questions or need guidance in refining your narrative, please reach out to us at osmosis.sisw@siemens.com

Schedules and processes
The deadline for abstract submissions is 6 p.m. Central EU time on Mon., Sept. 23, 2024.
Submissions will be evaluated as they are received. As we select abstracts, we will begin working with the authors on their presentations. If we fill the agenda early, we’ll close submissions.

We look forward to receiving your abstracts and seeing you in Munich!

On-demand presentations
Check out past, on-demand presentations.

Osmosis Aerospace and Defense – April 2024
Osmosis Aerospace and Defense – 2023

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ARM corelink, Arteris NoC, UCIe, Bunch-of-wires, CXL and PCIe- Designing the interconnect is not for the weak-hearted
2024-10-15 10:00 - 11:00 (America/Los_Angeles)
There are so many options for Network-on-Chip: ARM-Corelink CMN700, Arteris FlexNoC, open-source NoC interconnect, and of course developing home-grown fully customized solutions. Where does each solution fit? Where do we use it- backplane vs inside domains? How does AMBA AXI or PCIe or CXL fit in the mix? With the advent of chiplet, do we go with UCIe or bunch-of-wires. Where do we locate the DRAM and the task scheduler? Lots of questions need to be answered before the SoC or chiplets can be implemented.
In this Webinar, we will take the mystery out of these architecture decisions by demonstrating how system modeling can provide quantitative metrics to validate and optimize these requirements. For this purpose we will use the mapping of a CNN- Resnet 50 on an AI processor, Open Architecture Management (OAM) system, heterogeneous compute SoC-FPGA and development of a custom NoC.
To measure the quality of the design, we will show the running of standard and synthetic workloads. Quantitative metrics generated will include latency, throughput, buffer occupancy, peak power consumed, heat generated, cache hit-miss and memory bandwidth. We will also show how the source of bottlenecks can be identified. The design can be experimented with different routing schemes, schedulers, buffer size, clock speeds, flits, clock domains, flow control credit and quality-of-service.
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2024 OCP Global Summit
2024-10-15 08:00 - 2024-10-17 17:00 (America/Los_Angeles) | San Jose Convention Center, 150 W San Carlos Street, San Jose, CA, 95113, United States
The OCP Summit is the premier event uniting the most forward-thinking minds in open IT Ecosystem development. The Summit presents a unique platform for our Community from around the globe to share their insights, foster partnerships and showcase cutting-edge advancements in open hardware and software.
The 2024 OCP Global Summit theme is “From Ideas to Impact”. This encapsulates the transformative journey at the heart of the Open Compute Project. This year’s theme reflects OCP’s commitment to fostering innovation that transcends theoretical discussions and manifests into real-world solutions. As the pace of technological evolution accelerates and development cycles shorten, our industry is forced to rapidly respond to emerging trends and needs. By harnessing the collective expertise of our global community, we turn visionary ideas into groundbreaking technologies that drive openness, efficiency, sustainability, scalability and growth in the data center industry. Our focus honors the relentless pursuit of progress and the profound impact that OCP’s community-driven innovation can achieve. OCP transforms concepts into impactful advancements.
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DVCon Europe 2024
2024-10-15 08:00 - 2024-10-16 17:00 (Europe/Berlin) | Holiday Inn Munich – City Centre, Hochstraße 3, Munich, 81669, Germany
The Design and Verification Conference in Europe (DVCon Europe) is the leading European event covering the application of languages, tools, and intellectual property for the design and verification of electronic systems and integrated circuits. Sponsored by Accellera Systems Initiative, DVCon Europe brings chip architects, design and verification engineers, and IP integrators the latest methodologies, techniques, applications, and demonstrations for the practical use of EDA solutions for electronic design.
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The Development and Evolution of Verilog & SystemVerilog
2024-10-10 11:00 - 12:00 (America/Los_Angeles)
Abstract:
SystemVerilog is a super next-generation Verilog with a fancy marketing name. SystemVerilog leveraged many of its features from other languages and methodologies. Class-based capabilities, constrained random testing (CRT), and functional coverage were all features that were added to SystemVerilog and incorporated into the Universal Verification Methodology (UVM). UVM has become the most dominant and powerful verification methodology used to verify designs by engineers today.
Cliff Cummings has been a member of the Verilog & SystemVerilog Standards Groups since 1994 and will offer his unique and historical perspective on how features were added to SystemVerilog, why the features were added, and the origins of many of those features.

Agenda:

Verilog HDL and Its Ancestors and Descendants (reference paper)
Brief History of Verilog & SystemVerilog
HILO, Verilog, C, PLI
SDF, Synthesis, VHDL, VPI
Superlog, IHDL (Intel), SystemC, Vera
OOP, e-Specman, SystemVerilog, C++
OVL, PSL, SVA
OVM / UVM history
Simulation & Functional Coverage
Q&A

Webinar Duration

45 min presentation/live demo
15 min Q&A

Bio:
Clifford E. Cummings,
Vice President of Training at Paradigm Works and Founder of Sunburst Design
Cliff Cummings is Vice President of Training at Paradigm Works and Founder of Sunburst Design. Cliff teaches world-class SystemVerilog, UVM, CDC and synthesis training classes. Cliff has 42 years of ASIC, FPGA and system design experience and 32 years of combined Verilog, SystemVerilog, UVM verification, synthesis, and methodology training experience. Cliff has taught expert Verilog, SystemVerilog, Design Synthesis, CDC and UVM Verification to thousands of engineers world-wide and has presented more than 50 papers on these topics. Cliff holds a BSEE from Brigham Young University and an MSEE from Oregon State University.
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Cocotb 2.0: Modernize your testbenches for even more productivity
2024-10-08 12:00 - 13:00 (Europe/London)
Cocotb 2.0 is the latest major version of cocotb, ironing out many quirks that have accumulated over the years. With only small changes to your testbenches, you can benefit from improved typing and less surprising corner cases. In this talk, we’ll show what’s new in cocotb 2.0, and how you can modernize your code bases to make best use of it. We also have a presentation from a cocotb user performing HDL simulation with python cocotb, with a Transaction Level Modelling (TLM) approach with a completely free and open source chain (GHDL simulator and WSL Linux).

Agenda (BST):

Time
Session Description
Slides
Videos

12.00 BST
Welcome and Introduction
Mike Bartley,Tessolve

12.00 BST
Simple yet powerful: Open-source HDL simulation with Cocotb
Hayder Al-Hakeem ( Wärtsilä Finland)

12.30 BST
Cocotb 2.0: Modernize your testbenches for even more productivity
Philipp Wagner ( FOSSi Foundation)

13.00 BST

Close

About DVClub

The principal goal of each DVCLUB meeting is to have fun while helping build the European verification community through regular educational and networking events. Attendance at DVClub Europe meetings is free and is open to all non-service provider semiconductor professionals. Each meeting addresses a specific issue faced by the design and verification community and whatever your speciality provides an excellent opportunity for updating knowledge as well as share experiences, insights and issues with other members of the verification community.

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Accelerating DFT verification sign-off with the Questa DFT Verification Platform
2024-10-08 10:00 - 15:00 (America/Los_Angeles) | Siemens EDA, 46871 Bayside Parkway, Building B, Fremont, CA, United States
Accelerating DFT verification sign-off with the Questa DFT Verification Platform
This seminar will update you on technologies and techniques you can adopt to increase your DFT verification productivity today. Specifically, we will cover:
‌
Navigating the Growing Complexity of Design-for-Test and Evolving Verification Challenges
Revolutionizing Test Strategies to deliver reliable products into HPC, Automotive, Aerospace, Medical, and beyond
‌
Agenda:
10:00 am – 10:25 am
Registration and check-in
Coffee and networking with your peers.
‌
10:25 am – 10:30 am
Welcome/Intro
Harsh Patel | Sr. AE Manager, Functional Verification
‌
10:30 am -11:15 am
Understanding and navigating the new challenges in Design-for-Test
Lee Harrison | Director of Product Marketing -Tessent
‌
11:15 am – 12:00 noon
Accelerating verification closure with Siemens DFT tailored verification solutions
Jake Wiltgen | Director, IC Verification Solutions
‌
12:00 noon – 12:30 pm
Lunch and networking
‌
12:30 pm – 1:15 pm
Embracing a New Era in DFT: Addressing High Defect Coverage, Silent Data Errors, and Emerging Challenges
Lee Harrison | Director of Product Marketing -Tessent
‌
1:15 pm – 2:00 pm
Increasing fault coverage with Siemens Functional Fault Grading solutions
Ann Keffer | Product Manager
‌
2:00 pm – 3:00 pm
Wrap-up and networking
We look forward to seeing you!
‌
Siemens Advanced Functional Verification Team
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PCB West 2024
2024-10-08 08:00 - 2024-10-11 17:00 (America/Los_Angeles) | Santa Clara Convention Center, 5001 Great America Parkway, Santa Clara, CA, 95054, United States
For more than 30 years PCB West has trained designers, engineers, fabricators and, lately, assemblers on making printed circuit boards for every product or use imaginable. More than 2,000 designers, fabricators, assemblers and engineers register and more than 100 companies exhibit each year at the four-day technical conference and one-day sold-out exhibition. From high-reliability military/aerospace to cutting-edge IoT and wearables, there’s something for everyone involved in the electronics supply chain. This is one show you cannot afford to miss.
Brought to you by PCEA: Engineering Tomorrow’s Electronics!
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AutoSens Europe 2024
2024-10-08 08:00 - 2024-10-10 17:00 (Europe/Madrid) | Palau de Congressos, Av. de la Reina Maria Cristina, Barcelona, Spain
Join us as we embark on an exciting new journey in the vibrant city of Barcelona!

From 8-10 October 2024, we will unite the AutoSens community at the Palau de Congressos in Barcelona to shape the future of ADAS and AV.
Expect over 60 expert speakers, engaging panels, technical case studies, and exploration of 12 key themes. Dive into an exhibition with cutting-edge demos from sensor and computer vision leaders.
Don’t miss AutoSens Europe 2024 in Barcelona – the future of sensing tech awaits!

Discover the latest technology

From innovative start-ups to industry giants, the AutoSens exhibition floor is where our community comes together to make key connections over coffee, have critical conversations in our igloo meeting pods, and negotiate new partnerships over drinks at our networking sessions.
Register now to make the most of:

Access to an expert community of over 500 experts and engineers

Extensive exhibition with over 50 stands showcasing the latest technology

Vehicle demos from leading Tier 1 and systems companies

High quality technical presentations from genuine experts

Thought-leader panel discussions that shape the industry’s future direction

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Signoff Special Interest Group
2024-10-03 11:30 - 17:00 (America/Los_Angeles) | Santa Clara Marriott, 2700 Mission College Blvd, Santa Clara, CA, 95054, United States
Join us at this year’s Synopsys Signoff SIG (Special Interest Group) event.
Signoff is a critical quality control checkpoint in the chip development process, but design complexity and advance process nodes are pushing the boundaries of what is expected of signoff solutions. Meeting these scaling challenges is becoming more difficult. At this year’s Synopsys Signoff SIG event, we’ll explore how signoff can help meet these scalability challenges. We’ll here from several industry-leading companies how they are using the latest technology advances in timing, power, extraction, and eco to realize the full PPA potential of their designs with the fastest path to design closure.

Agenda

More details coming soon.

Thu. October 03, 2024
11:30 – 12:30 PM PDT

Registration Check in & Lunch

Badge pick-up begins at 11:30. Lunch will be served, come early for a chance to eat and network before sessions begin.
Read Less

Thu. October 03, 2024
12:30 – 01:15 PM PDT

Keynote

Thu. October 03, 2024
01:15 – 04:05 PM PDT

Technical Sessions

Thu. October 03, 2024
04:05 – 05:00 PM PDT

Networking Reception

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VC Formal Special Interest Group
2024-10-03 09:00 - 17:00 (America/Los_Angeles) | Santa Clara Marriott, 2700 Mission College Blvd, Santa Clara, CA, 95054, United States
Register for the Synopsys VC Formal Special Interest Group (SIG) event today. This event provides an opportunity for users, managers, and enthusiasts to stay connected with the latest formal verification innovations, techniques and methodologies.
Industry leaders such as Amazon, Black Sesame, Microsoft, NVIDIA, Samsung, and Untether AI will share their experiences with the latest formal verification technologies. Topics that will be covered include strategies for achieving formal convergence, exploring formal methodologies used for RISC-V verification, and the integration of VC Formal with generative AI functionalities – which offer the potential to automate the creation of formal verification testbenches.
Keynote Session

The Impact of LLMs on Formal Verification
Explore how LLMs can transform formal verification, reducing manual effort and improving results. We’ll discuss current benchmarks and future goals for deploying LLMs to enhance formal verification processes.
Presented by Syed Suhaib, NVIDIA
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Electronic Design Process Symposium (EDPS) - 2024
2024-10-03 08:00 - 2024-10-04 17:00 (America/Los_Angeles) | SEMI, 673 S. Milpitas Blvd, Milpitas, CA, United States
EDPS 2024 is now taking shape. The place to be is once again SEMI, in Milpitas, and the dates are Thursday and Friday, Oct 3rd and 4th, 2024.
Registration is now open: https://2024-ieee-edps.eventbrite.com. Who needs to register? Please see the Registration page.
Talks from EDPS 2023 and the last 24 years of EDPS, are are available and searchable, on the Prior Years page.
Day 1, Thursday 9:00am; Session 1
9:05am

Energy and Thermal Management of Chips, Systems and Datacenters Necessitates a Return to Fundamentals
Chandrakant Patel
HP

The latter part of 20th century witnessed the rise of the compute utility made up of large-scale data centers housing densely packed compute, storage and networking equipment. The cyber age data centers became modern day factories requiring megawatts of power for the information technology (IT) equipment much like the process equipment in a factory of the machine age. Electrical energy supplied to the chips and systems in the data centers turned into multi-megawatts of heat energy which in turn required heat removal means. The active heat removal means also required power. While many innovative measures have been used for heat removal and energy management in data centers, there is a substantial gap in application of fundamentals of engineering when compared to the approaches taken by the contributors of the 19th and early 20th century machine age. As an example, machine age contributors performed exergy (2nd law of thermodynamics) analysis and deemed it necessary to build a hydro-electric plant as part of the design of an Aluminum factory. Indeed, majority of data centers today rely on the power infrastructure built by our predecessors. Given the inexorable trajectory of data centers strongly driven by AI, and associated demands on available energy, it is time we returned to such fundamentals particularly given the environmental challenges.
In my talk, I will present a holistic approach that traces the energy flow from a power plant to a chip, and from the chip core to the cooling tower.
10:00am

Enabling Effortless Machine Learning for Embedded Edge Applications
Gopal Hegde
SiMa.ai

Machine Learning is a game changing technology of our generation and similar Internet in the 1990s, will impact every aspect of our life. While Machine Learning use cases and applications are well established in the cloud & IoT devices, in the embedded edge market, its usage is in its infancy. We at SiMa.ai are focused on disrupting this market by turbo charging embedded compute with the addition of machine learning. Embedded edge has space and power constraints and has a huge expertise gap relative to cloud computing when it comes to machine learning. The presentation covers market requirements, key challenges and our unique software first approach to machine learning at embedded edge. We will discuss key market segments, their unique requirements and how our silicon and software solutions provide a way for our customers to easily develop and deploy machine learning solutions that address their use cases and applications.
10:35am

AI: Trailblazing the Next Generation of Semiconductor Innovation
Vishal Khandewal
Synopsys

With AI-based applications coming pervasively mainstream through ChatGPT, digital healthcare, and almost everything else we do with our devices daily, digital chip design is seeing an exponential push towards complexity, performance, power, and time-to market. EDA tool flows are becoming mission critical to meet the demands of a hardware-led 4th industrial revolution that is driving everything towards being intelligent, connected, monitored and data-driven. In this talk we go into the details of how hardware design and EDA tools are evolving to deliver the next generation of performance, power, and productivity (PP&P) boost. Even with exponential growth in design productivity in the past decade, overall design cycle is not meeting its intended targets. The technical complexity of advanced node design with new dominant effects like thermal and IR, are leading to highly complex tool/methodology flows. This is where at Synopsys, we have taken a full tool-stack approach to build pervasive AI into our tools to deliver unprecedented PP&P boost. We will share examples of applications ranging from design implementation, verification, test, and analog/manufacturing to showcase the potential of this technology and how it is reshaping chip design workflows. Many of these technologies are taking us closer to the no-human-in-the-loop goal for chip design. With serious talent shortage and increase in solution complexity beyond human expertise, AI-augmented solutions for chip design are the way forward.
11:10am

Harnessing LLMs for Advanced EDA Platforms: Code Generation and Beyond
Akhilesh Kumar
Ansys

Large Language Models (LLMs) such as GPT-4, Gemini, Llama etc., have demonstrated astounding capabilities in a range of tasks such as knowledge extraction, Q&A, summarization, code generation, contextual problem solving etc. The LLMs can also be adapted to specific applications through a variety of methods such as fine tuning, in-context learning, RAG, agent-based systems etc., making them quite versatile.
Modern EDA platforms, such as Ansys SeaScape, have sophisticated workflows, hundreds of user APIs, complex input data requirements, and require deep domain knowledge and expertise for efficiently using the platform. This talk will discuss how LLMs can greatly improve the productivity and user experiences for such EDA platforms. The talk presents an overview of code generation techniques using LLMs and will discuss our experience in developing an LLM-based code generation solution for the Ansys SeaScape platform. Going beyond the code generation, this presentation will discuss creating an LLM agent-based copilot for providing intuitive assistance to the users of the Ansys SeaScape platform for a variety of operational modalities.
12:45pm

The Application of AI to Chip Design
Mark Ren
NVidia

The applications of AI in chip design undergo an evolutionary path.
Inspired by the success of AlphaGO, Reinforcement Learning techniques were deployed to a number of design problems, achieving results showing the potential of AI.
The advancement of Large Language Models further enabled the application of AI in a much broader set of design activities.
LLM-based copilots can improve design productivity by providing knowledge and coding assistance; agents can provide further assistance in key design tasks such as analysis, debugging, and optimization.
The evolution of AI will continue, and we will discuss critical challenges to realizing its revolutionary potential in the chip design process
1:35pm

How AI is changing every aspect of EDA, starting from transistor-level simulation
Sathishkumar Balasubramanian
Siemens

There is a lot of hype in the industry around AI, but behind the hype there is the reality. That reality is that AI really is impacting virtually every aspect of semiconductor design. However, its not as simple as taking general purpose AI solutions and hoping they work for EDA, the risks are too high and when dealing with parts per billion (or trillion) in acceptable errors, hallucinations are not acceptable. What is needed are Verifiable AI solutions that deliver results that users can trust and that reduce the overall resources needed to complete a task. At Siemens EDA we have been able to leverage Verifiable AI to accelerate virtually every aspect of the design and verification process.
In this presentation we will explore the requirements for, and state of the art of, AI in EDA application. We will explore AI’s impact on every aspect of design starting from transistor-level simulation.
2:10pm

Test, Repair and Reliability Challenges of Chip-let Interconnects
Sreejit Chakravarty
Ampere Computing

Chip-let based design, fueled by various advanced packaging technologies, is projected to revolutionize the semiconductor industry. This brings along with it associated challenges to achieve adequate yield and aging related reliability issues. This talk will present manufacturing defect profiles associated with advanced packaging; the test and repair requirement, during high volume manufacturing, to achieve adequate yield; and challenges associated with latent defects leading to aging related field failures. RAS solutions required to address such reliability issues are highlighted.
2:45pm

Artificial Intelligence and Machine Learning for RF and Microwave Design
Jianjun Xu
Keysight

This talk reviews some powerful and practical Artificial Intelligence and Machine Learning (AI/ML) technologies for applications in traditional RF and Microwave design and beyond. After a very brief overview of the AI/ML landscape, we focus on Artificial Neural Networks (ANNs) and provide several key examples of modern ANN applications to electronic, electro-thermal, and electro-chemical device modeling, and behavioral modeling to illustrate the substantial benefits and generality of present techniques.
The talk concludes with a discussion of the potential of AI/ML technologies to address and solve future challenging and important RF and Microwave design problems, e.g., for 6G.
3:30pm

Promises and Challenges of Digital Twin for Semiconductor Manufacturing
Ala Moradian
Applied Materials

The advancement of cutting-edge technologies like Artificial Intelligence (AI), Large Language Models (LLM), and Electric Vehicles (EV) demands sophisticated semiconductor devices with precise specifications.
Concurrently, the emergence of digital twins and AI stands as pivotal in facilitating the development and enablement of such technologies.
This talk delves into the vision and significance of AppliedTwin(tm), a proposed digital twin framework tailored for semiconductor manufacturing.
AppliedTwin delineates various levels of abstractions ranging from digital fabrication facility down to digital twin of individual devices, each characterized by distinct attributes governing their interaction with physical assets, fidelity, etc.
Applied Materials has spearheaded the application of digital twins in semiconductor manufacturing with the introduction of EcoTwin(tm), a platform designed to promote sustainability.
In this talk the critical role of digital twins in propelling innovation and efficiency in semiconductor equipment manufacturing.
4:05pm

Making Data Center Digital Twins a Reality
Paul Harrison
Cadence

This talk will discuss the application of Digital Twins to Data Centers.
Historically decisions for data center operations were made based on rules of thumb or the person who would most confidently put across their point of view.
Cabinet power densities continue to rise, accelerated by AI, increasing the need complex technologies like liquid cooling to be more widely implemented. This means data center operations have become more difficult to manage, while the impact of their downtime can be catastrophic for companies. Fortunately, data center operators are starting to adopt CFD-based Digital Twins to help inform their operational decisions, improve their understanding, and reduce the risks. This talk will explain how to create a Data Center Digital Twin, some of the challenges with creating them, how they integrate with data sources and existing processes, and the benefits to operators this technology brings.
4:40pm

Innovating Semiconductor Manufacturing with ML-augmented Digital Twins
Norman Chang
Electronics, Semiconductor, and Optics BU, Ansys

Developing each processing step in semiconductor manufacturing has heavily relied on in-situ sensors in the equipment and numerous try-outs in recipe generation. However, with advancements in multiphysics simulation technologies, an innovative ML-augmented hybrid simulation methodology has been developed. This methodology combines the strengths of multiphysics simulation and in-situ measurement in building semiconductor processing digital twins. In this talk, we will review the current state-of-the-art digital twin technologies and identify the gaps that need to be addressed to fully utilize digital twins in developing new process recipes in semiconductor manufacturing.
6:45pm

Semiconductors and Artificial Intelligence:The Virtuous Cycle
Pushkar Apte
SEMI

Artificial Intelligence (AI) has taken the world by storm, and has become a strategic imperative for most industries. While the concept of AI is over half a century old, it has accelerated rapidly just over the past decade, in large part due to amazing advances in semiconductor chips. In turn, AI is driving growth in semiconductor revenues and improvements in operational efficiency, creating a virtuous cycle.
However, there are formidable roadblocks ahead. AI models and datasets are growing at an exponential rate, far outpacing hardware advances – creating both performance and sustainability challenges. System-level innovation is required for continued progress in AI, which requires meaningful collaboration and data-sharing – often difficult in an industry where IP is critical.
This presentation will focus on this virtuous cycle between semiconductors and AI, highlighting the benefits, challenges and solution paths for continued progress.
Day 2, Friday 9:00am; Session 1
9:05am

Is AI intelligent?
Ronjon Nag
Stanford Medicine

Artificial intelligence is in the news daily, and people ask whether they are truly intelligent.
Maybe it still lacks the depth of human intelligence today, but where is already cleverer, and what stops it from reaching the ultimate pinnacle of ”general intelligence” – could that ever be possible? We will consider the implications of creating truly intelligent machines and the potential consequences for human society.
10:00am

Trust Based Modeling for Improved Security
Naresh Sehgal
Deeply Human AI

The present state of Edge Computing is an environment of different computing capabilities connected via various communication paths. Actors on the Edge may interact with each other and a central datacenter. An important part of information security is the evaluation of trust between actors, whether those actors are people or machines. Although many distributed trust models exist, our proposed model introduces three key concepts. The first concept is that trust is not bidirectional between two parties. The second concept is that trust is different between different actors, based upon the nature of their relationships. The third concept is that trust depends on the content of a transaction. We will present some real-life examples to illustrate these concepts.
10:35am

Advancing Hardware Security in the Post-Quantum Cryptography Landscape: Challenges and Solutions
Qian Wang
U. Cal. Merced

Hardware security in the era of post-quantum cryptography has become increasingly crucial due to the potential threat quantum computers pose to traditional cryptographic algorithms. Post-quantum cryptography aims to develop cryptographic algorithms that are resistant to attacks from quantum computers. However, ensuring the security of these algorithms requires not only advancements in software but also robust hardware security measures. In this talk, we will first discuss the implementation of quantum-resistant cryptographic modules on hardware platforms, necessitating upgrades in both hardware and firmware to accommodate new algorithms efficiently. Moreover, hardware implementations of cryptographic algorithms are vulnerable to side-channel attacks, where an attacker exploits information leaked through physical characteristics such as power consumption or electromagnetic radiation. Post-quantum cryptographic hardware must incorporate countermeasures to mitigate these risks.
11:20am

Scaling to Meet the Needs of AI
Pradeep Dubey
Intel

Artificial intelligence (AI) is impacting not just what computing can do for us, rather how computing gets done. Fast-evolving AI algorithms are driving demand for growing performance at an unprecedented rate and scale. This talk is about some of our research aimed at exploring technological and system-level opportunities for cost-effective scaling of emerging AI datacenters.
1:00pm

The Future of Generative AI: Key Technology Trends and Innovations
Shiva Kintali
R3AI

LLMs have emerged as powerful tools, revolutionizing various domains from natural language processing to content generation, but beneath their remarkable capabilities lie intricate challenges and perils that demand our attention.
While they offer convenience and productivity, we dissect how they can also be manipulated and weaponized by malicious actors, raising concerns about inherent biases, jailbreaking potential, security concerns, privacy issues, misinformation, deepfakes, cyber threats and their unsettling societal consequences. We explore how biases present in training data, historical injustices, and societal prejudices can be perpetuated and even amplified by these models, posing a significant threat to fairness, equity, and inclusivity.
This talk is aimed at raising awareness and engage the audience in a critical dialogue on these multifaceted challenges posed by LLMs. By understanding these challenges, we can collectively work towards harnessing the power of these models for the betterment of society while safeguarding against their unintended consequences.
1:35pm

Emerging Technologies for Computing Paradigm Shift
Brandon Wang
Synopsys

The explosive growth of AI has triggered a rapid increase in semiconductor demand, leading to soaring power consumption and unsustainable water usage. This presentation will explore emerging technologies essential for driving a paradigm shift towards energy-efficient computing. Topics will include the “Shift Left” design methodology, the impact of SLMs (Small Language Models) on computational efficiency in AI, and the potential of neuromorphic and quantum computing as next-generation architectures. These advancements are poised to enable significant digital transformation and drive pervasive intelligence across various industries. The speaker will also provide insights into how organizations can stay at the cutting edge of these innovations, offering a forward-looking perspective on the future of computational systems and the strategic steps needed to lead in this rapidly evolving landscape.
2:10pm

TBD
Chris Cheng
Hewlett-Packard Enterprise

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Redefining Mobile Experiences with AI - Session 2
2024-10-02 09:00 - 10:00 (America/Los_Angeles)
The Arm platform is providing the foundation for the next wave of AI smartphones and laptops. As AI models rapidly evolve, we’re seeing that software begins to outpace hardware, requiring additional innovation at all levels of the compute stack.
To meet these growing demands, the Arm platform offers a new compute solution for maximum performance and efficiency, on leading process nodes. Join this webinar series to learn more about this solution, including the latest Arm Armv9 CPUs and GPUs, the benefits and opportunities of running AI on device, and how to innovate and speed time to market.
The CPU Cluster on Wednesday, Oct 2, 2024

9:00 a.m. BST / 4:00 p.m. Beijing
5:00 p.m. BST / 9:00 a.m. PT

This webinar covers:

An overview of Arm’s most performant, efficient, and versatile CPU cluster based on the Armv9 architecture for maximum performance and power efficiency.
Features, benefits, and performance enhancements of Arm Cortex-X925, Cortex-A725 CPU, Cortex-A520 CPU and Arm DSU-120.
How this CPU cluster can improve consumer experiences on mobile devices.

Speaker: Manish Pandey, Senior Product Manager, Arm
First Session – September 18th
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Memory Users Conference 2024 - China, Taiwan
2024-10-02 08:00 - 17:00 (Asia/Taipei)
Advancements in memory technology are fueling rapid growth in big data applications across AI, 5G, Automotive, and HPC. These demanding applications create many challenges for memory designers. Some long-standing challenges are exacerbated, while the latest technology nodes have introduced some new ones. At Synopsys, there is a corporate-wide commitment to developing broad-based solutions that address these challenges.

Why Attend?
Memory vendors are accelerating the shift to next-generation HBM and new memory architectures to cater to the insatiable demand for high bandwidth, high performance memories driven by AI applications.
These next-generation designs pose many challenges for memory designers. Some long-standing challenges have been exacerbated, and some new ones have been introduced.
The Synopsys Memory Users Conference aims to provide a forum for memory companies and Synopsys experts to share their perspectives on ways to address the industry’s most compelling and topical challenges. Drop in to learn more

Agenda At-a-Glance

Learn more about the themes we will explore during this virtual event. More information around sessions are being confirmed daily, so be sure to check back often for new information.

Time
Topic

08:00 am
Opening Keynote

08:30 am
Accelerating the Path from Technology Development to High-Volume Manufacturing
with participation of Western Digital

09:00 am

09:30 am
Solving “Unsolvable Problems” in Memory Design & Verification
with participation of Samsung

10:00 am

10 Minute Break

10:40 am
Accelerating SoC Development with Memory IP
with participation of STMicroelectronics and Weebit Nano

11:10 am

11:40 am
Ensuring Memory Reliability for Mission Critical Applications

12:10 pm

12:40 pm
Industry Panel

Virtual Event

October 1st, 8:00AM PST
October 2nd, 8:00AM GMT +8

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Interactive SPICE Model Verification Platform ME-Pro
2024-10-01 11:00 - 11:30 (America/Los_Angeles)
ME-Pro™ is a unified tool for designers, process developers, modeling engineers, and PDK engineer providing robust simulation and analysis capabilities for semiconductor device model verification and evaluation.
This comprehensive platform supports evaluation across device, circuit, and process domains enabling interactive development and offering critical feedback for process improvements. With decades of Primarius’ expertise, ME-Pro™ features pre-configured templates, hundreds of verification data entries, and the built-in NanoSpice parallel simulator that is all designed to streamline setup and reduce learning curves.
Presenter
Erik Supnet is a Senior Application Engineer at Primarius for two years supporting pre-sales and post-sales activities for modeling and simulation products. He earned his B.S. in Computer Engineering and M.A in Education at the University of the Pacific. Prior to his current role, he held design engineering positions as D.E.C, SiByte, Broadcom, and Intel, and has a background in custom circuit design, automation, methodologies, and education.
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