Marketing EDA

GTS 2023 - Munich
2023-09-27 08:00 - 2023-09-28 17:00 (Europe/Berlin) | Sofitel Munich Bayerpost, Bayerstrasse 12, Munich, 80335, Germany
Register now and join us at GlobalFoundries Technology Summit 2023!
GF Technology Summit (GTS) 2023 is our worldwide, annual series of technology-focused events. GTS brings together leaders from the commercial, business and research worlds to understand the latest technology challenges and opportunities, and partner to create the most innovative applications and solutions.
GTS 2023 Highlights
This year’s GTS will focus on GF’s industry and technology differentiation, highlighted by three key areas of innovation:

Power, power, power – Ultra-low power technology platforms and applications, power management and power delivery solutions
Best RF wins – RF and mmWave connectivity solutions for mobile and infrastructure applications
Intelligence & security – Localized, low-power intelligent applications with secure eNVM

GF’s market-focused development includes partnerships across the broad electronics ecosystem – OEM, fabless, OSAT, EDA and IP. The results of those collaborations will be seen and heard in the guest keynote addresses, detailed technology roadmaps, hardware and software demonstrations, and leading applications for automotive, IoT, smart mobile, datacenter and communications infrastructure markets.
New in 2023! GF Technology, Business and Commercial teams will be at GTS to host 1:1 and small group meetings during the event. Please consider if there is someone you would like to meet with during your time in Munich – requests will be submitted during the registration process.

GTS Program Overview
Day One Programming: 12:00 – 16:00 Networking Hour to follow
CEO Dr. Thomas Caulfield, joined by leaders in the fabless semiconductor and end-markets industries, shares GF’s corporate vision and roadmap of manufacturing the essential chips we rely on for life, work and connection.
Day Two Programming: 9:00 – 14:00 with Networking Reception to follow
GF’s technology and product management leaders share the company’s detailed technology and solutions roadmap, joined by leaders in the semiconductor design and manufacturing ecosystem – working together to deliver a new era of more.
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Synopsys VSO.ai Virtual Workshop
2023-09-27 09:00 - 13:00 (America/Los_Angeles) | CA
Virtual workshop with hands-on labs
Achieving coverage closure continues to remain a challenge for customers and there is a growing need for a system to work autonomously to reach the target as quickly and cheaply as possible with the highest quality of results. The recently released Synopsys VSO.ai address this challenge in addition to inferring coverage from RTL and finding bugs.
In this hands-on half day virtual workshop you will learn:
The different components of Synopsys VSO.ai
The value proposition demonstrated at customers
Upcoming technologies
These technologies are natively integrated with VCS, the industry performance leader, and will be presented by Synopsys Verification experts.
Attendees will gain hands-on experience in live labs and walk away with the confidence to use this technology in your current projects. Lab participation will be limited.
Workshop Agenda
PacificTime

Time
Session

9:00 – 9:15 a.m.
Overview of coverage closure

9:15 – 10:00 a.m.
Regression optimization

10:00 – 10:45 a.m.
Lab 1

10:45 – 11:00 a.m.
Break

11:00 – 11:45 a.m.
Coverage directed solver

11:45 a.m. – 12:30 p.m.
Lab 2

12:30 – 12:45 p.m.
Roadmap

12:45 – 1:00 p.m.
Wrap-up + Q&A

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TSMC 2023 North America OIP Ecosystem Forum
2023-09-27 09:00 - 17:00 (America/Los_Angeles) | Santa Clara Convention Center, 5001 Great America Parkway, Santa Clara, CA, 95054, United States
Learn About:

Emerging advanced node design challenges and corresponding design flows and methodologies for N2, N3/N3E/N3P/N3AE, N4/N4P, N5/N5A, N6/N6e/N6RF/N7, N12e, and N22
Latest updates on TSMC 3DFabric™ chip stacking and advanced packaging processes, InFO, CoWoS®, and SoIC, 3DFabric Alliance, and 3Dblox™ standard, plus innovative 3Dblox-based design enablement technologies and solutions, targeting HPC, AI/ML, and mobile applications
Comprehensive design solutions for specialty technologies enabling ultra-low power, ultra-low voltage, analog migration, RF, mmWave, and automotive designs targeting 5G, automotive, and IoT designs
Ecosystem specific TSMC reference flow implementations, P&R optimization, machine learn-ing to improve design quality and productivity, and cloud-based design solutions
Successful , real-life applications of design technologies and IP solutions from TSMC’s Open Innovation Platform® Ecosystem members and TSMC customers to speed up time-to-design and time-to-market

For more information on the TSMC OIP Ecosystem Forum, e-mail us at: tsmcevents@tsmc.com.
We look forward to seeing you at the 2023 TSMC OIP Ecosystem Forum!
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Cadence Training: Cerebrus Intelligent Chip Explorer
2023-09-27 10:00 - 11:00 (America/New_York) | CA
Please join me, Cadence Training and Application Engineer Krishna Atreya, for this free technical Training Webinar.
What Is the Webinar About?
The Cadence Cerebrus Intelligent Chip Explorer is a revolutionary, machine learning-driven, automated approach to chip design flow optimization. Block engineers specify the design goals, and Cadence Cerebrus intelligently optimizes the Cadence digital full flow to meet power, performance, and area (PPA) goals in a completely automated way—letting engineers concurrently optimize multiple block flows, which is particularly important for the large, complex system-on-chip (SoC) designs needed for today’s ever more powerful electronic systems.
We’ll dive into:

Understanding the Cadence Cerebrus flows
Understanding flow wrapping
Flow wrapping your design for Cadence Cerebrus readiness

When Is the Webinar?
Wednesday, September 27
07:00 PDT San Jose / 10:00 EDT New York / 15:00 BST London / 16:00 CEST Berlin / 17:00 IDT Jerusalem / 19:30 IST Bangalore / 22:00 CST Beijing
To register for the “Flow Wrapping: The Cadence Cerebrus Intelligent Chip Explorer Must Have” webinar, use the REGISTER button below and sign in with your Cadence Support account (email ID and password) to log in to the Learning and Support System. Then select Enroll to register for the session. Once registered, you’ll receive a confirmation email containing all login details.
REGISTER
If you don’t have a Cadence Support account, go to Registration Help or Cadence User Registration, and complete the requested information.
For questions and inquiries or issues with registration, reach out to eur_training@cadence.com
Keep up with the revolution! Join Cadence’s Cerebrus Intelligent Chip Explorer Training and learn how to use Cadence Cerebrus to scale and automate your design, improve your productivity, and much more.
The online class is free for all Cadence customers with a Learning and Support account.
We can also organize this Cadence Cerebrus Intelligent Chip Explorer Training for you as a “Blended” or “Live” training. Please reach out to Cadence Training for further information.
You can also enjoy this video to get a first impression what is waiting for you!
Want to share this and other great Cadence learning opportunities with someone else? Tell them to subscribe.
Hungry for Training?
Choose the Cadence Training Menu that’s right for you. To view our complete training offerings, visit the Cadence Training website.
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Stratus HLS Automated Power Shutoff to Minimize Power and Retention Registers
2023-09-27 12:00 - 13:00 (America/Los_Angeles) | CA
Power Shutoff is a popular technique for saving power during functionally idle periods. Implementing Power Shutoff requires a detailed understanding of which resisters must be retained to enable bring-up from the power-off state. Identifying the minimal set of retention registers is challenging and grows more difficult with design complexity.

This CadenceTECHTALK introduces a novel High-Level Synthesis-based solution for the automated implementation of Power Shutoff. This solution automatically identifies and implements Power Shutoff using the minimal set of retention registers, yielding the lowest leakage power and saving weeks of implementation time vs. manual methods.

Join this webinar to learn how to apply this technology to your own design and interact with product experts who will demonstrate the technology in a real-world testcase. Design engineers working on low-power digital IC designs or algorithms will benefit from this TECHTALK.
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FPGA Design Verification - Advanced Testbench Implementation
2023-09-28 11:00 - 12:00 (America/Los_Angeles) | CA
Abstract
As FPGA technology continues to evolve – to provide us with full-blown SoCs with CPU, GPU, and high-speed peripherals, for example, joining the traditional programmable logic area – design verification becomes increasingly challenging. Lab-based FPGA testing and bring-up alone are clearly insufficient, especially for safety-critical designs, and FPGA teams are adopting advanced design verification methodologies and techniques to develop homegrown verification processes.

In this three-part webinar series, we will discuss design verification with a focus on creating an advanced simulation-based verification process; from verification planning and team organization, and moving on to regression setup, functional coverage collection, randomization and ‘verification done’ definitions. We will also show you how to develop simple yet powerful and reusable testbenches using Verilog and SystemVerilog constructs and how to functionally verify designs in the most efficient way.

In part 2 of this webinar series, we will show you important verification patterns providing solutions to repeatable randomization, error management and end-of-test checks. We will also provide an overview of how to define, develop and re-use verification components such as drivers, responders, and monitors. Then, we will talk about how to develop testbenches, and how to validate their correctness with reporting and statistics collection. We will provide code examples to illustrate the topics of discussion.

Agenda:

Common Verification Patterns:
o Repeatable Randomization
o Reporting, Error management
o End-of-Test Procedure
Verification Components (VC) Development:
o Verification Component Types
o Defining Transactions for VC Development
o Legal and Error Operation Modes
o Controllable Randomization
o Verification in Standalone Testbenches
Testbench Development and Verification:
o Statistical methods for Testbench Validation
o Scripting Support
Demo with example design and testbench
Conclusion
Q&A

Webinar Duration:

45 min presentation/live demo
15 min Q&A

Presenter BIO
Alexander Gnusin, Design Verification Technologist, Aldec
Alexander Gnusin accumulated 27 years of hands-on experience in various aspects of ASIC and FPGA design and verification. As a verification prime for a multi-million gates project in companies such as IBM, Nortel, Ericsson and Synopsys Inc, he combined various verification methods such as static linting, formal property checking, dynamic simulation and hardware-assisted acceleration to efficiently achieve design verification goals. He received his M.S. in Electronics from Technion, Israel Institute of Technology.
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56th International Microelectronics Assembly and Packaging Society (IMAPS)
2023-10-02 08:00 - 2023-10-05 17:00 (America/Los_Angeles) | CA
This packed conference brings together industry engineers, researchers and top experts involved in advanced packaging and microelectronics assembly. IMAPS Symposium offers a robust technical program with 5 concurrent tracks and 100+ speakers and posters covering SiP Design / Manufacturing Optimization; Wafer Level / Panel Level (Advanced RDL); High Performance, High Reliability; Advanced Packages (Flip Chip, 2.5D, 3D, Optical); and Advanced Process & Materials.
Professional Development Courses are supplemental two-hour classroom-style tutorials with a narrow educational focus taught by the best in the industry. The topics offered at IMAPS 2023 are designed to help attendees broaden their scope of knowledge.
The 2023 PDC courses are offered on Monday, October 2, prior to IMAPS 2023. Attendees must register for each course as an add-on to their overall symposium registration – additional fee for each PDC selected. Attendees may select up to one course in each time slot. Make sure to review your preferred course’s time slot before registration.
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TSMC 2023 Europe OIP Ecosystem Forum
2023-10-04 08:00 - 17:00 (Europe/Amsterdam) | Hilton Amsterdam Airport Schiphol, Schiphol Boulevard 701 Amsterdam, Amsterdam, Netherlands

Verisium Debug for UVM Testbench
2023-10-04 11:00 - 12:00 (America/Los_Angeles) | CA
Verisium Debug offers comprehensive debugging capabilities. From RTL and UVM testbench to UPF low-power designs, Cadence’s unified debugging platform helps users debug. In this webinar, users will learn about the available features in Verisium Debug for UVM testbench and use these unique capabilities to visualize and debug the UVM testbench.
What you will learn

Understand the features available in Verisium Debug
​Learn about the UVM debug capabilities in Verisium Debug
Learn to debug UVM testbench using Verisium Debug

Who should attend

Design engineers
Verification engineers
CAD engineers

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EDPS 2023
2023-10-05 08:00 - 2023-10-06 17:00 (America/Los_Angeles) | Synopsys Building 1, 800 North Mary Avenue, Sunnyvale, CA, 94085, United States
EDPS 2023 is approaching fast! The program is firming up – please see the program page for a preliminary list of talks. REGISTRATION IS NOW OPEN. Everyone, including speakers, must register. 2023-ieee-edps.eventbrite.com
Note that this year we’ll be meeting on the Synopsys Campus.
Synopsys Building 1
800 North Mary Avenue
Sunnyvale, CA, 94085

Most of the talks from EDPS 2022 and the last 23 years of EDPS are now available, and searchable, on the Prior Years page.
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FPGA Design Verification - Advanced Methods
2023-10-05 11:00 - 12:00 (America/Los_Angeles) | CA
Abstract
As FPGA technology continues to evolve – to provide us with full-blown SoCs with CPU, GPU, and high-speed peripherals, for example, joining the traditional programmable logic area – design verification becomes increasingly challenging. Lab-based FPGA testing and bring-up alone are clearly insufficient, especially for safety-critical designs, and FPGA teams are adopting advanced design verification methodologies and techniques to develop homegrown verification processes.

In this three-part webinar series, we will discuss design verification with a focus on creating an advanced simulation-based verification process; from verification planning and team organization, and moving on to regression setup, functional coverage collection, randomization and ‘verification done’ definitions. We will also show you how to develop simple yet powerful and reusable testbenches using Verilog and SystemVerilog constructs and how to functionally verify designs in the most efficient way.

In this, the concluding episode of the webinar series, we will present advanced verification solutions for verifying complex design properties. We will talk about randomization, functional coverage, and the importance of code coverage to achieve overall design verification completeness. Also, we will provide an overview on other important topics such as assertion and transaction-based verification and debug, static design verification with linting tools and regressions support. Finally, we will talk about ‘Verification Done’, in terms of at what point can the verification be considered complete and how do we achieve it?

Agenda:

Checkers and Scoreboards Development
Randomization Methods
Functional Coverage and Tests Grading
Code Coverage
Assertion-based Verification
Transaction-based Debugging with Riviera-PRO
Static Verification with Linting tools
Setting up Regressions
Defining “Verification Done”
Packet-based Design Verification Example
Conclusion
Q&A

Webinar Duration:

45 min presentation/live demo
15 min Q&A

Presenter BIO
Alexander Gnusin, Design Verification Technologist, Aldec
Alexander Gnusin accumulated 27 years of hands-on experience in various aspects of ASIC and FPGA design and verification. As a verification prime for a multi-million gates project in companies such as IBM, Nortel, Ericsson and Synopsys Inc, he combined various verification methods such as static linting, formal property checking, dynamic simulation and hardware-assisted acceleration to efficiently achieve design verification goals. He received his M.S. in Electronics from Technion, Israel Institute of Technology.
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International Test Conference 2023
2023-10-08 08:00 - 2023-10-13 17:00 (America/Los_Angeles) | Disneyland Hotel, 1150 West Magic Way, Anaheim, CA, 92802, United States
International Test Conference, the cornerstone of TestWeek™ events, is the world’s premier conference dedicated to the electronic test of devices, boards and systems-covering the complete cycle from design verification, test, diagnosis, failure analysis and back to process and design improvement. At ITC, test and design professionals can confront the challenges the industry faces, and learn how these challenges are being addressed by the combined efforts of academia, design tool and equipment suppliers, designers, and test engineers.
ITC: A FORUM FOR EXCHANGE… THE HARBINGER OF CHANGE
In 1970, engineers facing the test challenges posed by the then-novel semiconductor memory device organized a symposium on IC testing. That meeting at the Rickshaw Inn in Cherry Hill, NJ drew a crowd of 147 people. That symposium is now a week-long conference attended by more than 2,000 engineers from around the world including sister ITC conferences in India and Asia.
In its fifty-year history, International Test Conference has become the world’s leading electronics test conference. No other industry has changed as much – or changed the world as much – in those fifty years as semiconductor technology. ITC has kept pace, always seeking to develop new and innovative ways to fulfill its primary objective: the exchange of technical information.
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CadenceLIVE Europe 2023
2023-10-10 08:00 - 2023-10-11 17:00 (Europe/Berlin) | Holiday Inn Munich – City Centre, Hochstraße 3, Munich, 81669, Germany
CadenceLIVE Europe 2023 – experience the power of intelligent system design – brings together users, developers, and industry experts to network, share ideas, and inspire design innovation in the most complex electronics and intelligent systems. The event features peer presentations that offer solutions for today’s design challenges that will impact tomorrow’s products.
Attendees will be able to attend captivating keynotes, watch user presentations packed full of innovation, see new product demos, and learn new ways to solve design challenges from industry leaders and Cadence experts.
Cadence® products, solutions, flow, and techniques will be featured at the conference in the following areas:

Multiphysics In-Design Analysis
Heterogeneous Integration
Custom IC / Mixed-Signal / RF
Digital Full Flow
PCB / Advanced Packaging
Verification Hardware and Software
Workforce Development

Cadence customers and partners can attend the event for FREE.
Check out the agenda to see what’s in store.
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Synopsys Verification Technical Symposium 2023 - Israel
2023-10-10 08:30 - 16:45 (Asia/Jerusalem) | Daniel Herzliya Hotel, Ramat Yam St 60, Herzliya, Israel
Join us for a day filled with insights, innovation, and networking in the semiconductor industry.
The verification landscape is evolving, and we’re here to help you navigate it. At this symposium, we’ll be going through some of the most challenging use cases in chip design today, while exploring best practices and the latest innovations for each use case.
Here’s what’s on the agenda:
– General sessions, including an Executive Keynote.
– Topics covering Power Efficiency, Protocols, and Cloud Solutions.
– Choose between two tracks: Software (simulation, static, formal) and Hardware (emulation and prototyping).
If you have any immediate questions, please feel free to reach out to us at verificationts@synopsys.com.
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Keysight EDA 2024
2023-10-10 10:00 - 11:00 (America/Los_Angeles) | CA
Shift Left to Raise Design Productivity
We’re ready to demo the latest release of our suite of electronic design automation (EDA) software tools so that you can learn how to increase productivity by shifting left your design process and product development cycles.
Four Tracks to Choose from
We’ll kick off each session with an overview of the Keysight EDA 2024 roadmap from VP and General Manager Niels Faché, and then you’ll pick the track you are most interested in for the highlights and demo videos.
Track 1: PathWave ADS for RF Circuit Design

See how faster EM solvers and streamlined, interoperable workflows accelerate complex module designs that integrate multiple technologies.
Learn how accelerated electro-thermal modeling and other new technologies reduce design risks and catch performance issues early.
See how expanded Python automation is not only transforming multi-technology workflows but also accelerating productivity for common design tasks, including new applications for PA designers.

Track 2: PathWave RF System Design

Learn how to analyze 5G NTN and DVB-S2/S2X scenarios with new RF link-level and channel-modeling simulation.
See how new phased-array simulations accurately model the load pull interaction between the power amplifiers and the active array impedance.
Learn how the RF System Explorer integrates circuit and system designs by enabling RF system engineers to share designs between RF system and circuit level design teams.

Track 3: PathWave ADS for High-Speed Digital Design

Learn how to design for the latest interconnect technologies (DDR5 and PCIe6) and investigate pathfinding for future technologies using an end-to-end simulation workflow for signal and power integrity.
See industry-leading capabilities to optimize signal and power performance, including multi-level modulations (PAM3/4), decision feedback equalization (DFE), and simulations for conducted EMI.

Track 4: Device Modeling and Characterization

Learn how to deliver accurate models faster for silicon CMOS, bipolar, and compound semiconductors to accelerate your technology innovations.
See the latest enhancements we’ve added to our device modeling arsenal, which could slash model extraction time by >70%.
Learn about best practices for model re-centering, fast model verification, automated de-embedding, and accurate random telegraph noise measurement and data analysis.

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Mapping signal processing algorithms on AMD-Xilinx Versal to meet timing and power constraints
2023-10-11 09:00 - 10:00 (America/Los_Angeles) | CA
In this Webinar, we will focus on the performance-power-area trade-off in implementing signal processing algorithms on Xilinx FPGA by partitioning the tasks of the algorithms onto the processors, logic and AI Engines resident in the AMD-Xilinx Versal FPGA.

Key Takeaways:

Discover the inner workings of FPGA components: Processor, Logic Elements, AIE/Tensor, and more.
Understand latency and throughput trade-offs when using NoC vs. direct interfaces.
Learn how different data cache sizes impact AIE Tile network utilization.
Dive into various mapping decisions and their effect on application throughput and power consumption.

So, what are you waiting for? Don’t miss this opportunity
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Synopsys Technology Symposium UK 2023
2023-10-12 08:30 - 17:30 (Europe/London) | Reading FC Conference Centre, Reading RG2 0FL, Berkshire, United Kingdom
Synopsys is hosting a Technical Symposium focusing on critical aspects of doing state of the art designs at established and emerging nodes. This event provides an opportunity for users to stay connected with the latest innovations as well as getting tips & tricks and best practices that fellow users and Synopsys experts will share.
Multiple sessions will be offered where experts will update you on exciting new technologies and features.
We will conclude the day with a social event where you will have the opportunity to meet and discuss with your industry peers and Synopsys experts in an informal atmosphere.

Direct booking link: Synopsys
There are a limited number of discounted rooms available for the night of Wednesday 11th October at the adjoining Voco Hotel. To book your room now please use this link: Synopsys

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Proactively Address Thermal Concerns in Advanced IC Packages
2023-10-12 10:00 - 11:00 (America/Los_Angeles) | CA
The heterogeneous integration of chips and chiplets in IC packages is all the rage as we face “More than Moore” performance challenges. While these innovative design practices successfully address performance goals, some design teams find that IC packages may overheat if they do not carefully plan for heat dissipation.
This webinar will show how design teams that implement thermal mitigation strategies early in the design cycle are facing fewer thermal concerns with their IC package prototypes.  We will walk through a reference design and discuss how Cadence Advanced Package Designer Plus combined with Celsius Thermal Solver address feasibility during the design planning stage to the full-system final signoff.
Join our webinar to learn how you can:

Efficiently address thermal concerns throughout the design cycle
Reduce design iterations
Proactively drive predictability into your design schedules

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The UCIe™ 1.1 Specification: Future Applications of Chiplets
2023-10-12 10:00 - 11:00 (America/Los_Angeles) | CA
Presenter: Dr. Debendra Das Sharma, UCIe Consortium Chairman and Intel Senior Fellow, Chief Architect of I/O Technology and Standards at Intel

The UCIe™ (Universal Chiplet Interconnect Express™) 1.1 Specification was released in August 2023, delivering valuable improvements to the chiplet ecosystem, extending reliability mechanisms to more protocols and supporting broader usage models. This webinar will provide an overview on enhancements made in the UCIe 1.1 specification and architectural specification attributes to define system setups and registers that will be used in test plans and compliance testing to ensure device interoperability. The presentation will also explore additional enhancements included for automotive usages – such as predictive failure analysis and health monitoring – and enabling lower-cost packaging implementations. Attendees will have a chance to participate in a live Q&A discussion immediately after the webinar to address questions from the presentation.

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IEEE 32nd Asian Test Symposium
2023-10-14 08:00 - 2023-10-17 17:00 (Asia/Shanghai) | CA
With the test technology facing its grand challenges to ensure the quality of ICs and electronic systems, incorporating more and more sophisticated manufacturing processes and system integration technologies in various emerging applications such as Internet of Things, cloud computing, automotive electronics, etc., global proliferation and cooperation is increasingly more important. The Asian Test Symposium (ATS) provides an open forum for researchers and industrial practitioners from all countries of the world to exchange innovative ideas on system, board, and device testing with design, manufacturing, and field consideration in mind.
ATS 2023, the 32nd in the series, will be held in Beijing China, on Oct.14-17, 2023.
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EPEPS 2023
2023-10-15 08:00 - 2023-10-18 17:00 (America/Los_Angeles) | Sonesta San Jose – Milpitas, 777 Bellew Drive, Milpitas, CA, United States
EPEPS is the premier international conference on advanced and emerging issues in electrical modeling, analysis and design of electronic interconnections, packages and systems. It also focuses on new methodologies and design techniques for evaluating and ensuring signal, power and thermal integrity in high-speed designs. EPEPS is jointly sponsored by the IEEE Electronics Packaging Society, IEEE Microwave Theory and Techniques Society, and IEEE Antenna and Propagation Society.
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DVClub Europe - AI/ML in Verification
2023-10-17 12:00 - 13:00 (Europe/London) | CA
This is to inform you that the next DVClub Europe meeting takes place on Tuesday 17th October with a theme of “AI/ML in Verification”.

This DVClub consider how we can save time and effort whilst improving time-to-market through the application of AI/ML to verification.

Agenda (BST)
12:00 Welcome and Introduction – Mike Bartley, Senior Vice President – VLSI Design, Tessolve
12:00 Rajendra Prasad, Infineon – Smart Adaptive Regression using Nearest Neighbour Algorithm
12:45 Daniel Hansson, Cadence Design System –
13:00 Close

Register now to become a part of this event. Free to attend online.
Eventbrite – DVClub Europe
Best Regards
Mike Bartley, Senior Vice President – VLSI Design, Tessolve
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Samsung Foundry Forum 2023 Tokyo, Japan
2023-10-17 12:00 - 17:30 (Asia/Tokyo) | Belle Salle Tokyo Nihonbashi, 2-7-1 Nihombashi, Chuo-ku, Tokyo, Japan
Welcoming Remarks

Seishu Arai
VP, Head of Japan Office, Samsung Electronics

Samsung Keynote

Siyoung Choi
President and GM, Foundry Business, Samsung Electronics
Guest Speech I

Junichiro Makino
Professor, Kobe University
Guest Speech II

Sumiko Kanamori
Automotive HPC, Analog & Power Solutions Gr. Digital Head of H/W Unit, VP, Renesas Electronics Corporation
Guest Speech III

Kazuoki Matsugatani
Senior Director, R&D Center, Denso Corporation
Process Technology

Ja-Hum Ku
EVP, Head of Technology Development,Samsung Electronics
Design Platform

Jongwook Kye
EVP, Head of Foundry Design Platform Development, Samsung Electronics
Manufacturing Excellence

Sang Sup Jeong
EVP, Head of Foundry Manufacturing Technology Center, Samsung Electronics
Business & Customers

Sang-Pil Sim
EVP, Head of Worldwide Sales and Marketing, Samsung Electronics
Automotive and HPC Solutions

Jongshin Shin
EVP, Head of Foundry IP Ecosystem, Samsung Electronics
Closing Remarks

Sang-Pil Sim
EVP, Head of Worldwide Sales and Marketing, Samsung Electronics

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Jasper User Group 2023
2023-10-18 08:00 - 2023-10-19 17:00 (America/Los_Angeles) | CA
Ready to share and discuss the latest design and verification best practices with your peers from around the world?
It’s time for our annual CadenceCONNECT: Jasper™ User Group Conference, held on October 18 and 19 at the Cadence San Jose campus. This interactive, in-depth technical conference connects designers, verification engineers, and engineering managers from around the world to share the latest design and verification practices based on Cadence’s Jasper formal verification technologies and methodologies. The conference will be held in person at the Cadence auditorium in San Jose, CA. The Jasper User Group Conference has become the premier industry event for formal experts and beginners alike to learn from each other how to effectively accelerate their design and validation processes by applying formal methods.
Got a Story to Share? Our Call for Presentations Is Open
We’re seeking your unique perspectives on using Jasper technologies and methodologies to achieve better results. If your presentation is accepted, you can:

Increase industry visibility for you and your team’s field of expertise
Improve and fine-tune your methods with insights from colleagues across the industry
Earn wide acclaim with a Best Presentation Award nomination

Please visit the website for further information. Accepted authors will be expected to attend the conference and present in person. The deadline for abstract submission is 5:00pm (PDT) on Wednesday, August 23, 2023.
Hot Topics for 2023

Best practices to achieve formal signoff
Algorithmic and datapath verification
Safety and security verification
Sequential equivalence checking
Deep deadlock and bug hunting
Machine learning for performance and convergence gains
Formal regressions and optimizing compute resources
Complex proofs, abstraction, and reduction techniques
Processor ISA verification
Protocol verification with assertion-based VIP
Blending formal and dynamic verification flows
Driving broader adoption of formal methods
Formal verification for design teams
Novel applications for formal verification
RISC-V verification

Conference registration will open at the end of August. We look forward to meeting you at CadenceCONNECT: Jasper User Group 2023!
Questions? Please email us.
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Soar to New Heights of Productivity using Cadence Managed Cloud Services
2023-10-18 08:30 - 09:15 (America/Los_Angeles) | CA
Date: Wednesday, October 18, 2023
Time: 8:30am PT | 10:30am CT | 11:30am ET

Join us for this 45-minute webinar to learn how the Cadence-managed, EDA-optimized, ready-to-use, and secure ISO-certified cloud platform delivers a fully integrated and proven environment to jump-start product design, verification, and implementation. See the platform in action as we demo the productivity features of Cadence’s digital and analog design flows.

What You Will Learn

How hundreds of customers have accelerated their design, verification, and implementation projects, whether for full or partial design flow in the cloud
How the cloud can solve your peak capacity needs, driving faster tapeouts and time-to-market
How to request compute hosts and access Rapid Adoption Kits (RAKs) in the cloud for interactive and batch jobs utilizing Virtuoso and Xcelium
How to request a free 30-day evaluation of the environment

Who Should Attend

This webinar will be useful for:

Design/Verification engineers
IT/Cloud Architects
Technical/Business Decision Makers

Speakers:

Ketan Joshi
Sr. Group Director, Cloud Team, Cadence

Mike Stanton
Group Director, IT, Cadence

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The Race is On!
2023-10-18 08:30 - 16:00 (America/Los_Angeles) | Brazos Hall, East 4th Street, Austin, TX, United States
Event Overview

Date: Wednesday, October 18, 2023
Time: 8:30am – 4:00pm, followed by an exclusive networking event
Location: Brazos Hall, Austin, TX

There is an unprecedented demand for advanced-node chip design that pushes beyond traditional boundaries. Computing power, security, reliability, and other multifaceted requirements have surpassed the basic performance, power consumption, and area constraints of traditional chip design. The race is on to enable traditional automotive companies to enter the new field of automotive electronic chips quickly, and to improve the performance of established automotive chips to deliver higher and higher computing capabilities while meeting safety and reliability requirements.

Join Cadence on October 18, at Brazos Hall in Austin, as we present a new generation of automotive electronics chip design full-flow solutions. Learn about the most recent advancements in the field of automotive chips, including upcoming technology trends and innovations, such as autonomous driving to electric vehicles, functional safety, reliability of automotive semiconductors, and more.

Who Should Attend:

CAE professionals with a background in electrical engineering, fluid dynamics, engineering directors and managers, and engineering team members who work in automotive electronics (SoC) design.

What You Will Learn:

Design IP for Automotive SoC Design
3D-IC Design and Interconnect IP Solution for Chiplet-Based Design
Configurable Multi-Core DSP and AI Platform for Automotive Applications
FMEDA-Driven Safety Analysis and Verification
Safety-Aware Implementation
Analog/Mixed-Signal Safety Verification
System Design and Analysis (EMI, EMC, Electrothermal)
Automotive CFD Solutions (Aerodynamics, Aeroacoustics, HVAC, Turbo/Pumps, ​
Thermal Management)

“The race is on!” not just on the circuits, but also here in the center of our event. Accelerate your knowledge at our seminar and shift your networking into high gear.
We’re thrilled to announce that a special guest will be joining us. Be ready to mingle with an elite McLaren Formula 1 driver at our exclusive networking event. Don’t miss this unique opportunity to meet and interact with one of racing’s finest up close and personal. Whether you’re a die-hard F1 fan or simply looking to network with experts in the industry, this is a pit stop you won’t want to miss!

Stay tuned for more information!

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System-Level Thermal Signoff from Chips Through to Racks
2023-10-18 10:00 - 10:45 (America/New_York) | CA
Today’s modern electronic designs require ever more functionality and performance to meet consumer demand. These challenges become more critical and complex when resistive losses in PCB and package structures are significant since resistive losses are temperature dependent. In this webinar, we will look at an electrothermal co-simulation solution for the full hierarchy of electronic systems from ICs to physical enclosures using Cadence’s Celsius technologies. By combining finite-element analysis (FEA) for solid structures with computational fluid dynamics (CFD) for both liquid and gas, as well as airflow, designers can perform complete system analysis in a single tool. The combined workflow that ties the Celsius Thermal Solver with the Celsius EC electronic cooling solver provides even higher accuracy and faster simulation time in the modeling of electronics equipment.

Speakers

Dr. Melika Roshandell
Product Marketing Director
Cadence

Dr. Melika Roshandell is product marketing director for Celsius Thermal Solver software at Cadence. Prior to Cadence she held positions as a system on chip (SoC) thermal engineer at Qualcomm for nine years and thermal engineer at Broadcom for two years. Dr. Roshandell earned her BS in mechanical engineering at the University of California, San Diego, and her MS and PhD in mechanical engineering at the University of California, Irvine.

Karthick Gopalakrishnan
Product Engineer
Cadence

Karthick Gopalakrishnan is a product engineer at Cadence supporting the Celsius line of electrothermal analysis products. Prior to joining Cadence, he was a thermal/CFD application engineer at Mentor Graphics. Karthick holds an MS in mechanical engineering from the North Carolina State University, where he specialized in thermal and fluid sciences.

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Samsung Foundry Forum 2023 EMEA
2023-10-19 08:00 - 17:00 (Europe/Berlin) | Sofitel Munich Bayerpost, Bayerstrasse 12, Munich, 80335, Germany
We’re inviting global partners and customers to our upcoming Samsung Foundry Forum (SFF) and Samsung Advanced Foundry Ecosystem (SAFE™) Forum 2023. The events will provide opportunities to share insights and innovative technologies to build a strong foundry ecosystem to accelerate innovation beyond boundaries. Join us to experience the spirit and power of innovation. SFF & SAFE™ Forum 2023 will be held in several different countries around the world. Check the map below to see where our other forums will be held this year.

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High Reliability and Functional Safety Applications for FPGA
2023-10-19 10:00 - 11:00 (America/Los_Angeles) | CA
When designing any new system, safety and reliability are key factors in determining if a system is safe for real-world deployment and if there are sufficient contingency plans for worst case scenarios. This is no different for the designs targeted for FPGAs based deployments. Today, FPGA based designs are utilized in many safety critical systems in the military, aerospace, medical, industrial, robotics, and automotive industries. These systems require meeting stringent safety regulations such as defined by ISO 26262 standard for automotive and the IEC 61508 standard for industrial applications.
To address this need, Synopsys provides a comprehensive family of integrated FPGA verification products. For FPGA synthesis, Synplify provides the state of the art and most ease-of-use automated features for functional safety and high reliability for FPGA designs. Synplify Synthesis tool can automate design logic insertion at module to register level and as well as provide full features for functional testing and debugging. This includes features such as logic duplication, triplication, error flag insertion and fault injection.
In this webinar, we will cover and demonstrate, how Synplify and Synopsys family of verification products enable users to meet their functional safety and high reliability needs for FPGA based designs.

Speakers

Listed below are the industry leaders scheduled to speak.

Khalid Khan

Senior Staff Applications Engineer
Synopsys Inc

Khalid Khan is a Senior Staff Application Engineer with Synopsys System Design Group based out of Synopsys HQ in Sunnyvale, CA. He has 20+ years of experience in FPGA Synthesis, Verification and ASIC Prototyping fields. He is currently the overall lead for the Synplify FPGA synthesis product for field application engineering team in helping define the product road map and strategy.
He also helps support many of the major FPGA Synthesis and Prototyping customers in the Silicon Valley region.

DeAndre Hoskins

Staff Applications Engineer
Synopsys Inc

DeAndre Hopkins is a Staff Application Engineer based in San Diego, CA.
He has 15+ of experience in FPGA Synthesis and Verification flows. He has extensive background working with Military/Aerospace customers using VHDL and FPGA synthesis flows. He is based out of San Diego, CA and supports major FPGA accounts in southern CA, AZ, NM, TX regions.

Bobby Zuiss

Senior Applications Engineer
Synopsys Inc

Bobby Zuiss is a Senior Applications Engineer with the Synopsys System Design Group. He has 10+ years of experience with FPGA Synthesis products. He is based out of Los Angeles, CA. He has experience working with FPGAs in both Defense and High Speed Trading industries. He supports major Military/Aerospace accounts in Southern CA, CO, & UT.

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SemIsrael Expo 2023
2023-10-24 08:00 - 17:00 (Asia/Jerusalem) | Avenue Convention Center, Airport City, Israel
SemIsrael Expo 2023 is the premier professional semiconductor event in Israel. The event brings together hundreds of Israeli semiconductor professionals from all fields and aspects of the semiconductor industry.
The Expo will host some 750 semiconductor professionals from all the Israeli semiconductor community; local fabless & startups, local R&D offices of multinationals and IDMs, foundries, design houses, labs and universities.​
Meet Our Keynote Speakers
Vivek MishraCorporate Vice President – Product EngineeringCadence
Dr. Charlie SuCo-Founder, President and CTOAndes Technology
Dr. Yervant ZorianChief Architect and FellowSynopsys
Kay EnjojiPresidentTEL Ventures
Lee HarrisonDirector Tessent Product MarketingSiemens EDA
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