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DTSTART;TZID=Europe/London:20240924T094500
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UID:8297-1727171100-1727188200@marketingeda.com
SUMMARY:FPGA Front Runner: FPGA Verification Strategies
DESCRIPTION:Time\nSpeaker\nDetails\n\n\n09.30\nArrival and Registration\n\n\n10.00\nDave Sanders\, Rolls-Royce\nOverview of Rolls Royce @ Solihull \nPresentation Title – Rolls-Royce… the past\, the present and the future \nAbstract – Rolls-Royce has come a long way since its inception as a car manufacturer at the start of the twentieth century\, for starters it doesn’t make cars anymore! This talk will provide an insight into Rolls-Royce’s past present and future with a focus on the pivotal role that electronics now plays in a company traditionally known for its mechanical engineering solutions.\n\n\n10.30\nEspen Tallaksen\, EmLogic\nPresentation Title – Modern VHDL testbenches – An AXI-stream example\, first dead simple\, then advanced \nAbstract – Do you want to see how easily you can verify your FPGA or ASIC? Join in to see this exemplified with a testbench for an AXI-stream based data flow design – using UVVM\, which is currently used by more than one third of all European FPGA designers. \nMost testbenches verifying a complex DUT are relatively unstructured and difficult to understand\, modify\, extend\, maintain and reuse. You can often easily reduce the verification time by at least a factor of two by having a well structured and easy to understand test harness\, and writing commands at a higher abstraction level – allowing a good and complete testcase overview by just looking at a simple test sequencer with easy to understand high-level commands. \nThis presentation will first show how interface handling procedures (BFMs) can be applied in a very simple way to verify a DUT. Then we will show how a more advanced testbench using verification components\, models\, scoreboards and high-level transactions will allow more thorough verification of more complex DUT scenarios in a very structured and simple way.\n\n\n11.00\nJim Lewis\, SynthWorks Design Inc\nPresentation Title – Why Should Our Team be Using VHDL + OSVVM for Verification? \nAbstract – Developing and deploying a verification methodology can be costly and time consuming. Going without one will be even more costly due to bugs escaping into production hardware systems. \nOpen Source VHDL Verification Methodology (OSVVM) provides the VHDL community with an already developed\, open-source solution. OSVVM implements all of the capabilities of a modern verification methodology: transaction-based testing\, a verification framework\, verification components\, self-checking tests\, messaging handling\, error tracking\, requirements tracking\, constrained random testing\, scoreboards\, functional coverage\, co simulation with software\, test automation\, and a comprehensive set of test reports. \nThis presentation examines how these capabilities will benefit your projects. \nSystemVerilog+UVM also provides a similar set of capabilities. Unfortunately\, SV+UVM ended up absurdly complex to use – instead of using a module (entity/architecture in VHDL) with its built-in concurrency\, SV+UVM uses OO\, sequential code\, and fork and join (to get concurrency). As a result\, SV has failed to unify the design and verification communities. \nVHDL+OSVVM on the other hand uses entity/architectures to create verification components and libraries of subprograms (procedures and functions) to extend VHDL into a complete verification language. In doing this\, OSVVM creates verification capabilities that rival SystemVerilog+UVM while at the same time it uses VHDL language elements that are familiar to VHDL design engineers. \nAs a result\, with VHDL+OSVVM and a good verification lead\, any VHDL engineer can do verification as well as RTL design.\n\n\n11.30\nRefreshment break\n\n\n12.00\nPhilipp Wagner\, FOSSi Foundation\nPresentation Title – cocotb is making verification fun! \nAbstract – cocotb lets you verify chips like software: productive\, simulator-agnostic\, in Python. In this talk\, you’ll learn what cocotb is and how using Python for verification can make your next verification job more productive. There’s even something in there for those of you who already know cocotb: a look at cocotb 2.0 and tips and tricks how to update your testbenches to make best use of the new features.\n\n\n12.30\nChristian Tchilikov\, semify GmbH\nPresentation Title – Utilizing the Cocotb Python Framework for Efficient Functional Verification \nAbstract – Cocotb is a framework that allows for verification test cases written in Python to interact with DUTs being simulated in common simulation tools. Compared to classical approaches for verification\, Cocotb has very low upfront engineering costs. With access to the full functionality of the Python programming language\, the complexity of testbenches can scale up as required. \nCocotb comes with built-in functionalities for many of the tasks required of a modern testbench\, like constrained random input generation\, coverage tracking\, and assertions. \nCocotb’s foundation being the Python language means that software models of the design can be written in a high-level Object-Oriented language. Additionally\, higher-level objects such as drivers or monitors can be designed for the bit-wiggling of DUT input signals\, providing a higher level of abstraction\, similar to UVM sequences. The software model can then be easily scoreboarded with the DUT through Cocotb. \nAdditionally\, Cocotb provides high-level abstractions for interfacing with the simulated design. This comes in the form of hierarchical signal reading and assignment\, event triggers\, and parallel execution of coroutines similar to SystemVerilog’s forks. Leveraging these tools\, it becomes simple to launch verification modules like drivers and monitors\, running and interfacing with the DUT in parallel. \nThird-party verification IP modules for many standard interfaces are available via the cocotb extensions packages hosted on PyPi\, so devices using SPI or AXI\, amongst others\, can be verified with minimal effort. In addition\, engineers can write and reuse their own verification IP\, such as bus monitors\, drivers\, etc\, similar to the UVM approach of verification. \nA special emphasis is on using cocotb alongside an open-source toolchain like Icarus Verilog\, acheiving a similar quality of results compared to commercial offerings. This combination of tools provides features that are otherwise hidden behind expensive licence paywalls\, and makes digital verification accessible to a wider audience. \nCocotb serves as a great alternative to traditional SystemVerilog Object-Oriented verification by working around the limitations of the simulators that do not support the full feature set of SystemVerilog by providing similar functionality in the Python language instead.\n\n\n13.00\nDave Amor\, Ultra Maritime\nPresentation Title – Integration of Atlassian Bamboo with MathWorks Tools for FPGA Development \nAbstract – In safety critical FPGA development\, the need for efficiency\, reliability\, and predictability while maintaining agility is vital. \nUltra Maritime has embraced these demands by integrating Continuous Integration (CI) practices with MathWorks tools and Agile methodologies\, creating a streamlined and robust development process that ensures high-quality outcomes in mission-critical applications. \nThis presentation will explore the strategies and technologies we use to achieve consistent\, and resilient FPGA development\, focusing on how these practices contribute to the success of our projects. \nAtlassian Bamboo allows us to automate testing\, code generation\, and the bitstream creation processes. \nThis integration ensures that every change in our FPGA designs can be automatically validated through rigorous testing\, significantly reducing the risk of errors and accelerating the development lifecycle. \nBy automating these processes\, a higher standard of code quality is possible while freeing up our engineers to focus on innovation and problem-solving. \nThis presentation will touch on the adoption of Agile Scrum practices within our FPGA development teams. \nAgile Scrum provides a flexible framework that allows us to adapt to changing requirements\, prioritise tasks effectively\, and deliver incremental improvements throughout the project lifecycle. Key ceremonies such as sprint planning\, daily stand-ups\, and retrospectives are essential to maintaining focus and ensuring continuous improvement. We will discuss how these practices have enhanced our ability to respond to challenges\, manage complexity\, and maintain alignment across our teams. \nA crucial aspect of our development process is the integration of Jira with Bamboo and Simulink. This connection enables seamless tracking of tasks\, test results\, and code changes. Automated reporting of test failures and direct linking to Jira tasks ensure that issues are identified\, prioritised and resolved. \nThe presentation will also address the advantages of CI in ensuring resilience against the turnover of key personnel. By standardising workflows and maintaining consistent environments\, we reduce the dependency on individual knowledge and ensure that our processes are sustainable. \nLooking to the future\, we will explore potential enhancements to our current setup\, by leveraging developments in Large Language Models. \nUltra Maritime’s approach to FPGA processes evolving over the last 25 years has created a environment that is effective\, adaptable and resilient\, ensuring the delivery of high-quality\, reliable products.\n\n\n13.30\nLunch\n\n\n14.00\nTour\n\n\n14.30\nFinish refreshments/networking
URL:https://marketingeda.com/event/fpga-front-runner-fpga-verification-strategies/
LOCATION:Rolls Royce Control Systems\, 5000 Solihull Parkway\, Birmingham\, B37\, United Kingdom
CATEGORIES:EDA,Forum
ATTACH;FMTTYPE=image/jpeg:https://marketingeda.com/wp-content/uploads/Tessolve-September-24-2024.jpg
END:VEVENT
BEGIN:VEVENT
DTSTART;TZID=America/New_York:20240918T100000
DTEND;TZID=America/New_York:20240918T110000
DTSTAMP:20240820T165235Z
CREATED:20240820T165149Z
LAST-MODIFIED:20240820T165235Z
UID:8255-1726653600-1726657200@marketingeda.com
SUMMARY:A Beginner's Guide to RTL-to-GDSII Front-End Flow
DESCRIPTION:In this Training Webinar\, explore the concepts of RTL design\, design verification\, and coverage analysis while unveiling the exciting world of front-end design flow. Walk through the essential steps in creating integrated circuits\, the building blocks of modern electronics. \nThis webinar provides practical knowledge\, making it your gateway to understanding the magic behind RTL-to-GDSII front-end design flow. \nWe’ll break down the process into manageable stages\, from defining the chip’s functionality to its physical realization. We’ll investigate the front-end part of the RTL-to-GDSII flow—from specification to functional verification and design coverage—and explore: \n\nKey concepts of specifying chip behavior and performance\nHow to translate ideas into a digital blueprint and transform that into a design\nHow to ensure your design is free of errors\n\nWebinar: A Beginner’s Guide to RTL-to-GDSII Front-End Flow\nDate: Wednesday\, September 18\, 2024\nTime: 07:00 PDT San Jose / 10:00 EDT New York / 15:00 BST London / 16:00 CEST Munich / 17:00 IDT Jerusalem / 19:30 IST Bangalore / 22:00 CST Beijing
URL:https://marketingeda.com/event/beginners-guide-rtl-gdsii-front-end-flow/
CATEGORIES:EDA,Webinar
ATTACH;FMTTYPE=image/jpeg:https://marketingeda.com/wp-content/uploads/Cadence-September-18-2024-1.jpg
END:VEVENT
BEGIN:VEVENT
DTSTART;TZID=America/Los_Angeles:20240918T090000
DTEND;TZID=America/Los_Angeles:20240918T100000
DTSTAMP:20240906T215837Z
CREATED:20240906T215234Z
LAST-MODIFIED:20240906T215837Z
UID:8304-1726650000-1726653600@marketingeda.com
SUMMARY:Redefining Mobile Experiences with AI
DESCRIPTION:The Arm platform is providing the foundation for the next wave of AI smartphones and laptops. As AI models rapidly evolve\, we’re seeing that software begins to outpace hardware\, requiring additional innovation at all levels of the compute stack. \nTo meet these growing demands\, the Arm platform offers a new compute solution for maximum performance and efficiency\, on leading process nodes. Join this webinar series to learn more about this solution\, including the latest Arm Armv9 CPUs and GPUs\, the benefits and opportunities of running AI on device\, and how to innovate and speed time to market. \nSession 1: The Arm Platform on Wednesday\, Sept 18\, 2024\n\n9:00 a.m. BST / 4:00 p.m. Beijing\n5:00 p.m. BST / 9:00 a.m. PT\n\nThis webinar covers: \n\nThe latest Arm technology\, Arm Compute Subsystems (CSS) for Client\, which helps push the boundaries of premium mobile experiences.\nFeatures\, benefits\, and performance enhancements of Armv9 based Arm Cortex CPUs and Immortalis and Mali GPUs.\nHow Arm partners can rapidly innovate and speed time to market.\nPerformance and efficiency enhancements that increase the responsiveness of GenAI.\nHow to unlock 3 nm PPA benefits with physical implementations.\n\nSpeaker: Kinjal Dave\, Senior Director Product Management\, Arm \nSecond Session – October 2nd
URL:https://marketingeda.com/event/redefining-mobile-experiences-with-ai/
CATEGORIES:IP,Webinar
ATTACH;FMTTYPE=image/jpeg:https://marketingeda.com/wp-content/uploads/Arm-September-18-2024.jpg
END:VEVENT
BEGIN:VEVENT
DTSTART;TZID=Asia/Kolkata:20240918T080000
DTEND;TZID=Asia/Kolkata:20240919T170000
DTSTAMP:20240807T162934Z
CREATED:20240807T162703Z
LAST-MODIFIED:20240807T162934Z
UID:8215-1726646400-1726765200@marketingeda.com
SUMMARY:DVCon India 2024
DESCRIPTION:On behalf of the DVCon India 2024 steering committee\, it is my pleasure to welcome you all to the 9th edition of the Design and Verification Conference in India planned from 18- 19th September 2024 in Bangalore\, India. The theme of this year’s conference is “Architecture to Analytics – A2A“. \nWe want to carry forward the momentum\, excitement and the enthusiasm witnessed during last year’s edition into DVCon India 2024. The conference would be following the contemporary Indian version of a two-day conference with in-depth technical content spreading across both the days and will have an Awards Night\, which saw an amazing response last year. \nOn behalf of the DVCon India 2024 steering committee\, it gives me immense pleasure to extend a warm welcome to each and every one of you to the 9th edition of the Design and Verification Conference in India. Set to unfold from the 18th to 19th of September 2024 in the vibrant city of Bangalore\, India\, this conference promises to be a pinnacle of innovation\, collaboration and insight. \nAs we embark on this journey\, we are fuelled by the electrifying momentum\, the techno-genius excitement and the enthusiasm that characterized last year’s edition of DVCon India. Our goal for DVCon India 2024 is clear: to build upon the successes of the past and propel the conference to even greater heights. \nThis year\, our focus is laser-sharp: we aim to demystify the essence of DVCon. While some may perceive it solely as a Digital Verification Conference\, DVCon embodies much more—it encapsulates the entire spectrum of Design and Verification\, spanning from Architecture and Design to Post Silicon Validation. \nTo ensure that this message resonates loud and clear across our community\, we have formed dedicated focus groups in pivotal areas: \n\nSystem and IP level modelling\, Virtual Prototyping & ESL\nArchitecture and Design\nRISC-V and its ecosystem\nAnalog and Mixed-Signal Design and Verification and\nPost Silicon Validation.\n\nThrough these specialized groups\, we seek to foster deeper understanding\, facilitate meaningful dialogue and foster inclusive participation. \nFurthermore\, in our relentless pursuit of excellence\, we are expanding our Technical Program Committee and implementing structural enhancements to optimize the participant experience. These changes underscore our commitment to delivering value-driven content and enriching interactions. \nWe extend an open invitation to the entire technical fraternity to actively engage\, collaborate and share insights at DVCon India 2024. Your collective expertise\, passion\, and dedication are instrumental in shaping the success of this conference\, and we eagerly anticipate your invaluable contributions. \nTogether\, let us ignite the spirit of Designnovation\, celebrate the power of collaboration and chart a path towards a future defined by excellence. \nWelcome to DVCon India 2024—a platform where ideas converge\, innovations thrive\, and possibilities abound. \nHere’s to a resounding success! \n\n \nPradeep Salla\nSiemens EDA\nGeneral Chair\, DVCon India 2024
URL:https://marketingeda.com/event/dvcon-india-2024/
LOCATION:Hotel Radission Blu\, Marathalli ORR\, 90/4 Outer Ring Road\, Bengaluru\, India
CATEGORIES:Conference,EDA
ATTACH;FMTTYPE=image/jpeg:https://marketingeda.com/wp-content/uploads/DVCon-India-2024-1.jpg
END:VEVENT
BEGIN:VEVENT
DTSTART;TZID=America/Los_Angeles:20240918T080000
DTEND;TZID=America/Los_Angeles:20240918T090000
DTSTAMP:20240813T192856Z
CREATED:20240813T192856Z
LAST-MODIFIED:20240813T192856Z
UID:8231-1726646400-1726650000@marketingeda.com
SUMMARY:Managing Constraints Like a Pro in OrCAD X
DESCRIPTION:Join us in this constraint-focused webinar to learn all the best practices for managing constraints in your design with OrCAD X Presto PCB Editor. \nWe’ll cover everything from the basics of setting up spacing and physical constraints to advanced electrical constraints\, which are critical for HDI designs. \nThe webinar will feature a brief presentation\, a live demonstration using the NVIDIA Jetson Xavier Developer Kit Carrier Board\, and a Q&A session. \nTopics Covered:\n\nNavigating the constraint manager and reusing constraints\nCreating constraint sets\nSetting up physical and spacing constraints\nSetting up advanced constraints for HDI\nElectrical constraints (Propagation Delay\, Net Scheduling\, Differential Pairs)\nSetting up blind\, buried\, and microvias\nAnalysis setup\nPreview of the new constraints panel in OrCAD X Presto PCB Editor\n\n\nWe welcome PCB designers of all experience levels to join us. Enhance your expertise in managing basic and advanced constraints in your OrCAD X Presto designs! \n\nSPEAKERS: \nAdam Fuchs\, Principal Product Engineer\, Cadence \nHOST: \nSupreeth Mannava\, Senior Principal Product Manager\, Cadence
URL:https://marketingeda.com/event/managing-constraints-like-a-pro-in-orcad-x/
CATEGORIES:EDA,Webinar
ATTACH;FMTTYPE=image/jpeg:https://marketingeda.com/wp-content/uploads/Cadence-September-18-2024.jpg
END:VEVENT
BEGIN:VEVENT
DTSTART;TZID=Asia/Tokyo:20240917T080000
DTEND;TZID=Asia/Tokyo:20240917T170000
DTSTAMP:20240823T182503Z
CREATED:20240823T182145Z
LAST-MODIFIED:20240823T182503Z
UID:8269-1726560000-1726592400@marketingeda.com
SUMMARY:IP-SoC Japan 24
DESCRIPTION:A worldwide connected Event !! \nD&R IP-SoC Japan 2024 Day is the unique worldwide Spring event fully dedicated to IP (Silicon Intellectual Property) and IP based Electronic Systems. \nIP-SoC providers\, the seed of innovation in Electronic Industry\, are invited to highlight their latest products and services and share their vision about the next innovation steps in the Electronic Industry. \nIP consumers can view at a glance the latest Technology trends and exciting Innovative IP/SoC products. Through a global view\, Electronic systems leaders may identify disruptive innovation leading to new market segment growth. \nAny question? Please contact us \n\n\n\n\n\n\n\n\n\n9:00 am\nWelcome\n\n\n\nWelcome to the IP-SoC community \nGabrièle Saucier\nCEO\nDesign And Reuse \nAbout me\n\n\n\n\nAdding Intelligence in Green Technology \nPhilippe Flatresse\nProduct Marketing\nSoitec \nAbout me\n\n\n\n\n9:40 am\nBreak\n\n\n\n10:00 am\nAnalog and Memory IP\n \nChairperson: Gabrièle Saucier\, D&R\n\n\n\n\nHigh-performance PLL frequency synthesizers for wireless and wireline communications \nM. Annamalai Arasu\nDirector\, R&D\nCM Engineering Labs Singapore Pte. Ltd \nAbout me\n\n\n\n\nThe Uniquely Suitable eNVM Ip for Auto Grade MCU from Floadia \nYasuhiro Taniguchi\nCTO and COO\nFloadia Corporation \nAbout me\n\n\n\n\nSemiconductor IPs for Memory\, Flash storage and wireless applications \nRavi Thummarukudy\nCEO\nMobiveil Inc. \nAbout me\n\n\n\n\n11:00 am\nBreak\n\n\n\n11:20 am\nInterface IP\n \nChairperson: Gabrièle Saucier\, D&R\n\n\n\n\nHigh Speed Interface\, keys and Trend \nJunzoh Shimizu\nCEO & President\nSilicon Library Inc. \nAbout me\n\n\n\n\nScaling Hyperscale Data Centers for AI Workloads with High-Speed Interface IP \nHiroyuki Hasegawa\nApplication Engineering Manager\nSynopsys\, Inc. \nAbout me\n\n\n\n\n12:00 pm\nLunch Break\n\n\n\n1:00 pm\nDesign Platform\n \nChairperson: Philippe Flatresse\, Soitec\n\n\n\n\nThe Critical Role of Embedded Monitor IP in Enabling Silicon Lifecycle Management Use Cases \nYuya Suzuki\nApplications Engineering\, Staff Engineer\nSynopsys\, Inc. \nAbout me\n\n\n\n\nArchitecture challenges in meeting power\, thermal and performance needs in partitioning Chiplets for rapid deployment \nDeepak Shankar and Shuzo Tanaka\nFounder\nMirabilis Design Inc. \nAbout me\n\n\n\n\nCurious’ latest High Performance IP Introduction \nKen ichi Shimomura\nDirector of Design department\nCurious Corp. \nAbout me\n\n\n\n\nEmbedded Programmable Logic – A risk insurance for your next chip design \nYoan Dupret\nMenta \nAbout me\nOnline Only\n\n\n\n\n2:00 pm\nBreak\n\n\n\n2:20 pm\nArtificial Intelligence\n \nChairperson: Philippe Flatresse\, Soitec\n\n\n\n\nMeeting the Needs of AI Training with HBM3E \nMotoyasu Kobayashi\nDirector of Sales\nRambus\, Inc. \nAbout me\n\n\n\n\nScalable\, Flexible Edge AI accelerator: Silicon-Proven IP for Consumer Electronics \nChangSoo Kim\nCEO\nAiM Future\, Inc. \nAbout me\n\n\n\n\nEnabling Multimodal AI on Edge Devices \nShanghung Lin\nVP\, Vision and Image Product\nVerisilicon \nAbout me\n\n\n\n\n3:20 pm\nBreak\n\n\n\n3:40 pm\nSecurity and high safety Solutions\n \nChairperson: Philippe Flatresse\, Soitec\n\n\n\n\nQuantum Safe Cryptography: Protecting Devices and Data in the Quantum Era \nToru Furukawa\nSenior Field Application Engineer\nRambus\, Inc. \nAbout me\n\n\n\n\nFuture-Proof Your Design with Hardware-Based Post-Quantum Cryptographic IP Cores \nDr. Matti Tommiska\nXiphera Ltd \nAbout me\n\n\n\n\nSecurity From Chip-To-Cloud with PQC (Post Quantum Cryptography) \nAhmed BOUGRIANE\nPre-Sales Engineer North Asia\nSecure-IC \nAbout me\n\n\n\n\nHow SafeIP(TM) enables fail operational vehicles\, robotics and drones \nBenjamin Weinhardt\nHead of Business & Collaboration\nSiliconally GmbH \nAbout me\n\n\n\n\n5:00 pm\nVideo IP\n \nChairperson: Philippe Flatresse\, Soitec\n\n\n\n\nVideo Codecs Landscape and Challenges Ahead \nYujing Wei\nVP\, APAC Business Development\nAllegro DVT \nAbout me\n\n\n\n\n6:00 pm\nEvent Closure
URL:https://marketingeda.com/event/ip-soc-japan-24/
LOCATION:Tokyo Convention Hall\, 3 Chome-1-1 Kyobashi\, Toyo\, Japan
CATEGORIES:Conference,IP
ATTACH;FMTTYPE=image/jpeg:https://marketingeda.com/wp-content/uploads/IP-SoC-Japan-24.jpg
END:VEVENT
BEGIN:VEVENT
DTSTART;TZID=America/Los_Angeles:20240914T080000
DTEND;TZID=America/Los_Angeles:20240919T170000
DTSTAMP:20240909T164418Z
CREATED:20240909T164418Z
LAST-MODIFIED:20240909T164418Z
UID:8313-1726300800-1726765200@marketingeda.com
SUMMARY:46th Annual EOS/ESD Symposium & Exhibits
DESCRIPTION:The EOS/ESD Symposium is dedicated to the understanding of issues related to electrostatic discharge and electrical transients/overstress\, and the application of this knowledge to the solution of problems in consumer\, industrial\, and automotive applications\, including electronic components\, as well as in systems\, subsystems\, and equipment.
URL:https://marketingeda.com/event/46th-annual-eos-esd-symposium-exhibits/
LOCATION:Peppermill Resort and Casino\, 2707 South Virginia Street\, Reno\, NV\, United States
CATEGORIES:EDA,Symposium
ATTACH;FMTTYPE=image/jpeg:https://marketingeda.com/wp-content/uploads/EOSESD-2024.jpg
END:VEVENT
BEGIN:VEVENT
DTSTART;TZID=Europe/Stockholm:20240913T080000
DTEND;TZID=Europe/Stockholm:20240915T170000
DTSTAMP:20240717T214406Z
CREATED:20240717T214315Z
LAST-MODIFIED:20240717T214406Z
UID:8159-1726214400-1726419600@marketingeda.com
SUMMARY:ORConf 2024
DESCRIPTION:Our 10th ORConf!\nThe FOSSi Foundation is proud to announce the 10th installment of ORConf\, a conference dedicated to free and open source silicon to be held over the weekend of Friday September 13 to Sunday September 15 in Gothenburg\, Sweden. \nORConf is a weekend of presentations and networking for the open source silicon community. Browse through previous installments of ORConf here. \nRegistration is now open and available via Eventbrite. \nQuestions? Ping the organizers via email at orconf@fossi-foundation.org. \nChat\nChat with fellow ORConf attendees in our Matrix chat room at #orconf2024:fossi-foundation.org. Any Matrix client works\, or just use the Element web chat. \nSubmit a talk\nPresentation submissions are made through the Eventbrite registration interface. \nPlease make your submissions as early as you can\, as the presentation slots are likely to fill up at ORConf this year. \nCode of conduct\nWe ask all ORConf participants to adhere to the the FOSSi Foundation code of conduct throughout the event. \nSponsors\nA variety of sponsorship packages are available for this year’s ORConf. You’ll find all of the details in our sponsorship prospectus. \nPlease get in touch via email to explore the opportunities: orconf@fossi-foundation.org. \nVenue\nGothenburg\, Sweden. \nPrecise venue details TBD\, but it will be relatively central to town. \nSchedule\nThe detailed schedule will be available once we have all of the presentation submissions. \nFriday\nPresentations from about mid-morning. \nSaturday\nPresentations all day\, conference event Saturday evening. \nSunday\nPresentations and workshops until midday/early afternoon. \nProgramme\nPlease submit your presentation proposals when registering via the Eventbrite page. \nPreliminary programme. More to come later. \nAccelerating software development for emerging ISA extensions with cloud-based FPGAs: RVV case study\nMarek Pikuła\nThe RISC-V Vector Extension (RVV) promises an enhanced performance and power efficiency across various complex computational tasks. However\, the efficient utilization of RVV demands careful consideration of the optimization approach. This article examines strategies for accelerating this process. Key challenges include assessing performance differences among algorithmic approaches and overcoming initial hardware constraints. FireSim provides a comprehensive solution by offering advanced software and hardware simulation capabilities. Utilizing FireSim\, we started the process of enhancing source code with RVV instructions (called vectorization) for the pixman project. Our experience outlines the efficacy of a cloud-based FPGA simulation in expediting software development for emerging ISA extensions. Overall\, FireSim facilitates faster iteration cycles and informed design decisions\, benefiting individual developers and fostering collaboration in remote teams. \nFazyRV: A RISC-V Core that Scales to Your Needs\nMeinhard Kissich\nFazyRV is a scalable RISC-V core that can be synthesized into a (1-)bit-serial\, 2-\, 4-\, or 8-bit-serial implementation to fulfill your performance requirements with the least area (resp. resources) demand. FazyRV provides manifold variants to adapt to the target technology by\, e.g.\, avoiding dual-port BRAM at the cost of an additional clock cycle. Contradictory to hand-optimized cores at the gate level\, FazyRV tries to avoid manual low-level optimizations to increase readability and simplify adaptations. This talk gives an insight into the open-source FazyRV core and its design objectives. We show how the area demand scales\, answer why there is no 16-bit variant\, discuss how the performance can be improved\, and outline possible extensions to improve the current FazyRV design. \nUnderstanding and Supporting Open Source Silicon Communities\nStefan Wallentowitz\nTBD \nDebug your Design with a Tiny Interpreter\nChristopher Lozinski\nInterpreters are very helpful tools for hardware development\, but the existing tools require slow interprocess communication\, and lots of memory. Best to use a tiny interpreter that runs on both the FPGA\, and in the simulator. . Less than 2KBytes of memory required and there is no slow interprocess communication. There are even two ASICs that run similar interpreters. . \nVexiiRiscv : A Debian demonstration\nCharles Papon\nThe VexiiRiscv (Vex2Risc5) project aim at remplacing VexRiscv and extends its scope with features such as multi-issue\, hardware prefetcher\, 64 bits support\, … This presentation will mainly be a live demonstration of the project running Debian on FPGA\, exposing the level of performance achievable on such system including boot\, userland\, some demos and finaly a few slides. \nProject Arrakeen: One API to rule all PDKs\nStaf Verhaegen\nProject Arrakeen is an umbrella project for providing a python framework for portable and scalable digital and analog circuits. It is based on the PDKMaster base project which provide a uniform API to PDK data and generation of circuit and layouts. On this base project other projects are being built that provide standard cells\, IO cells\, SRAM compiler and analog blocks. In this talk the state of the Arrakeen project and it’s subprojects for the three supported open source PDKs\, e.g. Sky130\, IHP SG13G2 and GF180MCU will be presented. \nnaja_edit: An Open Source Tool for Gate-Level Netlist editing and optimization\nChristophe Alexandre\nnaja_edit is an open source tool designed to optimize and edit gate-level netlists. It features algorithms for Dead Logic Elimination\, Constant Propagation\, and Primitives Optimization\, all performed with minimal changes to the hierarchical netlist structure. This tool can be interleaved with Yosys and OpenROAD\, making it particularly useful for large designs requiring hierarchical synthesis. naja_edit also features a Python interface for power users to inspect and edit the netlist using simple scripts. This talk will present optimization results on a set of open source designs. \nForastero: cocotb testbenches with batteries included\nPeter Birch\nForastero is a Python library that builds on top of cocotb adding standard components like drivers\, monitors\, and scoreboards but without bringing the full weight of a UVM environment. While in some ways a spiritual successor to cocotb-bus\, Forastero goes further and provides mechanisms for generating complex random stimulus. In this talk I’ll present how you can use Forastero to quickly construct a testbench around a DUT\, driving and monitoring multiple interfaces\, and producing complex stimulus patterns. Forastero is fully open source and comes with both documentation and examples. It can be found on GitHub at github.com/Intuity/forastero \nDFHDL: The 3-in-1 Abstraction Approach to Hardware Design\nOron Port\nJoin us for a dive into DFHDL (DFiant Hardware Description Language)\, where we break down a fresh approach to hardware design. This talk introduces a unique three-layer abstraction method that blends Dataflow (DF)\, Register-Transfer (RT)\, and Event-Driven (ED) models into one streamlined framework. We’ll explore how DFHDL simplifies and speeds up the logic design processes and our goals to do the same for verification. Expect a straightforward discussion on how each layer of DFHDL works\, why it matters\, and what it means for the future of hardware design. We’ll share real-life examples and insights that show DFHDL in action. Whether you’re deep into hardware design or just curious about how chips come to life\, this talk has something for you. DFHDL is an opensource framework available at https://dfianthdl.github.io/ (WIP) \nBYOL (Build Your Own Linter) – UVMLint for IEEE-UVM core code development\nAjeetha Kumari Venkatesan\nUVM is the most adopted design verification methodology in the field of ASIC and FPGA designs. Lint and static checking of code has proven to be very effective in projects that have wide user base\, longer lifetime and distributed developers. During the recent UVM IEEE 1800.2-2023 release cycle\, an observation was made regarding the potential application of a custom UVMLint solution to lint the UVM Base Class Library (BCL) as it gets developed\, updated etc. We at AsFigo have developed custom rules for linting UVM BCL code on top of PySlint\, an open-source SystemVerilog testbench linter. We intend to offer this as an opensource lint package to the UVM IEEE committee and to the general audience via GitHub. The eventual goal is to have these rules as gatekeepers via GitHub actions so that any future code addition to the UVM BCL is free from common pitfalls. Based on early brainstorming\, below are some of the sample lint rules that are relevant to the UVM BCL codebase: • Avoid race condition around “static const” (use localparam instead) • Avoid one-liner conditional statements: o if (cond) $display (“cond”); o if (cond) .. else $display (“Else cond as single line”); o case..endcase • Avoid one-liner code in loops: o for\, repeat\, while\, do..while\, foreach • Use enadlabels for elements such as endclass\, endfunction\, endtask etc. • Flag non-virtual methods Typical UVMLint rules for a VIP user would be quite different from the requirements of UVM BCL. These rules are tailored for UVM BCL codebase. As an example\, a typical UVMLint rule for a VIP would be: • Check that agent is reusable by ensuring that active components are guarded with a conditional check to is_active == UVM_ACTIVE Such a rule is quite useless for UVM BCL as it provides the base class library for tens of thousands of engineers around the globe using this library to build VIPs\, verify their IPs\, systems etc. In this talk we show how we approach this cusotm UVMLint development with sample Python code\, tests and results. A snapshot of UVMLint findings on latest IEEE 1800.2-2023 codebase is below: ** Violation count by Rule-IDs ** DBG_CL_MISSING_ENDLABEL : 286 DBG_METHOD_MISSING_ENDLABEL : 1899 DBG_FN_MISSING_ENDLABEL : 752 DBG_AVOID_ONE_LINER_IF : 73 DBG_AVOID_ONE_LINER_ELSE : 88 RACE_NO_STATIC_CONST : 8 REUSE_NON_VIRTUAL_METHOD : 1407 — UVMLint Concise Report — Total number of rules violated: 7 \nContact\nPlease feel free to reach out to the event organizers via orconf@fossi-foundation.org at any point. Or send a message on the Matrix channel: #orconf2024:fossi-foundation.org.
URL:https://marketingeda.com/event/orconf-2024/
LOCATION:Gothenburg\, Gothenburg\, Sweden
CATEGORIES:Conference,EDA,IP
ATTACH;FMTTYPE=image/jpeg:https://marketingeda.com/wp-content/uploads/ORConf-2024.jpg
END:VEVENT
BEGIN:VEVENT
DTSTART;TZID=America/Los_Angeles:20240912T120000
DTEND;TZID=America/Los_Angeles:20240912T130000
DTSTAMP:20240823T181126Z
CREATED:20240823T181114Z
LAST-MODIFIED:20240823T181126Z
UID:8265-1726142400-1726146000@marketingeda.com
SUMMARY:Unleash Performance\, Save Power: Mastering Processor Customization with the Tensilica Instruction Extension (TIE) Language
DESCRIPTION:Join us for an engaging webinar where we show you how to turbocharge performance and minimize power consumption by harnessing the power of custom instructions using the TIE language. Don’t miss this opportunity to optimize your processors like never before! \nTIE enables you to compute and move data many times faster than conventional processors\, resulting in faster yet more power-efficient cores while maintaining full programmability and debugability. \nThis webinar will introduce users to the easy-to-use TIE language and techniques for accelerating computation that can be used to optimize processors for specific target applications. \nLearn how Tensilica TIE language can be implemented to: \n\nSignificantly save SOC Power\nTurbocharge SOC Performance\nMaster processor customization with custom instructions
URL:https://marketingeda.com/event/unleash-performance-save-power-mastering-processor-customization-with-the-tensilica-instruction-extension-tie-language/
CATEGORIES:EDA,IP,Webinar
ATTACH;FMTTYPE=image/jpeg:https://marketingeda.com/wp-content/uploads/Cadence-September-12-2024-1.jpg
END:VEVENT
BEGIN:VEVENT
DTSTART;TZID=America/Los_Angeles:20240912T100000
DTEND;TZID=America/Los_Angeles:20240912T110000
DTSTAMP:20240814T174526Z
CREATED:20240814T174526Z
LAST-MODIFIED:20240814T174526Z
UID:8237-1726135200-1726138800@marketingeda.com
SUMMARY:Leveraging Verisium Debug to Debug Digital-Mixed Signal Designs
DESCRIPTION:Many of today’s designs that are primarily digital also contain analog components. We refer to such designs as “Digital-Mixed-Signal” or DMS designs. In this webinar\, we will demonstrate using the Verisium Debug App to debug such DMS designs. \n\n\n\n\n\n\n\n\n\n\n\n\nWhat You Will Learn \n\n\n\n\n\n\n\n\n\n\n\n\n\nHow Verisium Debug supports debugging Xcelium (Real Number Modeling) RNM and mixed Xcelium and Spectre simulations\nHow Verisium Debug can be used to debug User-Defined Nets (UDNs)\nThe analog waveform debug features of Verisium Debug\n\n\n\n\n\n\n\n\n\n\n\n\n\nWho Should Attend \n\n\n\n\n\n\n\n\n\n\n\n\nThis webinar is designed for design and verification engineers of all levels who need to debug Digital-Mixed-Signal designs when simulating using Xcelium Real Number Modeling (RNM) or mixed Xcelium/Spectre Digital-Mixed-Signal simulations. \n\n\n\n\n\n\n\n\n\n\n\n\nSpeakers \n\n\n\n\n\n\n\n\n\n\n\n\n\nDoug Koslow\, Product Engineering Architect\, Cadence\nRich Chang\, Product Marketing Director\, Cadence
URL:https://marketingeda.com/event/leveraging-verisium-debug-to-debug-digital-mixed-signal-designs/
CATEGORIES:EDA,Webinar
ATTACH;FMTTYPE=image/jpeg:https://marketingeda.com/wp-content/uploads/Cadence-September-12-2024.jpeg
END:VEVENT
BEGIN:VEVENT
DTSTART;TZID=America/Los_Angeles:20240912T100000
DTEND;TZID=America/Los_Angeles:20240912T110000
DTSTAMP:20240813T193558Z
CREATED:20240813T193538Z
LAST-MODIFIED:20240813T193558Z
UID:8234-1726135200-1726138800@marketingeda.com
SUMMARY:Addressing 3D-IC Power Integrity Design Challenges
DESCRIPTION:Power network design and analysis of 3D-ICs is a major challenge because of the complex nature and large size of the power network. In addition\, designers must deal with the complexity of routing power through the interposer\, multiple dies\, through-silicon vias (TSVs)\, and through-dielectric vias (TDVs). In this webinar\, you will learn how the Cadence Integrity 3D-IC Platform and Voltus IC Power Integrity Solution provides: \n\nFully integrated solution for early planning and analysis of 3D-IC power networks\n3D-IC chip-centric power integrity signoff\nHierarchical methods that significantly improve the capacity and performance of power integrity signoff while maintaining a very high level of accuracy at signoff
URL:https://marketingeda.com/event/addressing-3d-ic-power-integrity-design-challenges/
CATEGORIES:EDA,IP,Webinar
ATTACH;FMTTYPE=image/jpeg:https://marketingeda.com/wp-content/uploads/Cadence-September-12-2024.jpg
END:VEVENT
BEGIN:VEVENT
DTSTART;TZID=Asia/Shanghai:20240912T080000
DTEND;TZID=Asia/Shanghai:20240912T170000
DTSTAMP:20240605T173645Z
CREATED:20240605T173645Z
LAST-MODIFIED:20240605T173645Z
UID:8079-1726128000-1726160400@marketingeda.com
SUMMARY:D&R IP-SoC China 2024 Day
DESCRIPTION:D&R IP-SoC China 2024 Day is the unique worldwide event in China fully dedicated to IP (Silicon Intellectual Property) and IP based Electronic Systems. \nIP-SoC providers\, the seed of innovation in Electronic Industry\, are invited to highlight their latest products and services and share their vision about the next innovation steps in the Electronic Industry. \nIP consumers can view at a glance the latest Technology trends and exciting Innovative IP/SoC products. Through a global view\, Electronic systems leaders may identify disruptive innovation leading to new market segment growth. \nThe event is a face to face meeting. In order to enhance the market attention the talk material and videos are posted concurrently on www.design-reuse-china.com and Youku.
URL:https://marketingeda.com/event/dr-ip-soc-china-2024-day/
LOCATION:Evergreen Laurel Hotel\, Evergreen Laurel Hotel (Taichung)No. 666\, Sec. 2 Taiwan Boulevard\, Taichung\, Taiwan
CATEGORIES:Conference,EDA,IP
ATTACH;FMTTYPE=image/jpeg:https://marketingeda.com/wp-content/uploads/DR-IP-SOC-China-2024.jpg
END:VEVENT
BEGIN:VEVENT
DTSTART;TZID=America/Chicago:20240912T080000
DTEND;TZID=America/Chicago:20240912T170000
DTSTAMP:20240409T162326Z
CREATED:20240409T162326Z
LAST-MODIFIED:20240409T162326Z
UID:7817-1726128000-1726160400@marketingeda.com
SUMMARY:Verification Futures Conference 2024 Austin
DESCRIPTION:The Verification Futures conference provides a unique blend of conference presentations\, exhibitions\, training and industry networking sessions dedicated to discussing the challenges faced in hardware and software verification. Verification Futures provides a unique opportunity for end-users to define their current and future verification challenges and collaborate with the vendors to create solutions. It also provides an excellent opportunity to network and catch up with other verification engineers and vendors from across Europe. Finally\, we welcome students to encourage them on their first step into semiconductors as verification engineers. \nWe have the first speaker details on CPU User Presentations \nAccelerating RISC-V testbench development with open source RISC-V RTL and emulation\n– Varun Koyyalagunta\, Design Verification Engineer\, Tenstorrent\nToday’s shorter product time to market makes silicon verification runway shorter. Tenstorrent is working on CPUs based on RISC-V architecture for many AI applications. Since this is an emerging processor environment having RTL ready is not an easy task. Once RTL is available the testbench should be ready for both simulation and emulation workloads. Also\, we should have all test collaterals ready to go\, which involves firmware\, drivers\, applications etc. \nAt Tenstorrent we solved this problem by adopting RTL from RISC-V open source. This enabled us to shift left the emulation and simulation testbench creation. We use a standard memory interface\, AXI\, standard instruction interface\, RISC-V Formal Interface (RVFI)\, and the open source CVA-6 RISC-V cpu to develop testbench architecture and collateral in advance with full architectural instruction-by- instruction checking. This helped us complete the testbench development and test infrastructure ready without our custom CPU RTL. When the inhouse RTL is ready\, we could be able to replace our custom CPU RTL with open source CVA-6 processor. \nThis methodology helped us significantly shift left the testbench and test infrastructure readiness. Due to this\, we could able to innovate in the area of test collateral creation\, making emulation ready infrastructure and were confident to run application level tests the minute RTL was available. We used ZeBu for emulation work on this accelerated testbench creation with open source RTL. \n3 Key Points  \n·       Tenstorrent seeks to develop a high performance RISC-V core and bring it market ASAP \n·       Emulation is a must for software development and function verification \n·       How do we keep DV out of the critical path? \n\n\nConference Program\n\n\n\n\n\n\n\n\n\n\n\n\n\n\n\n\n\n\n08:30\nArrival: Breakfast and Networking\nSlides\nVideos\n\n\n09:25\nWelcome: Mike Bartley\, Tessolve Semiconductor Ltd\n\n\n\n\n\nKeynote Speakers\n\n\n\n\n09:30\nPresentation Title Hemendra Talesara (Company Name)\n\n\n\n\n10:15\nUser Top Verification Challenges\n\n\n\n\n10:15\nPresentation Title Speaker Name (Company Name)\n\n\n\n\n10:30\nPresentation Title Speaker Name (Company Name) – Platinum Sponsor\n\n\n\n\n11:00\nRefreshments and Networking\n\n\n\n\n\nMulti-Track Session (AM)\n\n\n\n\n\nCPU User Presentations\n\n\n\n\n11:30\nPresentation Title Mike Thompson (OpenHW Group)\n\n\n\n\n11:50\nAccelerating RISC-V testbench development development with open source RISC-V RTL and emulation \nVarun Koyyalagunta(Tenstorrent)\n\n\n\n\n12:10\nPresentation Title Speaker Name (Company Name)\n\n\n\n\n\nTrack 2 – Training Session 1\n\n\n\n\n11:30\nPresentation Title Speaker Name (Doulos) – Gold Sponsor\n\n\n\n\n\nTrack 3 – UVM for AMS Verification\n\n\n\n\n11:30\nPresentation Title Speaker Name (Company Name)\n\n\n\n\n12:30\nLunch and Networking\n\n\n\n\n13:30\nPresentation Title Speaker Name (Company Name) – Platinum Sponsor\n\n\n\n\n14:00\nPresentation Title Speaker Name (Company Name) Gold Sponsor\n\n\n\n\n14:20\nPresentation Title Speaker Name (Company Name)\n\n\n\n\n14:40\nPresentation Title Speaker Name (Company Name)\n\n\n\n\n15:00\nRefreshments and Networking\n\n\n\n\n\nMulti-Track Session (PM)\n\n\n\n\n\nTrack 1 – Latest topics in Verification\n\n\n\n\n15:30\nPresentation Title Speaker Name (Company Name)\n\n\n\n\n15:50\nPresentation Title Speaker Name (Company Name)\n\n\n\n\n16:10\nPresentation Title Speaker Name (Company Name)\n\n\n\n\n\nTrack 2 – Training Session 2\n\n\n\n\n15:30\nPresentation Title Speaker Name (Doulos) – Gold Sponsor\n\n\n\n\n\nTrack 4 – VHDL Verification\n\n\n\n\n15:30\nPresentation Title Speaker Name (Company Name)\n\n\n\n\n16:30\nEvent Closes
URL:https://marketingeda.com/event/verification-futures-conference-2024-austin/
LOCATION:Austin Marriott South\, 4415 South Interstate 35 Frontage Road\, Austin\, TX\, United States
CATEGORIES:Conference,EDA,IP
ATTACH;FMTTYPE=image/jpeg:https://marketingeda.com/wp-content/uploads/Verification-Futures-2024-Austin.jpg
END:VEVENT
BEGIN:VEVENT
DTSTART;TZID=America/Los_Angeles:20240911T080000
DTEND;TZID=America/Los_Angeles:20240911T090000
DTSTAMP:20240821T163437Z
CREATED:20240821T163437Z
LAST-MODIFIED:20240821T163437Z
UID:8259-1726041600-1726045200@marketingeda.com
SUMMARY:Questa Formal Verification IP AMBA: Achieve Protocol Compliance in Designs
DESCRIPTION:Delve into how Questa Formal Verification IP (VIP) for the AMBA protocol ensures that designs incorporating AMBA adhere strictly to the protocol; all without the need for simulation. The solution integrates comprehensive protocol knowledge and provides user-friendly interfaces\, significantly reducing the setup time for verification environments. Optimized for top-tier performance and scalability\, Questa Formal VIP AMBA is the ideal tool for achieving high-efficiency and accurate protocol compliance. Don’t miss this opportunity to learn how to streamline your verification process and enhance your design workflows. \n  \nWhat You Will Learn:  \n\nChallenges in IP Integration\nUnderstand the common obstacles faced by designers and verification teams during IP integration and how to overcome them.\nBenefits of Formal Verification Ips\nDiscover the advantages of using formal verification IPs\, including enhanced accuracy and reduced need for simulation.\nCapabilities and Supported Protocols\nExplore the extensive capabilities of Questa Formal VIP AMBA and the range of protocols it supports.\nFrom Specification to Formal Properties\nLearn how protocol specifications are transformed into formal properties for effective verification.\nDebugging Protocol Violations\nGain insights into debugging techniques for protocol violations to ensure compliance and reliability.\n\n            \nWho Should Attend:  \n\nRTL Design Engineers\nDesign Integrators\nDesign Verification Engineers\n\nWhat/Which Products are Covered:   \n\nQuesta Formal VIP AMBA\nQuesta Formal VIP OnChip\nQuesta Check Register\n\n\n\nSpeaker:\n\n\n\n\n\n\nNicolae Tusinschi\nFormal Verification Solutions Product Manager\, Siemens EDA\n\n\n\n\nNicolae Tusinschi is a product manager for formal verification solutions at Siemens EDA. He holds a master’s degree combined between the University of Southampton and the University of Kaiserslautern. After a master’s thesis at Continental\, Nicolae joined OneSpin\, where he worked in QA\, then as a product specialist and later served as product owner for design verification tools at OneSpin. His key projects include integrating simulation coverage with formal metrics\, leveraging coverage results in the verification process\, formal verification of RISC-V cores.
URL:https://marketingeda.com/event/questa-formal-verification-ip-amba-achieve-protocol-compliance-in-designs/
CATEGORIES:EDA,IP,Webinar
ATTACH;FMTTYPE=image/jpeg:https://marketingeda.com/wp-content/uploads/Siemens-Setember-11-2024.jpg
END:VEVENT
BEGIN:VEVENT
DTSTART;TZID=America/Los_Angeles:20240910T100000
DTEND;TZID=America/Los_Angeles:20240910T110000
DTSTAMP:20240909T174044Z
CREATED:20240909T174044Z
LAST-MODIFIED:20240909T174044Z
UID:8317-1725962400-1725966000@marketingeda.com
SUMMARY:Faster Design TAT and Upscaled Team Productivity with Cadence’s True Hybrid Cloud
DESCRIPTION:Join us for an informative webinar as we unveil the new hybrid cloud capabilities of our cloud solutions designed to revolutionize EDA workloads. Whether you need peak capacity for a short duration or want a front-to-back turnkey cloud environment\, our cloud solutions offer unparalleled flexibility and efficiency. \nWe will discuss how Cadence True Hybrid Cloud and Cadence Managed Cloud can optimize cost-efficiency and productivity for your design projects. \nDon’t miss our live demonstrations\, where we’ll showcase the rapid deployment of peak capacity in the cloud\, productivity benefits\, and robust security features. Plus\, discover how you can kickstart your journey with a 30-day free trial. \n\n\n\n\n\n\n\n\n\n\n\n\nWho Should Attend \n\n\n\n\n\n\n\n\n\n\n\n\nThis webinar is designed for chip designers\, Cloud IT architects\, CAD platform teams\, and business decision makers. \n\n\n\n\n\n\n\n\n\n\n\n\nSpeakers \n\n\n\n\n\n\n\n\n\n\n\n\n\nKetan Joshi\, Sr. Business Development Group Director\, Cadence\nMichael Reed\, Sr. Staff Systems Engineer\, Cadence
URL:https://marketingeda.com/event/faster-design-tat-and-upscaled-team-productivity-with-cadences-true-hybrid-cloud/
CATEGORIES:EDA,Webinar
ATTACH;FMTTYPE=image/jpeg:https://marketingeda.com/wp-content/uploads/Cadence-September-10-2024.jpg
END:VEVENT
BEGIN:VEVENT
DTSTART;TZID=America/Los_Angeles:20240910T090000
DTEND;TZID=America/Los_Angeles:20240910T100000
DTSTAMP:20240820T162341Z
CREATED:20240820T162341Z
LAST-MODIFIED:20240820T162341Z
UID:8252-1725958800-1725962400@marketingeda.com
SUMMARY:Can AI make cameras see in the dark?
DESCRIPTION:Abstract\n  \n\nAs cameras become ubiquitous in applications such as surveillance\, mobile\, drones\, and automotive systems\, achieving clear vision 24/7 under any condition—including extreme low light and high dynamic range scenarios—has become essential. By leveraging Edge AI processors\, a software ISP based on neural network technology can process and optimize video in real-time\, surpassing human vision capabilities in these challenging conditions.\nIn this webinar\, we will explore how to harness the power of Ceva’s NPU alongside Visionary.ai’s advanced AI software Image Signal Processing (ISP) to significantly enhance video quality across various camera-enabled applications. Visionary.ai utilizes Neural Processing Units (NPUs) to boost camera performance\, especially in demanding environments like extreme low-light and high dynamic range (HDR) scenarios.\nFinally\, we will introduce an available reference design for this joint solution and showcase the impressive results achieved. \nJoin Ceva and Visionary.ai experts to learn about: \n\nThe power of Edge AI for computer vision\nModern NPU architecture fundamentals\nTrue Night Vision software ISP\nThe role of video denoising in solving the low-light challenge\nThe technical challenges to implement an AI based ISP on an NPU\nHow can Ceva and Visionary.ai enhance your camera enabled application\n\n\nTarget Audience\n  \nVision system architects\, hardware and software engineers\, and product managers targeting camera enabled devices\, that are looking to enhance their product ability to cope with extreme low-light conditions using the power of Edge AI.\n\nSpeakers\n\n\n\n\n\n\n\nRonny Vatelmacher\nDirector of Product Marketing\, Vision and AI\, Ceva\n\n\n\n\n\n\n\n\n\nDavid Jarmon\nSVP Worldwide Sales\, Visionary.ai
URL:https://marketingeda.com/event/can-ai-make-cameras-see-in-the-dark/
CATEGORIES:IP,Webinar
ATTACH;FMTTYPE=image/jpeg:https://marketingeda.com/wp-content/uploads/Ceva-September-10-2024.jpg
END:VEVENT
BEGIN:VEVENT
DTSTART;TZID=America/Los_Angeles:20240909T083000
DTEND;TZID=America/Los_Angeles:20240909T180000
DTSTAMP:20240830T171619Z
CREATED:20240830T171619Z
LAST-MODIFIED:20240830T171619Z
UID:8287-1725870600-1725904800@marketingeda.com
SUMMARY:IP-SoC South Korea 24
DESCRIPTION:A worldwide connected Event !! \nD&R IP-SoC South Korea 2024 Day is the unique worldwide Spring event fully dedicated to IP (Silicon Intellectual Property) and IP based Electronic Systems. \nIP-SoC providers\, the seed of innovation in Electronic Industry\, are invited to highlight their latest products and services and share their vision about the next innovation steps in the Electronic Industry. \nIP consumers can view at a glance the latest Technology trends and exciting Innovative IP/SoC products. Through a global view\, Electronic systems leaders may identify disruptive innovation leading to new market segment growth. \nAny question? Please contact us \n\n\n\n\n\n\n\n\nWelcome\n \nChairperson: Yu Byoung Du\, KSIA\n\n\n\n\nOpening talk from KSIA Vice Chairman \nJeong-Hoi Kim\nViceChair\nKSIA \nAbout me\n\n\n\n\nWelcome to IP-SoC Community \nGabrièle Saucier\nCEO\nDesign And Reuse \nAbout me\n\n\n\n\n9:00 am\nAnalog IP\n \nChairperson: Yu Byoung Du\, KSIA\n\n\n\n\nAnalog IP Solution for SAMSUNG Foundry \nMyeon-Lyong Ko\nR&D Center Director\nLeoLSI \nAbout me\n\n\n\n\nPower Management Sensor IP’s for FinFet and GAA processes \nMahesh Tirupattur\nExecutive Vice President\nAnalog Bits Inc. \nAbout me\n\n\n\n\n9:40 am\nBreak\n\n\n\n10:00 am\nInterface and Connectivity IP\n \nChairperson: Yu Byoung Du\, KSIA\n\n\n\n\nLPDDR Support on Mature Technology Nodes \nDave DongHun Kim\nSenior Manager\, FAE\nOPENEDGES Technology\, Inc. \nAbout me\n\n\n\n\nBeyond the interface IP \nTae-Pyeong Kim\nCadence Design Systems\, Inc. \nAbout me\n\n\n\n\nUCIe Progress Report: Big Enhancements\, IP Maturity\, and Ecosystem Interoperability \nHyoung-Bae Choi\nSr. Director\nSynopsys\, Inc. \nAbout me\n\n\n\n\n11:00 am\nBreak\n\n\n\n11:20 am\nRISC-V\n \nChairperson: Yu Byoung Du\, KSIA\n\n\n\n\nLeveraging the RISC-V Efficient Trace (E-Trace) Standard \nSoo Yong Lee\nAccount Technology Manager\nSiemens \nAbout me\n\n\n\n\nImagination APXM-6200 CPU: Performance meets Trust in RISC-V \nJongChan (Brian) Mun\nSenior Sales Director\nImagination Technologies Group Ltd. \nAbout me\n\n\n\n\n12:00 pm\nLunch Break\n\n\n\n1:00 pm\nArtificial Intelligence\n \nChairperson: Mahesh Tirupattur\, Analog Bits\n\n\n\n\nScalable\, Flexible Edge AI accelerator: Silicon-Proven IP for Consumer Electronics \nChangSoo Kim (CEO)\nCEO\nAiM Future\, Inc. \nAbout me\n\n\n\n\nMeeting the Needs of AI Training with HBM3E \nSuk Keun Youn\nDirector of Sales\nRambus\, Inc. \nAbout me\n\n\n\n\nAI on RISC-V \nHojung Han\nStaff Applications Engineer\nImagination Technologies Group Ltd. \nAbout me\n\n\n\n\n2:00 pm\nBreak\n\n\n\n2:20 pm\nVideo\n \nChairperson: Philippe Flatresse\, Soitec\n\n\n\n\nFuture of ISP ( Camera ISP & Display ISP ) \nDaeha Kook\nDirector\nBTREE Co. Ltd. \nAbout me\n\n\n\n\nAI-based video pre-processor to reduce the storage cost and network traffic for video applications \nHyung-Seok Han\nDirector of Marketing\nBLUEDOT \nAbout me\n\n\n\n\n3:00 pm\nBreak\n\n\n\n3:20 pm\nSecurity and High Safety Solutions\n \nChairperson: Philippe Flatresse\, Soitec\n\n\n\n\nQuantum Safe Cryptography: Protecting Devices and Data in the Quantum Era \nJihan Moon\nSenior Principal Engineer in Field Application Engineering\nRambus\, Inc. \nAbout me\n\n\n\n\nPUF based Root of Trust for Emerging Post Quantum Cryptography \nDuhyun Jeon\nSenior Engineer\nICTK \nAbout me\n\n\n\n\nAI-powered cybersecurity: Securyzr™ Intrusion Detection System (IDS)​ \nAhmed BOUGRIANE\nPre-Sales Engineer North Asia\nSecure-IC \nAbout me\n\n\n\n\nHow SafeIP(TM) enables fail operational vehicles\, robotics and drones \nDiana Strohbach\nHead of Marketing & Collaboration\nSiliconally GmbH \nAbout me\n\n\n\n\n4:40 pm\nMonitoring & Design Platform\n \nChairperson: Philippe Flatresse\, Soitec\n\n\n\n\nThe Critical Role of Embedded Monitor IP in Enabling Silicon Lifecycle Management Use Cases \nSangmin Lee\nProject/Program Manager EDA Group\nSynopsys\, Inc. \nAbout me\n\n\n\n\nThe Advantages of Using HW Stacks in Your Design \nDr. Calliope-Louisa Sotiropoulou\nSales Engineer\nCAST\, Inc. \nAbout me\n\n\n\n\n6:00 pm\nEvent Closure
URL:https://marketingeda.com/event/ip-soc-south-korea-24/
LOCATION:EL Tower 6F\, 213 Gangnamdaero\, Seoul\, Korea\, Republic of
ATTACH;FMTTYPE=image/jpeg:https://marketingeda.com/wp-content/uploads/IP-SoC-South-Korea-24.jpg
END:VEVENT
BEGIN:VEVENT
DTSTART;TZID=America/Los_Angeles:20240909T080000
DTEND;TZID=America/Los_Angeles:20240912T170000
DTSTAMP:20240718T193601Z
CREATED:20240718T193601Z
LAST-MODIFIED:20240718T193601Z
UID:8164-1725868800-1726160400@marketingeda.com
SUMMARY:AI Hardware & Edge AI Summit 2024
DESCRIPTION:The AI Hardware & Edge AI Summit is the ultimate destination for the entire AI and ML ecosystem\, with a collaborative mission to train\, deploy and scale machine learning systems that are fast\, affordable\, and efficient. \nWhether it’s forging new partnerships\, staying ahead of the ever-changing semi-conductor landscape\, learning how to build\, train\, and deploy efficient systems\, meeting peers\, learning from AI luminaries\, or simply gaining exposure to the world of AI infrastructure\, you’ll find over 1\,200 likeminded people at our event. \nTake it from the thousands of industry peers who have attended in the past\, if you’re in the AI infrastructure and semiconductor worlds\, this is one not to miss!
URL:https://marketingeda.com/event/ai-hardware-edge-ai-summit-2024/
LOCATION:Signia by Hilton\, 170 S Market Street\, San Jose\, CA\, 95113\, United States
CATEGORIES:Conference,IP,Semiconductor
ATTACH;FMTTYPE=image/jpeg:https://marketingeda.com/wp-content/uploads/AI-Hardware-Edge-AI-Summit-2024.jpg
ORGANIZER;CN="Kisaco Research":MAILTO:events@kisacoresearch.com
END:VEVENT
BEGIN:VEVENT
DTSTART;TZID=America/Denver:20240909T080000
DTEND;TZID=America/Denver:20240911T170000
DTSTAMP:20240524T202400Z
CREATED:20240524T202400Z
LAST-MODIFIED:20240524T202400Z
UID:8043-1725868800-1726074000@marketingeda.com
SUMMARY:MLCAD Symposium 2024
DESCRIPTION:The symposium focuses on Machine Learning (ML) for all aspects of CAD and electronic system design. The symposium is sponsored by both the ACM Special Interest Group on Design Automation (SIGDA) and the IEEE Council on Electronic Design Automation (CEDA). The symposium program will have keynote and invited speakers in addition to technical presentations.\nMLCAD 2024 will be held physically in Snowbird\, Utah. \nFocus\nAdvances in machine learning (ML) over the past half-dozen years have revolutionized the effectiveness of ML for a variety of applications. However\, design processes present challenges that require synergetic advances in ML and CAD as compared to traditional ML applications. As such\, the purpose of the symposium is to discuss\, define and provide a roadmap for the special needs for ML for CAD where CAD is broadly defined to include both design-time techniques as well as run-time techniques.\nTopics of interest to this symposium include but are not limited to:\n• LLM-CAD: Large Language Model for CAD\n• ML approaches to logic design.\n• ML for physical design.\n• ML for analog design.\n• ML for FPGA designs.\n• ML methods to predict and optimize circuit aging and reliability.\n• Labeled and unlabeled data in ML for CAD.\n• ML for power and thermal management.\n• ML techniques for resource management in many-cores.\n• ML for Design Technology Co-Optimization (DTCO).\n• ML for design verification.\n• ML for manufacturing test.
URL:https://marketingeda.com/event/mlcad-symposium-2024/
LOCATION:Snowbird\, 9385 Snowbird Center Trail\, Sandy\, UT\, United States
CATEGORIES:EDA,Symposium
ATTACH;FMTTYPE=image/jpeg:https://marketingeda.com/wp-content/uploads/MLCAD-2024.jpg
END:VEVENT
BEGIN:VEVENT
DTSTART;TZID=America/Los_Angeles:20240905T110000
DTEND;TZID=America/Los_Angeles:20240905T120000
DTSTAMP:20240903T175441Z
CREATED:20240903T175441Z
LAST-MODIFIED:20240903T175441Z
UID:8291-1725534000-1725537600@marketingeda.com
SUMMARY:Using OSVVM’s AXI4 Verification Components
DESCRIPTION:Abstract: \nThis “Getting Started” presentation is for engineers who need to use the OSVVM AXI4 verification components (VCs) in their testbenches. Part 2 of this presentation focuses on how to write tests and configure the AXI4 VCs. \nAXI4 VCs are probably the most complex VCs in the OSVVM library. This complexity is due to the AXI4 interface having 5 independent interfaces: Write Address\, Write Data\, Write Response\, Read Address\, and Read Data.   Going further\, the interface supports user configurable optional aspects of the interface – such as the ID and User fields. \nIn this presentation we examine the structure of OSVVM test cases\, the AXI4 transaction API\, how to do byte transfers\, how to do burst transfers\, how to handle arrays of VCs\, how to configure AXI4 VC options\, how to randomize delays for xValid or xReady\, and how the test case can directly read or write values in the Axi4Memory. \nAs we look at the OSVVM transaction API we will note that it does not specify the byte enables. Instead\, OSVVM determines the byte enables by looking at the width of the data and the lower bits of the address. \nOSVVM’s burst interface is supported by FIFOs that are in the transaction interface. These FIFOs allow any size of std_logic_vector value to be pushed into them. This allows the burst interface to be used in either byte mode or word mode. In byte mode\, the burst is a sequence of bytes that are assembled by the VC into interface words. This allows OSVVM to create test cases that are independent of the actual data bus width. \nAbout OSVVM \n\nOSVVM is a suite of libraries designed to streamline your VHDL entire verification process\, boosting productivity and reducing development time. Each library provides independent capabilities\, allowing selective adoption and a learn-as-you-go approach. Whether using directed or random testing\, OSVVM facilitates writing concise and readable test cases for both unit/RTL tests and complex FPGA and ASIC tests. \nOSVVM provides VHDL with verification capabilities that rival SystemVerilog + UVM. These include transaction-level modeling\, verification components\, co-simulation with software\, randomized test generation\, self-checking test support\, verification data structures\, comprehensive test reporting in HTML and text\, and synchronization primitives.\n\nWith OSVVM and a good team lead\, any VHDL engineer can do verification – and have fun doing it. As a result\, having your entire team united in using OSVVM will simplify deploying VHDL engineers to projects.\n\nSynthWorks has been using OSVVM for 25+ years in our training classes and consulting work. During that time\, we have innovated new capabilities and evolved our existing ones to increase re-use and reduce effort and time spent.\n\nWhy VHDL for verification? According to the 2022 Wilson Research Group Functional Verification Study\, in the FPGA market\, 66% use VHDL for design\, 58% use VHDL for verification\, and 28% use OSVVM. Hence\, VHDL is #1 for FPGA development and OSVVM is #1 for VHDL verification.\n\nWebinar Duration:  \n\n50 min presentation/live demo\n15 min Q&A\n\nPresenter Bio: \n \nJim Lewis\, VHDL Design and Verification Expert\, Trainer\, OSVVM developer\, and IEEE VHDL Chair \nJim Lewis is an innovator and leader in the VHDL community. He has 30 plus years of design and teaching experience. He is the Chair of the IEEE 1076 VHDL Standards Working Group. He is a co-founder of the Open Source VHDL Verification Methodology (OSVVM) and the chief architect of the packages and methodology. He is an expert VHDL trainer for SynthWorks Design Inc. In his design practice\, he has created designs for print servers\, IMA E1/T1 networking\, fighter jets\, video phones\, and space craft. \nWhether teaching\, developing OSVVM\, consulting on VHDL design and verification projects\, or working on the IEEE VHDL standard\, Mr. Lewis brings a deep understanding of VHDL to architect solutions that solve difficult problems in simple ways.
URL:https://marketingeda.com/event/using-osvvms-axi4-verification-components/
CATEGORIES:EDA,Webinar
ATTACH;FMTTYPE=image/jpeg:https://marketingeda.com/wp-content/uploads/Aldec-September-5-2024.jpg
END:VEVENT
BEGIN:VEVENT
DTSTART;TZID=America/New_York:20240905T100000
DTEND;TZID=America/New_York:20240905T110000
DTSTAMP:20240807T213739Z
CREATED:20240807T213739Z
LAST-MODIFIED:20240807T213739Z
UID:8219-1725530400-1725534000@marketingeda.com
SUMMARY:Enhanced Packaging Performance and Manufacturing with Physics-Based 3D Simulation
DESCRIPTION:About this webinar\nDigital engineering is ramping up across the CPG\, healthcare and wider packaging sector. Packaging engineers are tasked with producing fit-for-purpose packaging that is optimised for customer-use\, transportation\, storage and for production-line filling/handling. In addition\, manufacturing the packaging containers as optimally as possible to avoid defects is vitally important. All in the landscape of sustainability. \nAnsys provides leading physics-based 3D simulation tools applicable to a wide range of scenarios from filling of liquids and solids\, drop-testing\, thermal management\, vibration under transportation\, top-load strength testing\, conveying\, package crimping\, blow moulding\, thermoforming\, heat-sealing and board-creasing. \nJoin this webinar to be updated on the latest virtual engineering simulation capabilities from Ansys in the packaging domain. \n  \nWhat you will learn\n\nThe use of physics-based 3D simulation to gain engineering insight into the performance of packaging whilst in the hands of an end-user\, in storage\, under transportation and during manufacture.\nThe state of the art from an Ansys perspective on the use of digital engineering to drive innovation\, efficiency and sustainability in the packaging sector.\nThe use of Ansys Granta Selector software for smarter material selection\n\n  \nWho should attend\n\nPackaging engineers and designers interested in the use of simulation in the packaging industry.\nMaterial scientists involved in the selection of materials for packaging.\nCurrent users of CFD\, Discrete Element Modelling\, structural and thermal simulation FEA tools in the packaging domain.\n\n  \nSpeakers\n\nMikael Schill\, Senior Manager and Application Engineering\, Ansys\nMarcus Redhe\, Director Application Engineering\, Ansys
URL:https://marketingeda.com/event/enhanced-packaging-performance-and-manufacturing-with-physics-based-3d-simulation/
CATEGORIES:EDA,Webinar
ATTACH;FMTTYPE=image/jpeg:https://marketingeda.com/wp-content/uploads/Ansys-September-5-2024.jpg
END:VEVENT
BEGIN:VEVENT
DTSTART;TZID=America/Los_Angeles:20240905T090000
DTEND;TZID=America/Los_Angeles:20240905T183000
DTSTAMP:20240711T225247Z
CREATED:20240711T225247Z
LAST-MODIFIED:20240711T225247Z
UID:8138-1725526800-1725561000@marketingeda.com
SUMMARY:Synopsys Processor IP Summit 2024: RISC-V\, DSP and NPU IP for Your Diverse SoC Processing Needs
DESCRIPTION:As electronic systems continue to become more complex and integrate greater functionality\, SoC developers are faced with the challenge of developing more powerful\, yet more energy-efficient devices. The processors used in these applications must be efficient to deliver high levels of performance within limited power and silicon area budgets. \n  \nWhy Attend?\nJoin us for the Processor IP Summit to get in-depth information from industry leaders on the latest in ARC-V™ RISC-V processor IP\, ARC® VPX DSP IP and ARC NPX NPU IP along with related hardware/software technologies that enable you to achieve PPA differentiation in your chip or system design. Synopsys experts\, partners\, and our processor IP user community will discuss electronic market trends and present on a range of topics including artificial intelligence\, automotive safety\, software development and more. Sessions will be followed by a networking reception where you can see live demos. \n  \nWho Should Attend?\nWhether you are a developer of chips\, systems or software\, the Synopsys Processor IP Summit will give you practical information to help you create more differentiated products in the shortest amount of time. \n  \nAgenda\nAgenda is coming soon
URL:https://marketingeda.com/event/synopsys-processor-ip-summit-2024-risc-v-dsp-and-npu-ip-for-your-diverse-soc-processing-needs/
LOCATION:Santa Clara Marriott\, 2700 Mission College Blvd\, Santa Clara\, CA\, 95054\, United States
CATEGORIES:Forum,IP
ATTACH;FMTTYPE=image/jpeg:https://marketingeda.com/wp-content/uploads/Synopsys-September-5-2024.jpg
END:VEVENT
BEGIN:VEVENT
DTSTART;TZID=America/New_York:20240904T100000
DTEND;TZID=America/New_York:20240904T110000
DTSTAMP:20240815T155544Z
CREATED:20240815T155544Z
LAST-MODIFIED:20240815T155544Z
UID:8245-1725444000-1725447600@marketingeda.com
SUMMARY:Hardware-Accurate Digital Twins  in Defense: Case Study
DESCRIPTION:The defense industry is increasingly seeking innovative approaches to accelerate system development while ensuring reliability. Hardware-accurate digital twins offer a promising solution. This webinar will explore the concept of hardware-accurate digital twins and their application in defense. \nJoin Cadence and Northrop Grumman as we delve into a real-world case study demonstrating the power of digital twins in defense program execution. Discover how hardware-accurate digital twins can be leveraged to streamline development processes\, reduce risks\, and improve overall system performance. This case study will give you practical insights into implementing digital twins in your next program development. \n\nAttendees Will Learn \n\nThe definition and benefits of hardware-accurate digital twins\nPractical applications in the defense industry\nA detailed case study showcasing successful implementation\nBest practices for adopting digital twin technology\n\n\nSpeakers \nAdam Sherer\, Account Technical Director\, Cadence\nMichael Gowan\, Verification Engineer\, Northrop Grumman\nBilly Gomez\, Sr. Principal Engineer Embedded Software\, Northrop Grumman
URL:https://marketingeda.com/event/hardware-accurate-digital-twins-in-defense-case-study/
CATEGORIES:EDA,Webinar
ATTACH;FMTTYPE=image/jpeg:https://marketingeda.com/wp-content/uploads/Cadence-September-4-2025.jpg
END:VEVENT
BEGIN:VEVENT
DTSTART;TZID=America/Los_Angeles:20240904T090000
DTEND;TZID=America/Los_Angeles:20240904T100000
DTSTAMP:20240806T194128Z
CREATED:20240806T194128Z
LAST-MODIFIED:20240806T194128Z
UID:8205-1725440400-1725444000@marketingeda.com
SUMMARY:Elevate Your Analog Layout Design to New Heights
DESCRIPTION:Are you ready to transform your career and become a master of analog layout design? Look no further than The Advanced Analog Layout Course! This course is meticulously crafted to enhance your physical design skills\, guiding you through the advanced techniques essential for creating top-notch\, well-matched\, and noise-resistant layouts on a CMOS process. \nLearn Anytime\, Anywhere! Our course is delivered through a user-friendly online portal\, granting you the power to learn at your own pace. Enjoy the flexibility of completing modules and watching nearly 100 instructional videos whenever it suits you best. \nTailored for Excellence! Whether you’re a seasoned layout engineer aiming to refine your skills or a front-end schematic designer eager to enhance your design methods\, this course is designed for you. With over 19 hours of content\, including seven comprehensive modules and regular assessments\, you’ll be equipped to produce more efficient and superior quality layouts. \nComprehensive Learning Experience! Dive into a wealth of knowledge with our extensive video library\, totalling over 19 hours of expert content. Our regular assessments ensure that you’re on track\, solidifying your understanding and boosting your confidence. \nJoin the ranks of the industry’s best and make your mark in the world of analog layout design. Enroll in The Advanced Analog Layout Course today and start your journey to becoming an analog layout virtuoso! \nReady to take the next step in your career? Join this webinar to learn more and sign up for the course that will set you apart in the competitive field of analog layout design.
URL:https://marketingeda.com/event/elevate-your-analog-layout-design-to-new-heights/
CATEGORIES:IP,Webinar
ATTACH;FMTTYPE=image/jpeg:https://marketingeda.com/wp-content/uploads/IC-Mask-Design-September-2024.jpg
END:VEVENT
BEGIN:VEVENT
DTSTART;TZID=Europe/London:20240903T120000
DTEND;TZID=Europe/London:20240903T130000
DTSTAMP:20240731T161732Z
CREATED:20240731T161715Z
LAST-MODIFIED:20240731T161732Z
UID:8191-1725364800-1725368400@marketingeda.com
SUMMARY:DVClub Europe - September 2024
DESCRIPTION:This DVClub event will have talks on verification of low power features of VLSI designs\, discussing strategies for accurately measuring power consumption and ensuring that power-saving mechanisms are effective. Additionally\, speakers will share insights on how to simulate and analyze different power scenarios to identify potential issues and optimize power management techniques. Attendees will have the opportunity to learn best practices for low power verification and gain valuable knowledge on how to successfully implement energy-efficient designs in their projects. Overall\, this event promises to provide valuable insights and practical strategies for ensuring the success of low power verification in VLSI designs. \nAgenda (BST)\n12:00 Welcome and Introduction – Mike Bartley\, Tessolve\n12:00 Satinder Paul\n12:20 Synopsys\n12:40 TBD\n13:00 Close
URL:https://marketingeda.com/event/dvclub-europe-september-2024/
CATEGORIES:EDA,Webinar
ATTACH;FMTTYPE=image/jpeg:https://marketingeda.com/wp-content/uploads/DVClub-Europe-2024.jpg
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BEGIN:VEVENT
DTSTART;TZID=America/Los_Angeles:20240829T100000
DTEND;TZID=America/Los_Angeles:20240829T110000
DTSTAMP:20240808T172706Z
CREATED:20240808T172706Z
LAST-MODIFIED:20240808T172706Z
UID:8222-1724925600-1724929200@marketingeda.com
SUMMARY:Micron Utilizes Silvaco’s Fab Technology Co-Optimization for Development and Manufacturing of Memory Technologies
DESCRIPTION:Memory products from Micron Technology\, such as DRAM components and 3D NAND\, are propelling the advancement of process technologies. Innovative modeling methods are required to tackle the complexities in fabricating structures and to evaluate process variation effects on electrical performance. \nThis webinar highlights how Micron Technology utilizes Silvaco’s Fab Technology Co-Optimization (FTCOTM) platform for the development and manufacturing of advanced memory technologies. Use cases demonstrate the application of virtual process models\, sensitivity analysis\, and stress modeling to optimize semiconductor processes. The collaborative effort between Silvaco and Micron shows how to build a digital twin of a fabrication process\, enabling a transformative solution for scaling memory technologies. \n\n\n\n\nPresenter\n\n\n\n\nSumeet Pandey\, Distinguished Member of Technical Staff\, Micron Technology \n\n\n\n\nWHO SHOULD ATTEND:\n\n\n\n\nTCAD engineers\, fab engineers\, process engineers\, product managers\, and engineering management.
URL:https://marketingeda.com/event/micron-utilizes-silvacos-fab-technology-co-optimization-for-development-and-manufacturing-of-memory-technologies/
CATEGORIES:EDA,Webinar
ATTACH;FMTTYPE=image/jpeg:https://marketingeda.com/wp-content/uploads/Silvaco-August-29-2024.jpg
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BEGIN:VEVENT
DTSTART;TZID=Asia/Tokyo:20240829T080000
DTEND;TZID=Asia/Tokyo:20240829T170000
DTSTAMP:20240805T220150Z
CREATED:20240805T220150Z
LAST-MODIFIED:20240805T220150Z
UID:8198-1724918400-1724950800@marketingeda.com
SUMMARY:DVCon Japan 2024
DESCRIPTION:The Design & Verification Conference & Exhibition is the premier conference on the application of languages\, tools\, methodologies and standards for the design and verification of electronic systems and integrated circuits. The focus of this highly technical conference is on the practical aspects of these technologies and their use in leading-edge projects to encourage attendees to adopt similar techniques to improve their own design and verification flows. \n\n\n\nDVCon Japan 2024 will be held on August 29\, 2024 in Shinagawa\, Tokyo. \nDVCon (Design and Verification Conference) is a conference mainly sponsored by Accellera Systems Initiative. DVCon focuses on solving problems in a wide range of areas such as logic design\, architecture study\, functional verification\, HW/SW co-verification\, analog simulation\, functional safety compliance\, security verification\, and application of AI to development flow in semiconductors and systems\, DVCon is the premier conference for learning and discussing best practices in the application of IEEE and Accellera standard languages\, formats\, and methodologies. \nDVCon has been held in the U.S. for more than 30 years and has been held in Japan since 2022\, with online and on-demand delivery in 2022 and in-person in 2023. We were able to offer a diverse and in-depth program with a variety of paper presentations\, tutorial sessions\, and exhibits from sponsors and exhibitors. We would like to thank all the audiences\, presenters\, sponsors\, and all those involved. \nDVCon Japan 2024 will be held at a venue that is only a 3-minute walk from the Takanawa Exit of Shinagawa Station. The morning sessions will consist of general sessions and panel discussions\, and the afternoon will be technical sessions including many paper presentations and tutorials. DVCon is a forum for sharing and discussing the latest information in a wide variety of areas including functional verification strategies\, SystemVerilog\, UVM\, UPF\, SystemC\, PSS\, formal verification methodologies\, HLS\, AMS\, IP-XACT\, and more\, and discussion in a wide variety of fields. It is also a great opportunity to meet and mingle with other attendees\, presenters and attendees\, sponsors\, and Accellera representatives. I \nWe encourage designers\, engineers\, and managers to attend. We look forward to seeing you there. Finally\, I would like to take this opportunity to thank our Gold and Silver Sponsors and Supporters for their support of the event\, as well as the Information Processing Society of Japan and IEEE CEDA AJJC for their sponsorship. \nDVCon Japan 2023 General Chair : Genichi Tanaka
URL:https://marketingeda.com/event/dvcon-japan-2024/
LOCATION:TKP Garde CIty Premium – Shinagawa Takanawa\, Tokyo\, TKP Garden City Premium\, Tokyo\, Japan
CATEGORIES:Conference,EDA
ATTACH;FMTTYPE=image/jpeg:https://marketingeda.com/wp-content/uploads/DVCon-Japan-2024.jpg
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BEGIN:VEVENT
DTSTART;TZID=America/Los_Angeles:20240829T080000
DTEND;TZID=America/Los_Angeles:20240829T170000
DTSTAMP:20240729T162620Z
CREATED:20240729T162620Z
LAST-MODIFIED:20240729T162620Z
UID:8188-1724918400-1724950800@marketingeda.com
SUMMARY:GlobalFoundries Technology Summit 2024 - North America
DESCRIPTION:The annual GTS conference brings GF executives and technologists together with customers and partners to discuss the latest breakthroughs and innovations in the semiconductor industry.
URL:https://marketingeda.com/event/globalfoundries-technology-summit-2024-north-america/
LOCATION:Santa Clara Convention Center\, 5001 Great America Parkway\, Santa Clara\, CA\, 95054\, United States
CATEGORIES:Foundry,IP
ATTACH;FMTTYPE=image/jpeg:https://marketingeda.com/wp-content/uploads/GlobalFoundries-2024.jpg
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BEGIN:VEVENT
DTSTART;TZID=America/Los_Angeles:20240828T080000
DTEND;TZID=America/Los_Angeles:20240828T090000
DTSTAMP:20240809T162606Z
CREATED:20240809T162606Z
LAST-MODIFIED:20240809T162606Z
UID:8225-1724832000-1724835600@marketingeda.com
SUMMARY:Design\, Integrate\, Analyze and Manage with Allegro X
DESCRIPTION:Designing PCBs in today’s world means using multiple tools to get the job done. The Allegro X Design Platform allows you to access all these tools in one unified design environment. \nJoin us to discuss how you can reduce your cycle time\, ensure product reliability and get first-time-right designs with Allegro X. \n\nTopics we’ll cover during the webinar: \n\nHierarchical and multi-board design\nReliability analysis covering electrical overstress (EOS) and mean time between failure (MTBF)\nFloor planning and in-design analysis with integrated Cadence Celsius Solver\nConstraint-driven design to ensure functionality and manufacturability\nAnd how to utilize DesignTrue DFM to reduce costly manufacturing failures\n\n\nSpeakers: \nSaankhya Parekh\, Lead Product Engineer\, Cadence \nPablo Barraza\, Lead Application Engineer\, Cadence \nHost: \nSupreeth Mannava\, Sr. Principal Product Manager\, Cadence
URL:https://marketingeda.com/event/design-integrate-analyze-and-manage-with-allegro-x/
CATEGORIES:EDA,Webinar
ATTACH;FMTTYPE=image/jpeg:https://marketingeda.com/wp-content/uploads/Cadence-August-28-2024.jpg
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BEGIN:VEVENT
DTSTART;TZID=America/Los_Angeles:20240827T090000
DTEND;TZID=America/Los_Angeles:20240827T180000
DTSTAMP:20240814T180313Z
CREATED:20240814T175832Z
LAST-MODIFIED:20240814T180313Z
UID:8240-1724749200-1724781600@marketingeda.com
SUMMARY:Siemens EDA Custom IC Verification Forum - Austin\, TX
DESCRIPTION:Join us and learn how Siemens’ intelligent Custom IC Verification platform is transforming the custom IC verification landscape with AI-powered methods and the latest in circuit simulation technology! Our expert speakers will provide insight on IC verification topics such as circuit simulation\, mixed signal verification\, nominal to high-sigma variation analysis\, library characterization\, and IP QA. With customer testimonials presented in each session\, this event offers a great opportunity to learn how others within the electronic design community are using our solutions to solve their most complex real-world challenges. \n9:00 am – 9:30 am\nRegistration & Continental Breakfast \n9:30 am – 10:00 am\nIndustry Keynote \n10:00 am – 10:45 am\nIntroducing AI-accelerated Solido Simulation Suite for intelligent IC design and verification \n10:45 am – 11:30 am\nAccelerating SPICE accurate verification with Solido SPICE and Solido LibSPICE for analog\, mixed-signal\, RF\, 3D-IC and library IP applications \n11:30 am – 12:00 pm\nAccelerating memory and analog functional verification with Solido FastSPICE \n12:00 pm – 1:00 pm\nLunch \n12:30 pm – 1:00 pm\nKeynote – AI in EDA \n1:00 pm – 1:30 pm\nIndustry’s fastest mixed-signal simulation with Symphony for complex IC designs \n1:30 pm – 2:15 pm\nUtilizing AI-powered Solido Design Environment to accelerate production-accurate SPICE verification from nominal to high-sigma \n2:15 pm – 2:30 pm\nAfternoon Break \n2:30 pm – 3:15 pm\nAccelerating characterization and STA workflows with AI-powered Solido Characterization Suite \n3:15 pm – 4:00 pm\nTrust but verify your IP: Comprehensive IP QA with Solido IP Validation Suite \n4:00 pm – 6:00 pm\nReception and Golf Event
URL:https://marketingeda.com/event/siemens-eda-custom-ic-verification-forum-austin-tx/
LOCATION:Topgolf Austin\, 2700 Esperanza Crossing\, Austin\, TX\, 78758\, United States
CATEGORIES:EDA
ATTACH;FMTTYPE=image/jpeg:https://marketingeda.com/wp-content/uploads/topgolf.jpg
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