Calendar of Events
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1 event,
International Test Conference
We are back live and what a grand place to have our first live event in three years; Disneyland! We have a fantastic program that addresses new test technology challenges that significantly affect today’s electronic products! ITC is the world’s premier conference dedicated to electronics test. This year’s ITC continues with its mission to play… Read More »International Test Conference
2 events,
Synopsys 28th Annual Test & SLM Special Interest Group (SIG) Event
Synopsys 28th Annual Test & SLM Special Interest Group (SIG) Event
As a member of the design and test community, you are invited to attend Synopsys 28th Annual Test & SLM Special Interest Group (SIG) at the 2022 International Test Conference (ITC). This year’s event will be hosted by Dr. Ken Butler, Senior Director of Business Development from Advantest. Dr. Butler will be joined by experts… Read More »Synopsys 28th Annual Test & SLM Special Interest Group (SIG) Event
2 events,
U.S. Executive Forum
U.S. Executive Forum
The 2022 GSA U.S. Executive Forum is coming up on September 27 in Menlo Park, California. USEF 2022 is one of the most anticipated GSA events of the year and attendance is filling up quickly. Make sure to secure your spot before it's too late. In this unique and exclusive gathering, thought leaders, visionaries and innovators… Read More »U.S. Executive Forum
2 events,
Global Foundries Technology Summit – EMEA
DAY 1 Wednesday, September 28, 2022 Doors Open 3:00pm CET DINNER Restaurant KULTURWIRTSCHAFT, 7pm - 10pm DAY 2 Thursday, September 29, 2022 Doors Open 8:30am CET EVENT LOCATION GlobalFoundries FAB 1 Wilschdorfer Landstrasse 101 01109 Dresden, Germany We are thrilled to welcome you to GF Technology Summit 2022. This exclusive, invitation-only event… Read More »Global Foundries Technology Summit – EMEA
4 events,
Silicon Realization TechSummit
Silicon Realization TechSummit
This year's event brings together Synopsys' Digital Design Technical Symposium and Verification Day into a single event - Synopsys Silicon Realization TechSummit. This one-day, in-person event is designed to inform executives, managers, and design and verification engineers about how the EDA industry is evolving. What Attendees Can Expect A keynote and presentations from leaders in… Read More »Silicon Realization TechSummit
Architecture Exploration of Automotive Networks, Radars, and Semiconductors
Architecture Exploration of Automotive Networks, Radars, and Semiconductors
The buzzwords of 2022 are autonomous driving, radars, and semiconductor and they are all similar in more than one-way. All have protocols, schedulers, sensors, high performance computing, software, networks, interfaces, antennas, and attenuators. VisualSim Architect is used to architect and verify all these applications. Join us for this Webinar on Commonality in the Architecture Exploration… Read More »Architecture Exploration of Automotive Networks, Radars, and Semiconductors
1 event,
Samsung Foundry Forum & SAFE Forum 2022 – US
Through the various session programs, clients, partners, and experts in each field will be able to meet again in person and prepare to go forth into the new future of the semiconductor market. The 2022 Samsung Foundry Forum and SAFE Forum are in-person events, and will be held in San Jose in the U.S.,Munich… Read More »Samsung Foundry Forum & SAFE Forum 2022 – US
3 events,
PCB West 2022
For more than 30 years PCB West has trained designers, engineers, fabricators and, lately, assemblers on making printed circuit boards for every product or use imaginable. More than 2,500 designers, fabricators, assemblers and engineers register and more than 100 companies exhibit each year at the four-day technical conference and one-day sold-out exhibition. From high-reliability military/aerospace… Read More »PCB West 2022
Post-layout Circuit Sizing Optimization
Post-layout Circuit Sizing Optimization
My IC design career started out with manually sizing transistors to improve performance, while minimizing layout area and power consumption. Fortunately we don’t have to do manual transistor sizing anymore, thanks to EDA tools that are quicker and more accurate than manual methods. MunEDA is an EDA vendor that has developed a tool suite for IC design… Read More »Post-layout Circuit Sizing Optimization
2 events,
2022 IEEE Electronic Design Process Symposium (EDPS)
We are planning to hold 2022 IEEE EDPS live! Looking forward to meeting with you face-to-face. About this event 2022 IEEE EDPS will be held on Oct 6 and Oct 7 2022 in Milpitas, CA. We have invited industry practitioners and leaders from academia to present their work in following areas: Innovative Designs and Design… Read More »2022 IEEE Electronic Design Process Symposium (EDPS)
2 events,
IESA Vision Summit 2022
The 17th edition of IESA flagship event, IESA Vision Summit 2022 is scheduled on 12th and 13th October 2022 in Bengaluru. This is our flagship event where most of the Semiconductor and ESDM companies from India and the world come under one roof. The objective of the event is to enable DESIGN IN INDIA and… Read More »IESA Vision Summit 2022
Everything You Need to Know About Virtual ECU Abstraction Levels
Everything You Need to Know About Virtual ECU Abstraction Levels
Growing electronic/electrical (E/E) architecture complexity and software content in modern vehicles has propelled the use of virtualization-based testing to develop and validate functions and software components more effectively. The simulation of electronic control units (ECUs) as virtual ECUs (vECUs) has found rapid adoption in several phases of automotive development. This 30-minute Webinar will provide a… Read More »Everything You Need to Know About Virtual ECU Abstraction Levels
2 events,
Assertions-Based Verification for VHDL Designs
Assertions-Based Verification for VHDL Designs
Assertion-based verification (ABV) enables the use of assertions for the efficient verification of low-level design properties. These assertions could be verified by simulation and formal verification methods. The VHDL 2008 standard includes Property Specification language (PSL) to express design properties for both simulation and static formal analysis. For mixed-mode simulations of VHDL designs with SystemVerilog… Read More »Assertions-Based Verification for VHDL Designs
1 event,
SNUG Europe
Since 1991, the Synopsys Users Group (SNUG) has represented a global design community focused on innovating from Silicon to Software. Today, as the electronics industry’s largest user conference, SNUG brings together over 12,000 Synopsys tool and technology users around the world. In addition to peer-reviewed technical presentations and insightful keynotes from industry leaders, SNUG provides… Read More »SNUG Europe
4 events,
Cadence Further Streamlines MMIC, RFIC, and RF SiP Design Workflows
Cadence Further Streamlines MMIC, RFIC, and RF SiP Design Workflows
Demand for next-generation wireless communication, aerospace, and transportation systems is driving the need for high-performance, cost-sensitive silicon RFICs and III-V compound semiconductor monolithic microwave integrated circuits (MMICs), often integrated into advanced system-in-package (SiP) modules. Join us as we demonstrate how the key new features of the Cadence® AWR Design Environment platform: Accelerates design entry and platform design sharing to… Read More »Cadence Further Streamlines MMIC, RFIC, and RF SiP Design Workflows
RISC-V Con
RISC-V Con
In order to foster stronger collaboration on RISC-V across the computing industry, RISC-V CON focuses on this disruptive technology, demonstrating its benefits and identifying commercial strategies. Through RISC-V CON, the RISC-V community and ecosystem can share the most up-to-date development and RISC-V based products and solutions. Seventeen years in business and a Founding Premier member… Read More »RISC-V Con
Improving Efficiency and Quality of Verification Environments with Automation
Improving Efficiency and Quality of Verification Environments with Automation
Bugs can be introduced at any stage in the hardware design development process and escape into tapeout if the verification environment is unqualified. Measuring and improving verification effectiveness to prevent bugs during functional verification is the key to taping out bug-free high-quality designs. Verification environments are often more complex than the designs they help verify.… Read More »Improving Efficiency and Quality of Verification Environments with Automation
2 events,
Jasper User Group 2022
Ready to share and discuss the latest design and verification best practices with your peers from around the world? It’s time for our annual Jasper™ User Group Conference held on October 19 and 20 at the Cadence San Jose campus. This interactive, in-depth technical conference connects designers, verification engineers, and engineering managers from around the… Read More »Jasper User Group 2022
Synopsys Photonic Symposium
Synopsys Photonic Symposium
Photonics and photonic IC technologies are crucial to support rapidly evolving internet, healthcare, mobility, and security needs. Driven by data communications, photonic ICs are moving rapidly from the laboratory to mainstream and fueling a wave of innovations and product introductions. Join our virtual Photonic Symposium to hear about the latest developments, application requirements, best practices,… Read More »Synopsys Photonic Symposium
3 events,
Best Practices to Achieve the Highest Performance using Xcelium Logic Simulator
Best Practices to Achieve the Highest Performance using Xcelium Logic Simulator
Simulator performance is critical owing to the exponentially increasing complexity of SoC designs and shrinking market time. Cadence® Xcelium™ is a leader in simulation performance, and we focus relentlessly on improving the core performance of the simulator. We keep developing new performance optimizations that are delivered with each new release of Xcelium. It is easy to achieve… Read More »Best Practices to Achieve the Highest Performance using Xcelium Logic Simulator
Optimizing Simulations for Efficient Coverage Collection
Optimizing Simulations for Efficient Coverage Collection
Coverage is an essential part of any verification environment. Coverage can be simple as a statement and branch coverage, or it can be more complex as a covergroup with constrained-random tests. Implementation, collection and analysis of coverage on your designs might look challenging but with a few steps you can optimize your design flow to… Read More »Optimizing Simulations for Efficient Coverage Collection
1 event,
The Dawn of AI Revolution in Chip Design
The Dawn of AI Revolution in Chip Design
Abstract: We are at the dawn of an AI revolution for every human activity including chip design. The AI revolution in chip design is absolutely necessary because of key macro trends influencing chip design and would further accelerate the AI revolution in all other fields. In this talk I will start with my personal journey… Read More »The Dawn of AI Revolution in Chip Design
1 event,
The Applied Superconductivity Conference
The Applied Superconductivity Conference is the premier international conference on applied superconductivity and quantum computing. Engineers, scientists and industry representatives interested in developments related to the electronics and materials for superconductors that are involved in any type of quantum system should attend. ASC'22 Conference Chair's Statement Aloha to ASC 2022 in Hawaii! On behalf of… Read More »The Applied Superconductivity Conference
4 events,
Arm DevSummit
After two years of virtual networking, we’re thrilled to announce the return of Arm DevSummit in-person in October. As you’re a past attendee, we’re delighted to welcome you to this milestone event. Arm DevSummit is for people developing and deploying on Arm-based hardware. We want to give you, the future builders, the insight and edge… Read More »Arm DevSummit
TSMC 2022 OIP – California
TSMC 2022 OIP – California
Join the TSMC 2022 Open Innovation Platform Ecosystem Forum and learn from OIP partners how to leverage their technology for your design challenges! Register Now Learn About: Emerging advanced node design challenges and corresponding design flows and methodologies for N3/N3E, N4/N4P, N5/N5A, N6/N7, N12e, N22, and 28eF technologies Latest 3DIC chip stacking and advanced packaging… Read More »TSMC 2022 OIP – California
Protium Enterprise Prototyping: Higher Productivity, Lower Costs
Protium Enterprise Prototyping: Higher Productivity, Lower Costs
Prototyping has become essential for chip and IP developers as they deal with exponentially greater testing requirements that come with growing design size, software content, and input data and workloads to run. The increasing complexity in prototyping has naturally increased costs, both in hardware, tools, and engineering talent. For many projects, build-your-own prototypes are no… Read More »Protium Enterprise Prototyping: Higher Productivity, Lower Costs
5 events,
Synopsys Technology Symposium 2022 – UK
Synopsys Technology Symposium 2022 – UK
Synopsys Northern Europe is hosting a Technical Symposium providing updates on all aspects of doing state of the art designs at emerging and established nodes. This event provides an opportunity for users to stay connected with the latest products and innovations as well as getting tips & tricks and best practices that our experts will… Read More »Synopsys Technology Symposium 2022 – UK
Silvaco – SURGE, North America
Silvaco – SURGE, North America
Silvaco is pleased to invite you to join its annual Silvaco UseRs Global Event (SURGE), taking place virtually on October 27, 2022. SURGE brings the TCAD, EDA, and IP communities together to discuss new technologies, share users’ experiences, and discover innovative techniques for advanced semiconductor design. Everyone that registers will be entered to win one… Read More »Silvaco – SURGE, North America
Evaluating UCIe based multi-die architectures to meet timing and power constraints
Evaluating UCIe based multi-die architectures to meet timing and power constraints
Multi-die architectures have evolved from proprietary to industry standard UCIe. UCIe can accommodate the bulk of designs today from 8 Gbps per pin to 32 Gbps per pin for high-bandwidth applications from networking to Hyperscale data centers. To help your UCIe adoption journey, we present VisualSim Architect and the associated UCIe/PCIe6.0 IPs to explore and… Read More »Evaluating UCIe based multi-die architectures to meet timing and power constraints
2 events,
ISTFA 2022
The demand for higher performance and lower power-consumption microelectronic devices has driven semiconductor technology to shrink continuously according to Moore’s Law. Furthermore, for latest technologies in nano realm, a new set of disruptive development in new structures and novel materials was introduced. Thus, defects causing semiconductor device failures have become smaller and more elusive. To… Read More »ISTFA 2022
ICCAD 2022
Jointly sponsored by ACM and IEEE, ICCAD is the premier forum to explore the new challenges, present leading-edge innovative solutions, and identify emerging technologies in the electronic design automation research areas. ICCAD covers the full range of CAD topics – from device and circuit-level up through system-level, as well as post-CMOS design. ICCAD has a long-standing tradition of producing a… Read More »ICCAD 2022
3 events,
CEDA Virtual Distinguished Lecturer Series: Anupam Chattopadhyay
CEDA Virtual Distinguished Lecturer Series: Anupam Chattopadhyay
The continued scaling of horizontal and vertical physical features of silicon-based complementary metal-oxide-semiconductor (CMOS) transistors, termed as “More Moore”, has a limited runway and would eventually be replaced with “Beyond CMOS” technologies. There has been a tremendous effort to follow Moore’s law but it is currently approaching atomistic and quantum mechanical physics boundaries. This has… Read More »CEDA Virtual Distinguished Lecturer Series: Anupam Chattopadhyay
3 events,
Linley Fall Processor Conference 2022
TechInsights is pleased to announce that the Linley Fall Processor Conference powered by TechInsights - a Hybrid Event, will be held in Santa Clara, California on November 1-2, 2022. If you cannot attend in person, tune in to our virtual livestream or watch the presentations OnDemand at your convenience. Presentations will address processors and IP… Read More »Linley Fall Processor Conference 2022
5 events,
Analog Design on the Cloud
Analog Design on the Cloud
Customers love the Synopsys Analog Design Solution and have been adopting it at a record pace. Now it's available on the cloud. Synopsys Cloud Analog Instance includes everything you need to get started quickly: software, hardware setup, training, and scripts to help setup and manage your design. Designers not only have access to a full… Read More »Analog Design on the Cloud
How CXL Technology will Revolutionize the Data Center
How CXL Technology will Revolutionize the Data Center
Data Centers face many challenges in an environment of exponentially rising data volume growth. With workload demands increasing rapidly, the need for more bandwidth and capacity continues to rise. Join us for a live webinar next week on November 2nd and hear IDC guest speaker, Jeff Janukowicz, and Rambus' Mark Orthodoxou discuss how CXL technology… Read More »How CXL Technology will Revolutionize the Data Center
5 events,
THE FUTURE OF MORE THAN MOORE—Chiplets, Advanced Packaging, and More
THE FUTURE OF MORE THAN MOORE—Chiplets, Advanced Packaging, and More
Presented by the SEMI Pacific Northwest and Silicon Valley Chapters How can we extend Moore's Law and drive new capabilities in the More than Moore era? The answer lies in the technology, economics, and new opportunities in the semiconductor supply chain. Join us at the Forum on Thursday, November 3, 2022, 8–11:30am Pacific Time to… Read More »THE FUTURE OF MORE THAN MOORE—Chiplets, Advanced Packaging, and More
Workshop on Open-Source EDA Technology
Workshop on Open-Source EDA Technology
Virtually co-sponsored by ICCAD 2022 on November 3, 2022! The WOSET workshop aims to galvanize the open-source EDA movement. The workshop will bring together EDA researchers who are committed to open-source principles to share their experiences and coordinate efforts towards developing a reliable, fully open-source EDA flow. The workshop will feature presentations and posters that… Read More »Workshop on Open-Source EDA Technology
How Designing a Custom ASIC Chip Will Help Scientists Detect Neutrinos From Outer Space
How Designing a Custom ASIC Chip Will Help Scientists Detect Neutrinos From Outer Space
Join us on Thursday, November 3rd to learn how Lawrence Berkeley National Laboratory, Fermilab, and Brookhaven National Laboratory collaborated and designed a custom ASIC chip to run at extremely cold temperatures, so that it can detect neutrinos! Register Today! Here’s what you can learn: Why study neutrinos and how to detect them DUNE experiment –… Read More »How Designing a Custom ASIC Chip Will Help Scientists Detect Neutrinos From Outer Space