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DTSTART;TZID=Asia/Kolkata:20241120T090000
DTEND;TZID=Asia/Kolkata:20241120T170000
DTSTAMP:20241114T182631Z
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UID:8514-1732093200-1732122000@marketingeda.com
SUMMARY:Ansys IDEAS User Conference India 2024
DESCRIPTION:Join us for the Ansys IDEAS India User Conference 2024 — a place to catch up on industry best practices and the latest Semiconductor design advances. IDEAS will explore future trends with keynotes from industry leaders and offer technical insights from expert chip designers from many of the world’s top semiconductor companies. \nOverview\nAt this premier conference\, you will: \n\nDiscover Key Insights: Learn from industry experts and simulation specialists about cutting-edge techniques and strategies in on-chip power integrity and reliability\nExplore Multi-Scale Multiphysics Challenges: Dive into complex topics\, including multi-scale\, multiphysics simulations essential for 3DICs and heterogeneous integration\nAccelerate Innovation: Gain valuable knowledge on how advanced simulation technologies like Sigma-DVD can streamline design processes and drive innovation\nNetwork with Experts: Connect with peers and Ansys experts\, sharing experiences and exploring new opportunities for collaboration\n\nIDEAS India is your opportunity to deepen your understanding of power-noise-reliability sign-off for Chip-Package systems\, enhance your skills\, and advance your engineering capabilities. Don’t miss this chance to be part of the conversation shaping the future of technology. \nKey Discussion Topics\n\nSoC Power-Integrity and Reliability Sign-off\nAdvanced Power Integrity Flows: Sigma-DVD\, ROM\, IR-ECO\, etc\n3DIC / Interposer – Power\, Signal\, Thermal Integrity\nAnalog & Mixed-Signal Designs Power and Reliability\nRTL Power Analysis and Optimization\nReliability Analysis: Electromigration\, ESD\, and Thermal\nShift-left /In-design Analysis and Optimization\nChip-Package-System Co-Simulation\n\n\n\n\nAgenda\n\n\n\nTime\nSession\nSpeakers\n\n\n9:00 am – 10:00 am\nRegistration + Hi-Tea\n\n\n10:00 am – 10:15 am\nWelcome & Inauguration\nJai Pollayil\nSenior Director & Global Semiconductor AE Head\nAnsys\n\n\n10:15 am – 10:45 am\nIndustry Keynote\nBalajee Sowrirajan\nCorporate EVP & MD\nSamsung Semiconductor India Research\n\n\n10:45 am – 11:15 am\nAnsys Keynote\nJohn Lee\nGeneral Manager and Vice President\nAnsys\n\n\n11:15 am – 11:30 am\nTea/Coffee Break\n\n\n\nTrack 1: Advanced SOC Power Integrity & Reliability\n(Convention Hall)\nTrack 2: Power-Signal-Thermal-ESD Integrity across RTL / Custom IP / IC / 3DIC\n(Tactic 5)\n\n\n\nSession\nSpeakers\nSession\nSpeakers\n\n\n11:30 am – 12:00 pm\nConquering IR ECO complexity with PrimeClosure\nSynopsys\nRaghavendra Swami Sadhu\nBackside power delivery and advanced technology EM/IR analysis in Totem\nIntel\nAnil Dsouza\n\n\n12:00 pm – 12:30 pm\nMaximizing IR signoff coverage using Sigma-AV and its benefit on PPA\nGoogle\n Sandeep Gajbhare\nComprehensive Electrical & Thermal integrity of Power Management IC using a new Integrated solution\nTexas Instruments\nGirish Bijjal\n\n\n12:30 pm – 1:00 pm\nAccelerating Full Flat EMIR Sign-off of Multi-billion Instance Design using RedHawk-SC ROM (Reduced Order Model)\nSamsung Semiconductor India Research\nRaja Ramachandra Rao & Satyaki Mandal\nOptimizing Standard cell library development flow using “ParagonX” – EDA tool for IC layout parasitics analysis\nNXP Semiconductors\nRavi JN & Santhosh Kamatam\n\n\n1:00 om – 2:00 pm\nLunch Break\n\n\n2:00 pm – 2:30 pm\nAn efficient methodology for Multi-PVT EMIR analysis of Large SOCs\nNVIDIA\nRamesh Aggarwal\nSignal and Power Integrity analysis of Silicon Interposer for multi-chiplet integration\nAlphawave Semi\nGangaraju M & Yadavalli Jagadeeswari\n\n\n2:30 pm – 3:00 pm\nAccounting for IR Drop in Static Timing Analysis: A Path to Accurate Delay Estimation\nIntel\nPurushotham Reddy N & Manoj Varama S\nComprehensive Thermal Analysis of 3DIC design using Redhawk_SC-ElectroThermal (RHSC-ET\nSamsung\nRishikanth Mekala & Abhishek Chinchani\n\n\n3:00 pm – 3:30 pm\nNovel method of Vectorless IR Analysis for DFT\nMediaTek\nArun CS\nAccelerated ESD Sign-off with Pathfinder-SC: An Efficient and Scalable Approach\nGoogle\nSmaritha Kasukurthi\n\n\n3:30 pm – 4:00 pm\nOptimizing Power Integrity with RHSC in Smart PDN Framework Qualcomm\nGaurav Jain & Rajender Nune\nAn Integrated Approach to Power Analysis & Optimization: Synergizing Emulation\, RTL Design\, and Physical Design\nAMD\nNeeraj Dwivedi\n\n\n4:00 pm – 4:30 pm\nRobust techniques for IR prediction\nAMD\nSayani Das\nA Novel approach to cost-Efficient Hybrid Cloud Solutions with SeaScape’s DataLake and Micro-Resiliency\nARM\nChandrakumar A\n\n\n4:30 pm – 4:35 pm\nConcluding Remarks\n\nConcluding Remarks\n\n\n\n4:35 pm – 5:00 pm\nTea & Networking\n\n\n\nShare this:\n				Share on LinkedIn (Opens in new window)\n				LinkedIn\n			\n				Share on X (Opens in new window)\n				X\n			\n				Share on Facebook (Opens in new window)\n				Facebook\n			Like this:Like Loading…
URL:https://marketingeda.com/event/ansys-ideas-user-conference-india-2024/
CATEGORIES:Conference,EDA
ATTACH;FMTTYPE=image/jpeg:https://marketingeda.com/wp-content/uploads/Ansys-November-20-2024.jpeg
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DTSTART;TZID=America/Los_Angeles:20241120T090000
DTEND;TZID=America/Los_Angeles:20241120T180000
DTSTAMP:20241113T213239Z
CREATED:20241113T213125Z
LAST-MODIFIED:20241113T213239Z
UID:8510-1732093200-1732125600@marketingeda.com
SUMMARY:Tower Semiconductor - Technical Global Symposium 2024
DESCRIPTION:TGS offers a wonderful opportunity for networking\, learning\, and sharing\nthe latest technology developments with our community\, as well as\nmeeting with Tower’s executives and team of experts.\nWe invite you to join us! \n\n\nTime\n\n\n\n\nSession\n\n\n\n\nSpeaker\n\n\n\n\n9:00 – 10:00\n\n\n\n\nRegistration\n\n\n\n\n10:00 – 10:05\n\n\n\n\nOpening\n\n\n\n\nMr. Lei Qin\, SVP of Worldwide Sales\n\n\n\n\n10:05 – 10:40\n\n\n\n\nCEO Keynote\n\n\n\n\nMr. Russell Ellwanger\, CEO\n\n\n\n\n10:40 – 11:00\n\n\n\n\nWhy an Analog Foundry is Critical for AI\n\n\n\n\nDr. Avi Strum\, CTO\n\n\n\n\n11:00 – 11:30\n\n\n\n\nInvited Talk by Nvidia:\nIntegrated Optics Ecosystem for Future Gen AI Systems\n\n\n\n\nDr. Ashkan Seyedi\, Director\, LinkX Products\, Nvidia\n\n\n\n\n11:30 – 12:00\n\n\n\n\nMarket Megatrends and Tower’s Technology Solutions in RF Mobile\, Infrastructure\, Power\, and Sensors\n\n\n\n\nDr. Marco Racanelli\, President\n\n\n\n\n12:00 – 13:30\n\n\n\n\nLunch\n\n\n\n\n13:30 – 14:15\n\n\n\n\nTower’s RF and Silicon Photonics Technology Platforms – Advanced Solutions for High-speed Connectivity\n\n\n\n\nDr. Ed Preisler\, VP & Co-General Manager of RF Business Unit\n\n\n\n\n14:15 – 15:00\n\n\n\n\nTower’s Power 65nm BCD and 0.18um BCD Offering for Power Applications\n\n\n\n\nDr. David Mistele\, Director of Power Management R&D\n\n\n\n\n15:00 – 15:15\n\n\n\n\nCoffee Break\n\n\n\n\n15:15 – 15:45\n\n\n\n\nTechnologies for the Future of Digital Imaging\, from Sensors to Displays\n\n\n\n\nDr. Benoit Dupont\, Marketing Director of Sensors and Display Business\n\n\n\n\n15:45 -16:15\n\n\n\n\nTower’s Design Enablement – Transforming Ideas into Products\, Rapidly and Accurately\n\n\n\n\nDr. Samir Chaudhry\, VP of Design Enablement\n\n\n\n\n16:15 – 16:45\n\n\n\n\nAerospace and Defense – Partner for R&D and Manufacturing Solutions\n\n\n\n\nDr. David Howard\, Executive Director & Fellow\n\n\n\n\n16:45 – 17:00\n\n\n\n\nClosing Remarks\n\n\n\n\n\n\n\n\n\n17:00 – 18:00\n\n\n\n\nCocktail\n\n\nShare this:\n				Share on LinkedIn (Opens in new window)\n				LinkedIn\n			\n				Share on X (Opens in new window)\n				X\n			\n				Share on Facebook (Opens in new window)\n				Facebook\n			Like this:Like Loading…
URL:https://marketingeda.com/event/tower-semiconductor-technical-global-symposium-2024/
LOCATION:Hyatt Regency Santa Clara\, 5101 Great America Parkway\, Santa Clara\, CA\, 95054\, United States
CATEGORIES:Foundry,Semiconductor,Symposium
ATTACH;FMTTYPE=image/jpeg:https://marketingeda.com/wp-content/uploads/Tower-November-20-2024.jpg
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