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Practical Flows for Continuous Integration: Making The Most of Your EDA Tools

Verifying changes to RTL and testbench code prior to releasing to the rest of your team is the best way to avoid committing bugs that cause massive, team-wide disruptions. This webinar takes you through example tool flows that, when used within a Continuous Integration (CI) system, can avoid or even eliminate those bugs and disruptions.… Read More »Practical Flows for Continuous Integration: Making The Most of Your EDA Tools

Protocol and Memory Interface Verification in the Shrinking World of 3DIC

Emerging 2.5D and 3DIC packaging technologies enable more design complexity, and bring some new verification challenges. We look at how to scale your verification capability to match and how to plan ahead for verification of die-to-die interconnect protocols such as UCIe and memory verification with HBM. Packaging technologies for 2.5D and 3DIC are becoming more… Read More »Protocol and Memory Interface Verification in the Shrinking World of 3DIC