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UID:8372-1727942400-1728061200@marketingeda.com
SUMMARY:Electronic Design Process Symposium (EDPS) - 2024
DESCRIPTION:EDPS 2024 is now taking shape. The place to be is once again SEMI\, in Milpitas\, and the dates are Thursday and Friday\, Oct 3rd and 4th\, 2024. \nRegistration is now open: https://2024-ieee-edps.eventbrite.com. Who needs to register? Please see the Registration page. \nTalks from EDPS 2023 and the last 24 years of EDPS\, are are available and searchable\, on the Prior Years page. \nDay 1\, Thursday 9:00am; Session 1\n9:05am\n\nEnergy and Thermal Management of Chips\, Systems and Datacenters Necessitates a Return to Fundamentals\nChandrakant Patel\nHP\n\n  \nThe latter part of 20th century witnessed the rise of the compute utility made up of large-scale data centers housing densely packed compute\, storage and networking equipment. The cyber age data centers became modern day factories requiring megawatts of power for the information technology (IT) equipment much like the process equipment in a factory of the machine age. Electrical energy supplied to the chips and systems in the data centers turned into multi-megawatts of heat energy which in turn required heat removal means. The active heat removal means also required power. While many innovative measures have been used for heat removal and energy management in data centers\, there is a substantial gap in application of fundamentals of engineering when compared to the approaches taken by the contributors of the 19th and early 20th century machine age. As an example\, machine age contributors performed exergy (2nd law of thermodynamics) analysis and deemed it necessary to build a hydro-electric plant as part of the design of an Aluminum factory. Indeed\, majority of data centers today rely on the power infrastructure built by our predecessors. Given the inexorable trajectory of data centers strongly driven by AI\, and associated demands on available energy\, it is time we returned to such fundamentals particularly given the environmental challenges. \nIn my talk\, I will present a holistic approach that traces the energy flow from a power plant to a chip\, and from the chip core to the cooling tower. \n10:00am\n\nEnabling Effortless Machine Learning for Embedded Edge Applications\nGopal Hegde\nSiMa.ai\n\n  \nMachine Learning is a game changing technology of our generation and similar Internet in the 1990s\, will impact every aspect of our life. While Machine Learning use cases and applications are well established in the cloud & IoT devices\, in the embedded edge market\, its usage is in its infancy. We at SiMa.ai are focused on disrupting this market by turbo charging embedded compute with the addition of machine learning. Embedded edge has space and power constraints and has a huge expertise gap relative to cloud computing when it comes to machine learning. The presentation covers market requirements\, key challenges and our unique software first approach to machine learning at embedded edge. We will discuss key market segments\, their unique requirements and how our silicon and software solutions provide a way for our customers to easily develop and deploy machine learning solutions that address their use cases and applications. \n10:35am\n\nAI: Trailblazing the Next Generation of Semiconductor Innovation\nVishal Khandewal\nSynopsys\n\n  \nWith AI-based applications coming pervasively mainstream through ChatGPT\, digital healthcare\, and almost everything else we do with our devices daily\, digital chip design is seeing an exponential push towards complexity\, performance\, power\, and time-to market. EDA tool flows are becoming mission critical to meet the demands of a hardware-led 4th industrial revolution that is driving everything towards being intelligent\, connected\, monitored and data-driven. In this talk we go into the details of how hardware design and EDA tools are evolving to deliver the next generation of performance\, power\, and productivity (PP&P) boost. Even with exponential growth in design productivity in the past decade\, overall design cycle is not meeting its intended targets. The technical complexity of advanced node design with new dominant effects like thermal and IR\, are leading to highly complex tool/methodology flows. This is where at Synopsys\, we have taken a full tool-stack approach to build pervasive AI into our tools to deliver unprecedented PP&P boost. We will share examples of applications ranging from design implementation\, verification\, test\, and analog/manufacturing to showcase the potential of this technology and how it is reshaping chip design workflows. Many of these technologies are taking us closer to the no-human-in-the-loop goal for chip design. With serious talent shortage and increase in solution complexity beyond human expertise\, AI-augmented solutions for chip design are the way forward. \n11:10am\n\nHarnessing LLMs for Advanced EDA Platforms: Code Generation and Beyond\nAkhilesh Kumar\nAnsys\n\n  \nLarge Language Models (LLMs) such as GPT-4\, Gemini\, Llama etc.\, have demonstrated astounding capabilities in a range of tasks such as knowledge extraction\, Q&A\, summarization\, code generation\, contextual problem solving etc. The LLMs can also be adapted to specific applications through a variety of methods such as fine tuning\, in-context learning\, RAG\, agent-based systems etc.\, making them quite versatile. \nModern EDA platforms\, such as Ansys SeaScape\, have sophisticated workflows\, hundreds of user APIs\, complex input data requirements\, and require deep domain knowledge and expertise for efficiently using the platform. This talk will discuss how LLMs can greatly improve the productivity and user experiences for such EDA platforms. The talk presents an overview of code generation techniques using LLMs and will discuss our experience in developing an LLM-based code generation solution for the Ansys SeaScape platform. Going beyond the code generation\, this presentation will discuss creating an LLM agent-based copilot for providing intuitive assistance to the users of the Ansys SeaScape platform for a variety of operational modalities. \n12:45pm\n\nThe Application of AI to Chip Design\nMark Ren\nNVidia\n\n  \nThe applications of AI in chip design undergo an evolutionary path. \nInspired by the success of AlphaGO\, Reinforcement Learning techniques were deployed to a number of design problems\, achieving results showing the potential of AI. \nThe advancement of Large Language Models further enabled the application of AI in a much broader set of design activities. \nLLM-based copilots can improve design productivity by providing knowledge and coding assistance; agents can provide further assistance in key design tasks such as analysis\, debugging\, and optimization. \nThe evolution of AI will continue\, and we will discuss critical challenges to realizing its revolutionary potential in the chip design process \n1:35pm\n\nHow AI is changing every aspect of EDA\, starting from transistor-level simulation\nSathishkumar Balasubramanian\nSiemens\n\n  \nThere is a lot of hype in the industry around AI\, but behind the hype there is the reality. That reality is that AI really is impacting virtually every aspect of semiconductor design. However\, its not as simple as taking general purpose AI solutions and hoping they work for EDA\, the risks are too high and when dealing with parts per billion (or trillion) in acceptable errors\, hallucinations are not acceptable. What is needed are Verifiable AI solutions that deliver results that users can trust and that reduce the overall resources needed to complete a task. At Siemens EDA we have been able to leverage Verifiable AI to accelerate virtually every aspect of the design and verification process. \nIn this presentation we will explore the requirements for\, and state of the art of\, AI in EDA application. We will explore AI’s impact on every aspect of design starting from transistor-level simulation. \n2:10pm\n\nTest\, Repair and Reliability Challenges of Chip-let Interconnects\nSreejit Chakravarty\nAmpere Computing\n\n  \nChip-let based design\, fueled by various advanced packaging technologies\, is projected to revolutionize the semiconductor industry. This brings along with it associated challenges to achieve adequate yield and aging related reliability issues. This talk will present manufacturing defect profiles associated with advanced packaging; the test and repair requirement\, during high volume manufacturing\, to achieve adequate yield; and challenges associated with latent defects leading to aging related field failures. RAS solutions required to address such reliability issues are highlighted. \n2:45pm\n\nArtificial Intelligence and Machine Learning for RF and Microwave Design\nJianjun Xu\nKeysight\n\n  \nThis talk reviews some powerful and practical Artificial Intelligence and Machine Learning (AI/ML) technologies for applications in traditional RF and Microwave design and beyond. After a very brief overview of the AI/ML landscape\, we focus on Artificial Neural Networks (ANNs) and provide several key examples of modern ANN applications to electronic\, electro-thermal\, and electro-chemical device modeling\, and behavioral modeling to illustrate the substantial benefits and generality of present techniques. \nThe talk concludes with a discussion of the potential of AI/ML technologies to address and solve future challenging and important RF and Microwave design problems\, e.g.\, for 6G. \n3:30pm\n\nPromises and Challenges of Digital Twin for Semiconductor Manufacturing\nAla Moradian\nApplied Materials\n\n  \nThe advancement of cutting-edge technologies like Artificial Intelligence (AI)\, Large Language Models (LLM)\, and Electric Vehicles (EV) demands sophisticated semiconductor devices with precise specifications. \nConcurrently\, the emergence of digital twins and AI stands as pivotal in facilitating the development and enablement of such technologies. \nThis talk delves into the vision and significance of AppliedTwin(tm)\, a proposed digital twin framework tailored for semiconductor manufacturing. \nAppliedTwin delineates various levels of abstractions ranging from digital fabrication facility down to digital twin of individual devices\, each characterized by distinct attributes governing their interaction with physical assets\, fidelity\, etc. \nApplied Materials has spearheaded the application of digital twins in semiconductor manufacturing with the introduction of EcoTwin(tm)\, a platform designed to promote sustainability. \nIn this talk the critical role of digital twins in propelling innovation and efficiency in semiconductor equipment manufacturing. \n4:05pm\n\nMaking Data Center Digital Twins a Reality\nPaul Harrison\nCadence\n\n  \nThis talk will discuss the application of Digital Twins to Data Centers. \nHistorically decisions for data center operations were made based on rules of thumb or the person who would most confidently put across their point of view. \nCabinet power densities continue to rise\, accelerated by AI\, increasing the need complex technologies like liquid cooling to be more widely implemented. This means data center operations have become more difficult to manage\, while the impact of their downtime can be catastrophic for companies. Fortunately\, data center operators are starting to adopt CFD-based Digital Twins to help inform their operational decisions\, improve their understanding\, and reduce the risks. This talk will explain how to create a Data Center Digital Twin\, some of the challenges with creating them\, how they integrate with data sources and existing processes\, and the benefits to operators this technology brings. \n4:40pm\n\nInnovating Semiconductor Manufacturing with ML-augmented Digital Twins\nNorman Chang\nElectronics\, Semiconductor\, and Optics BU\, Ansys\n\n  \nDeveloping each processing step in semiconductor manufacturing has heavily relied on in-situ sensors in the equipment and numerous try-outs in recipe generation. However\, with advancements in multiphysics simulation technologies\, an innovative ML-augmented hybrid simulation methodology has been developed. This methodology combines the strengths of multiphysics simulation and in-situ measurement in building semiconductor processing digital twins. In this talk\, we will review the current state-of-the-art digital twin technologies and identify the gaps that need to be addressed to fully utilize digital twins in developing new process recipes in semiconductor manufacturing. \n6:45pm\n\nSemiconductors and Artificial Intelligence:The Virtuous Cycle\nPushkar Apte\nSEMI\n\n  \nArtificial Intelligence (AI) has taken the world by storm\, and has become a strategic imperative for most industries. While the concept of AI is over half a century old\, it has accelerated rapidly just over the past decade\, in large part due to amazing advances in semiconductor chips. In turn\, AI is driving growth in semiconductor revenues and improvements in operational efficiency\, creating a virtuous cycle. \nHowever\, there are formidable roadblocks ahead. AI models and datasets are growing at an exponential rate\, far outpacing hardware advances – creating both performance and sustainability challenges. System-level innovation is required for continued progress in AI\, which requires meaningful collaboration and data-sharing – often difficult in an industry where IP is critical. \nThis presentation will focus on this virtuous cycle between semiconductors and AI\, highlighting the benefits\, challenges and solution paths for continued progress. \nDay 2\, Friday 9:00am; Session 1\n9:05am\n\nIs AI intelligent?\nRonjon Nag\nStanford Medicine\n\n  \nArtificial intelligence is in the news daily\, and people ask whether they are truly intelligent. \nMaybe it still lacks the depth of human intelligence today\, but where is already cleverer\, and what stops it from reaching the ultimate pinnacle of ”general intelligence” – could that ever be possible? We will consider the implications of creating truly intelligent machines and the potential consequences for human society. \n10:00am\n\nTrust Based Modeling for Improved Security\nNaresh Sehgal\nDeeply Human AI\n\n  \nThe present state of Edge Computing is an environment of different computing capabilities connected via various communication paths. Actors on the Edge may interact with each other and a central datacenter. An important part of information security is the evaluation of trust between actors\, whether those actors are people or machines. Although many distributed trust models exist\, our proposed model introduces three key concepts. The first concept is that trust is not bidirectional between two parties. The second concept is that trust is different between different actors\, based upon the nature of their relationships. The third concept is that trust depends on the content of a transaction. We will present some real-life examples to illustrate these concepts. \n10:35am\n\nAdvancing Hardware Security in the Post-Quantum Cryptography Landscape: Challenges and Solutions\nQian Wang\nU. Cal. Merced\n\n  \nHardware security in the era of post-quantum cryptography has become increasingly crucial due to the potential threat quantum computers pose to traditional cryptographic algorithms. Post-quantum cryptography aims to develop cryptographic algorithms that are resistant to attacks from quantum computers. However\, ensuring the security of these algorithms requires not only advancements in software but also robust hardware security measures. In this talk\, we will first discuss the implementation of quantum-resistant cryptographic modules on hardware platforms\, necessitating upgrades in both hardware and firmware to accommodate new algorithms efficiently. Moreover\, hardware implementations of cryptographic algorithms are vulnerable to side-channel attacks\, where an attacker exploits information leaked through physical characteristics such as power consumption or electromagnetic radiation. Post-quantum cryptographic hardware must incorporate countermeasures to mitigate these risks. \n11:20am\n\nScaling to Meet the Needs of AI\nPradeep Dubey\nIntel\n\n  \nArtificial intelligence (AI) is impacting not just what computing can do for us\, rather how computing gets done. Fast-evolving AI algorithms are driving demand for growing performance at an unprecedented rate and scale. This talk is about some of our research aimed at exploring technological and system-level opportunities for cost-effective scaling of emerging AI datacenters. \n1:00pm\n\nThe Future of Generative AI: Key Technology Trends and Innovations\nShiva Kintali\nR3AI\n\n  \nLLMs have emerged as powerful tools\, revolutionizing various domains from natural language processing to content generation\, but beneath their remarkable capabilities lie intricate challenges and perils that demand our attention. \nWhile they offer convenience and productivity\, we dissect how they can also be manipulated and weaponized by malicious actors\, raising concerns about inherent biases\, jailbreaking potential\, security concerns\, privacy issues\, misinformation\, deepfakes\, cyber threats and their unsettling societal consequences. We explore how biases present in training data\, historical injustices\, and societal prejudices can be perpetuated and even amplified by these models\, posing a significant threat to fairness\, equity\, and inclusivity. \nThis talk is aimed at raising awareness and engage the audience in a critical dialogue on these multifaceted challenges posed by LLMs. By understanding these challenges\, we can collectively work towards harnessing the power of these models for the betterment of society while safeguarding against their unintended consequences. \n1:35pm\n\nEmerging Technologies for Computing Paradigm Shift\nBrandon Wang\nSynopsys\n\n  \nThe explosive growth of AI has triggered a rapid increase in semiconductor demand\, leading to soaring power consumption and unsustainable water usage. This presentation will explore emerging technologies essential for driving a paradigm shift towards energy-efficient computing. Topics will include the “Shift Left” design methodology\, the impact of SLMs (Small Language Models) on computational efficiency in AI\, and the potential of neuromorphic and quantum computing as next-generation architectures. These advancements are poised to enable significant digital transformation and drive pervasive intelligence across various industries. The speaker will also provide insights into how organizations can stay at the cutting edge of these innovations\, offering a forward-looking perspective on the future of computational systems and the strategic steps needed to lead in this rapidly evolving landscape. \n2:10pm\n\nTBD\nChris Cheng\nHewlett-Packard Enterprise\n  \n\n\n\n\n\n\n\n\n\n\n\n\n\n\n\n\n\n\nShare this:\n				Share on LinkedIn (Opens in new window)\n				LinkedIn\n			\n				Share on X (Opens in new window)\n				X\n			\n				Share on Facebook (Opens in new window)\n				Facebook\n			Like this:Like Loading...
URL:https://marketingeda.com/event/electronic-design-process-symposium-edps-2024/
LOCATION:SEMI\, 673 S. Milpitas Blvd\, Milpitas\, CA\, United States
CATEGORIES:EDA,Symposium
ATTACH;FMTTYPE=image/jpeg:https://marketingeda.com/wp-content/uploads/edps-2024.jpg
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BEGIN:VEVENT
DTSTART;TZID=America/Los_Angeles:20241008T080000
DTEND;TZID=America/Los_Angeles:20241011T170000
DTSTAMP:20260404T013718
CREATED:20240906T174011Z
LAST-MODIFIED:20240926T000653Z
UID:8301-1728374400-1728666000@marketingeda.com
SUMMARY:PCB West 2024
DESCRIPTION:For more than 30 years PCB West has trained designers\, engineers\, fabricators and\, lately\, assemblers on making printed circuit boards for every product or use imaginable. More than 2\,000 designers\, fabricators\, assemblers and engineers register and more than 100 companies exhibit each year at the four-day technical conference and one-day sold-out exhibition. From high-reliability military/aerospace to cutting-edge IoT and wearables\, there’s something for everyone involved in the electronics supply chain. This is one show you cannot afford to miss. \nBrought to you by PCEA: Engineering Tomorrow’s Electronics! \nShare this:\n				Share on LinkedIn (Opens in new window)\n				LinkedIn\n			\n				Share on X (Opens in new window)\n				X\n			\n				Share on Facebook (Opens in new window)\n				Facebook\n			Like this:Like Loading...
URL:https://marketingeda.com/event/pcb-west-2024/
LOCATION:Santa Clara Convention Center\, 5001 Great America Parkway\, Santa Clara\, CA\, 95054\, United States
CATEGORIES:Conference,EDA
ATTACH;FMTTYPE=image/jpeg:https://marketingeda.com/wp-content/uploads/PCB-West-2024.jpg
END:VEVENT
BEGIN:VEVENT
DTSTART;TZID=Europe/Berlin:20241015T080000
DTEND;TZID=Europe/Berlin:20241016T170000
DTSTAMP:20260404T013718
CREATED:20240130T165521Z
LAST-MODIFIED:20240130T165521Z
UID:7564-1728979200-1729098000@marketingeda.com
SUMMARY:DVCon Europe 2024
DESCRIPTION:The Design and Verification Conference in Europe (DVCon Europe) is the leading European event covering the application of languages\, tools\, and intellectual property for the design and verification of electronic systems and integrated circuits. Sponsored by Accellera Systems Initiative\, DVCon Europe brings chip architects\, design and verification engineers\, and IP integrators the latest methodologies\, techniques\, applications\, and demonstrations for the practical use of EDA solutions for electronic design. \nShare this:\n				Share on LinkedIn (Opens in new window)\n				LinkedIn\n			\n				Share on X (Opens in new window)\n				X\n			\n				Share on Facebook (Opens in new window)\n				Facebook\n			Like this:Like Loading...
URL:https://marketingeda.com/event/dvcon-europe-2024/
LOCATION:Holiday Inn Munich – City Centre\, Hochstraße 3\, Munich\, 81669\, Germany
CATEGORIES:Conference,EDA
ATTACH;FMTTYPE=image/jpeg:https://marketingeda.com/wp-content/uploads/DVCon-Europe-2024.jpg
END:VEVENT
BEGIN:VEVENT
DTSTART;TZID=America/Los_Angeles:20241017T080000
DTEND;TZID=America/Los_Angeles:20241017T170000
DTSTAMP:20260404T013718
CREATED:20240806T194900Z
LAST-MODIFIED:20240806T194900Z
UID:8209-1729152000-1729184400@marketingeda.com
SUMMARY:OSMOSIS 2024
DESCRIPTION:Elevate your success with osmosis 2024\nThe annual osmosis event is a dynamic platform for exchanging successes achieved through applying formal techniques to overcome verification challenges. It offers a unique opportunity to connect and engage with our accomplished research and development (R&D) experts and participants. If you possess a compelling achievement narrative\, we invite you to unveil it at osmosis. \nYou will benefit from increased industry visibility as a subject matter expert\, and the conversations that follow may help you and others improve formal-based verification solutions. \n\n\nAbstract guidelines\nCraft a concise narrative outlining the essential bits of your success story\, encompassing: \n\nthe intricate problem you addressed\nrationale for employing formal technology-based solutions\ntangible outcomes\, ideally quantifiable\nkey learnings and findings\n\nFor utmost impact\, please limit your abstract to a single page\, front and back. \nInclude diagrams and code examples if desired. \nIf you have questions or need guidance in refining your narrative\, please reach out to us at osmosis.sisw@siemens.com \n\n\nSchedules and processes\nThe deadline for abstract submissions is 6 p.m. Central EU time on Mon.\, Sept. 23\, 2024. \nSubmissions will be evaluated as they are received. As we select abstracts\, we will begin working with the authors on their presentations. If we fill the agenda early\, we’ll close submissions. \n\n\nWe look forward to receiving your abstracts and seeing you in Munich! \n\n\nOn-demand presentations\nCheck out past\, on-demand presentations. \n\nOsmosis Aerospace and Defense – April 2024\nOsmosis Aerospace and Defense – 2023\n\n\nShare this:\n				Share on LinkedIn (Opens in new window)\n				LinkedIn\n			\n				Share on X (Opens in new window)\n				X\n			\n				Share on Facebook (Opens in new window)\n				Facebook\n			Like this:Like Loading...
URL:https://marketingeda.com/event/osmosis-2024/
LOCATION:Holiday Inn City Center\, Hochstraße 3\, Munich\, 81669\, Germany
CATEGORIES:EDA,User Group
ATTACH;FMTTYPE=image/jpeg:https://marketingeda.com/wp-content/uploads/OSMOSIS-2024-1.jpg
END:VEVENT
BEGIN:VEVENT
DTSTART;TZID=America/Los_Angeles:20241022T080000
DTEND;TZID=America/Los_Angeles:20241023T170000
DTSTAMP:20260404T013718
CREATED:20240805T221455Z
LAST-MODIFIED:20240805T221745Z
UID:8202-1729584000-1729702800@marketingeda.com
SUMMARY:RISC-V Summit - North America 2024
DESCRIPTION:RISC-V is defining the future of open computing by providing unprecedented freedom to innovate. More than 13 billion RISC-V cores have shipped\, powering new innovations in AI/ML\, wireless\, automotive. data center\, space\, IoT\, embedded and more. Each day\, thousands of engineers around the world collaborate and contribute to advance RISC-V. The RISC-V community shares the technical investment and helps shape the architecture’s strategic future so everyone may create more rapidly\, enjoy a new level of design freedom\, and substantially reduce the cost of innovation. Anyone\, anywhere can benefit from these contributions. \nThis October\, the global RISC-V community – including technical\, industry\, domain\, ecosystem and special interest groups who define the architecture’s specifications – will meet in Santa Clara\, California to share technology breakthroughs\, industry milestones\, and case studies\, as well as to network and build relationships. Come be part of the RISC-V movement. \n\n\n\nThe festivities kick off with RISC-V Member Day\, where technical and industry working groups meet in person to share updates on the status of various efforts.\nNext\, the RISC-V Summit North America features two days of compelling technical and industry keynotes and conference sessions\, paired with an expo featuring dozens of community members showcasing their the latest solutions.\n\nIt’s community-curated content\, research and innovation driving the next wave of growth for RISC-V. \nLearn about software\, systems\, development tools\, security\, the latest use cases in key markets and more. It’s all here. \nDefine the future. Build your knowledge and expertise. Grow your network. It’s all during RISC-V Summit North America. Come join us! \nShare this:\n				Share on LinkedIn (Opens in new window)\n				LinkedIn\n			\n				Share on X (Opens in new window)\n				X\n			\n				Share on Facebook (Opens in new window)\n				Facebook\n			Like this:Like Loading...
URL:https://marketingeda.com/event/risc-v-summit-north-america-2024/
LOCATION:Santa Clara Convention Center\, 5001 Great America Parkway\, Santa Clara\, CA\, 95054\, United States
CATEGORIES:Conference,IP
ATTACH;FMTTYPE=image/jpeg:https://marketingeda.com/wp-content/uploads/RISC-V-Summit-US-2024.jpg
END:VEVENT
BEGIN:VEVENT
DTSTART;TZID=America/Los_Angeles:20241023T090000
DTEND;TZID=America/Los_Angeles:20241023T100000
DTSTAMP:20260404T013718
CREATED:20241009T193236Z
LAST-MODIFIED:20241009T193236Z
UID:8402-1729674000-1729677600@marketingeda.com
SUMMARY:Hardware Verification using VirtuaLAB
DESCRIPTION:VirtuaLAB protocol solutions offer a full-stack testing environment with seamless connectivity and stimulus traffic generation for designs under test. It operates autonomously\, adapting to scenarios without requiring protocol knowledge from the user. VirtuaLAB significantly reduces test and compliance suite regression times\, running at high emulation speeds\, integrated with Protocol Analyzer for complete protocol visibility and performance metrics. Supporting any scenario\, it enables users to focus on their design’s unique value while ensuring reliable standard protocol interactions. \nWho Should Attend: \n\nEngineers and Managers responsible for System Design Verification of complex SoCs\nEngineers and Managers responsible for design performance verification\n\nWhat you will learn: \n\nAttendees will learn how VirtuaLAB protocol solutions provide a full stack from the physical to the application layer to connect to your design under test and create stimulus traffic as a host\, or respond to commands in the form of a compliant device.\nAttendees will learn the ease of bring-up of a VirtuaLAB environment with no testbench required\, but how to use real-world software to create workloads exactly matching the end-user of your silicon.\nAttendees will see a demonstration of VirtuaLAB running a back-to-back UFS4 host model and RTL SSD model DUT\, running the LLAMA 3.1 LLM\, and providing query responses in real-time.\n\nSpeaker:\n\n\n\n\n\n\nBen Whitehead\nDirector of Product Management\, Siemens EDA\n\n\n\n\n\nShare this:\n				Share on LinkedIn (Opens in new window)\n				LinkedIn\n			\n				Share on X (Opens in new window)\n				X\n			\n				Share on Facebook (Opens in new window)\n				Facebook\n			Like this:Like Loading...
URL:https://marketingeda.com/event/hardware-verification-using-virtualab/
LOCATION:CA
CATEGORIES:EDA,Webinar
ATTACH;FMTTYPE=image/jpeg:https://marketingeda.com/wp-content/uploads/Siemens-October-23-2024.jpg
END:VEVENT
BEGIN:VEVENT
DTSTART;TZID=America/New_York:20241027T080000
DTEND;TZID=America/New_York:20241031T170000
DTSTAMP:20260404T013718
CREATED:20240925T172254Z
LAST-MODIFIED:20240925T172254Z
UID:8353-1730016000-1730394000@marketingeda.com
SUMMARY:ICCAD 2024
DESCRIPTION:The International Conference on Computer-Aided Design focuses on advancements and research in the field of electronic design automation (EDA) and computer-aided design (CAD) for integrated circuits and systems. Topics include innovations in design methodologies\, tools\, algorithms\, and technologies related to the development of electronic systems. \nThe International Conference on Computer-Aided Design focuses on advancements and research in the field of electronic design automation (EDA) and computer-aided design (CAD) for integrated circuits and systems. Topics include innovations in design methodologies\, tools\, algorithms\, and technologies related to the development of electronic systems. \nJointly sponsored by IEEE and ACM\, ICCAD is the premier forum to explore new challenges\, present leading-edge innovative solutions\, and identify emerging technologies in the electronic design automation research areas. ICCAD covers the full range of CAD topics – from device and circuit level up through system level\, as well as post-CMOS design. ICCAD has a longstanding tradition of producing cutting-edge\, innovative technical program for attendees. \nShare this:\n				Share on LinkedIn (Opens in new window)\n				LinkedIn\n			\n				Share on X (Opens in new window)\n				X\n			\n				Share on Facebook (Opens in new window)\n				Facebook\n			Like this:Like Loading...
URL:https://marketingeda.com/event/iccad-2024/
LOCATION:Newark Liberty International Airport Marriott\, 1 Hotel Rd\, Newark\, NJ\, United States
CATEGORIES:Conference,EDA
ATTACH;FMTTYPE=image/jpeg:https://marketingeda.com/wp-content/uploads/ICCAD-2024-1.jpg
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BEGIN:VEVENT
DTSTART;TZID=America/Los_Angeles:20241030T090000
DTEND;TZID=America/Los_Angeles:20241030T100000
DTSTAMP:20260404T013718
CREATED:20241016T180601Z
LAST-MODIFIED:20241016T180601Z
UID:8419-1730278800-1730282400@marketingeda.com
SUMMARY:Verifying the next generation High Bandwidth Memory controllers for AI and HPC applications
DESCRIPTION:High Bandwidth Memory (HBM) has revolutionized AI\, machine learning\, and High-Performance Computing by significantly increasing data transfer speeds and alleviating performance bottlenecks. The introduction of next-generation HBM4 is especially transformative\, enabling faster training and execution of complex AI models. JEDEC has announced that the HBM4 specification is nearing finalization. In this webinar\, you will learn how Siemens’s scalable and customizable Avery HBM Verification IP helps companies like Rambus verify their industry-leading HBM4 Controller IP through rigorous testing to ensure reliability and performance. \n\n  \nWhat You Will Learn:  \n\nWhat’s new in HBM4\nChallenges involved in verifying advanced HBM generations\nUnique features in Siemens’s HBM4 memory models\nRambus’s newly-announced HBM4 memory controller IP\n\nWho Should Attend:  \n\nDesign & Verification Engineers\, Architects\nManagers and Directors for memory controllers\n\nWhat/Which Products are Covered:   \n\nSiemens Avery HBM4 Verification IP\nRambus HBM4 Memory Controller\n\nSpeakers:\n\n\n\n\n\n\nKamlesh Mulchandani\nApplication Engineering Consultant\, Siemens EDA\n\n\n\n\nKamlesh Mulchandani is an Application Engineering Consultant at Siemens EDA. In his role as a Verification IP AE\, Kamlesh bridges the gap between Verification IP technology and customer needs through collaboration\, technical support and by tailoring Siemens solutions for specific user applications. Prior to Siemens\, Kamlesh worked at Cadence as a Memory Subsystem Design & Verification Engineer where he worked on verifying LPDDRx/DDRx & GDDRx IPs. \n\n\n\n\n\n\n\nNidish Kamath\nDirector of Product Management for Memory Interface IP\, Rambus\n\n\n\n\nNidish Kamath is the Director of Product Management for Memory Interface IP at Rambus.  He previously held marketing and product management roles at AMD\, Kioxia (formerly Toshiba Memory)\, Avalanche Technologies\, Brocade and Qualcomm\, where he worked on computational storage\, SmartNICs and GPU cluster networking solutions. He has served in various standards and industry associations such as SNIA\, Center for Open Source Software (CROSS)\, CXL Consortium\, UEC and JEDEC. \n\n\n\nShare this:\n				Share on LinkedIn (Opens in new window)\n				LinkedIn\n			\n				Share on X (Opens in new window)\n				X\n			\n				Share on Facebook (Opens in new window)\n				Facebook\n			Like this:Like Loading...
URL:https://marketingeda.com/event/verifying-the-next-generation-high-bandwidth-memory-controllers-for-ai-and-hpc-applications/
LOCATION:CA
CATEGORIES:EDA,Webinar
ATTACH;FMTTYPE=image/jpeg:https://marketingeda.com/wp-content/uploads/Siemens-October-30-2024.jpg
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