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DTSTART;TZID=America/Los_Angeles:20240909T080000
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DTSTAMP:20260404T014001
CREATED:20240718T193601Z
LAST-MODIFIED:20240718T193601Z
UID:8164-1725868800-1726160400@marketingeda.com
SUMMARY:AI Hardware & Edge AI Summit 2024
DESCRIPTION:The AI Hardware & Edge AI Summit is the ultimate destination for the entire AI and ML ecosystem\, with a collaborative mission to train\, deploy and scale machine learning systems that are fast\, affordable\, and efficient. \nWhether it’s forging new partnerships\, staying ahead of the ever-changing semi-conductor landscape\, learning how to build\, train\, and deploy efficient systems\, meeting peers\, learning from AI luminaries\, or simply gaining exposure to the world of AI infrastructure\, you’ll find over 1\,200 likeminded people at our event. \nTake it from the thousands of industry peers who have attended in the past\, if you’re in the AI infrastructure and semiconductor worlds\, this is one not to miss! \nShare this:\n				Share on LinkedIn (Opens in new window)\n				LinkedIn\n			\n				Share on X (Opens in new window)\n				X\n			\n				Share on Facebook (Opens in new window)\n				Facebook\n			Like this:Like Loading...
URL:https://marketingeda.com/event/ai-hardware-edge-ai-summit-2024/
LOCATION:Signia by Hilton\, 170 S Market Street\, San Jose\, CA\, 95113\, United States
CATEGORIES:Conference,IP,Semiconductor
ATTACH;FMTTYPE=image/jpeg:https://marketingeda.com/wp-content/uploads/AI-Hardware-Edge-AI-Summit-2024.jpg
ORGANIZER;CN="Kisaco Research":MAILTO:events@kisacoresearch.com
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DTSTART;TZID=America/Los_Angeles:20240911T080000
DTEND;TZID=America/Los_Angeles:20240911T090000
DTSTAMP:20260404T014001
CREATED:20240821T163437Z
LAST-MODIFIED:20240821T163437Z
UID:8259-1726041600-1726045200@marketingeda.com
SUMMARY:Questa Formal Verification IP AMBA: Achieve Protocol Compliance in Designs
DESCRIPTION:Delve into how Questa Formal Verification IP (VIP) for the AMBA protocol ensures that designs incorporating AMBA adhere strictly to the protocol; all without the need for simulation. The solution integrates comprehensive protocol knowledge and provides user-friendly interfaces\, significantly reducing the setup time for verification environments. Optimized for top-tier performance and scalability\, Questa Formal VIP AMBA is the ideal tool for achieving high-efficiency and accurate protocol compliance. Don’t miss this opportunity to learn how to streamline your verification process and enhance your design workflows. \n  \nWhat You Will Learn:  \n\nChallenges in IP Integration\nUnderstand the common obstacles faced by designers and verification teams during IP integration and how to overcome them.\nBenefits of Formal Verification Ips\nDiscover the advantages of using formal verification IPs\, including enhanced accuracy and reduced need for simulation.\nCapabilities and Supported Protocols\nExplore the extensive capabilities of Questa Formal VIP AMBA and the range of protocols it supports.\nFrom Specification to Formal Properties\nLearn how protocol specifications are transformed into formal properties for effective verification.\nDebugging Protocol Violations\nGain insights into debugging techniques for protocol violations to ensure compliance and reliability.\n\n            \nWho Should Attend:  \n\nRTL Design Engineers\nDesign Integrators\nDesign Verification Engineers\n\nWhat/Which Products are Covered:   \n\nQuesta Formal VIP AMBA\nQuesta Formal VIP OnChip\nQuesta Check Register\n\n\n\nSpeaker:\n\n\n\n\n\n\nNicolae Tusinschi\nFormal Verification Solutions Product Manager\, Siemens EDA\n\n\n\n\nNicolae Tusinschi is a product manager for formal verification solutions at Siemens EDA. He holds a master’s degree combined between the University of Southampton and the University of Kaiserslautern. After a master’s thesis at Continental\, Nicolae joined OneSpin\, where he worked in QA\, then as a product specialist and later served as product owner for design verification tools at OneSpin. His key projects include integrating simulation coverage with formal metrics\, leveraging coverage results in the verification process\, formal verification of RISC-V cores. \n\n\n\nShare this:\n				Share on LinkedIn (Opens in new window)\n				LinkedIn\n			\n				Share on X (Opens in new window)\n				X\n			\n				Share on Facebook (Opens in new window)\n				Facebook\n			Like this:Like Loading...
URL:https://marketingeda.com/event/questa-formal-verification-ip-amba-achieve-protocol-compliance-in-designs/
LOCATION:CA
CATEGORIES:EDA,IP,Webinar
ATTACH;FMTTYPE=image/jpeg:https://marketingeda.com/wp-content/uploads/Siemens-Setember-11-2024.jpg
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