VC Formal
Pre-empt Late-stage Low Power Issues using Predictive Analysis
Low power is an increasingly critical requirement for all modern SoCs. Moreover, it is becoming more and more difficult with complex architectures being used in modern designs. This has made it necessary for designers to invest heavily in this verification effort throughout the design development cycle starting from architecture definition, RTL development, to final netlist tape-out. Conventionally, static low power flow constitutes defining and cleaning… Read More »Pre-empt Late-stage Low Power Issues using Predictive Analysis
VC Formal SIG 2022, Day 1
Each year, the Synopsys VC Formal Special Interest Group (SIG) aims to help develop, grow and encourage the formal verification community to exchange the latest innovations, techniques and methodologies to address complex verification challenges. This year’s event will share details about groundbreaking applications and successful deployments of formal verification from industry leaders and formal enthusiasts worldwide.… Read More »VC Formal SIG 2022, Day 1
VC Formal SIG 2022, Day 2
Each year, the Synopsys VC Formal Special Interest Group (SIG) aims to help develop, grow and encourage the formal verification community to exchange the latest innovations, techniques and methodologies to address complex verification challenges. This year’s event will share details about groundbreaking applications and successful deployments of formal verification from industry leaders and formal enthusiasts worldwide.… Read More »VC Formal SIG 2022, Day 2
Formal Validation of a Datapath Pipelined Design with VC Formal
Finite Impulse Response (FIR) filters are widely used in communication, consumer electronics, and many other digital signal process (DSP) applications. A FIR filter includes a complex pipelined datapath based on arithmetic functions such as multipliers with its output at any given time depending on the previous state. Exhaustive verification of an FIR filter is important… Read More »Formal Validation of a Datapath Pipelined Design with VC Formal
Synopsys VC Formal DPV Virtual Workshop Series
Day 1 (February 1, 2023) of this workshop series will cover practical knowledge of the best datapath verification strategies and provide hands-on experience with the industry's best-in-class datapath validation app – Synopsys VC Formal DPV. This workshop includes a featured session presented by Theo Drane, Datapath Architect at Intel, who will share his experience on how… Read More »Synopsys VC Formal DPV Virtual Workshop Series
Synopsys VC Formal DPV Virtual Workshop Series
Day 1 (February 1, 2023) of this workshop series will cover practical knowledge of the best datapath verification strategies and provide hands-on experience with the industry's best-in-class datapath validation app – Synopsys VC Formal DPV. This workshop includes a featured session presented by Theo Drane, Datapath Architect at Intel, who will share his experience on how… Read More »Synopsys VC Formal DPV Virtual Workshop Series
Don’t Take the Risk, Formally Verify Your RISC-V Cores
Synopsys Webinar | Thursday, May 25, 2023 | 9:00 a.m. PT According to a recent Semico Research report, the RISC-V Core IP market is expected to grow at a 34.9% CAGR through year 2027. With increasing popularity, it is of utmost importance that the RISC-V Core IPs are secure and bug free. In this… Read More »Don’t Take the Risk, Formally Verify Your RISC-V Cores