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  • Pre-empt Late-stage Low Power Issues using Predictive Analysis

    Low power is an increasingly critical requirement for all modern SoCs. Moreover, it is becoming more and more difficult with complex architectures being used in modern designs. This has made it necessary for designers to invest heavily in this verification effort throughout the design development cycle starting from architecture definition, RTL development, to final netlist tape-out. Conventionally, static low power flow constitutes defining and cleaning… Pre-empt Late-stage Low Power Issues using Predictive Analysis

  • VC Formal SIG 2022, Day 1

    Each year, the Synopsys VC Formal Special Interest Group (SIG) aims to help develop, grow and encourage the formal verification community to exchange the latest innovations, techniques and methodologies to address complex verification challenges. This year’s event will share details about groundbreaking applications and successful deployments of formal verification from industry leaders and formal enthusiasts worldwide.… VC Formal SIG 2022, Day 1

  • VC Formal SIG 2022, Day 2

    Each year, the Synopsys VC Formal Special Interest Group (SIG) aims to help develop, grow and encourage the formal verification community to exchange the latest innovations, techniques and methodologies to address complex verification challenges. This year’s event will share details about groundbreaking applications and successful deployments of formal verification from industry leaders and formal enthusiasts worldwide.… VC Formal SIG 2022, Day 2

  • Formal Validation of a Datapath Pipelined Design with VC Formal

    Finite Impulse Response (FIR) filters are widely used in communication, consumer electronics, and many other digital signal process (DSP) applications. A FIR filter includes a complex pipelined datapath based on arithmetic functions such as multipliers with its output at any given time depending on the previous state. Exhaustive verification of an FIR filter is important… Formal Validation of a Datapath Pipelined Design with VC Formal

  • Synopsys VC Formal DPV Virtual Workshop Series

    Day 1 (February 1, 2023) of this workshop series will cover practical knowledge of the best datapath verification strategies and provide hands-on experience with the industry's best-in-class datapath validation app – Synopsys VC Formal DPV. This workshop includes a featured session presented by Theo Drane, Datapath Architect at Intel, who will share his experience on how… Synopsys VC Formal DPV Virtual Workshop Series

  • Synopsys VC Formal DPV Virtual Workshop Series

    Day 1 (February 1, 2023) of this workshop series will cover practical knowledge of the best datapath verification strategies and provide hands-on experience with the industry's best-in-class datapath validation app – Synopsys VC Formal DPV. This workshop includes a featured session presented by Theo Drane, Datapath Architect at Intel, who will share his experience on how… Synopsys VC Formal DPV Virtual Workshop Series

  • VC Formal Virtual Workshop – North America & Europe

    Location: Virtual workshop with hands-on labs. This workshop is best suited for attendees based in North America and Western Europe. For attendees based in Eastern Europe or Asia, please register for this workshop being held on June 21st instead. Registration will close on June 14th. Space is limited! Do you want to harness the force of formal verification to ensure… VC Formal Virtual Workshop – North America & Europe

  • VC Formal Special Interest Group

    Santa Clara Marriott 2700 Mission College Blvd, Santa Clara, CA, United States

    Register for the Synopsys VC Formal Special Interest Group (SIG) event today. This event provides an opportunity for users, managers, and enthusiasts to stay connected with the latest formal verification innovations, techniques and methodologies. Industry leaders such as Amazon, Black Sesame, Microsoft, NVIDIA, Samsung, and Untether AI will share their experiences with the latest formal… VC Formal Special Interest Group