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DTSTART;TZID=Europe/London:20240924T094500
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UID:8297-1727171100-1727188200@marketingeda.com
SUMMARY:FPGA Front Runner: FPGA Verification Strategies
DESCRIPTION:Time\nSpeaker\nDetails\n\n\n09.30\nArrival and Registration\n\n\n10.00\nDave Sanders\, Rolls-Royce\nOverview of Rolls Royce @ Solihull \nPresentation Title – Rolls-Royce… the past\, the present and the future \nAbstract – Rolls-Royce has come a long way since its inception as a car manufacturer at the start of the twentieth century\, for starters it doesn’t make cars anymore! This talk will provide an insight into Rolls-Royce’s past present and future with a focus on the pivotal role that electronics now plays in a company traditionally known for its mechanical engineering solutions.\n\n\n10.30\nEspen Tallaksen\, EmLogic\nPresentation Title – Modern VHDL testbenches – An AXI-stream example\, first dead simple\, then advanced \nAbstract – Do you want to see how easily you can verify your FPGA or ASIC? Join in to see this exemplified with a testbench for an AXI-stream based data flow design – using UVVM\, which is currently used by more than one third of all European FPGA designers. \nMost testbenches verifying a complex DUT are relatively unstructured and difficult to understand\, modify\, extend\, maintain and reuse. You can often easily reduce the verification time by at least a factor of two by having a well structured and easy to understand test harness\, and writing commands at a higher abstraction level – allowing a good and complete testcase overview by just looking at a simple test sequencer with easy to understand high-level commands. \nThis presentation will first show how interface handling procedures (BFMs) can be applied in a very simple way to verify a DUT. Then we will show how a more advanced testbench using verification components\, models\, scoreboards and high-level transactions will allow more thorough verification of more complex DUT scenarios in a very structured and simple way.\n\n\n11.00\nJim Lewis\, SynthWorks Design Inc\nPresentation Title – Why Should Our Team be Using VHDL + OSVVM for Verification? \nAbstract – Developing and deploying a verification methodology can be costly and time consuming. Going without one will be even more costly due to bugs escaping into production hardware systems. \nOpen Source VHDL Verification Methodology (OSVVM) provides the VHDL community with an already developed\, open-source solution. OSVVM implements all of the capabilities of a modern verification methodology: transaction-based testing\, a verification framework\, verification components\, self-checking tests\, messaging handling\, error tracking\, requirements tracking\, constrained random testing\, scoreboards\, functional coverage\, co simulation with software\, test automation\, and a comprehensive set of test reports. \nThis presentation examines how these capabilities will benefit your projects. \nSystemVerilog+UVM also provides a similar set of capabilities. Unfortunately\, SV+UVM ended up absurdly complex to use – instead of using a module (entity/architecture in VHDL) with its built-in concurrency\, SV+UVM uses OO\, sequential code\, and fork and join (to get concurrency). As a result\, SV has failed to unify the design and verification communities. \nVHDL+OSVVM on the other hand uses entity/architectures to create verification components and libraries of subprograms (procedures and functions) to extend VHDL into a complete verification language. In doing this\, OSVVM creates verification capabilities that rival SystemVerilog+UVM while at the same time it uses VHDL language elements that are familiar to VHDL design engineers. \nAs a result\, with VHDL+OSVVM and a good verification lead\, any VHDL engineer can do verification as well as RTL design.\n\n\n11.30\nRefreshment break\n\n\n12.00\nPhilipp Wagner\, FOSSi Foundation\nPresentation Title – cocotb is making verification fun! \nAbstract – cocotb lets you verify chips like software: productive\, simulator-agnostic\, in Python. In this talk\, you’ll learn what cocotb is and how using Python for verification can make your next verification job more productive. There’s even something in there for those of you who already know cocotb: a look at cocotb 2.0 and tips and tricks how to update your testbenches to make best use of the new features.\n\n\n12.30\nChristian Tchilikov\, semify GmbH\nPresentation Title – Utilizing the Cocotb Python Framework for Efficient Functional Verification \nAbstract – Cocotb is a framework that allows for verification test cases written in Python to interact with DUTs being simulated in common simulation tools. Compared to classical approaches for verification\, Cocotb has very low upfront engineering costs. With access to the full functionality of the Python programming language\, the complexity of testbenches can scale up as required. \nCocotb comes with built-in functionalities for many of the tasks required of a modern testbench\, like constrained random input generation\, coverage tracking\, and assertions. \nCocotb’s foundation being the Python language means that software models of the design can be written in a high-level Object-Oriented language. Additionally\, higher-level objects such as drivers or monitors can be designed for the bit-wiggling of DUT input signals\, providing a higher level of abstraction\, similar to UVM sequences. The software model can then be easily scoreboarded with the DUT through Cocotb. \nAdditionally\, Cocotb provides high-level abstractions for interfacing with the simulated design. This comes in the form of hierarchical signal reading and assignment\, event triggers\, and parallel execution of coroutines similar to SystemVerilog’s forks. Leveraging these tools\, it becomes simple to launch verification modules like drivers and monitors\, running and interfacing with the DUT in parallel. \nThird-party verification IP modules for many standard interfaces are available via the cocotb extensions packages hosted on PyPi\, so devices using SPI or AXI\, amongst others\, can be verified with minimal effort. In addition\, engineers can write and reuse their own verification IP\, such as bus monitors\, drivers\, etc\, similar to the UVM approach of verification. \nA special emphasis is on using cocotb alongside an open-source toolchain like Icarus Verilog\, acheiving a similar quality of results compared to commercial offerings. This combination of tools provides features that are otherwise hidden behind expensive licence paywalls\, and makes digital verification accessible to a wider audience. \nCocotb serves as a great alternative to traditional SystemVerilog Object-Oriented verification by working around the limitations of the simulators that do not support the full feature set of SystemVerilog by providing similar functionality in the Python language instead.\n\n\n13.00\nDave Amor\, Ultra Maritime\nPresentation Title – Integration of Atlassian Bamboo with MathWorks Tools for FPGA Development \nAbstract – In safety critical FPGA development\, the need for efficiency\, reliability\, and predictability while maintaining agility is vital. \nUltra Maritime has embraced these demands by integrating Continuous Integration (CI) practices with MathWorks tools and Agile methodologies\, creating a streamlined and robust development process that ensures high-quality outcomes in mission-critical applications. \nThis presentation will explore the strategies and technologies we use to achieve consistent\, and resilient FPGA development\, focusing on how these practices contribute to the success of our projects. \nAtlassian Bamboo allows us to automate testing\, code generation\, and the bitstream creation processes. \nThis integration ensures that every change in our FPGA designs can be automatically validated through rigorous testing\, significantly reducing the risk of errors and accelerating the development lifecycle. \nBy automating these processes\, a higher standard of code quality is possible while freeing up our engineers to focus on innovation and problem-solving. \nThis presentation will touch on the adoption of Agile Scrum practices within our FPGA development teams. \nAgile Scrum provides a flexible framework that allows us to adapt to changing requirements\, prioritise tasks effectively\, and deliver incremental improvements throughout the project lifecycle. Key ceremonies such as sprint planning\, daily stand-ups\, and retrospectives are essential to maintaining focus and ensuring continuous improvement. We will discuss how these practices have enhanced our ability to respond to challenges\, manage complexity\, and maintain alignment across our teams. \nA crucial aspect of our development process is the integration of Jira with Bamboo and Simulink. This connection enables seamless tracking of tasks\, test results\, and code changes. Automated reporting of test failures and direct linking to Jira tasks ensure that issues are identified\, prioritised and resolved. \nThe presentation will also address the advantages of CI in ensuring resilience against the turnover of key personnel. By standardising workflows and maintaining consistent environments\, we reduce the dependency on individual knowledge and ensure that our processes are sustainable. \nLooking to the future\, we will explore potential enhancements to our current setup\, by leveraging developments in Large Language Models. \nUltra Maritime’s approach to FPGA processes evolving over the last 25 years has created a environment that is effective\, adaptable and resilient\, ensuring the delivery of high-quality\, reliable products.\n\n\n13.30\nLunch\n\n\n14.00\nTour\n\n\n14.30\nFinish refreshments/networking\n\n\n\nShare this:\n				Share on LinkedIn (Opens in new window)\n				LinkedIn\n			\n				Share on X (Opens in new window)\n				X\n			\n				Share on Facebook (Opens in new window)\n				Facebook\n			Like this:Like Loading...\n\n	Related
URL:https://marketingeda.com/event/fpga-front-runner-fpga-verification-strategies/
LOCATION:Rolls Royce Control Systems\, 5000 Solihull Parkway\, Birmingham\, B37\, United Kingdom
CATEGORIES:EDA,Forum
ATTACH;FMTTYPE=image/jpeg:https://marketingeda.com/wp-content/uploads/Tessolve-September-24-2024.jpg
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