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UID:7073-1702450800-1702461600@marketingeda.com
SUMMARY:RTL-to-GDSII Flow for ASIC Design Using Cadence Tools
DESCRIPTION:Would you like to know how to design a complete chip using the RTL-to-GDSII Flow? \nIn this free technical Training Webinar with Application Engineer Sai Srinivas Pamula\, we’ll teach you the essential steps in the RTL-to-GDSII design flow using a wide variety of industry-leading Cadence tools—such as the Xcelium Logic Simulator\, Modus DFT Software Solution\, Genus Synthesis Solution\, Conformal technologies\, Innovus Implementation System\, and Tempus Timing Solution—that provide great power\, performance\, and area (PPA). \nWe’ll explore topics like: \n\nWriting RTL code using Verilog or VHDL\nSynthesizing the RTL design into a gate-level netlist\nInserting scan chains into the netlist for testing and debugging\nPerforming logic equivalence checking to verify that the synthesized design is functionally equivalent to the original RTL design\nImplementing the netlist by performing floorplanning\, placement\, clock tree synthesis\, and routing\nPerforming timing signoff to verify that the design meets all of its timing requirements\nExtracting the GDSII file from the physical layout to manufacture the chip\n\nWebinar\nRTL-to-GDSII Flow for ASIC Design Using Cadence Tools \nDate and Time\nWednesday\, December 13\n07:00 PST San Jose / 10:00 EST New York / 15:00 GMT London / 16:00 CET Berlin / 17:00 IST Jerusalem / 20:30 IST Bangalore / 23:00 CST Beijing \n\nTo register for the RTL-to-GDSII Flow for ASIC Design Using Cadence Tools webinar\, sign in with your Cadence Support account (email ID and password) to log in to the Learning and Support System. Then select Enroll to register for the session. Once registered\, you’ll receive a confirmation email containing all login details. If you don’t have a Cadence Support account\, go to Registration Help or Cadence User Registration and complete the requested information. \nShare this:\n				Share on LinkedIn (Opens in new window)\n				LinkedIn\n			\n				Share on X (Opens in new window)\n				X\n			\n				Share on Facebook (Opens in new window)\n				Facebook\n			Like this:Like Loading...\n\n	Related
URL:https://marketingeda.com/event/rtl-to-gdsii-flow-for-asic-design-using-cadence-tools/
CATEGORIES:EDA,Webinar
ATTACH;FMTTYPE=image/jpeg:https://marketingeda.com/wp-content/uploads/Cadence-December-13-2023.jpg
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