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SUMMARY:STAC Summit
DESCRIPTION:STAC Summits bring together CTOs and other industry leaders responsible for solution architecture\, infrastructure engineering\, application development\, machine learning/deep learning engineering\, data engineering\, and operational intelligence to discuss important technical challenges in trading and investment. \nWHEN\nTuesday\, October 31\, 2023\nSTAC Exchange (Exhibits) opens at 8:30am CDT\nConference starts at 9:00am CDT\nNetworking lunch at ~12:00pm CDT\nConference concludes at ~4:00pm CDT\nReception immediately following \nWHERE\nThe Metropolitan Club\nWillis Tower\n233 South Wacker Drive\n66th Floor\nChicago \n\n\n\n9:00am\nSTAC Update: Historical tick analytics\n\n\n\n\n\nPeter Nabicht\, President\, Strategic Technology Analysis Center\n\nPeter will present the latest results in STAC-M3 (tick analytics).\n\n\n\n\n\n\n9:15am\nInnovation Roundup\n\n\n\n“How to maximize your GPU investment”\nJeff Chu\, Financial Services Sales\, Penguin Solutions\n\n\n\n“Using a vector database to unlock the power of your data”\nJosh Kalina\, Pre-Sales Engineer\, KX\n\n\n\n“Data at Scale: Overcoming Challenges in Generative AI and LLM Development”\nKeith Miller\, VP Technical Sales\, Services and Support\, DDN\n\n\n\n\n\n\n9:35am\nEnforcing the foundation: Improving data lineage      ;\n\n\n\n\n\nMarc Gale\, Director of Data Engineering\, OncoHealth; former Manager of Data Engineering\, Chicago Trading Company\nJosh Kalina\, Pre-Sales Engineer\, KX\nKeith Miller\, VP Technical Sales\, Services and Support\, DDN\n\nIt’s no secret that the automation of insights drives forward the financial industry. Both traditional quantitative analysis and newer AI models require a solid data foundation. Data engineers have to build this foundation from an ever-increasing universe of data sets\, which come from many sources with varying quality. Even worse\, today’s data could be corrected tomorrow\, next week\, or next year. For models to stay stable during rapid innovation\, data engineers must properly track\, maintain\, and leverage the data’s lineage. How should they track change sets\, version data\, and stay synchronized across the enterprise? How should licensing and permissions be taken into account? What are the best practices for maintaining metadata? How do storage architectures impact data lineage solutions? Join our panel of experts and add your questions to the mix.\n\n\n\n\n\n\n10:05am\nThe unbearable heaviness of data: Can modern approaches help?\n\n\n\n\n\nVrashank Jain\, Sr. Director of Product Management for Data Management Solutions\, Dell Technologies\n\nIt’s common for data architects and engineers to spend more time managing data than creating value from it. They have to deal with data-hungry end users\, capture real-time streams\, and manage multiple derivative data sets for historical research. AI adoption is piling on troves of model inputs and outputs that are required for explainability and fine tuning. And hybrid cloud infrastructures mean copies in multiple locations. How can architects and engineers enable new value from data rather than simply managing the inventory? Vrashank has seen financial firms greatly reduce the burden of data maintenance\, allowing technologists to focus on developing data products. Using Dell’s experience with an international bank as a guide\, he’ll show how applying an open data platform\, from edge to core to cloud\, can reduce data movement\, consolidate data intelligently\, and allow access to diverse tools and uses\, all while keeping data secure. Be sure to bring your questions for Vrashank as he covers best practices in data modernization and the benefits they can bring.\n\n\n\n\n\n\n10:30am\nBreak\n\n\n\n\n\n\n11:00am\nSTAC Update: Big compute\n\n\n\n\n\nBishop Brock\, Head of Research\, Strategic Technology Analysis Center\n\nBishop and Peter will present the latest STAC Benchmark Council activities compute critical workloads\, including STAC-A2 (complex deriviatives risk computation) and an update from the STAC-ML Working Group.\n\n\n\n\n\n\n11:10am\nWaste not\, want not: Avoiding idle GPUs\n\n\n\n\n\nTroy Kaster\, VP of AI\, Penguin Solutions\n\nMany financial firms are looking to large-scale GPU clusters to meet the demands of compute-hungry AI and HPC workloads in price discovery\, portfolio management\, and quantitative research. But once they fill the compute gap\, a knowledge gap remains. How should system engineers and admins best utilize these enormous investments and avoid the pitfalls that result in poor performance? Troy will help us understand how to ensure high availability and maximize the utilization of expensive computing platforms. Using Penguin’s experience bringing a 16k GPU cluster online for Meta\, he’ll walk us through some real-life issues encountered and solutions applied. Along the way he’ll cover best practices for designing\, building\, deploying\, and managing large-scale GPU clusters.\n\n\n\n\n\n\n11:35am\nInnovation Roundup\n\n\n\n“Build. Connect. Analyse. Beeks solves your colo and network visibility challenges.”\nMatthew Cretney\, Head of Product Management\, Beeks Group\n\n\n\n“Mechanics of Low Latency Capture”\nPramod Nayak\, Director of Product Management\, Low Latency\, Refinitiv\, an LSEG Business\n\n\n\n“The Smart Way to Configure a Tap Aggregator”\nKevin Formby\, VP Finance and Capital Markets\, Keysight Technologies\n\n\n\n\n\n\n11:50am\nEncrypting our markets: The impact of security on high-performance infrastructures\n\n\n\n\n\nVenkat Doddapuneni\, Senior Director of Software Engineering\, CME Group\nKevin Formby\, VP Finance and Capital Markets\, Keysight Technologies\nAdditional speakers to be announced\n\nSecurity has become a key component of the systemic risk conversation. Market oversight groups are discussing encrypted connections\, and at least one exchange has rolled them out. Encryption can provide a layer of protection\, helping prevent threats from moving horizontally through financial systems. But our markets benefit from high-performance\, low-friction connectivity. What conflicts can arise when security meets market access? Our panel of experts will discuss how to solve for security without exacerbating other tech risks. They’ll dive into important aspects\, including what concerns motivate a desire for higher security\, what should be in scope\, the impact on performance\, and how to maintain network-based risk\, compliance\, and data monitoring systems when encryption is a must. Bring your questions and join us to explore the impact of encryption on market connectivity.\n\n\n\n\n\n\n12:20pm\nNetworking Luncheon\n\n\n\n\n\n\n1:20pm\nSTAC Update: Network communications\n\n\n\n\n\nPeter Nabicht\, President\, Strategic Technology Analysis Center\n\nPeter will present on the latest STACT Benchmark Council activities in network communications\, including recent test results on a high frequency radio link and benchmark development activities for cloud networking.\n\n\n\n\n\n\n1:35pm\nInnovation Roundup\n\n\n\n“Leveraging HATI for high resolution timing to FPGA’s.”\nCiaran Kennedy\, Sales\, Safran Timing & Navigation\n\n\n\n“Create a Better and Faster Consolidated View Across Markets Using FPGAs”\nCliff Maddox\, Director of Business Development\, NovaSparks\n\n\n\n“Cancel on Behalf is a Game Changer”\nJohn Hagerman\, VP Marketing and Business Development\, Algo-Logic\n\n\n\n“Using Equivalence Checking to Rapidly Evolve Your Design”\nMartin Rowe\, Sr. Application Engineer\, Siemens\n\n\n\n“Mastering Ultra-Low Latency: The Technical Blueprint of FPGA and Software Hybrid Solutions”\nJean-François Gagnon\, Ultra-Low Latency FPGA Solutions Architect\, Orthogone\n\n\n\n\n\n\n2:00pm\nTalent shortages in hardware verification: Can ML plug the gaps?\n\n\n\n\n\nAdam Sherer\, Verification Technology Executive\, Cadence\n\nAs discussed at recent STAC Summits\, financial firms suffer from a lack of verification engineers. They can achieve significant latency gains with properly designed and implemented hardware solutions\, but a shortage of experienced\, skilled personnel causes painful lead times and uncomfortable prioritization decisions. Adam thinks that\, given the proper setup\, advances in ML can provide some relief by increasing the productivity of current staff. He’ll dive into tasks that grind on an engineer’s time—like regression optimization\, failure triage analysis\, and bug localization—and explain how ML can ease the burden. Bring your questions and join him as he discusses using ML to accelerate your FPGA and ASIC verification.\n\n\n\n\n\n\n2:20pm\nBreak\n\n\n\n\n\n\n2:50pm\nSTAC Update: Fast data\n\n\n\n\n\nPeter Nabicht\, President\, Strategic Technology Analysis Center\n\nPeter will discuss the latest test results for STAC-N1 (full stack networking).\n\n\n\n\n\n\n2:55pm\nInnovation Roundup\n\n\n\n“ÜberNIC can do… Can Yours?”\nAlex Stein\, Global Head Business Development\, Liquid-Markets-Solutions\n\n\n\n“Trading at the speed of light – Beyond ultra-low latency with Salience Labs”\nChris Porthouse\, Chief Product Officer\, Salience Labs\n\n\n\n“nxFramework update: Added features and improved latency for the Exegy FPGA development framework”\n Laurent de Barry\, Sr. Director\, Global Head of Solutions Consulting\, Exegy\n\n\n\n\n\n\n3:15pm\nDesigning the right hardware stack for FPGA\n\n\n\n\n\nMichael Gorbovitski\, Executive Director\, Morgan Stanley\nRobert DeWitt\, Director Product Marketing\, AMD\nDarrin Machay\, Principal Engineer\, Arista\n\nFGPAs are a go-to component for firms looking to improve their latencies\, whether by getting strategies as close to the network as possible or offloading critical workflows from the CPU. But as the best engineers know\, FPGAs are but one component of the custom hardware stack that affects performance. Given recent and upcoming changes in that stack\, designing the best systems requires answering a number of questions. How do on-board HBM3E and tiering impact memory-intensive applications? Do PCIe 5 and CXL change how we think about accessing compute\, memory\, and storage? Will new designs that pair ASIC with FPGA open new latency possibilities\, and what can we achieve with programmable switches? What’s the state of the art with FPGA sharing a fabric with CPU and other compute accelerators? Join our panel of experts as they explore these questions and yours.To kick off\, there will be some brief presentations:\n\n\n\n“Trade Smarter and Trade Faster with the New AMD FPGA accelerator for Ultra-Low Latency Trading”\n Hamid Reza Salehi\, Director Product Marketing\, AMD\n\n\n\n“Arista 7130 Update: Ultra Low Latency 25G”\n Darrin Machay\, Principal Engineer\, Arista\n\n\n\n\n\n\n~4:00pm\nNetworking Reception\n\n\n\nShare this:\n				Share on LinkedIn (Opens in new window)\n				LinkedIn\n			\n				Share on X (Opens in new window)\n				X\n			\n				Share on Facebook (Opens in new window)\n				Facebook\n			Like this:Like Loading...\n\n	Related
URL:https://marketingeda.com/event/stac-summit-2/
LOCATION:The Metropolitan Club\, 233 South Wacker Drive\, Chicago\, IL\, United States
CATEGORIES:Conference,EDA,IP,Semiconductor
ATTACH;FMTTYPE=image/jpeg:https://marketingeda.com/wp-content/uploads/STAC-October-31-2023.jpg
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