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Electronic Design Automation for Emerging Technologies
Presenter: Anupam Chattopadhyay Title: Electronic Design Automation for Emerging Technologies Abstract: The continued scaling of horizontal and vertical physical features of silicon-based complementary metal-oxide-semiconductor (CMOS) transistors, termed as “More Moore”, has a limited runway and would eventually be replaced with “Beyond CMOS” technologies. There has been a tremendous effort to follow Moore’s law but it is currently… Electronic Design Automation for Emerging Technologies
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Thermal Integrity Challenges and Solutions of Silicon Interposer Design
In this latest installment of the year-long 3D-IC webinar series, Dr. Lang Lin will discuss the Thermal Integrity issues associated with 3D-IC designs. The presentation will cover thermal hotspots, mechanical stresses induced by thermal issues, and methods for capturing these problems with simulation and virtual prototyping, with a focus on designs that utilize silicon interposers.… Thermal Integrity Challenges and Solutions of Silicon Interposer Design
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Learn About Advanced TFT-Based Flat Panel Design with SmartSpice
In this webinar, we will present the benefits of adopting SmartSpice’s unique 4-terminal TFT compact model, and we will also describe how SmartSpice Flex Modeling technology can be used to simulate image retention issues. Many TFT technologies in the market today are based on 4-terminal devices, while SPICE simulators from other vendors can only support… Learn About Advanced TFT-Based Flat Panel Design with SmartSpice
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International Symposium on Physical Design (ISPD) 2023
General Information The International Symposium on Physical Design (ISPD) provides a premier forum to exchange ideas and promote innovative research in all aspects of physical design ranging from traditional topics for ASIC and FPGA designs to emerging technologies that impact physical design of integrated circuits (ICs). In 2023, ISPD will be online with virtual participation,… International Symposium on Physical Design (ISPD) 2023
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IRPS 2023
Hyatt Regency Monterey 1 Old Golf Course Rd, Monterey, CA, United StatesFor 60 years, IRPS has been the premiere conference for engineers and scientists to present new and original work in the area of microelectronics reliability. Drawing participants from the United States, Europe, Asia, and all other parts of the world… IRPS 2023 will be presented as an in-person conference, with a virtual component available. The… IRPS 2023
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2023 US ESD Workshop
Hyatt Regency Monterey 1 Old Golf Course Rd, Monterey, CA, United StatesWe are happy to announce that once again the International Electrostatic Discharge Workshop (IEW) will be co-locating with IRPS this year. Their submission deadline is January 23, 2023. For further details, including the Call for Posters, please visit their webpage here.
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Maximizing yields through collaboration
Semiconductor companies have long recognized the importance of yield management and having the right support in place to maximize results. In this 30-minute webinar brought to you by yieldHUB and SemiWiki, attendees will learn about a key to success in the world of yield management (and something that can be underestimated) - collaboration. This is… Maximizing yields through collaboration
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ESD Alliance Export Seminar
Cadence Design Systems, Bldg 10 2655 Seeley Avenue, San Jose, CA, United StatesThe ESD Alliance Export Committee will hold a seminar called “The Impact of New Regulations on the Semiconductor Design Ecosystem.” This seminar is presented by the ESD Alliance, a SEMI Technology Community, and will be hosted by Cadence Design Systems at their San Jose Headquarters. The Cadence Government and Trade Team will cover general trade compliance… ESD Alliance Export Seminar
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FPGA Frontrunner Meet & Greet
Leonardo EH5 2XS, Edinburgh, United KingdomTechNES is pleased to announce the next FPGA Front Runners event – to he hosted by Leonardo at their venue in Edinburgh on March 29th, and will focus on FPGA Design using High Level Languages. The FPGA Front runners is all about bringing together the UK FPGA & ASIC design communities to discuss all things… FPGA Frontrunner Meet & Greet
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SNUG Silicon Valley 2023
Santa Clara Convention Center 5001 Great America Parkway, Santa Clara, CA, United StatesSince 1991, the Synopsys Users Group (SNUG) has represented a global design community focused on innovating from Silicon to Software. Today, as the electronics industry’s largest user conference, SNUG brings together over 12,000 Synopsys tool and technology users across North America, Europe, Asia, and Japan. In addition to peer-reviewed technical presentations and insightful keynotes from… SNUG Silicon Valley 2023
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Siemens Tessent DFT Forum 2023 India
Hotel Radisson Blu Marathalli ORR, Bengaluru, IndiaAbout Siemens Tessent DFT Forum 2023 India Presenting silicon lifecycle solutions from Siemens EDA: Engineering a smarter future faster Join us for the Siemens Tessent Design-for-Test (DFT) India Tech Forum, being held in Hotel Radisson Blu, Marathalli ORR, Bengalur India, on 29th March, 2023 learn from Industry leaders, fellow designers and experts from Siemens about how to leverage the Tessent… Siemens Tessent DFT Forum 2023 India
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How to Achieve Seamless Deployment of Level 3 Virtual ECUs for Automotive Digital Twins
Driven by the trend towards software-defined vehicles (SDV), more complex software stacks are now being integrated into innovative automotive E/E architectures. Today the early integration testing of automotive software is already supported by using virtual ECUs (vECUs). However, the production basic software (BSW) is often not included because the virtualization of the hardware-specific microcontroller abstraction layer (MCAL)… How to Achieve Seamless Deployment of Level 3 Virtual ECUs for Automotive Digital Twins
12 events found.