Read my trip reports:
- DAC 2012 – Sunday Night Kick Off
- Physical IP Not From ARM or Synopsys
- Collaboration at 28nm, 20nm and 14nm: IBM, Cadence, ARM, GLOBALFOUNDRIES, Samsung
- Fast Monte Carlo and Analog Fast SPICE from ProPlus at DAC
- Schematic, IC Layout, Clock and Timing Closure from IC Scape at DAC
- ST using Cadence IC Tools with Module Generators at DAC
- A DAC Update from Mentor Graphics on IC Layout and Circuit Simulation Tools
- Fast SPICE from Kiev at DAC
- From SPICE Netlist back to Schematics at DAC
- 1,000,000,000,000 Transistor IC Layout Editing at DAC
- IC Layout Tools from Japan at DAC
- Soft Error Rate prediction software
- Fast Monte Carlo from Infiniscale at DAC
- What’s New with HSPICE at DAC?
- Samsung, Synopsys, GLOBALFOUNDRIES and ARM at DAC
- Analog Macromodels at DAC
- Shape-based IC Routing at DAC
- 3D Thermal and Mechanical Stress for IC Packaging at DAC
- IPL Alliance at DAC
- Custom IC Layout Automation at DAC
- Double Patterning Technology at DAC
- IC Cell Library Characterization at DAC
- Finding RTL Bugs Live at DAC using Formal Techniques
- EDA Tools to Optimize Memory Design, Size Standard Cells, Verify Low-Power Design, Center Analog Designs
- Laker IC Layout Update at DAC
- Electromagnetic Simulation Update from Nimbic at DAC
- DesignSync update from Dassault Systems at DAC
- FinFET Standard Cells at DAC
- AMS Simulation Update from Mentor Graphics at DAC
- Robustness, Reliability and Yield at DAC
- Analog FastSPICE update at DAC
- Methodics update at DAC
- Photo and Video overview of DAC 2012
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