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Advantest VOICE 2022

OMNI Scottsdale Resort Scottsdale, AZ

VOICE Registration is sold out and the event is at full capacity. We apologize for any inconvenience. VOICE is a developer conference, created by test engineers for test engineers. Each year, the VOICE Developer Conference unites semiconductor test professionals representing the world's leading integrated device manufacturers (IDMs), foundries, fabless semiconductor companies and outsourced semiconductor assembly… Read More »Advantest VOICE 2022

Embedded Vision Summit

Santa Clara Convention Center 5001 Great America Parkway, Santa Clara, CA

The premier event for practical, deployable computer vision and visual AI, for product creators who want to bring visual intelligence to products. The Summit attracts a global audience of technology professionals from companies developing computer vision and edge AI-enabled products including embedded systems, cloud solutions and mobile applications. Why attend? It's a First-Rate Program with… Read More »Embedded Vision Summit

Writing C/C++ Models for Efficient Datapath Validation Using VC Formal DPV

Wednesday, May 18, 2022 | 10:00 - 11:00 a.m. Pacific AI, Graphics, CPU, and many modern designs have arithmetic intensive blocks that are hard to verify with traditional techniques. Synopsys VC Formal DPV (Datapath Validation) has been the industry's golden standard to get closure on datapath verification.   In this Synopsys webinar, we will discuss why… Read More »Writing C/C++ Models for Efficient Datapath Validation Using VC Formal DPV

Conquer SI/PI Challenges and Reduce Time to Signoff for PCIe 6.0

The Peripheral Component Interconnect Express (PCIe®) high-speed interface has become the standard for computer expansion cards due to its high bandwidth combined with manageable component costs. However, the latest PCIe 6.0 release raises new challenges for design engineers, as the popular interface standard moves to pulse-amplitude modulation-4 (PAM-4) signaling for the first time. This webinar… Read More »Conquer SI/PI Challenges and Reduce Time to Signoff for PCIe 6.0

FPGA Design/Verification: Code, Functional and Specification Coverage

Functional coverage is often mentioned together with constrained-random verification, and this is a great combination. However, functional coverage is also very useful even if you have no randomization at all. This is a great method for ensuring that you are in fact checking the right things in your testbench.  Unfortunately, not many designers are applying… Read More »FPGA Design/Verification: Code, Functional and Specification Coverage

European Test Symposium 2022

Casa Convalescencia Barcelona

The IEEE European Test Symposium (ETS) is Europe’s premier forum dedicated to presenting and discussing scientific results, emerging ideas, applications, hot topics and new trends in the area of electronic-based circuits and system testing, reliability, security and validation. ETS’22 will be held in Casa Convalescència, located in the historical modernist site Hospital de la Santa… Read More »European Test Symposium 2022

A Faster Path to Analog Layout

Pulsic Webinars are back! Fast forward to the future of analog layout with this Mark Waller's webinar. In this webinar you will learn how to shrink your design time by 60% with Animate Preview. You are just one (free) click away from the future of analog design:

Automotive Cyber-Security: Off-board and On-board, standards and technologies

This webinar will help you understand: • The different standards that exist and why is compliance so important? • How to protect against tampering attacks? • What is lifecycle security and how can it benefit the automotive industry? • Why is it important to protect the whole lifecycle of a device?

Versal ACAP Workshop Online

The Xilinx Versal ACAP platform is multi-featured, offering unprecedented system level performance and integration. This informative workshop (delivered in 2 half day sessions) is a comprehensive and practical introduction to the features and capabilities. We’ll first cover the broader Versal ACAP device. We’ll then focus on a practical example, optimizing a given application for the… Read More »Versal ACAP Workshop Online

DSP IP for High Performance Sensor Fusion on an Embedded Budget

The growing use of a variety of sensors in edge devices – from wearables to virtual assistants to automotive radar/LiDAR – requires SoCs to have an optimal balance of DSP performance and low power/area. In addition, SoC developers must be able to easily scale their hardware architectures to handle a varying number of data streams… Read More »DSP IP for High Performance Sensor Fusion on an Embedded Budget

Veriest – Verification Meetup in Budapest

Regus Milpark Center 44 Soroksári St., Budapest

At Veriest, we believe in knowledge sharing. In our recent meetup events, hundreds of professionals from 20+ different countries gathered to listen to different industry experts from companies such as Intel, ST Microelectronics, arm, Texas Instruments, Nvidia and more. This time, we’ll host our first event in Budapest. Mr. Szabolcs Szolnoki, from the Hungarian Innovation agency, will… Read More »Veriest – Verification Meetup in Budapest

Better FPGA Verification with VHDL: OSVVM – Leading Edge Verification for the VHDL Community

OSVVM is an advanced verification methodology that defines a VHDL verification framework, verification utility library, verification component library, and a scripting flow that simplifies your FPGA verification projects from start to finish. Using these libraries, you can create a simple, readable, and powerful testbench that is suitable for either simple or complex FPGA blocks. Looking… Read More »Better FPGA Verification with VHDL: OSVVM – Leading Edge Verification for the VHDL Community

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