Latest Past Events
Hardware Verification using VirtuaLAB
VirtuaLAB protocol solutions offer a full-stack testing environment with seamless connectivity and stimulus traffic generation for designs under test. It operates autonomously, adapting to scenarios without requiring protocol knowledge from the user. VirtuaLAB significantly reduces test and compliance suite regression times, running at high emulation speeds, integrated with Protocol Analyzer for complete protocol visibility and… Hardware Verification using VirtuaLAB
RISC-V Summit – North America 2024
Santa Clara Convention Center 5001 Great America Parkway, Santa ClaraRISC-V is defining the future of open computing by providing unprecedented freedom to innovate. More than 13 billion RISC-V cores have shipped, powering new innovations in AI/ML, wireless, automotive. data center, space, IoT, embedded and more. Each day, thousands of engineers around the world collaborate and contribute to advance RISC-V. The RISC-V community shares the… RISC-V Summit – North America 2024
Jasper User Group San Jose 2024
Cadence Design Systems, Bldg 10 2655 Seeley Avenue, San JoseThe CadenceCONNECT: Jasper User Group San Jose will be held in person on October 22 - 23 at the Cadence San Jose campus. This interactive, in-depth technical conference connects designers, verification engineers, and engineering managers from around the world to share the latest design and verification practices based on Cadence’s Jasper formal verification technologies and… Jasper User Group San Jose 2024