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Marketing EDA

Freelance EDA Consultant

Home
About
Events
Clients
Services
Blogs
DAC Trip Reports
- DAC 2022
- DAC 2021
- DAC 2020
- DAC 2019
- DAC 2018
- DAC 2017
- DAC 2016
- DAC 2015
- DAC 2014
- DAC 2013
- DAC 2012
- DAC 2011
- DAC 2010
Contact

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Tweets

Mentions in the Press

AMS, RF and Digital Full Custom IC Designs need Circuit Sizing
MunEDA
September 2021
Automating the Design of Flat Panel Displays
Empyrean
October 2020
Xilinx Moves from Internal Flow to Commercial Flow for IP Integration
Empyrean
August 2020
Viewing the Largest IC Layout Files Quickly
Empyrean
March 2020
Where Circuit Simulation Model Files Come From
Silvaco
August 2019
ST, Intento: EDA for Faster Analog Design in FD-SOI
SOI Industry Consortium
July 2018
Predictions about EDA and IP at #52DAC
Design & Reuse
June 2015
Networking at 52nd DAC
DAC
April 2015
WLAN Design Optimization at Lantiq
MunEDA News
January 2015
Gary Smith EDA
Comments
July 2013
Verilog-AMS & Multi-Level Simulation
Aldec blog
July 2013
Daniel Payne reviews new Mixed-Signal Methodology book. He enjoyed it. Discount ends tomorrow!
Steve Leibson
August 30, 2012
DAC 2012 Preview: Focus on Formal and ABV Events and Papers
Cadence blog
May 14, 2012
ClioSoft Celebrates 2011 Year-end with 53% Increase in Bookings
Press Release
March 8, 2012
Mentor spins off product line, takes stake in buyer
Portland Business Journal
August 26, 2011
Establishing a new standard-the #SemiEDA hashtag
Synopsys blog
April 28, 2011
Mentor Graphics right to reject Icahn’s bid
Portland Business Journal
March 28, 2011
Rival Mentor bids could be market grab
Portland Business Journal
February 23, 2011
A New Collaboration for the Semiconductor Industry
Synopsys blog
November 18, 2010
Mentor Graphics rebounds, but Carl Icahn casts a shadow
Oregonian
July 10, 2010
Mentor Graphics waits to hear from Carl Icahn
Portland Business Journal
June 17, 2010
Analyst Newsletter
Cadence
Q2 2009
Tela Innovations – 1D Layout is Good for DFM
July 2009

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Address:

10440 SW Kellogg Drive
Tualatin, OR 97062

Automotive IP Certification June 5, 2023
Why Secure Ethernet Connections? May 29, 2023
Chiplet Interconnect Challenges and Standards May 25, 2023
Overcoming Semiconductor Supply Chain Bottlenecks May 15, 2023
Using ML for Statistical Circuit Verification May 3, 2023

News

Applying AI/ML Technology for Rapid Design Optimization June 6, 2023
RISC-V Days Tokyo 2023 Summer June 6, 2023
Microelectronics Design Security: Better with Formal Methods June 5, 2023
Verify Your SoC Design Efficiently from Planning to Coverage Closure using Synopsys Verification Family June 5, 2023
UCIe PHY Modeling and Simulation with XMODEL June 2, 2023

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