Formality ECO

RTL engineering change order (ECO) is vital to ensuring proper functionality of integrated circuits (ICs). Retiming and auto ungrouping optimize RTL implementation and enhance PPA. However, aggressive optimizations in CPU RTL designs present challenges due to increased design complexity and potential mapping issues.   Synopsys Formality ECO offers an efficient and accurate solution for RTL ECO… A Novel Approach to Implementing Logical ECOs with Synopsys Formality ECO on High Performance RISC-V Cores