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Formality ECO
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A Novel Approach to Implementing Logical ECOs with Synopsys Formality ECO on High Performance RISC-V Cores
RTL engineering change order (ECO) is vital to ensuring proper functionality of integrated circuits (ICs). Retiming and auto ungrouping optimize RTL implementation and enhance PPA. However, aggressive optimizations in CPU… A Novel Approach to Implementing Logical ECOs with Synopsys Formality ECO on High Performance RISC-V Cores